1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek Pinctrl Moore Driver, which implement the generic dt-binding
4 * pinctrl-bindings.txt for MediaTek SoC.
6 * Copyright (C) 2017-2018 MediaTek Inc.
7 * Author: Sean Wang <sean.wang@mediatek.com>
11 #include "pinctrl-moore.h"
13 #define PINCTRL_PINCTRL_DEV KBUILD_MODNAME
15 /* Custom pinconf parameters */
16 #define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1)
17 #define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2)
18 #define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3)
19 #define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4)
21 static const struct pinconf_generic_params mtk_custom_bindings[] = {
22 {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0},
23 {"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0},
24 {"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1},
25 {"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1},
28 #ifdef CONFIG_DEBUG_FS
29 static const struct pin_config_item mtk_conf_items[] = {
30 PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true),
31 PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
32 PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true),
33 PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true),
37 static int mtk_pinmux_set_mux(struct pinctrl_dev *pctldev,
38 unsigned int selector, unsigned int group)
40 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
41 struct function_desc *func;
42 struct group_desc *grp;
45 func = pinmux_generic_get_function(pctldev, selector);
49 grp = pinctrl_generic_get_group(pctldev, group);
53 dev_dbg(pctldev->dev, "enable function %s group %s\n",
54 func->name, grp->name);
56 for (i = 0; i < grp->num_pins; i++) {
57 const struct mtk_pin_desc *desc;
58 int *pin_modes = grp->data;
59 int pin = grp->pins[i];
61 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
63 mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
70 static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
71 struct pinctrl_gpio_range *range,
74 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
75 const struct mtk_pin_desc *desc;
77 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
79 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
83 static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
84 struct pinctrl_gpio_range *range,
85 unsigned int pin, bool input)
87 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
88 const struct mtk_pin_desc *desc;
90 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
92 /* hardware would take 0 as input direction */
93 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input);
96 static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
97 unsigned int pin, unsigned long *config)
99 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
100 u32 param = pinconf_to_config_param(*config);
101 int val, val2, err, reg, ret = 1;
102 const struct mtk_pin_desc *desc;
104 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
107 case PIN_CONFIG_BIAS_DISABLE:
108 if (hw->soc->bias_disable_get) {
109 err = hw->soc->bias_disable_get(hw, desc, &ret);
116 case PIN_CONFIG_BIAS_PULL_UP:
117 if (hw->soc->bias_get) {
118 err = hw->soc->bias_get(hw, desc, 1, &ret);
125 case PIN_CONFIG_BIAS_PULL_DOWN:
126 if (hw->soc->bias_get) {
127 err = hw->soc->bias_get(hw, desc, 0, &ret);
134 case PIN_CONFIG_SLEW_RATE:
135 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &val);
143 case PIN_CONFIG_INPUT_ENABLE:
144 case PIN_CONFIG_OUTPUT_ENABLE:
145 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val);
149 /* HW takes input mode as zero; output mode as non-zero */
150 if ((val && param == PIN_CONFIG_INPUT_ENABLE) ||
151 (!val && param == PIN_CONFIG_OUTPUT_ENABLE))
155 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
156 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val);
160 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &val2);
168 case PIN_CONFIG_DRIVE_STRENGTH:
169 if (hw->soc->drive_get) {
170 err = hw->soc->drive_get(hw, desc, &ret);
177 case MTK_PIN_CONFIG_TDSEL:
178 case MTK_PIN_CONFIG_RDSEL:
179 reg = (param == MTK_PIN_CONFIG_TDSEL) ?
180 PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
182 err = mtk_hw_get_value(hw, desc, reg, &val);
189 case MTK_PIN_CONFIG_PU_ADV:
190 case MTK_PIN_CONFIG_PD_ADV:
191 if (hw->soc->adv_pull_get) {
194 pullup = param == MTK_PIN_CONFIG_PU_ADV;
195 err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
206 *config = pinconf_to_config_packed(param, ret);
211 static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
212 unsigned long *configs, unsigned int num_configs)
214 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
215 const struct mtk_pin_desc *desc;
219 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
221 for (cfg = 0; cfg < num_configs; cfg++) {
222 param = pinconf_to_config_param(configs[cfg]);
223 arg = pinconf_to_config_argument(configs[cfg]);
226 case PIN_CONFIG_BIAS_DISABLE:
227 if (hw->soc->bias_disable_set) {
228 err = hw->soc->bias_disable_set(hw, desc);
235 case PIN_CONFIG_BIAS_PULL_UP:
236 if (hw->soc->bias_set) {
237 err = hw->soc->bias_set(hw, desc, 1);
244 case PIN_CONFIG_BIAS_PULL_DOWN:
245 if (hw->soc->bias_set) {
246 err = hw->soc->bias_set(hw, desc, 0);
253 case PIN_CONFIG_OUTPUT_ENABLE:
254 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
259 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
264 case PIN_CONFIG_INPUT_ENABLE:
266 if (hw->soc->ies_present) {
267 mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES,
271 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
276 case PIN_CONFIG_SLEW_RATE:
277 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR,
283 case PIN_CONFIG_OUTPUT:
284 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
289 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
294 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
295 /* arg = 1: Input mode & SMT enable ;
296 * arg = 0: Output mode & SMT disable
299 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
304 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
309 case PIN_CONFIG_DRIVE_STRENGTH:
310 if (hw->soc->drive_set) {
311 err = hw->soc->drive_set(hw, desc, arg);
318 case MTK_PIN_CONFIG_TDSEL:
319 case MTK_PIN_CONFIG_RDSEL:
320 reg = (param == MTK_PIN_CONFIG_TDSEL) ?
321 PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
323 err = mtk_hw_set_value(hw, desc, reg, arg);
327 case MTK_PIN_CONFIG_PU_ADV:
328 case MTK_PIN_CONFIG_PD_ADV:
329 if (hw->soc->adv_pull_set) {
332 pullup = param == MTK_PIN_CONFIG_PU_ADV;
333 err = hw->soc->adv_pull_set(hw, desc, pullup,
349 static int mtk_pinconf_group_get(struct pinctrl_dev *pctldev,
350 unsigned int group, unsigned long *config)
352 const unsigned int *pins;
353 unsigned int i, npins, old = 0;
356 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
360 for (i = 0; i < npins; i++) {
361 if (mtk_pinconf_get(pctldev, pins[i], config))
364 /* configs do not match between two pins */
365 if (i && old != *config)
374 static int mtk_pinconf_group_set(struct pinctrl_dev *pctldev,
375 unsigned int group, unsigned long *configs,
376 unsigned int num_configs)
378 const unsigned int *pins;
379 unsigned int i, npins;
382 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
386 for (i = 0; i < npins; i++) {
387 ret = mtk_pinconf_set(pctldev, pins[i], configs, num_configs);
395 static const struct pinctrl_ops mtk_pctlops = {
396 .get_groups_count = pinctrl_generic_get_group_count,
397 .get_group_name = pinctrl_generic_get_group_name,
398 .get_group_pins = pinctrl_generic_get_group_pins,
399 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
400 .dt_free_map = pinconf_generic_dt_free_map,
403 static const struct pinmux_ops mtk_pmxops = {
404 .get_functions_count = pinmux_generic_get_function_count,
405 .get_function_name = pinmux_generic_get_function_name,
406 .get_function_groups = pinmux_generic_get_function_groups,
407 .set_mux = mtk_pinmux_set_mux,
408 .gpio_request_enable = mtk_pinmux_gpio_request_enable,
409 .gpio_set_direction = mtk_pinmux_gpio_set_direction,
413 static const struct pinconf_ops mtk_confops = {
415 .pin_config_get = mtk_pinconf_get,
416 .pin_config_set = mtk_pinconf_set,
417 .pin_config_group_get = mtk_pinconf_group_get,
418 .pin_config_group_set = mtk_pinconf_group_set,
419 .pin_config_config_dbg_show = pinconf_generic_dump_config,
422 static struct pinctrl_desc mtk_desc = {
423 .name = PINCTRL_PINCTRL_DEV,
424 .pctlops = &mtk_pctlops,
425 .pmxops = &mtk_pmxops,
426 .confops = &mtk_confops,
427 .owner = THIS_MODULE,
430 static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
432 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
433 const struct mtk_pin_desc *desc;
436 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
438 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
445 static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
447 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
448 const struct mtk_pin_desc *desc;
450 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
452 mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
455 static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
457 return pinctrl_gpio_direction_input(chip->base + gpio);
460 static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
463 mtk_gpio_set(chip, gpio, value);
465 return pinctrl_gpio_direction_output(chip->base + gpio);
468 static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
470 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
471 const struct mtk_pin_desc *desc;
476 desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
478 if (desc->eint_n == EINT_NA)
481 return mtk_eint_find_irq(hw->eint, desc->eint_n);
484 static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
485 unsigned long config)
487 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
488 const struct mtk_pin_desc *desc;
491 desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
494 pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE ||
495 desc->eint_n == EINT_NA)
498 debounce = pinconf_to_config_argument(config);
500 return mtk_eint_set_debounce(hw->eint, desc->eint_n, debounce);
503 static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
505 struct gpio_chip *chip = &hw->chip;
508 chip->label = PINCTRL_PINCTRL_DEV;
509 chip->parent = hw->dev;
510 chip->request = gpiochip_generic_request;
511 chip->free = gpiochip_generic_free;
512 chip->direction_input = mtk_gpio_direction_input;
513 chip->direction_output = mtk_gpio_direction_output;
514 chip->get = mtk_gpio_get;
515 chip->set = mtk_gpio_set;
516 chip->to_irq = mtk_gpio_to_irq,
517 chip->set_config = mtk_gpio_set_config,
519 chip->ngpio = hw->soc->npins;
521 chip->of_gpio_n_cells = 2;
523 ret = gpiochip_add_data(chip, hw);
527 /* Just for backward compatible for these old pinctrl nodes without
528 * "gpio-ranges" property. Otherwise, called directly from a
529 * DeviceTree-supported pinctrl driver is DEPRECATED.
530 * Please see Section 2.1 of
531 * Documentation/devicetree/bindings/gpio/gpio.txt on how to
532 * bind pinctrl and gpio drivers via the "gpio-ranges" property.
534 if (!of_find_property(np, "gpio-ranges", NULL)) {
535 ret = gpiochip_add_pin_range(chip, dev_name(hw->dev), 0, 0,
538 gpiochip_remove(chip);
546 static int mtk_build_groups(struct mtk_pinctrl *hw)
550 for (i = 0; i < hw->soc->ngrps; i++) {
551 const struct group_desc *group = hw->soc->grps + i;
553 err = pinctrl_generic_add_group(hw->pctrl, group->name,
554 group->pins, group->num_pins,
557 dev_err(hw->dev, "Failed to register group %s\n",
566 static int mtk_build_functions(struct mtk_pinctrl *hw)
570 for (i = 0; i < hw->soc->nfuncs ; i++) {
571 const struct function_desc *func = hw->soc->funcs + i;
573 err = pinmux_generic_add_function(hw->pctrl, func->name,
575 func->num_group_names,
578 dev_err(hw->dev, "Failed to register function %s\n",
587 static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw,
588 unsigned long eint_n)
590 const struct mtk_pin_desc *desc;
593 desc = (const struct mtk_pin_desc *)hw->soc->pins;
595 while (i < hw->soc->npins) {
596 if (desc[i].eint_n == eint_n)
597 return desc[i].number;
604 static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n,
605 unsigned int *gpio_n,
606 struct gpio_chip **gpio_chip)
608 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
609 const struct mtk_pin_desc *desc;
611 desc = (const struct mtk_pin_desc *)hw->soc->pins;
612 *gpio_chip = &hw->chip;
614 /* Be greedy to guess first gpio_n is equal to eint_n */
615 if (desc[eint_n].eint_n == eint_n)
618 *gpio_n = mtk_xt_find_eint_num(hw, eint_n);
620 return *gpio_n == EINT_NA ? -EINVAL : 0;
623 static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n)
625 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
626 struct gpio_chip *gpio_chip;
630 err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
634 return mtk_gpio_get(gpio_chip, gpio_n);
637 static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n)
639 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
640 const struct mtk_pin_desc *desc;
641 struct gpio_chip *gpio_chip;
645 err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
649 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
651 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
656 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_INPUT);
660 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, MTK_ENABLE);
667 static const struct mtk_eint_xt mtk_eint_xt = {
668 .get_gpio_n = mtk_xt_get_gpio_n,
669 .get_gpio_state = mtk_xt_get_gpio_state,
670 .set_gpio_as_eint = mtk_xt_set_gpio_as_eint,
674 mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev)
676 struct device_node *np = pdev->dev.of_node;
677 struct resource *res;
679 if (!IS_ENABLED(CONFIG_EINT_MTK))
682 if (!of_property_read_bool(np, "interrupt-controller"))
685 hw->eint = devm_kzalloc(hw->dev, sizeof(*hw->eint), GFP_KERNEL);
689 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eint");
691 dev_err(&pdev->dev, "Unable to get eint resource\n");
695 hw->eint->base = devm_ioremap_resource(&pdev->dev, res);
696 if (IS_ERR(hw->eint->base))
697 return PTR_ERR(hw->eint->base);
699 hw->eint->irq = irq_of_parse_and_map(np, 0);
703 hw->eint->dev = &pdev->dev;
704 hw->eint->hw = hw->soc->eint_hw;
706 hw->eint->gpio_xlate = &mtk_eint_xt;
708 return mtk_eint_do_init(hw->eint);
711 int mtk_moore_pinctrl_probe(struct platform_device *pdev,
712 const struct mtk_pin_soc *soc)
714 struct resource *res;
715 struct mtk_pinctrl *hw;
718 hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
723 hw->dev = &pdev->dev;
725 if (!hw->soc->nbase_names) {
727 "SoC should be assigned at least one register base\n");
731 hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
732 sizeof(*hw->base), GFP_KERNEL);
733 if (IS_ERR(hw->base))
734 return PTR_ERR(hw->base);
736 for (i = 0; i < hw->soc->nbase_names; i++) {
737 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
738 hw->soc->base_names[i]);
740 dev_err(&pdev->dev, "missing IO resource\n");
744 hw->base[i] = devm_ioremap_resource(&pdev->dev, res);
745 if (IS_ERR(hw->base[i]))
746 return PTR_ERR(hw->base[i]);
749 hw->nbase = hw->soc->nbase_names;
751 /* Setup pins descriptions per SoC types */
752 mtk_desc.pins = (const struct pinctrl_pin_desc *)hw->soc->pins;
753 mtk_desc.npins = hw->soc->npins;
754 mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings);
755 mtk_desc.custom_params = mtk_custom_bindings;
756 #ifdef CONFIG_DEBUG_FS
757 mtk_desc.custom_conf_items = mtk_conf_items;
760 err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw,
765 /* Setup groups descriptions per SoC types */
766 err = mtk_build_groups(hw);
768 dev_err(&pdev->dev, "Failed to build groups\n");
772 /* Setup functions descriptions per SoC types */
773 err = mtk_build_functions(hw);
775 dev_err(&pdev->dev, "Failed to build functions\n");
779 /* For able to make pinctrl_claim_hogs, we must not enable pinctrl
780 * until all groups and functions are being added one.
782 err = pinctrl_enable(hw->pctrl);
786 err = mtk_build_eint(hw, pdev);
789 "Failed to add EINT, but pinctrl still can work\n");
791 /* Build gpiochip should be after pinctrl_enable is done */
792 err = mtk_build_gpiochip(hw, pdev->dev.of_node);
794 dev_err(&pdev->dev, "Failed to add gpio_chip\n");
798 platform_set_drvdata(pdev, hw);