2 * at91 pinctrl driver based on at91 pinmux core
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 #include <linux/err.h>
11 #include <linux/init.h>
13 #include <linux/of_device.h>
14 #include <linux/of_address.h>
15 #include <linux/of_irq.h>
16 #include <linux/slab.h>
17 #include <linux/interrupt.h>
19 #include <linux/gpio/driver.h>
20 #include <linux/pinctrl/machine.h>
21 #include <linux/pinctrl/pinconf.h>
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
24 /* Since we request GPIOs from ourself */
25 #include <linux/pinctrl/consumer.h>
27 #include "pinctrl-at91.h"
30 #define MAX_GPIO_BANKS 5
31 #define MAX_NB_GPIO_PER_BANK 32
33 struct at91_pinctrl_mux_ops;
35 struct at91_gpio_chip {
36 struct gpio_chip chip;
37 struct pinctrl_gpio_range range;
38 struct at91_gpio_chip *next; /* Bank sharing same clock */
39 int pioc_hwirq; /* PIO bank interrupt identifier on AIC */
40 int pioc_virq; /* PIO bank Linux virtual interrupt */
41 int pioc_idx; /* PIO bank index */
42 void __iomem *regbase; /* PIO bank virtual address */
43 struct clk *clock; /* associated clock */
44 struct at91_pinctrl_mux_ops *ops; /* ops */
47 static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
49 static int gpio_banks;
51 #define PULL_UP (1 << 0)
52 #define MULTI_DRIVE (1 << 1)
53 #define DEGLITCH (1 << 2)
54 #define PULL_DOWN (1 << 3)
55 #define DIS_SCHMIT (1 << 4)
56 #define DRIVE_STRENGTH_SHIFT 5
57 #define DRIVE_STRENGTH_MASK 0x3
58 #define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
59 #define OUTPUT (1 << 7)
60 #define OUTPUT_VAL_SHIFT 8
61 #define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT)
62 #define DEBOUNCE (1 << 16)
63 #define DEBOUNCE_VAL_SHIFT 17
64 #define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
67 * These defines will translated the dt binding settings to our internal
68 * settings. They are not necessarily the same value as the register setting.
69 * The actual drive strength current of low, medium and high must be looked up
70 * from the corresponding device datasheet. This value is different for pins
71 * that are even in the same banks. It is also dependent on VCC.
72 * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
73 * strength when there is no dt config for it.
75 enum drive_strength_bit {
76 DRIVE_STRENGTH_BIT_DEF,
77 DRIVE_STRENGTH_BIT_LOW,
78 DRIVE_STRENGTH_BIT_MED,
79 DRIVE_STRENGTH_BIT_HI,
82 #define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
86 * struct at91_pmx_func - describes AT91 pinmux functions
87 * @name: the name of this specific function
88 * @groups: corresponding pin groups
89 * @ngroups: the number of groups
91 struct at91_pmx_func {
99 AT91_MUX_PERIPH_A = 1,
100 AT91_MUX_PERIPH_B = 2,
101 AT91_MUX_PERIPH_C = 3,
102 AT91_MUX_PERIPH_D = 4,
106 * struct at91_pmx_pin - describes an At91 pin mux
107 * @bank: the bank of the pin
108 * @pin: the pin number in the @bank
109 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
110 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
112 struct at91_pmx_pin {
120 * struct at91_pin_group - describes an At91 pin group
121 * @name: the name of this specific pin group
122 * @pins_conf: the mux mode for each pin in this group. The size of this
123 * array is the same as pins.
124 * @pins: an array of discrete physical pins used in this group, taken
125 * from the driver-local pin enumeration space
126 * @npins: the number of pins in this group array, i.e. the number of
127 * elements in .pins so we can iterate over that array
129 struct at91_pin_group {
131 struct at91_pmx_pin *pins_conf;
137 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
138 * on new IP with support for periph C and D the way to mux in
139 * periph A and B has changed
140 * So provide the right call back
141 * if not present means the IP does not support it
142 * @get_periph: return the periph mode configured
143 * @mux_A_periph: mux as periph A
144 * @mux_B_periph: mux as periph B
145 * @mux_C_periph: mux as periph C
146 * @mux_D_periph: mux as periph D
147 * @get_deglitch: get deglitch status
148 * @set_deglitch: enable/disable deglitch
149 * @get_debounce: get debounce status
150 * @set_debounce: enable/disable debounce
151 * @get_pulldown: get pulldown status
152 * @set_pulldown: enable/disable pulldown
153 * @get_schmitt_trig: get schmitt trigger status
154 * @disable_schmitt_trig: disable schmitt trigger
155 * @irq_type: return irq type
157 struct at91_pinctrl_mux_ops {
158 enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
159 void (*mux_A_periph)(void __iomem *pio, unsigned mask);
160 void (*mux_B_periph)(void __iomem *pio, unsigned mask);
161 void (*mux_C_periph)(void __iomem *pio, unsigned mask);
162 void (*mux_D_periph)(void __iomem *pio, unsigned mask);
163 bool (*get_deglitch)(void __iomem *pio, unsigned pin);
164 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
165 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
166 void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
167 bool (*get_pulldown)(void __iomem *pio, unsigned pin);
168 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
169 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
170 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
171 unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
172 void (*set_drivestrength)(void __iomem *pio, unsigned pin,
175 int (*irq_type)(struct irq_data *d, unsigned type);
178 static int gpio_irq_type(struct irq_data *d, unsigned type);
179 static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
181 struct at91_pinctrl {
183 struct pinctrl_dev *pctl;
190 struct at91_pmx_func *functions;
193 struct at91_pin_group *groups;
196 struct at91_pinctrl_mux_ops *ops;
199 static inline const struct at91_pin_group *at91_pinctrl_find_group_by_name(
200 const struct at91_pinctrl *info,
203 const struct at91_pin_group *grp = NULL;
206 for (i = 0; i < info->ngroups; i++) {
207 if (strcmp(info->groups[i].name, name))
210 grp = &info->groups[i];
211 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
218 static int at91_get_groups_count(struct pinctrl_dev *pctldev)
220 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
222 return info->ngroups;
225 static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
228 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
230 return info->groups[selector].name;
233 static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
234 const unsigned **pins,
237 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
239 if (selector >= info->ngroups)
242 *pins = info->groups[selector].pins;
243 *npins = info->groups[selector].npins;
248 static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
251 seq_printf(s, "%s", dev_name(pctldev->dev));
254 static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
255 struct device_node *np,
256 struct pinctrl_map **map, unsigned *num_maps)
258 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
259 const struct at91_pin_group *grp;
260 struct pinctrl_map *new_map;
261 struct device_node *parent;
266 * first find the group of this node and check if we need to create
267 * config maps for pins
269 grp = at91_pinctrl_find_group_by_name(info, np->name);
271 dev_err(info->dev, "unable to find group for node %pOFn\n",
276 map_num += grp->npins;
277 new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map),
286 parent = of_get_parent(np);
288 devm_kfree(pctldev->dev, new_map);
291 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
292 new_map[0].data.mux.function = parent->name;
293 new_map[0].data.mux.group = np->name;
296 /* create config map */
298 for (i = 0; i < grp->npins; i++) {
299 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
300 new_map[i].data.configs.group_or_pin =
301 pin_get_name(pctldev, grp->pins[i]);
302 new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
303 new_map[i].data.configs.num_configs = 1;
306 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
307 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
312 static void at91_dt_free_map(struct pinctrl_dev *pctldev,
313 struct pinctrl_map *map, unsigned num_maps)
317 static const struct pinctrl_ops at91_pctrl_ops = {
318 .get_groups_count = at91_get_groups_count,
319 .get_group_name = at91_get_group_name,
320 .get_group_pins = at91_get_group_pins,
321 .pin_dbg_show = at91_pin_dbg_show,
322 .dt_node_to_map = at91_dt_node_to_map,
323 .dt_free_map = at91_dt_free_map,
326 static void __iomem *pin_to_controller(struct at91_pinctrl *info,
329 if (!gpio_chips[bank])
332 return gpio_chips[bank]->regbase;
335 static inline int pin_to_bank(unsigned pin)
337 return pin /= MAX_NB_GPIO_PER_BANK;
340 static unsigned pin_to_mask(unsigned int pin)
345 static unsigned two_bit_pin_value_shift_amount(unsigned int pin)
347 /* return the shift value for a pin for "two bit" per pin registers,
348 * i.e. drive strength */
349 return 2*((pin >= MAX_NB_GPIO_PER_BANK/2)
350 ? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
353 static unsigned sama5d3_get_drive_register(unsigned int pin)
355 /* drive strength is split between two registers
356 * with two bits per pin */
357 return (pin >= MAX_NB_GPIO_PER_BANK/2)
358 ? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1;
361 static unsigned at91sam9x5_get_drive_register(unsigned int pin)
363 /* drive strength is split between two registers
364 * with two bits per pin */
365 return (pin >= MAX_NB_GPIO_PER_BANK/2)
366 ? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1;
369 static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
371 writel_relaxed(mask, pio + PIO_IDR);
374 static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
376 return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1);
379 static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
382 writel_relaxed(mask, pio + PIO_PPDDR);
384 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
387 static bool at91_mux_get_output(void __iomem *pio, unsigned int pin, bool *val)
389 *val = (readl_relaxed(pio + PIO_ODSR) >> pin) & 0x1;
390 return (readl_relaxed(pio + PIO_OSR) >> pin) & 0x1;
393 static void at91_mux_set_output(void __iomem *pio, unsigned int mask,
394 bool is_on, bool val)
396 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
397 writel_relaxed(mask, pio + (is_on ? PIO_OER : PIO_ODR));
400 static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
402 return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
405 static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
407 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
410 static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
412 writel_relaxed(mask, pio + PIO_ASR);
415 static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
417 writel_relaxed(mask, pio + PIO_BSR);
420 static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
423 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
425 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
429 static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
431 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
433 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
437 static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
439 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
440 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
443 static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
445 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
446 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
449 static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
453 if (readl_relaxed(pio + PIO_PSR) & mask)
454 return AT91_MUX_GPIO;
456 select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
457 select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);
462 static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
466 if (readl_relaxed(pio + PIO_PSR) & mask)
467 return AT91_MUX_GPIO;
469 select = readl_relaxed(pio + PIO_ABSR) & mask;
474 static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
476 return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1;
479 static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
481 writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
484 static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin)
486 if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1)
487 return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
492 static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
495 writel_relaxed(mask, pio + PIO_IFSCDR);
496 at91_mux_set_deglitch(pio, mask, is_on);
499 static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
501 *div = readl_relaxed(pio + PIO_SCDR);
503 return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) &&
504 ((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
507 static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
511 writel_relaxed(mask, pio + PIO_IFSCER);
512 writel_relaxed(div & PIO_SCDR_DIV, pio + PIO_SCDR);
513 writel_relaxed(mask, pio + PIO_IFER);
515 writel_relaxed(mask, pio + PIO_IFSCDR);
518 static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
520 return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1);
523 static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
526 writel_relaxed(mask, pio + PIO_PUDR);
528 writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
531 static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
533 writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
536 static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
538 return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1;
541 static inline u32 read_drive_strength(void __iomem *reg, unsigned pin)
543 unsigned tmp = readl_relaxed(reg);
545 tmp = tmp >> two_bit_pin_value_shift_amount(pin);
547 return tmp & DRIVE_STRENGTH_MASK;
550 static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
553 unsigned tmp = read_drive_strength(pio +
554 sama5d3_get_drive_register(pin), pin);
556 /* SAMA5 strength is 1:1 with our defines,
557 * except 0 is equivalent to low per datasheet */
559 tmp = DRIVE_STRENGTH_BIT_MSK(LOW);
564 static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
567 unsigned tmp = read_drive_strength(pio +
568 at91sam9x5_get_drive_register(pin), pin);
570 /* strength is inverse in SAM9x5s hardware with the pinctrl defines
571 * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
572 tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp;
577 static unsigned at91_mux_sam9x60_get_drivestrength(void __iomem *pio,
580 unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
583 return DRIVE_STRENGTH_BIT_HI;
585 return DRIVE_STRENGTH_BIT_LOW;
588 static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
590 unsigned tmp = readl_relaxed(reg);
591 unsigned shift = two_bit_pin_value_shift_amount(pin);
593 tmp &= ~(DRIVE_STRENGTH_MASK << shift);
594 tmp |= strength << shift;
596 writel_relaxed(tmp, reg);
599 static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin,
602 /* do nothing if setting is zero */
606 /* strength is 1 to 1 with setting for SAMA5 */
607 set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting);
610 static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
613 /* do nothing if setting is zero */
617 /* strength is inverse on SAM9x5s with our defines
618 * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
619 setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
621 set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
625 static void at91_mux_sam9x60_set_drivestrength(void __iomem *pio, unsigned pin,
630 if (setting <= DRIVE_STRENGTH_BIT_DEF ||
631 setting == DRIVE_STRENGTH_BIT_MED ||
632 setting > DRIVE_STRENGTH_BIT_HI)
635 tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
637 /* Strength is 0: low, 1: hi */
638 if (setting == DRIVE_STRENGTH_BIT_LOW)
643 writel_relaxed(tmp, pio + SAM9X60_PIO_DRIVER1);
646 static struct at91_pinctrl_mux_ops at91rm9200_ops = {
647 .get_periph = at91_mux_get_periph,
648 .mux_A_periph = at91_mux_set_A_periph,
649 .mux_B_periph = at91_mux_set_B_periph,
650 .get_deglitch = at91_mux_get_deglitch,
651 .set_deglitch = at91_mux_set_deglitch,
652 .irq_type = gpio_irq_type,
655 static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
656 .get_periph = at91_mux_pio3_get_periph,
657 .mux_A_periph = at91_mux_pio3_set_A_periph,
658 .mux_B_periph = at91_mux_pio3_set_B_periph,
659 .mux_C_periph = at91_mux_pio3_set_C_periph,
660 .mux_D_periph = at91_mux_pio3_set_D_periph,
661 .get_deglitch = at91_mux_pio3_get_deglitch,
662 .set_deglitch = at91_mux_pio3_set_deglitch,
663 .get_debounce = at91_mux_pio3_get_debounce,
664 .set_debounce = at91_mux_pio3_set_debounce,
665 .get_pulldown = at91_mux_pio3_get_pulldown,
666 .set_pulldown = at91_mux_pio3_set_pulldown,
667 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
668 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
669 .get_drivestrength = at91_mux_sam9x5_get_drivestrength,
670 .set_drivestrength = at91_mux_sam9x5_set_drivestrength,
671 .irq_type = alt_gpio_irq_type,
674 static const struct at91_pinctrl_mux_ops sam9x60_ops = {
675 .get_periph = at91_mux_pio3_get_periph,
676 .mux_A_periph = at91_mux_pio3_set_A_periph,
677 .mux_B_periph = at91_mux_pio3_set_B_periph,
678 .mux_C_periph = at91_mux_pio3_set_C_periph,
679 .mux_D_periph = at91_mux_pio3_set_D_periph,
680 .get_deglitch = at91_mux_pio3_get_deglitch,
681 .set_deglitch = at91_mux_pio3_set_deglitch,
682 .get_debounce = at91_mux_pio3_get_debounce,
683 .set_debounce = at91_mux_pio3_set_debounce,
684 .get_pulldown = at91_mux_pio3_get_pulldown,
685 .set_pulldown = at91_mux_pio3_set_pulldown,
686 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
687 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
688 .get_drivestrength = at91_mux_sam9x60_get_drivestrength,
689 .set_drivestrength = at91_mux_sam9x60_set_drivestrength,
690 .irq_type = alt_gpio_irq_type,
694 static struct at91_pinctrl_mux_ops sama5d3_ops = {
695 .get_periph = at91_mux_pio3_get_periph,
696 .mux_A_periph = at91_mux_pio3_set_A_periph,
697 .mux_B_periph = at91_mux_pio3_set_B_periph,
698 .mux_C_periph = at91_mux_pio3_set_C_periph,
699 .mux_D_periph = at91_mux_pio3_set_D_periph,
700 .get_deglitch = at91_mux_pio3_get_deglitch,
701 .set_deglitch = at91_mux_pio3_set_deglitch,
702 .get_debounce = at91_mux_pio3_get_debounce,
703 .set_debounce = at91_mux_pio3_set_debounce,
704 .get_pulldown = at91_mux_pio3_get_pulldown,
705 .set_pulldown = at91_mux_pio3_set_pulldown,
706 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
707 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
708 .get_drivestrength = at91_mux_sama5d3_get_drivestrength,
709 .set_drivestrength = at91_mux_sama5d3_set_drivestrength,
710 .irq_type = alt_gpio_irq_type,
713 static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
716 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n",
717 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
719 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n",
720 pin->bank + 'A', pin->pin, pin->conf);
724 static int pin_check_config(struct at91_pinctrl *info, const char *name,
725 int index, const struct at91_pmx_pin *pin)
729 /* check if it's a valid config */
730 if (pin->bank >= gpio_banks) {
731 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
732 name, index, pin->bank, gpio_banks);
736 if (!gpio_chips[pin->bank]) {
737 dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n",
738 name, index, pin->bank);
742 if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
743 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
744 name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
753 if (mux >= info->nmux) {
754 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
755 name, index, mux, info->nmux);
759 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
760 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
761 name, index, mux, pin->bank + 'A', pin->pin);
768 static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
770 writel_relaxed(mask, pio + PIO_PDR);
773 static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
775 writel_relaxed(mask, pio + PIO_PER);
776 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
779 static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
782 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
783 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
784 const struct at91_pmx_pin *pin;
785 uint32_t npins = info->groups[group].npins;
790 dev_dbg(info->dev, "enable function %s group %s\n",
791 info->functions[selector].name, info->groups[group].name);
793 /* first check that all the pins of the group are valid with a valid
795 for (i = 0; i < npins; i++) {
797 ret = pin_check_config(info, info->groups[group].name, i, pin);
802 for (i = 0; i < npins; i++) {
804 at91_pin_dbg(info->dev, pin);
805 pio = pin_to_controller(info, pin->bank);
810 mask = pin_to_mask(pin->pin);
811 at91_mux_disable_interrupt(pio, mask);
814 at91_mux_gpio_enable(pio, mask, 1);
816 case AT91_MUX_PERIPH_A:
817 info->ops->mux_A_periph(pio, mask);
819 case AT91_MUX_PERIPH_B:
820 info->ops->mux_B_periph(pio, mask);
822 case AT91_MUX_PERIPH_C:
823 if (!info->ops->mux_C_periph)
825 info->ops->mux_C_periph(pio, mask);
827 case AT91_MUX_PERIPH_D:
828 if (!info->ops->mux_D_periph)
830 info->ops->mux_D_periph(pio, mask);
834 at91_mux_gpio_disable(pio, mask);
840 static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
842 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
844 return info->nfunctions;
847 static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
850 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
852 return info->functions[selector].name;
855 static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
856 const char * const **groups,
857 unsigned * const num_groups)
859 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
861 *groups = info->functions[selector].groups;
862 *num_groups = info->functions[selector].ngroups;
867 static int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
868 struct pinctrl_gpio_range *range,
871 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
872 struct at91_gpio_chip *at91_chip;
873 struct gpio_chip *chip;
877 dev_err(npct->dev, "invalid range\n");
881 dev_err(npct->dev, "missing GPIO chip in range\n");
885 at91_chip = gpiochip_get_data(chip);
887 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
889 mask = 1 << (offset - chip->base);
891 dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
892 offset, 'A' + range->id, offset - chip->base, mask);
894 writel_relaxed(mask, at91_chip->regbase + PIO_PER);
899 static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
900 struct pinctrl_gpio_range *range,
903 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
905 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
906 /* Set the pin to some default state, GPIO is usually default */
909 static const struct pinmux_ops at91_pmx_ops = {
910 .get_functions_count = at91_pmx_get_funcs_count,
911 .get_function_name = at91_pmx_get_func_name,
912 .get_function_groups = at91_pmx_get_groups,
913 .set_mux = at91_pmx_set,
914 .gpio_request_enable = at91_gpio_request_enable,
915 .gpio_disable_free = at91_gpio_disable_free,
918 static int at91_pinconf_get(struct pinctrl_dev *pctldev,
919 unsigned pin_id, unsigned long *config)
921 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
928 dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id);
929 pio = pin_to_controller(info, pin_to_bank(pin_id));
934 pin = pin_id % MAX_NB_GPIO_PER_BANK;
936 if (at91_mux_get_multidrive(pio, pin))
937 *config |= MULTI_DRIVE;
939 if (at91_mux_get_pullup(pio, pin))
942 if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin))
944 if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div))
945 *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT);
946 if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin))
947 *config |= PULL_DOWN;
948 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
949 *config |= DIS_SCHMIT;
950 if (info->ops->get_drivestrength)
951 *config |= (info->ops->get_drivestrength(pio, pin)
952 << DRIVE_STRENGTH_SHIFT);
953 if (at91_mux_get_output(pio, pin, &out))
954 *config |= OUTPUT | (out << OUTPUT_VAL_SHIFT);
959 static int at91_pinconf_set(struct pinctrl_dev *pctldev,
960 unsigned pin_id, unsigned long *configs,
961 unsigned num_configs)
963 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
967 unsigned long config;
970 for (i = 0; i < num_configs; i++) {
974 "%s:%d, pin_id=%d, config=0x%lx",
975 __func__, __LINE__, pin_id, config);
976 pio = pin_to_controller(info, pin_to_bank(pin_id));
981 pin = pin_id % MAX_NB_GPIO_PER_BANK;
982 mask = pin_to_mask(pin);
984 if (config & PULL_UP && config & PULL_DOWN)
987 at91_mux_set_output(pio, mask, config & OUTPUT,
988 (config & OUTPUT_VAL) >> OUTPUT_VAL_SHIFT);
989 at91_mux_set_pullup(pio, mask, config & PULL_UP);
990 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
991 if (info->ops->set_deglitch)
992 info->ops->set_deglitch(pio, mask, config & DEGLITCH);
993 if (info->ops->set_debounce)
994 info->ops->set_debounce(pio, mask, config & DEBOUNCE,
995 (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
996 if (info->ops->set_pulldown)
997 info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
998 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
999 info->ops->disable_schmitt_trig(pio, mask);
1000 if (info->ops->set_drivestrength)
1001 info->ops->set_drivestrength(pio, pin,
1002 (config & DRIVE_STRENGTH)
1003 >> DRIVE_STRENGTH_SHIFT);
1005 } /* for each config */
1010 #define DBG_SHOW_FLAG(flag) do { \
1011 if (config & flag) { \
1014 seq_puts(s, #flag); \
1019 #define DBG_SHOW_FLAG_MASKED(mask, flag, name) do { \
1020 if ((config & mask) == flag) { \
1023 seq_puts(s, #name); \
1028 static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
1029 struct seq_file *s, unsigned pin_id)
1031 unsigned long config;
1032 int val, num_conf = 0;
1034 at91_pinconf_get(pctldev, pin_id, &config);
1036 DBG_SHOW_FLAG(MULTI_DRIVE);
1037 DBG_SHOW_FLAG(PULL_UP);
1038 DBG_SHOW_FLAG(PULL_DOWN);
1039 DBG_SHOW_FLAG(DIS_SCHMIT);
1040 DBG_SHOW_FLAG(DEGLITCH);
1041 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
1042 DRIVE_STRENGTH_LOW);
1043 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
1044 DRIVE_STRENGTH_MED);
1045 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
1047 DBG_SHOW_FLAG(DEBOUNCE);
1048 if (config & DEBOUNCE) {
1049 val = config >> DEBOUNCE_VAL_SHIFT;
1050 seq_printf(s, "(%d)", val);
1056 static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
1057 struct seq_file *s, unsigned group)
1061 static const struct pinconf_ops at91_pinconf_ops = {
1062 .pin_config_get = at91_pinconf_get,
1063 .pin_config_set = at91_pinconf_set,
1064 .pin_config_dbg_show = at91_pinconf_dbg_show,
1065 .pin_config_group_dbg_show = at91_pinconf_group_dbg_show,
1068 static struct pinctrl_desc at91_pinctrl_desc = {
1069 .pctlops = &at91_pctrl_ops,
1070 .pmxops = &at91_pmx_ops,
1071 .confops = &at91_pinconf_ops,
1072 .owner = THIS_MODULE,
1075 static const char *gpio_compat = "atmel,at91rm9200-gpio";
1077 static void at91_pinctrl_child_count(struct at91_pinctrl *info,
1078 struct device_node *np)
1080 struct device_node *child;
1082 for_each_child_of_node(np, child) {
1083 if (of_device_is_compatible(child, gpio_compat)) {
1084 if (of_device_is_available(child))
1085 info->nactive_banks++;
1088 info->ngroups += of_get_child_count(child);
1093 static int at91_pinctrl_mux_mask(struct at91_pinctrl *info,
1094 struct device_node *np)
1100 list = of_get_property(np, "atmel,mux-mask", &size);
1102 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1106 size /= sizeof(*list);
1107 if (!size || size % gpio_banks) {
1108 dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks);
1111 info->nmux = size / gpio_banks;
1113 info->mux_mask = devm_kcalloc(info->dev, size, sizeof(u32),
1115 if (!info->mux_mask)
1118 ret = of_property_read_u32_array(np, "atmel,mux-mask",
1119 info->mux_mask, size);
1121 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1125 static int at91_pinctrl_parse_groups(struct device_node *np,
1126 struct at91_pin_group *grp,
1127 struct at91_pinctrl *info, u32 index)
1129 struct at91_pmx_pin *pin;
1134 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
1136 /* Initialise group */
1137 grp->name = np->name;
1140 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
1141 * do sanity check and calculate pins number
1143 list = of_get_property(np, "atmel,pins", &size);
1144 /* we do not check return since it's safe node passed down */
1145 size /= sizeof(*list);
1146 if (!size || size % 4) {
1147 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1151 grp->npins = size / 4;
1152 pin = grp->pins_conf = devm_kcalloc(info->dev,
1154 sizeof(struct at91_pmx_pin),
1156 grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
1158 if (!grp->pins_conf || !grp->pins)
1161 for (i = 0, j = 0; i < size; i += 4, j++) {
1162 pin->bank = be32_to_cpu(*list++);
1163 pin->pin = be32_to_cpu(*list++);
1164 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
1165 pin->mux = be32_to_cpu(*list++);
1166 pin->conf = be32_to_cpu(*list++);
1168 at91_pin_dbg(info->dev, pin);
1175 static int at91_pinctrl_parse_functions(struct device_node *np,
1176 struct at91_pinctrl *info, u32 index)
1178 struct device_node *child;
1179 struct at91_pmx_func *func;
1180 struct at91_pin_group *grp;
1182 static u32 grp_index;
1185 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
1187 func = &info->functions[index];
1189 /* Initialise function */
1190 func->name = np->name;
1191 func->ngroups = of_get_child_count(np);
1192 if (func->ngroups == 0) {
1193 dev_err(info->dev, "no groups defined\n");
1196 func->groups = devm_kcalloc(info->dev,
1197 func->ngroups, sizeof(char *), GFP_KERNEL);
1201 for_each_child_of_node(np, child) {
1202 func->groups[i] = child->name;
1203 grp = &info->groups[grp_index++];
1204 ret = at91_pinctrl_parse_groups(child, grp, info, i++);
1214 static const struct of_device_id at91_pinctrl_of_match[] = {
1215 { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
1216 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
1217 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
1218 { .compatible = "microchip,sam9x60-pinctrl", .data = &sam9x60_ops },
1222 static int at91_pinctrl_probe_dt(struct platform_device *pdev,
1223 struct at91_pinctrl *info)
1228 struct device_node *np = pdev->dev.of_node;
1229 struct device_node *child;
1234 info->dev = &pdev->dev;
1235 info->ops = (struct at91_pinctrl_mux_ops *)
1236 of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
1237 at91_pinctrl_child_count(info, np);
1239 if (gpio_banks < 1) {
1240 dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n");
1244 ret = at91_pinctrl_mux_mask(info, np);
1248 dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
1250 dev_dbg(&pdev->dev, "mux-mask\n");
1251 tmp = info->mux_mask;
1252 for (i = 0; i < gpio_banks; i++) {
1253 for (j = 0; j < info->nmux; j++, tmp++) {
1254 dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
1258 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1259 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1260 info->functions = devm_kcalloc(&pdev->dev,
1262 sizeof(struct at91_pmx_func),
1264 if (!info->functions)
1267 info->groups = devm_kcalloc(&pdev->dev,
1269 sizeof(struct at91_pin_group),
1274 dev_dbg(&pdev->dev, "nbanks = %d\n", gpio_banks);
1275 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1276 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1280 for_each_child_of_node(np, child) {
1281 if (of_device_is_compatible(child, gpio_compat))
1283 ret = at91_pinctrl_parse_functions(child, info, i++);
1285 dev_err(&pdev->dev, "failed to parse function\n");
1294 static int at91_pinctrl_probe(struct platform_device *pdev)
1296 struct at91_pinctrl *info;
1297 struct pinctrl_pin_desc *pdesc;
1298 int ret, i, j, k, ngpio_chips_enabled = 0;
1300 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1304 ret = at91_pinctrl_probe_dt(pdev, info);
1309 * We need all the GPIO drivers to probe FIRST, or we will not be able
1310 * to obtain references to the struct gpio_chip * for them, and we
1311 * need this to proceed.
1313 for (i = 0; i < gpio_banks; i++)
1315 ngpio_chips_enabled++;
1317 if (ngpio_chips_enabled < info->nactive_banks) {
1318 dev_warn(&pdev->dev,
1319 "All GPIO chips are not registered yet (%d/%d)\n",
1320 ngpio_chips_enabled, info->nactive_banks);
1321 devm_kfree(&pdev->dev, info);
1322 return -EPROBE_DEFER;
1325 at91_pinctrl_desc.name = dev_name(&pdev->dev);
1326 at91_pinctrl_desc.npins = gpio_banks * MAX_NB_GPIO_PER_BANK;
1327 at91_pinctrl_desc.pins = pdesc =
1328 devm_kcalloc(&pdev->dev,
1329 at91_pinctrl_desc.npins, sizeof(*pdesc),
1332 if (!at91_pinctrl_desc.pins)
1335 for (i = 0, k = 0; i < gpio_banks; i++) {
1336 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
1338 pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
1343 platform_set_drvdata(pdev, info);
1344 info->pctl = devm_pinctrl_register(&pdev->dev, &at91_pinctrl_desc,
1347 if (IS_ERR(info->pctl)) {
1348 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
1349 return PTR_ERR(info->pctl);
1352 /* We will handle a range of GPIO pins */
1353 for (i = 0; i < gpio_banks; i++)
1355 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
1357 dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
1362 static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1364 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1365 void __iomem *pio = at91_gpio->regbase;
1366 unsigned mask = 1 << offset;
1369 osr = readl_relaxed(pio + PIO_OSR);
1370 return !(osr & mask);
1373 static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1375 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1376 void __iomem *pio = at91_gpio->regbase;
1377 unsigned mask = 1 << offset;
1379 writel_relaxed(mask, pio + PIO_ODR);
1383 static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
1385 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1386 void __iomem *pio = at91_gpio->regbase;
1387 unsigned mask = 1 << offset;
1390 pdsr = readl_relaxed(pio + PIO_PDSR);
1391 return (pdsr & mask) != 0;
1394 static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
1397 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1398 void __iomem *pio = at91_gpio->regbase;
1399 unsigned mask = 1 << offset;
1401 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1404 static void at91_gpio_set_multiple(struct gpio_chip *chip,
1405 unsigned long *mask, unsigned long *bits)
1407 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1408 void __iomem *pio = at91_gpio->regbase;
1410 #define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1))
1411 /* Mask additionally to ngpio as not all GPIO controllers have 32 pins */
1412 uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio);
1413 uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio);
1415 writel_relaxed(set_mask, pio + PIO_SODR);
1416 writel_relaxed(clear_mask, pio + PIO_CODR);
1419 static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1422 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1423 void __iomem *pio = at91_gpio->regbase;
1424 unsigned mask = 1 << offset;
1426 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1427 writel_relaxed(mask, pio + PIO_OER);
1432 #ifdef CONFIG_DEBUG_FS
1433 static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1437 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1438 void __iomem *pio = at91_gpio->regbase;
1440 for (i = 0; i < chip->ngpio; i++) {
1441 unsigned mask = pin_to_mask(i);
1442 const char *gpio_label;
1444 gpio_label = gpiochip_is_requested(chip, i);
1447 mode = at91_gpio->ops->get_periph(pio, mask);
1448 seq_printf(s, "[%s] GPIO%s%d: ",
1449 gpio_label, chip->label, i);
1450 if (mode == AT91_MUX_GPIO) {
1451 seq_printf(s, "[gpio] ");
1452 seq_printf(s, "%s ",
1453 readl_relaxed(pio + PIO_OSR) & mask ?
1454 "output" : "input");
1455 seq_printf(s, "%s\n",
1456 readl_relaxed(pio + PIO_PDSR) & mask ?
1459 seq_printf(s, "[periph %c]\n",
1465 #define at91_gpio_dbg_show NULL
1468 /* Several AIC controller irqs are dispatched through this GPIO handler.
1469 * To use any AT91_PIN_* as an externally triggered IRQ, first call
1470 * at91_set_gpio_input() then maybe enable its glitch filter.
1471 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1473 * First implementation always triggers on rising and falling edges
1474 * whereas the newer PIO3 can be additionally configured to trigger on
1475 * level, edge with any polarity.
1477 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1478 * configuring them with at91_set_a_periph() or at91_set_b_periph().
1479 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1482 static void gpio_irq_mask(struct irq_data *d)
1484 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1485 void __iomem *pio = at91_gpio->regbase;
1486 unsigned mask = 1 << d->hwirq;
1489 writel_relaxed(mask, pio + PIO_IDR);
1492 static void gpio_irq_unmask(struct irq_data *d)
1494 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1495 void __iomem *pio = at91_gpio->regbase;
1496 unsigned mask = 1 << d->hwirq;
1499 writel_relaxed(mask, pio + PIO_IER);
1502 static int gpio_irq_type(struct irq_data *d, unsigned type)
1506 case IRQ_TYPE_EDGE_BOTH:
1513 /* Alternate irq type for PIO3 support */
1514 static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1516 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1517 void __iomem *pio = at91_gpio->regbase;
1518 unsigned mask = 1 << d->hwirq;
1521 case IRQ_TYPE_EDGE_RISING:
1522 irq_set_handler_locked(d, handle_simple_irq);
1523 writel_relaxed(mask, pio + PIO_ESR);
1524 writel_relaxed(mask, pio + PIO_REHLSR);
1526 case IRQ_TYPE_EDGE_FALLING:
1527 irq_set_handler_locked(d, handle_simple_irq);
1528 writel_relaxed(mask, pio + PIO_ESR);
1529 writel_relaxed(mask, pio + PIO_FELLSR);
1531 case IRQ_TYPE_LEVEL_LOW:
1532 irq_set_handler_locked(d, handle_level_irq);
1533 writel_relaxed(mask, pio + PIO_LSR);
1534 writel_relaxed(mask, pio + PIO_FELLSR);
1536 case IRQ_TYPE_LEVEL_HIGH:
1537 irq_set_handler_locked(d, handle_level_irq);
1538 writel_relaxed(mask, pio + PIO_LSR);
1539 writel_relaxed(mask, pio + PIO_REHLSR);
1541 case IRQ_TYPE_EDGE_BOTH:
1543 * disable additional interrupt modes:
1544 * fall back to default behavior
1546 irq_set_handler_locked(d, handle_simple_irq);
1547 writel_relaxed(mask, pio + PIO_AIMDR);
1551 pr_warn("AT91: No type for GPIO irq offset %d\n", d->irq);
1555 /* enable additional interrupt modes */
1556 writel_relaxed(mask, pio + PIO_AIMER);
1561 static void gpio_irq_ack(struct irq_data *d)
1563 /* the interrupt is already cleared before by reading ISR */
1568 static u32 wakeups[MAX_GPIO_BANKS];
1569 static u32 backups[MAX_GPIO_BANKS];
1571 static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
1573 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1574 unsigned bank = at91_gpio->pioc_idx;
1575 unsigned mask = 1 << d->hwirq;
1577 if (unlikely(bank >= MAX_GPIO_BANKS))
1581 wakeups[bank] |= mask;
1583 wakeups[bank] &= ~mask;
1585 irq_set_irq_wake(at91_gpio->pioc_virq, state);
1590 void at91_pinctrl_gpio_suspend(void)
1594 for (i = 0; i < gpio_banks; i++) {
1600 pio = gpio_chips[i]->regbase;
1602 backups[i] = readl_relaxed(pio + PIO_IMR);
1603 writel_relaxed(backups[i], pio + PIO_IDR);
1604 writel_relaxed(wakeups[i], pio + PIO_IER);
1607 clk_disable_unprepare(gpio_chips[i]->clock);
1609 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n",
1614 void at91_pinctrl_gpio_resume(void)
1618 for (i = 0; i < gpio_banks; i++) {
1624 pio = gpio_chips[i]->regbase;
1627 clk_prepare_enable(gpio_chips[i]->clock);
1629 writel_relaxed(wakeups[i], pio + PIO_IDR);
1630 writel_relaxed(backups[i], pio + PIO_IER);
1635 #define gpio_irq_set_wake NULL
1636 #endif /* CONFIG_PM */
1638 static void gpio_irq_handler(struct irq_desc *desc)
1640 struct irq_chip *chip = irq_desc_get_chip(desc);
1641 struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc);
1642 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(gpio_chip);
1643 void __iomem *pio = at91_gpio->regbase;
1647 chained_irq_enter(chip, desc);
1649 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
1650 * When there are none pending, we're finished unless we need
1651 * to process multiple banks (like ID_PIOCDE on sam9263).
1653 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
1655 if (!at91_gpio->next)
1657 at91_gpio = at91_gpio->next;
1658 pio = at91_gpio->regbase;
1659 gpio_chip = &at91_gpio->chip;
1663 for_each_set_bit(n, &isr, BITS_PER_LONG) {
1664 generic_handle_irq(irq_find_mapping(
1665 gpio_chip->irq.domain, n));
1668 chained_irq_exit(chip, desc);
1669 /* now it may re-trigger */
1672 static int at91_gpio_of_irq_setup(struct platform_device *pdev,
1673 struct at91_gpio_chip *at91_gpio)
1675 struct gpio_chip *gpiochip_prev = NULL;
1676 struct at91_gpio_chip *prev = NULL;
1677 struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq);
1678 struct irq_chip *gpio_irqchip;
1681 gpio_irqchip = devm_kzalloc(&pdev->dev, sizeof(*gpio_irqchip), GFP_KERNEL);
1685 at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1687 gpio_irqchip->name = "GPIO";
1688 gpio_irqchip->irq_ack = gpio_irq_ack;
1689 gpio_irqchip->irq_disable = gpio_irq_mask;
1690 gpio_irqchip->irq_mask = gpio_irq_mask;
1691 gpio_irqchip->irq_unmask = gpio_irq_unmask;
1692 gpio_irqchip->irq_set_wake = gpio_irq_set_wake,
1693 gpio_irqchip->irq_set_type = at91_gpio->ops->irq_type;
1695 /* Disable irqs of this PIO controller */
1696 writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
1699 * Let the generic code handle this edge IRQ, the the chained
1700 * handler will perform the actual work of handling the parent
1703 ret = gpiochip_irqchip_add(&at91_gpio->chip,
1709 dev_err(&pdev->dev, "at91_gpio.%d: Couldn't add irqchip to gpiochip.\n",
1710 at91_gpio->pioc_idx);
1714 /* The top level handler handles one bank of GPIOs, except
1715 * on some SoC it can handle up to three...
1716 * We only set up the handler for the first of the list.
1718 gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq);
1719 if (!gpiochip_prev) {
1720 /* Then register the chain on the parent IRQ */
1721 gpiochip_set_chained_irqchip(&at91_gpio->chip,
1723 at91_gpio->pioc_virq,
1728 prev = gpiochip_get_data(gpiochip_prev);
1730 /* we can only have 2 banks before */
1731 for (i = 0; i < 2; i++) {
1735 prev->next = at91_gpio;
1743 /* This structure is replicated for each GPIO block allocated at probe time */
1744 static const struct gpio_chip at91_gpio_template = {
1745 .request = gpiochip_generic_request,
1746 .free = gpiochip_generic_free,
1747 .get_direction = at91_gpio_get_direction,
1748 .direction_input = at91_gpio_direction_input,
1749 .get = at91_gpio_get,
1750 .direction_output = at91_gpio_direction_output,
1751 .set = at91_gpio_set,
1752 .set_multiple = at91_gpio_set_multiple,
1753 .dbg_show = at91_gpio_dbg_show,
1755 .ngpio = MAX_NB_GPIO_PER_BANK,
1758 static const struct of_device_id at91_gpio_of_match[] = {
1759 { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1760 { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1761 { .compatible = "microchip,sam9x60-gpio", .data = &sam9x60_ops },
1765 static int at91_gpio_probe(struct platform_device *pdev)
1767 struct device_node *np = pdev->dev.of_node;
1768 struct resource *res;
1769 struct at91_gpio_chip *at91_chip = NULL;
1770 struct gpio_chip *chip;
1771 struct pinctrl_gpio_range *range;
1774 int alias_idx = of_alias_get_id(np, "gpio");
1778 BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
1779 if (gpio_chips[alias_idx]) {
1784 irq = platform_get_irq(pdev, 0);
1790 at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL);
1796 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1797 at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res);
1798 if (IS_ERR(at91_chip->regbase)) {
1799 ret = PTR_ERR(at91_chip->regbase);
1803 at91_chip->ops = (struct at91_pinctrl_mux_ops *)
1804 of_match_device(at91_gpio_of_match, &pdev->dev)->data;
1805 at91_chip->pioc_virq = irq;
1806 at91_chip->pioc_idx = alias_idx;
1808 at91_chip->clock = devm_clk_get(&pdev->dev, NULL);
1809 if (IS_ERR(at91_chip->clock)) {
1810 dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
1811 ret = PTR_ERR(at91_chip->clock);
1815 ret = clk_prepare_enable(at91_chip->clock);
1817 dev_err(&pdev->dev, "failed to prepare and enable clock, ignoring.\n");
1818 goto clk_enable_err;
1821 at91_chip->chip = at91_gpio_template;
1823 chip = &at91_chip->chip;
1825 chip->label = dev_name(&pdev->dev);
1826 chip->parent = &pdev->dev;
1827 chip->owner = THIS_MODULE;
1828 chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
1830 if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
1831 if (ngpio >= MAX_NB_GPIO_PER_BANK)
1832 pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1833 alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
1835 chip->ngpio = ngpio;
1838 names = devm_kcalloc(&pdev->dev, chip->ngpio, sizeof(char *),
1843 goto clk_enable_err;
1846 for (i = 0; i < chip->ngpio; i++)
1847 names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i);
1849 chip->names = (const char *const *)names;
1851 range = &at91_chip->range;
1852 range->name = chip->label;
1853 range->id = alias_idx;
1854 range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
1856 range->npins = chip->ngpio;
1859 ret = gpiochip_add_data(chip, at91_chip);
1861 goto gpiochip_add_err;
1863 gpio_chips[alias_idx] = at91_chip;
1864 gpio_banks = max(gpio_banks, alias_idx + 1);
1866 ret = at91_gpio_of_irq_setup(pdev, at91_chip);
1870 dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
1875 gpiochip_remove(chip);
1878 clk_disable_unprepare(at91_chip->clock);
1880 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
1885 static struct platform_driver at91_gpio_driver = {
1887 .name = "gpio-at91",
1888 .of_match_table = at91_gpio_of_match,
1890 .probe = at91_gpio_probe,
1893 static struct platform_driver at91_pinctrl_driver = {
1895 .name = "pinctrl-at91",
1896 .of_match_table = at91_pinctrl_of_match,
1898 .probe = at91_pinctrl_probe,
1901 static struct platform_driver * const drivers[] = {
1903 &at91_pinctrl_driver,
1906 static int __init at91_pinctrl_init(void)
1908 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
1910 arch_initcall(at91_pinctrl_init);