drivers/pinctrl/pinctrl-rockchip.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  *
   4  * Copyright (c) 2013 MundoReader S.L.
   5  * Author: Heiko Stuebner <heiko@sntech.de>
   6  *
   7  * With some ideas taken from pinctrl-samsung:
   8  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   9  *              http://www.samsung.com
  10  * Copyright (c) 2012 Linaro Ltd
  11  *              http://www.linaro.org
  12  *
  13  * and pinctrl-at91:
  14  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as published
  18  * by the Free Software Foundation.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #include <linux/init.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/io.h>
  29 #include <linux/bitops.h>
  30 #include <linux/gpio.h>
  31 #include <linux/of_address.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/pinctrl/machine.h>
  34 #include <linux/pinctrl/pinconf.h>
  35 #include <linux/pinctrl/pinctrl.h>
  36 #include <linux/pinctrl/pinmux.h>
  37 #include <linux/pinctrl/pinconf-generic.h>
  38 #include <linux/irqchip/chained_irq.h>
  39 #include <linux/clk.h>
  40 #include <linux/regmap.h>
  41 #include <linux/mfd/syscon.h>
  42 #include <dt-bindings/pinctrl/rockchip.h>
  43
  44 #include "core.h"
  45 #include "pinconf.h"
  46
  47 /* GPIO control registers */
  48 #define GPIO_SWPORT_DR          0x00
  49 #define GPIO_SWPORT_DDR         0x04
  50 #define GPIO_INTEN              0x30
  51 #define GPIO_INTMASK            0x34
  52 #define GPIO_INTTYPE_LEVEL      0x38
  53 #define GPIO_INT_POLARITY       0x3c
  54 #define GPIO_INT_STATUS         0x40
  55 #define GPIO_INT_RAWSTATUS      0x44
  56 #define GPIO_DEBOUNCE           0x48
  57 #define GPIO_PORTS_EOI          0x4c
  58 #define GPIO_EXT_PORT           0x50
  59 #define GPIO_LS_SYNC            0x60
  60
  61 enum rockchip_pinctrl_type {
  62         RV1108,
  63         RK2928,
  64         RK3066B,
  65         RK3128,
  66         RK3188,
  67         RK3288,
  68         RK3368,
  69         RK3399,
  70 };
  71
  72 /**
  73  * Encode variants of iomux registers into a type variable
  74  */
  75 #define IOMUX_GPIO_ONLY         BIT(0)
  76 #define IOMUX_WIDTH_4BIT        BIT(1)
  77 #define IOMUX_SOURCE_PMU        BIT(2)
  78 #define IOMUX_UNROUTED          BIT(3)
  79 #define IOMUX_WIDTH_3BIT        BIT(4)
  80
  81 /**
  82  * @type: iomux variant using IOMUX_* constants
  83  * @offset: if initialized to -1 it will be autocalculated, by specifying
  84  *          an initial offset value the relevant source offset can be reset
  85  *          to a new value for autocalculating the following iomux registers.
  86  */
  87 struct rockchip_iomux {
  88         int                             type;
  89         int                             offset;
  90 };
  91
  92 /**
  93  * enum type index corresponding to rockchip_perpin_drv_list arrays index.
  94  */
  95 enum rockchip_pin_drv_type {
  96         DRV_TYPE_IO_DEFAULT = 0,
  97         DRV_TYPE_IO_1V8_OR_3V0,
  98         DRV_TYPE_IO_1V8_ONLY,
  99         DRV_TYPE_IO_1V8_3V0_AUTO,
 100         DRV_TYPE_IO_3V3_ONLY,
 101         DRV_TYPE_MAX
 102 };
 103
 104 /**
 105  * enum type index corresponding to rockchip_pull_list arrays index.
 106  */
 107 enum rockchip_pin_pull_type {
 108         PULL_TYPE_IO_DEFAULT = 0,
 109         PULL_TYPE_IO_1V8_ONLY,
 110         PULL_TYPE_MAX
 111 };
 112
 113 /**
 114  * @drv_type: drive strength variant using rockchip_perpin_drv_type
 115  * @offset: if initialized to -1 it will be autocalculated, by specifying
 116  *          an initial offset value the relevant source offset can be reset
 117  *          to a new value for autocalculating the following drive strength
 118  *          registers. if used chips own cal_drv func instead to calculate
 119  *          registers offset, the variant could be ignored.
 120  */
 121 struct rockchip_drv {
 122         enum rockchip_pin_drv_type      drv_type;
 123         int                             offset;
 124 };
 125
 126 /**
 127  * @reg_base: register base of the gpio bank
 128  * @reg_pull: optional separate register for additional pull settings
 129  * @clk: clock of the gpio bank
 130  * @irq: interrupt of the gpio bank
 131  * @saved_masks: Saved content of GPIO_INTEN at suspend time.
 132  * @pin_base: first pin number
 133  * @nr_pins: number of pins in this bank
 134  * @name: name of the bank
 135  * @bank_num: number of the bank, to account for holes
 136  * @iomux: array describing the 4 iomux sources of the bank
 137  * @drv: array describing the 4 drive strength sources of the bank
 138  * @pull_type: array describing the 4 pull type sources of the bank
 139  * @valid: is all necessary information present
 140  * @of_node: dt node of this bank
 141  * @drvdata: common pinctrl basedata
 142  * @domain: irqdomain of the gpio bank
 143  * @gpio_chip: gpiolib chip
 144  * @grange: gpio range
 145  * @slock: spinlock for the gpio bank
 146  * @route_mask: bits describing the routing pins of per bank
 147  */
 148 struct rockchip_pin_bank {
 149         void __iomem                    *reg_base;
 150         struct regmap                   *regmap_pull;
 151         struct clk                      *clk;
 152         int                             irq;
 153         u32                             saved_masks;
 154         u32                             pin_base;
 155         u8                              nr_pins;
 156         char                            *name;
 157         u8                              bank_num;
 158         struct rockchip_iomux           iomux[4];
 159         struct rockchip_drv             drv[4];
 160         enum rockchip_pin_pull_type     pull_type[4];
 161         bool                            valid;
 162         struct device_node              *of_node;
 163         struct rockchip_pinctrl         *drvdata;
 164         struct irq_domain               *domain;
 165         struct gpio_chip                gpio_chip;
 166         struct pinctrl_gpio_range       grange;
 167         raw_spinlock_t                  slock;
 168         u32                             toggle_edge_mode;
 169         u32                             recalced_mask;
 170         u32                             route_mask;
 171 };
 172
 173 #define PIN_BANK(id, pins, label)                       \
 174         {                                               \
 175                 .bank_num       = id,                   \
 176                 .nr_pins        = pins,                 \
 177                 .name           = label,                \
 178                 .iomux          = {                     \
 179                         { .offset = -1 },               \
 180                         { .offset = -1 },               \
 181                         { .offset = -1 },               \
 182                         { .offset = -1 },               \
 183                 },                                      \
 184         }
 185
 186 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
 187         {                                                               \
 188                 .bank_num       = id,                                   \
 189                 .nr_pins        = pins,                                 \
 190                 .name           = label,                                \
 191                 .iomux          = {                                     \
 192                         { .type = iom0, .offset = -1 },                 \
 193                         { .type = iom1, .offset = -1 },                 \
 194                         { .type = iom2, .offset = -1 },                 \
 195                         { .type = iom3, .offset = -1 },                 \
 196                 },                                                      \
 197         }
 198
 199 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
 200         {                                                               \
 201                 .bank_num       = id,                                   \
 202                 .nr_pins        = pins,                                 \
 203                 .name           = label,                                \
 204                 .iomux          = {                                     \
 205                         { .offset = -1 },                               \
 206                         { .offset = -1 },                               \
 207                         { .offset = -1 },                               \
 208                         { .offset = -1 },                               \
 209                 },                                                      \
 210                 .drv            = {                                     \
 211                         { .drv_type = type0, .offset = -1 },            \
 212                         { .drv_type = type1, .offset = -1 },            \
 213                         { .drv_type = type2, .offset = -1 },            \
 214                         { .drv_type = type3, .offset = -1 },            \
 215                 },                                                      \
 216         }
 217
 218 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1,      \
 219                                       drv2, drv3, pull0, pull1,         \
 220                                       pull2, pull3)                     \
 221         {                                                               \
 222                 .bank_num       = id,                                   \
 223                 .nr_pins        = pins,                                 \
 224                 .name           = label,                                \
 225                 .iomux          = {                                     \
 226                         { .offset = -1 },                               \
 227                         { .offset = -1 },                               \
 228                         { .offset = -1 },                               \
 229                         { .offset = -1 },                               \
 230                 },                                                      \
 231                 .drv            = {                                     \
 232                         { .drv_type = drv0, .offset = -1 },             \
 233                         { .drv_type = drv1, .offset = -1 },             \
 234                         { .drv_type = drv2, .offset = -1 },             \
 235                         { .drv_type = drv3, .offset = -1 },             \
 236                 },                                                      \
 237                 .pull_type[0] = pull0,                                  \
 238                 .pull_type[1] = pull1,                                  \
 239                 .pull_type[2] = pull2,                                  \
 240                 .pull_type[3] = pull3,                                  \
 241         }
 242
 243 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1,    \
 244                                         iom2, iom3, drv0, drv1, drv2,   \
 245                                         drv3, offset0, offset1,         \
 246                                         offset2, offset3)               \
 247         {                                                               \
 248                 .bank_num       = id,                                   \
 249                 .nr_pins        = pins,                                 \
 250                 .name           = label,                                \
 251                 .iomux          = {                                     \
 252                         { .type = iom0, .offset = -1 },                 \
 253                         { .type = iom1, .offset = -1 },                 \
 254                         { .type = iom2, .offset = -1 },                 \
 255                         { .type = iom3, .offset = -1 },                 \
 256                 },                                                      \
 257                 .drv            = {                                     \
 258                         { .drv_type = drv0, .offset = offset0 },        \
 259                         { .drv_type = drv1, .offset = offset1 },        \
 260                         { .drv_type = drv2, .offset = offset2 },        \
 261                         { .drv_type = drv3, .offset = offset3 },        \
 262                 },                                                      \
 263         }
 264
 265 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins,      \
 266                                               label, iom0, iom1, iom2,  \
 267                                               iom3, drv0, drv1, drv2,   \
 268                                               drv3, offset0, offset1,   \
 269                                               offset2, offset3, pull0,  \
 270                                               pull1, pull2, pull3)      \
 271         {                                                               \
 272                 .bank_num       = id,                                   \
 273                 .nr_pins        = pins,                                 \
 274                 .name           = label,                                \
 275                 .iomux          = {                                     \
 276                         { .type = iom0, .offset = -1 },                 \
 277                         { .type = iom1, .offset = -1 },                 \
 278                         { .type = iom2, .offset = -1 },                 \
 279                         { .type = iom3, .offset = -1 },                 \
 280                 },                                                      \
 281                 .drv            = {                                     \
 282                         { .drv_type = drv0, .offset = offset0 },        \
 283                         { .drv_type = drv1, .offset = offset1 },        \
 284                         { .drv_type = drv2, .offset = offset2 },        \
 285                         { .drv_type = drv3, .offset = offset3 },        \
 286                 },                                                      \
 287                 .pull_type[0] = pull0,                                  \
 288                 .pull_type[1] = pull1,                                  \
 289                 .pull_type[2] = pull2,                                  \
 290                 .pull_type[3] = pull3,                                  \
 291         }
 292
 293 /**
 294  * struct rockchip_mux_recalced_data: represent a pin iomux data.
 295  * @num: bank number.
 296  * @pin: pin number.
 297  * @bit: index at register.
 298  * @reg: register offset.
 299  * @mask: mask bit
 300  */
 301 struct rockchip_mux_recalced_data {
 302         u8 num;
 303         u8 pin;
 304         u32 reg;
 305         u8 bit;
 306         u8 mask;
 307 };
 308
 309 /**
 310  * struct rockchip_mux_recalced_data: represent a pin iomux data.
 311  * @bank_num: bank number.
 312  * @pin: index at register or used to calc index.
 313  * @func: the min pin.
 314  * @route_offset: the max pin.
 315  * @route_val: the register offset.
 316  */
 317 struct rockchip_mux_route_data {
 318         u8 bank_num;
 319         u8 pin;
 320         u8 func;
 321         u32 route_offset;
 322         u32 route_val;
 323 };
 324
 325 /**
 326  */
 327 struct rockchip_pin_ctrl {
 328         struct rockchip_pin_bank        *pin_banks;
 329         u32                             nr_banks;
 330         u32                             nr_pins;
 331         char                            *label;
 332         enum rockchip_pinctrl_type      type;
 333         int                             grf_mux_offset;
 334         int                             pmu_mux_offset;
 335         int                             grf_drv_offset;
 336         int                             pmu_drv_offset;
 337         struct rockchip_mux_recalced_data *iomux_recalced;
 338         u32                             niomux_recalced;
 339         struct rockchip_mux_route_data *iomux_routes;
 340         u32                             niomux_routes;
 341
 342         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank,
 343                                     int pin_num, struct regmap **regmap,
 344                                     int *reg, u8 *bit);
 345         void    (*drv_calc_reg)(struct rockchip_pin_bank *bank,
 346                                     int pin_num, struct regmap **regmap,
 347                                     int *reg, u8 *bit);
 348         int     (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
 349                                     int pin_num, struct regmap **regmap,
 350                                     int *reg, u8 *bit);
 351 };
 352
 353 struct rockchip_pin_config {
 354         unsigned int            func;
 355         unsigned long           *configs;
 356         unsigned int            nconfigs;
 357 };
 358
 359 /**
 360  * struct rockchip_pin_group: represent group of pins of a pinmux function.
 361  * @name: name of the pin group, used to lookup the group.
 362  * @pins: the pins included in this group.
 363  * @npins: number of pins included in this group.
 364  * @func: the mux function number to be programmed when selected.
 365  * @configs: the config values to be set for each pin
 366  * @nconfigs: number of configs for each pin
 367  */
 368 struct rockchip_pin_group {
 369         const char                      *name;
 370         unsigned int                    npins;
 371         unsigned int                    *pins;
 372         struct rockchip_pin_config      *data;
 373 };
 374
 375 /**
 376  * struct rockchip_pmx_func: represent a pin function.
 377  * @name: name of the pin function, used to lookup the function.
 378  * @groups: one or more names of pin groups that provide this function.
 379  * @num_groups: number of groups included in @groups.
 380  */
 381 struct rockchip_pmx_func {
 382         const char              *name;
 383         const char              **groups;
 384         u8                      ngroups;
 385 };
 386
 387 struct rockchip_pinctrl {
 388         struct regmap                   *regmap_base;
 389         int                             reg_size;
 390         struct regmap                   *regmap_pull;
 391         struct regmap                   *regmap_pmu;
 392         struct device                   *dev;
 393         struct rockchip_pin_ctrl        *ctrl;
 394         struct pinctrl_desc             pctl;
 395         struct pinctrl_dev              *pctl_dev;
 396         struct rockchip_pin_group       *groups;
 397         unsigned int                    ngroups;
 398         struct rockchip_pmx_func        *functions;
 399         unsigned int                    nfunctions;
 400 };
 401
 402 static struct regmap_config rockchip_regmap_config = {
 403         .reg_bits = 32,
 404         .val_bits = 32,
 405         .reg_stride = 4,
 406 };
 407
 408 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
 409                                         const struct rockchip_pinctrl *info,
 410                                         const char *name)
 411 {
 412         int i;
 413
 414         for (i = 0; i < info->ngroups; i++) {
 415                 if (!strcmp(info->groups[i].name, name))
 416                         return &info->groups[i];
 417         }
 418
 419         return NULL;
 420 }
 421
 422 /*
 423  * given a pin number that is local to a pin controller, find out the pin bank
 424  * and the register base of the pin bank.
 425  */
 426 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 427                                                                 unsigned pin)
 428 {
 429         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 430
 431         while (pin >= (b->pin_base + b->nr_pins))
 432                 b++;
 433
 434         return b;
 435 }
 436
 437 static struct rockchip_pin_bank *bank_num_to_bank(
 438                                         struct rockchip_pinctrl *info,
 439                                         unsigned num)
 440 {
 441         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 442         int i;
 443
 444         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 445                 if (b->bank_num == num)
 446                         return b;
 447         }
 448
 449         return ERR_PTR(-EINVAL);
 450 }
 451
 452 /*
 453  * Pinctrl_ops handling
 454  */
 455
 456 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 457 {
 458         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 459
 460         return info->ngroups;
 461 }
 462
 463 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 464                                                         unsigned selector)
 465 {
 466         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 467
 468         return info->groups[selector].name;
 469 }
 470
 471 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 472                                       unsigned selector, const unsigned **pins,
 473                                       unsigned *npins)
 474 {
 475         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 476
 477         if (selector >= info->ngroups)
 478                 return -EINVAL;
 479
 480         *pins = info->groups[selector].pins;
 481         *npins = info->groups[selector].npins;
 482
 483         return 0;
 484 }
 485
 486 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 487                                  struct device_node *np,
 488                                  struct pinctrl_map **map, unsigned *num_maps)
 489 {
 490         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 491         const struct rockchip_pin_group *grp;
 492         struct pinctrl_map *new_map;
 493         struct device_node *parent;
 494         int map_num = 1;
 495         int i;
 496
 497         /*
 498          * first find the group of this node and check if we need to create
 499          * config maps for pins
 500          */
 501         grp = pinctrl_name_to_group(info, np->name);
 502         if (!grp) {
 503                 dev_err(info->dev, "unable to find group for node %s\n",
 504                         np->name);
 505                 return -EINVAL;
 506         }
 507
 508         map_num += grp->npins;
 509         new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
 510                                                                 GFP_KERNEL);
 511         if (!new_map)
 512                 return -ENOMEM;
 513
 514         *map = new_map;
 515         *num_maps = map_num;
 516
 517         /* create mux map */
 518         parent = of_get_parent(np);
 519         if (!parent) {
 520                 devm_kfree(pctldev->dev, new_map);
 521                 return -EINVAL;
 522         }
 523         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 524         new_map[0].data.mux.function = parent->name;
 525         new_map[0].data.mux.group = np->name;
 526         of_node_put(parent);
 527
 528         /* create config map */
 529         new_map++;
 530         for (i = 0; i < grp->npins; i++) {
 531                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 532                 new_map[i].data.configs.group_or_pin =
 533                                 pin_get_name(pctldev, grp->pins[i]);
 534                 new_map[i].data.configs.configs = grp->data[i].configs;
 535                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 536         }
 537
 538         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 539                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 540
 541         return 0;
 542 }
 543
 544 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 545                                     struct pinctrl_map *map, unsigned num_maps)
 546 {
 547 }
 548
 549 static const struct pinctrl_ops rockchip_pctrl_ops = {
 550         .get_groups_count       = rockchip_get_groups_count,
 551         .get_group_name         = rockchip_get_group_name,
 552         .get_group_pins         = rockchip_get_group_pins,
 553         .dt_node_to_map         = rockchip_dt_node_to_map,
 554         .dt_free_map            = rockchip_dt_free_map,
 555 };
 556
 557 /*
 558  * Hardware access
 559  */
 560
 561 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
 562         {
 563                 .num = 1,
 564                 .pin = 0,
 565                 .reg = 0x418,
 566                 .bit = 0,
 567                 .mask = 0x3
 568         }, {
 569                 .num = 1,
 570                 .pin = 1,
 571                 .reg = 0x418,
 572                 .bit = 2,
 573                 .mask = 0x3
 574         }, {
 575                 .num = 1,
 576                 .pin = 2,
 577                 .reg = 0x418,
 578                 .bit = 4,
 579                 .mask = 0x3
 580         }, {
 581                 .num = 1,
 582                 .pin = 3,
 583                 .reg = 0x418,
 584                 .bit = 6,
 585                 .mask = 0x3
 586         }, {
 587                 .num = 1,
 588                 .pin = 4,
 589                 .reg = 0x418,
 590                 .bit = 8,
 591                 .mask = 0x3
 592         }, {
 593                 .num = 1,
 594                 .pin = 5,
 595                 .reg = 0x418,
 596                 .bit = 10,
 597                 .mask = 0x3
 598         }, {
 599                 .num = 1,
 600                 .pin = 6,
 601                 .reg = 0x418,
 602                 .bit = 12,
 603                 .mask = 0x3
 604         }, {
 605                 .num = 1,
 606                 .pin = 7,
 607                 .reg = 0x418,
 608                 .bit = 14,
 609                 .mask = 0x3
 610         }, {
 611                 .num = 1,
 612                 .pin = 8,
 613                 .reg = 0x41c,
 614                 .bit = 0,
 615                 .mask = 0x3
 616         }, {
 617                 .num = 1,
 618                 .pin = 9,
 619                 .reg = 0x41c,
 620                 .bit = 2,
 621                 .mask = 0x3
 622         },
 623 };
 624
 625 static  struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
 626         {
 627                 .num = 2,
 628                 .pin = 20,
 629                 .reg = 0xe8,
 630                 .bit = 0,
 631                 .mask = 0x7
 632         }, {
 633                 .num = 2,
 634                 .pin = 21,
 635                 .reg = 0xe8,
 636                 .bit = 4,
 637                 .mask = 0x7
 638         }, {
 639                 .num = 2,
 640                 .pin = 22,
 641                 .reg = 0xe8,
 642                 .bit = 8,
 643                 .mask = 0x7
 644         }, {
 645                 .num = 2,
 646                 .pin = 23,
 647                 .reg = 0xe8,
 648                 .bit = 12,
 649                 .mask = 0x7
 650         }, {
 651                 .num = 2,
 652                 .pin = 24,
 653                 .reg = 0xd4,
 654                 .bit = 12,
 655                 .mask = 0x7
 656         },
 657 };
 658
 659 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
 660         {
 661                 .num = 2,
 662                 .pin = 12,
 663                 .reg = 0x24,
 664                 .bit = 8,
 665                 .mask = 0x3
 666         }, {
 667                 .num = 2,
 668                 .pin = 15,
 669                 .reg = 0x28,
 670                 .bit = 0,
 671                 .mask = 0x7
 672         }, {
 673                 .num = 2,
 674                 .pin = 23,
 675                 .reg = 0x30,
 676                 .bit = 14,
 677                 .mask = 0x3
 678         },
 679 };
 680
 681 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
 682                                       int *reg, u8 *bit, int *mask)
 683 {
 684         struct rockchip_pinctrl *info = bank->drvdata;
 685         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 686         struct rockchip_mux_recalced_data *data;
 687         int i;
 688
 689         for (i = 0; i < ctrl->niomux_recalced; i++) {
 690                 data = &ctrl->iomux_recalced[i];
 691                 if (data->num == bank->bank_num &&
 692                     data->pin == pin)
 693                         break;
 694         }
 695
 696         if (i >= ctrl->niomux_recalced)
 697                 return;
 698
 699         *reg = data->reg;
 700         *mask = data->mask;
 701         *bit = data->bit;
 702 }
 703
 704 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
 705         {
 706                 /* spi-0 */
 707                 .bank_num = 1,
 708                 .pin = 10,
 709                 .func = 1,
 710                 .route_offset = 0x144,
 711                 .route_val = BIT(16 + 3) | BIT(16 + 4),
 712         }, {
 713                 /* spi-1 */
 714                 .bank_num = 1,
 715                 .pin = 27,
 716                 .func = 3,
 717                 .route_offset = 0x144,
 718                 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
 719         }, {
 720                 /* spi-2 */
 721                 .bank_num = 0,
 722                 .pin = 13,
 723                 .func = 2,
 724                 .route_offset = 0x144,
 725                 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
 726         }, {
 727                 /* i2s-0 */
 728                 .bank_num = 1,
 729                 .pin = 5,
 730                 .func = 1,
 731                 .route_offset = 0x144,
 732                 .route_val = BIT(16 + 5),
 733         }, {
 734                 /* i2s-1 */
 735                 .bank_num = 0,
 736                 .pin = 14,
 737                 .func = 1,
 738                 .route_offset = 0x144,
 739                 .route_val = BIT(16 + 5) | BIT(5),
 740         }, {
 741                 /* emmc-0 */
 742                 .bank_num = 1,
 743                 .pin = 22,
 744                 .func = 2,
 745                 .route_offset = 0x144,
 746                 .route_val = BIT(16 + 6),
 747         }, {
 748                 /* emmc-1 */
 749                 .bank_num = 2,
 750                 .pin = 4,
 751                 .func = 2,
 752                 .route_offset = 0x144,
 753                 .route_val = BIT(16 + 6) | BIT(6),
 754         },
 755 };
 756
 757 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
 758         {
 759                 /* pwm0-0 */
 760                 .bank_num = 0,
 761                 .pin = 26,
 762                 .func = 1,
 763                 .route_offset = 0x50,
 764                 .route_val = BIT(16),
 765         }, {
 766                 /* pwm0-1 */
 767                 .bank_num = 3,
 768                 .pin = 21,
 769                 .func = 1,
 770                 .route_offset = 0x50,
 771                 .route_val = BIT(16) | BIT(0),
 772         }, {
 773                 /* pwm1-0 */
 774                 .bank_num = 0,
 775                 .pin = 27,
 776                 .func = 1,
 777                 .route_offset = 0x50,
 778                 .route_val = BIT(16 + 1),
 779         }, {
 780                 /* pwm1-1 */
 781                 .bank_num = 0,
 782                 .pin = 30,
 783                 .func = 2,
 784                 .route_offset = 0x50,
 785                 .route_val = BIT(16 + 1) | BIT(1),
 786         }, {
 787                 /* pwm2-0 */
 788                 .bank_num = 0,
 789                 .pin = 28,
 790                 .func = 1,
 791                 .route_offset = 0x50,
 792                 .route_val = BIT(16 + 2),
 793         }, {
 794                 /* pwm2-1 */
 795                 .bank_num = 1,
 796                 .pin = 12,
 797                 .func = 2,
 798                 .route_offset = 0x50,
 799                 .route_val = BIT(16 + 2) | BIT(2),
 800         }, {
 801                 /* pwm3-0 */
 802                 .bank_num = 3,
 803                 .pin = 26,
 804                 .func = 1,
 805                 .route_offset = 0x50,
 806                 .route_val = BIT(16 + 3),
 807         }, {
 808                 /* pwm3-1 */
 809                 .bank_num = 1,
 810                 .pin = 11,
 811                 .func = 2,
 812                 .route_offset = 0x50,
 813                 .route_val = BIT(16 + 3) | BIT(3),
 814         }, {
 815                 /* sdio-0_d0 */
 816                 .bank_num = 1,
 817                 .pin = 1,
 818                 .func = 1,
 819                 .route_offset = 0x50,
 820                 .route_val = BIT(16 + 4),
 821         }, {
 822                 /* sdio-1_d0 */
 823                 .bank_num = 3,
 824                 .pin = 2,
 825                 .func = 1,
 826                 .route_offset = 0x50,
 827                 .route_val = BIT(16 + 4) | BIT(4),
 828         }, {
 829                 /* spi-0_rx */
 830                 .bank_num = 0,
 831                 .pin = 13,
 832                 .func = 2,
 833                 .route_offset = 0x50,
 834                 .route_val = BIT(16 + 5),
 835         }, {
 836                 /* spi-1_rx */
 837                 .bank_num = 2,
 838                 .pin = 0,
 839                 .func = 2,
 840                 .route_offset = 0x50,
 841                 .route_val = BIT(16 + 5) | BIT(5),
 842         }, {
 843                 /* emmc-0_cmd */
 844                 .bank_num = 1,
 845                 .pin = 22,
 846                 .func = 2,
 847                 .route_offset = 0x50,
 848                 .route_val = BIT(16 + 7),
 849         }, {
 850                 /* emmc-1_cmd */
 851                 .bank_num = 2,
 852                 .pin = 4,
 853                 .func = 2,
 854                 .route_offset = 0x50,
 855                 .route_val = BIT(16 + 7) | BIT(7),
 856         }, {
 857                 /* uart2-0_rx */
 858                 .bank_num = 1,
 859                 .pin = 19,
 860                 .func = 2,
 861                 .route_offset = 0x50,
 862                 .route_val = BIT(16 + 8),
 863         }, {
 864                 /* uart2-1_rx */
 865                 .bank_num = 1,
 866                 .pin = 10,
 867                 .func = 2,
 868                 .route_offset = 0x50,
 869                 .route_val = BIT(16 + 8) | BIT(8),
 870         }, {
 871                 /* uart1-0_rx */
 872                 .bank_num = 1,
 873                 .pin = 10,
 874                 .func = 1,
 875                 .route_offset = 0x50,
 876                 .route_val = BIT(16 + 11),
 877         }, {
 878                 /* uart1-1_rx */
 879                 .bank_num = 3,
 880                 .pin = 13,
 881                 .func = 1,
 882                 .route_offset = 0x50,
 883                 .route_val = BIT(16 + 11) | BIT(11),
 884         },
 885 };
 886
 887 static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
 888         {
 889                 /* edphdmi_cecinoutt1 */
 890                 .bank_num = 7,
 891                 .pin = 16,
 892                 .func = 2,
 893                 .route_offset = 0x264,
 894                 .route_val = BIT(16 + 12) | BIT(12),
 895         }, {
 896                 /* edphdmi_cecinout */
 897                 .bank_num = 7,
 898                 .pin = 23,
 899                 .func = 4,
 900                 .route_offset = 0x264,
 901                 .route_val = BIT(16 + 12),
 902         },
 903 };
 904
 905 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
 906         {
 907                 /* uart2dbg_rxm0 */
 908                 .bank_num = 1,
 909                 .pin = 1,
 910                 .func = 2,
 911                 .route_offset = 0x50,
 912                 .route_val = BIT(16) | BIT(16 + 1),
 913         }, {
 914                 /* uart2dbg_rxm1 */
 915                 .bank_num = 2,
 916                 .pin = 1,
 917                 .func = 1,
 918                 .route_offset = 0x50,
 919                 .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
 920         }, {
 921                 /* gmac-m1_rxd0 */
 922                 .bank_num = 1,
 923                 .pin = 11,
 924                 .func = 2,
 925                 .route_offset = 0x50,
 926                 .route_val = BIT(16 + 2) | BIT(2),
 927         }, {
 928                 /* gmac-m1-optimized_rxd3 */
 929                 .bank_num = 1,
 930                 .pin = 14,
 931                 .func = 2,
 932                 .route_offset = 0x50,
 933                 .route_val = BIT(16 + 10) | BIT(10),
 934         }, {
 935                 /* pdm_sdi0m0 */
 936                 .bank_num = 2,
 937                 .pin = 19,
 938                 .func = 2,
 939                 .route_offset = 0x50,
 940                 .route_val = BIT(16 + 3),
 941         }, {
 942                 /* pdm_sdi0m1 */
 943                 .bank_num = 1,
 944                 .pin = 23,
 945                 .func = 3,
 946                 .route_offset = 0x50,
 947                 .route_val =  BIT(16 + 3) | BIT(3),
 948         }, {
 949                 /* spi_rxdm2 */
 950                 .bank_num = 3,
 951                 .pin = 2,
 952                 .func = 4,
 953                 .route_offset = 0x50,
 954                 .route_val =  BIT(16 + 4) | BIT(16 + 5) | BIT(5),
 955         }, {
 956                 /* i2s2_sdim0 */
 957                 .bank_num = 1,
 958                 .pin = 24,
 959                 .func = 1,
 960                 .route_offset = 0x50,
 961                 .route_val = BIT(16 + 6),
 962         }, {
 963                 /* i2s2_sdim1 */
 964                 .bank_num = 3,
 965                 .pin = 2,
 966                 .func = 6,
 967                 .route_offset = 0x50,
 968                 .route_val =  BIT(16 + 6) | BIT(6),
 969         }, {
 970                 /* card_iom1 */
 971                 .bank_num = 2,
 972                 .pin = 22,
 973                 .func = 3,
 974                 .route_offset = 0x50,
 975                 .route_val =  BIT(16 + 7) | BIT(7),
 976         }, {
 977                 /* tsp_d5m1 */
 978                 .bank_num = 2,
 979                 .pin = 16,
 980                 .func = 3,
 981                 .route_offset = 0x50,
 982                 .route_val =  BIT(16 + 8) | BIT(8),
 983         }, {
 984                 /* cif_data5m1 */
 985                 .bank_num = 2,
 986                 .pin = 16,
 987                 .func = 4,
 988                 .route_offset = 0x50,
 989                 .route_val =  BIT(16 + 9) | BIT(9),
 990         },
 991 };
 992
 993 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
 994         {
 995                 /* uart2dbga_rx */
 996                 .bank_num = 4,
 997                 .pin = 8,
 998                 .func = 2,
 999                 .route_offset = 0xe21c,
1000                 .route_val = BIT(16 + 10) | BIT(16 + 11),
1001         }, {
1002                 /* uart2dbgb_rx */
1003                 .bank_num = 4,
1004                 .pin = 16,
1005                 .func = 2,
1006                 .route_offset = 0xe21c,
1007                 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
1008         }, {
1009                 /* uart2dbgc_rx */
1010                 .bank_num = 4,
1011                 .pin = 19,
1012                 .func = 1,
1013                 .route_offset = 0xe21c,
1014                 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
1015         }, {
1016                 /* pcie_clkreqn */
1017                 .bank_num = 2,
1018                 .pin = 26,
1019                 .func = 2,
1020                 .route_offset = 0xe21c,
1021                 .route_val = BIT(16 + 14),
1022         }, {
1023                 /* pcie_clkreqnb */
1024                 .bank_num = 4,
1025                 .pin = 24,
1026                 .func = 1,
1027                 .route_offset = 0xe21c,
1028                 .route_val = BIT(16 + 14) | BIT(14),
1029         },
1030 };
1031
1032 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
1033                                    int mux, u32 *reg, u32 *value)
1034 {
1035         struct rockchip_pinctrl *info = bank->drvdata;
1036         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1037         struct rockchip_mux_route_data *data;
1038         int i;
1039
1040         for (i = 0; i < ctrl->niomux_routes; i++) {
1041                 data = &ctrl->iomux_routes[i];
1042                 if ((data->bank_num == bank->bank_num) &&
1043                     (data->pin == pin) && (data->func == mux))
1044                         break;
1045         }
1046
1047         if (i >= ctrl->niomux_routes)
1048                 return false;
1049
1050         *reg = data->route_offset;
1051         *value = data->route_val;
1052
1053         return true;
1054 }
1055
1056 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1057 {
1058         struct rockchip_pinctrl *info = bank->drvdata;
1059         int iomux_num = (pin / 8);
1060         struct regmap *regmap;
1061         unsigned int val;
1062         int reg, ret, mask, mux_type;
1063         u8 bit;
1064
1065         if (iomux_num > 3)
1066                 return -EINVAL;
1067
1068         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1069                 dev_err(info->dev, "pin %d is unrouted\n", pin);
1070                 return -EINVAL;
1071         }
1072
1073         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1074                 return RK_FUNC_GPIO;
1075
1076         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1077                                 ? info->regmap_pmu : info->regmap_base;
1078
1079         /* get basic quadrupel of mux registers and the correct reg inside */
1080         mux_type = bank->iomux[iomux_num].type;
1081         reg = bank->iomux[iomux_num].offset;
1082         if (mux_type & IOMUX_WIDTH_4BIT) {
1083                 if ((pin % 8) >= 4)
1084                         reg += 0x4;
1085                 bit = (pin % 4) * 4;
1086                 mask = 0xf;
1087         } else if (mux_type & IOMUX_WIDTH_3BIT) {
1088                 if ((pin % 8) >= 5)
1089                         reg += 0x4;
1090                 bit = (pin % 8 % 5) * 3;
1091                 mask = 0x7;
1092         } else {
1093                 bit = (pin % 8) * 2;
1094                 mask = 0x3;
1095         }
1096
1097         if (bank->recalced_mask & BIT(pin))
1098                 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
1099
1100         ret = regmap_read(regmap, reg, &val);
1101         if (ret)
1102                 return ret;
1103
1104         return ((val >> bit) & mask);
1105 }
1106
1107 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
1108                                int pin, int mux)
1109 {
1110         struct rockchip_pinctrl *info = bank->drvdata;
1111         int iomux_num = (pin / 8);
1112
1113         if (iomux_num > 3)
1114                 return -EINVAL;
1115
1116         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1117                 dev_err(info->dev, "pin %d is unrouted\n", pin);
1118                 return -EINVAL;
1119         }
1120
1121         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1122                 if (mux != RK_FUNC_GPIO) {
1123                         dev_err(info->dev,
1124                                 "pin %d only supports a gpio mux\n", pin);
1125                         return -ENOTSUPP;
1126                 }
1127         }
1128
1129         return 0;
1130 }
1131
1132 /*
1133  * Set a new mux function for a pin.
1134  *
1135  * The register is divided into the upper and lower 16 bit. When changing
1136  * a value, the previous register value is not read and changed. Instead
1137  * it seems the changed bits are marked in the upper 16 bit, while the
1138  * changed value gets set in the same offset in the lower 16 bit.
1139  * All pin settings seem to be 2 bit wide in both the upper and lower
1140  * parts.
1141  * @bank: pin bank to change
1142  * @pin: pin to change
1143  * @mux: new mux function to set
1144  */
1145 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1146 {
1147         struct rockchip_pinctrl *info = bank->drvdata;
1148         int iomux_num = (pin / 8);
1149         struct regmap *regmap;
1150         int reg, ret, mask, mux_type;
1151         u8 bit;
1152         u32 data, rmask, route_reg, route_val;
1153
1154         ret = rockchip_verify_mux(bank, pin, mux);
1155         if (ret < 0)
1156                 return ret;
1157
1158         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1159                 return 0;
1160
1161         dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
1162                                                 bank->bank_num, pin, mux);
1163
1164         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1165                                 ? info->regmap_pmu : info->regmap_base;
1166
1167         /* get basic quadrupel of mux registers and the correct reg inside */
1168         mux_type = bank->iomux[iomux_num].type;
1169         reg = bank->iomux[iomux_num].offset;
1170         if (mux_type & IOMUX_WIDTH_4BIT) {
1171                 if ((pin % 8) >= 4)
1172                         reg += 0x4;
1173                 bit = (pin % 4) * 4;
1174                 mask = 0xf;
1175         } else if (mux_type & IOMUX_WIDTH_3BIT) {
1176                 if ((pin % 8) >= 5)
1177                         reg += 0x4;
1178                 bit = (pin % 8 % 5) * 3;
1179                 mask = 0x7;
1180         } else {
1181                 bit = (pin % 8) * 2;
1182                 mask = 0x3;
1183         }
1184
1185         if (bank->recalced_mask & BIT(pin))
1186                 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
1187
1188         if (bank->route_mask & BIT(pin)) {
1189                 if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
1190                                            &route_val)) {
1191                         ret = regmap_write(regmap, route_reg, route_val);
1192                         if (ret)
1193                                 return ret;
1194                 }
1195         }
1196
1197         data = (mask << (bit + 16));
1198         rmask = data | (data >> 16);
1199         data |= (mux & mask) << bit;
1200         ret = regmap_update_bits(regmap, reg, rmask, data);
1201
1202         return ret;
1203 }
1204
1205 #define RV1108_PULL_PMU_OFFSET          0x10
1206 #define RV1108_PULL_OFFSET              0x110
1207 #define RV1108_PULL_PINS_PER_REG        8
1208 #define RV1108_PULL_BITS_PER_PIN        2
1209 #define RV1108_PULL_BANK_STRIDE         16
1210
1211 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1212                                          int pin_num, struct regmap **regmap,
1213                                          int *reg, u8 *bit)
1214 {
1215         struct rockchip_pinctrl *info = bank->drvdata;
1216
1217         /* The first 24 pins of the first bank are located in PMU */
1218         if (bank->bank_num == 0) {
1219                 *regmap = info->regmap_pmu;
1220                 *reg = RV1108_PULL_PMU_OFFSET;
1221         } else {
1222                 *reg = RV1108_PULL_OFFSET;
1223                 *regmap = info->regmap_base;
1224                 /* correct the offset, as we're starting with the 2nd bank */
1225                 *reg -= 0x10;
1226                 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1227         }
1228
1229         *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1230         *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1231         *bit *= RV1108_PULL_BITS_PER_PIN;
1232 }
1233
1234 #define RV1108_DRV_PMU_OFFSET           0x20
1235 #define RV1108_DRV_GRF_OFFSET           0x210
1236 #define RV1108_DRV_BITS_PER_PIN         2
1237 #define RV1108_DRV_PINS_PER_REG         8
1238 #define RV1108_DRV_BANK_STRIDE          16
1239
1240 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1241                                         int pin_num, struct regmap **regmap,
1242                                         int *reg, u8 *bit)
1243 {
1244         struct rockchip_pinctrl *info = bank->drvdata;
1245
1246         /* The first 24 pins of the first bank are located in PMU */
1247         if (bank->bank_num == 0) {
1248                 *regmap = info->regmap_pmu;
1249                 *reg = RV1108_DRV_PMU_OFFSET;
1250         } else {
1251                 *regmap = info->regmap_base;
1252                 *reg = RV1108_DRV_GRF_OFFSET;
1253
1254                 /* correct the offset, as we're starting with the 2nd bank */
1255                 *reg -= 0x10;
1256                 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1257         }
1258
1259         *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1260         *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1261         *bit *= RV1108_DRV_BITS_PER_PIN;
1262 }
1263
1264 #define RV1108_SCHMITT_PMU_OFFSET               0x30
1265 #define RV1108_SCHMITT_GRF_OFFSET               0x388
1266 #define RV1108_SCHMITT_BANK_STRIDE              8
1267 #define RV1108_SCHMITT_PINS_PER_GRF_REG         16
1268 #define RV1108_SCHMITT_PINS_PER_PMU_REG         8
1269
1270 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1271                                            int pin_num,
1272                                            struct regmap **regmap,
1273                                            int *reg, u8 *bit)
1274 {
1275         struct rockchip_pinctrl *info = bank->drvdata;
1276         int pins_per_reg;
1277
1278         if (bank->bank_num == 0) {
1279                 *regmap = info->regmap_pmu;
1280                 *reg = RV1108_SCHMITT_PMU_OFFSET;
1281                 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1282         } else {
1283                 *regmap = info->regmap_base;
1284                 *reg = RV1108_SCHMITT_GRF_OFFSET;
1285                 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1286                 *reg += (bank->bank_num  - 1) * RV1108_SCHMITT_BANK_STRIDE;
1287         }
1288         *reg += ((pin_num / pins_per_reg) * 4);
1289         *bit = pin_num % pins_per_reg;
1290
1291         return 0;
1292 }
1293
1294 #define RK2928_PULL_OFFSET              0x118
1295 #define RK2928_PULL_PINS_PER_REG        16
1296 #define RK2928_PULL_BANK_STRIDE         8
1297
1298 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1299                                     int pin_num, struct regmap **regmap,
1300                                     int *reg, u8 *bit)
1301 {
1302         struct rockchip_pinctrl *info = bank->drvdata;
1303
1304         *regmap = info->regmap_base;
1305         *reg = RK2928_PULL_OFFSET;
1306         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1307         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1308
1309         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1310 };
1311
1312 #define RK3128_PULL_OFFSET      0x118
1313
1314 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1315                                          int pin_num, struct regmap **regmap,
1316                                          int *reg, u8 *bit)
1317 {
1318         struct rockchip_pinctrl *info = bank->drvdata;
1319
1320         *regmap = info->regmap_base;
1321         *reg = RK3128_PULL_OFFSET;
1322         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1323         *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1324
1325         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1326 }
1327
1328 #define RK3188_PULL_OFFSET              0x164
1329 #define RK3188_PULL_BITS_PER_PIN        2
1330 #define RK3188_PULL_PINS_PER_REG        8
1331 #define RK3188_PULL_BANK_STRIDE         16
1332 #define RK3188_PULL_PMU_OFFSET          0x64
1333
1334 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1335                                     int pin_num, struct regmap **regmap,
1336                                     int *reg, u8 *bit)
1337 {
1338         struct rockchip_pinctrl *info = bank->drvdata;
1339
1340         /* The first 12 pins of the first bank are located elsewhere */
1341         if (bank->bank_num == 0 && pin_num < 12) {
1342                 *regmap = info->regmap_pmu ? info->regmap_pmu
1343                                            : bank->regmap_pull;
1344                 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
1345                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1346                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1347                 *bit *= RK3188_PULL_BITS_PER_PIN;
1348         } else {
1349                 *regmap = info->regmap_pull ? info->regmap_pull
1350                                             : info->regmap_base;
1351                 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1352
1353                 /* correct the offset, as it is the 2nd pull register */
1354                 *reg -= 4;
1355                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1356                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1357
1358                 /*
1359                  * The bits in these registers have an inverse ordering
1360                  * with the lowest pin being in bits 15:14 and the highest
1361                  * pin in bits 1:0
1362                  */
1363                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1364                 *bit *= RK3188_PULL_BITS_PER_PIN;
1365         }
1366 }
1367
1368 #define RK3288_PULL_OFFSET              0x140
1369 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1370                                     int pin_num, struct regmap **regmap,
1371                                     int *reg, u8 *bit)
1372 {
1373         struct rockchip_pinctrl *info = bank->drvdata;
1374
1375         /* The first 24 pins of the first bank are located in PMU */
1376         if (bank->bank_num == 0) {
1377                 *regmap = info->regmap_pmu;
1378                 *reg = RK3188_PULL_PMU_OFFSET;
1379
1380                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1381                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1382                 *bit *= RK3188_PULL_BITS_PER_PIN;
1383         } else {
1384                 *regmap = info->regmap_base;
1385                 *reg = RK3288_PULL_OFFSET;
1386
1387                 /* correct the offset, as we're starting with the 2nd bank */
1388                 *reg -= 0x10;
1389                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1390                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1391
1392                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1393                 *bit *= RK3188_PULL_BITS_PER_PIN;
1394         }
1395 }
1396
1397 #define RK3288_DRV_PMU_OFFSET           0x70
1398 #define RK3288_DRV_GRF_OFFSET           0x1c0
1399 #define RK3288_DRV_BITS_PER_PIN         2
1400 #define RK3288_DRV_PINS_PER_REG         8
1401 #define RK3288_DRV_BANK_STRIDE          16
1402
1403 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1404                                     int pin_num, struct regmap **regmap,
1405                                     int *reg, u8 *bit)
1406 {
1407         struct rockchip_pinctrl *info = bank->drvdata;
1408
1409         /* The first 24 pins of the first bank are located in PMU */
1410         if (bank->bank_num == 0) {
1411                 *regmap = info->regmap_pmu;
1412                 *reg = RK3288_DRV_PMU_OFFSET;
1413
1414                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1415                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1416                 *bit *= RK3288_DRV_BITS_PER_PIN;
1417         } else {
1418                 *regmap = info->regmap_base;
1419                 *reg = RK3288_DRV_GRF_OFFSET;
1420
1421                 /* correct the offset, as we're starting with the 2nd bank */
1422                 *reg -= 0x10;
1423                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1424                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1425
1426                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1427                 *bit *= RK3288_DRV_BITS_PER_PIN;
1428         }
1429 }
1430
1431 #define RK3228_PULL_OFFSET              0x100
1432
1433 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1434                                     int pin_num, struct regmap **regmap,
1435                                     int *reg, u8 *bit)
1436 {
1437         struct rockchip_pinctrl *info = bank->drvdata;
1438
1439         *regmap = info->regmap_base;
1440         *reg = RK3228_PULL_OFFSET;
1441         *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1442         *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1443
1444         *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1445         *bit *= RK3188_PULL_BITS_PER_PIN;
1446 }
1447
1448 #define RK3228_DRV_GRF_OFFSET           0x200
1449
1450 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1451                                     int pin_num, struct regmap **regmap,
1452                                     int *reg, u8 *bit)
1453 {
1454         struct rockchip_pinctrl *info = bank->drvdata;
1455
1456         *regmap = info->regmap_base;
1457         *reg = RK3228_DRV_GRF_OFFSET;
1458         *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1459         *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1460
1461         *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1462         *bit *= RK3288_DRV_BITS_PER_PIN;
1463 }
1464
1465 #define RK3368_PULL_GRF_OFFSET          0x100
1466 #define RK3368_PULL_PMU_OFFSET          0x10
1467
1468 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1469                                     int pin_num, struct regmap **regmap,
1470                                     int *reg, u8 *bit)
1471 {
1472         struct rockchip_pinctrl *info = bank->drvdata;
1473
1474         /* The first 32 pins of the first bank are located in PMU */
1475         if (bank->bank_num == 0) {
1476                 *regmap = info->regmap_pmu;
1477                 *reg = RK3368_PULL_PMU_OFFSET;
1478
1479                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1480                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1481                 *bit *= RK3188_PULL_BITS_PER_PIN;
1482         } else {
1483                 *regmap = info->regmap_base;
1484                 *reg = RK3368_PULL_GRF_OFFSET;
1485
1486                 /* correct the offset, as we're starting with the 2nd bank */
1487                 *reg -= 0x10;
1488                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1489                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1490
1491                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1492                 *bit *= RK3188_PULL_BITS_PER_PIN;
1493         }
1494 }
1495
1496 #define RK3368_DRV_PMU_OFFSET           0x20
1497 #define RK3368_DRV_GRF_OFFSET           0x200
1498
1499 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1500                                     int pin_num, struct regmap **regmap,
1501                                     int *reg, u8 *bit)
1502 {
1503         struct rockchip_pinctrl *info = bank->drvdata;
1504
1505         /* The first 32 pins of the first bank are located in PMU */
1506         if (bank->bank_num == 0) {
1507                 *regmap = info->regmap_pmu;
1508                 *reg = RK3368_DRV_PMU_OFFSET;
1509
1510                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1511                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1512                 *bit *= RK3288_DRV_BITS_PER_PIN;
1513         } else {
1514                 *regmap = info->regmap_base;
1515                 *reg = RK3368_DRV_GRF_OFFSET;
1516
1517                 /* correct the offset, as we're starting with the 2nd bank */
1518                 *reg -= 0x10;
1519                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1520                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1521
1522                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1523                 *bit *= RK3288_DRV_BITS_PER_PIN;
1524         }
1525 }
1526
1527 #define RK3399_PULL_GRF_OFFSET          0xe040
1528 #define RK3399_PULL_PMU_OFFSET          0x40
1529 #define RK3399_DRV_3BITS_PER_PIN        3
1530
1531 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1532                                          int pin_num, struct regmap **regmap,
1533                                          int *reg, u8 *bit)
1534 {
1535         struct rockchip_pinctrl *info = bank->drvdata;
1536
1537         /* The bank0:16 and bank1:32 pins are located in PMU */
1538         if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1539                 *regmap = info->regmap_pmu;
1540                 *reg = RK3399_PULL_PMU_OFFSET;
1541
1542                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1543
1544                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1545                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1546                 *bit *= RK3188_PULL_BITS_PER_PIN;
1547         } else {
1548                 *regmap = info->regmap_base;
1549                 *reg = RK3399_PULL_GRF_OFFSET;
1550
1551                 /* correct the offset, as we're starting with the 3rd bank */
1552                 *reg -= 0x20;
1553                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1554                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1555
1556                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1557                 *bit *= RK3188_PULL_BITS_PER_PIN;
1558         }
1559 }
1560
1561 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1562                                         int pin_num, struct regmap **regmap,
1563                                         int *reg, u8 *bit)
1564 {
1565         struct rockchip_pinctrl *info = bank->drvdata;
1566         int drv_num = (pin_num / 8);
1567
1568         /*  The bank0:16 and bank1:32 pins are located in PMU */
1569         if ((bank->bank_num == 0) || (bank->bank_num == 1))
1570                 *regmap = info->regmap_pmu;
1571         else
1572                 *regmap = info->regmap_base;
1573
1574         *reg = bank->drv[drv_num].offset;
1575         if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1576             (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1577                 *bit = (pin_num % 8) * 3;
1578         else
1579                 *bit = (pin_num % 8) * 2;
1580 }
1581
1582 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
1583         { 2, 4, 8, 12, -1, -1, -1, -1 },
1584         { 3, 6, 9, 12, -1, -1, -1, -1 },
1585         { 5, 10, 15, 20, -1, -1, -1, -1 },
1586         { 4, 6, 8, 10, 12, 14, 16, 18 },
1587         { 4, 7, 10, 13, 16, 19, 22, 26 }
1588 };
1589
1590 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
1591                                      int pin_num)
1592 {
1593         struct rockchip_pinctrl *info = bank->drvdata;
1594         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1595         struct regmap *regmap;
1596         int reg, ret;
1597         u32 data, temp, rmask_bits;
1598         u8 bit;
1599         int drv_type = bank->drv[pin_num / 8].drv_type;
1600
1601         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1602
1603         switch (drv_type) {
1604         case DRV_TYPE_IO_1V8_3V0_AUTO:
1605         case DRV_TYPE_IO_3V3_ONLY:
1606                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1607                 switch (bit) {
1608                 case 0 ... 12:
1609                         /* regular case, nothing to do */
1610                         break;
1611                 case 15:
1612                         /*
1613                          * drive-strength offset is special, as it is
1614                          * spread over 2 registers
1615                          */
1616                         ret = regmap_read(regmap, reg, &data);
1617                         if (ret)
1618                                 return ret;
1619
1620                         ret = regmap_read(regmap, reg + 0x4, &temp);
1621                         if (ret)
1622                                 return ret;
1623
1624                         /*
1625                          * the bit data[15] contains bit 0 of the value
1626                          * while temp[1:0] contains bits 2 and 1
1627                          */
1628                         data >>= 15;
1629                         temp &= 0x3;
1630                         temp <<= 1;
1631                         data |= temp;
1632
1633                         return rockchip_perpin_drv_list[drv_type][data];
1634                 case 18 ... 21:
1635                         /* setting fully enclosed in the second register */
1636                         reg += 4;
1637                         bit -= 16;
1638                         break;
1639                 default:
1640                         dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1641                                 bit, drv_type);
1642                         return -EINVAL;
1643                 }
1644
1645                 break;
1646         case DRV_TYPE_IO_DEFAULT:
1647         case DRV_TYPE_IO_1V8_OR_3V0:
1648         case DRV_TYPE_IO_1V8_ONLY:
1649                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1650                 break;
1651         default:
1652                 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1653                         drv_type);
1654                 return -EINVAL;
1655         }
1656
1657         ret = regmap_read(regmap, reg, &data);
1658         if (ret)
1659                 return ret;
1660
1661         data >>= bit;
1662         data &= (1 << rmask_bits) - 1;
1663
1664         return rockchip_perpin_drv_list[drv_type][data];
1665 }
1666
1667 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1668                                      int pin_num, int strength)
1669 {
1670         struct rockchip_pinctrl *info = bank->drvdata;
1671         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1672         struct regmap *regmap;
1673         int reg, ret, i;
1674         u32 data, rmask, rmask_bits, temp;
1675         u8 bit;
1676         int drv_type = bank->drv[pin_num / 8].drv_type;
1677
1678         dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
1679                 bank->bank_num, pin_num, strength);
1680
1681         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1682
1683         ret = -EINVAL;
1684         for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
1685                 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
1686                         ret = i;
1687                         break;
1688                 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1689                         ret = rockchip_perpin_drv_list[drv_type][i];
1690                         break;
1691                 }
1692         }
1693
1694         if (ret < 0) {
1695                 dev_err(info->dev, "unsupported driver strength %d\n",
1696                         strength);
1697                 return ret;
1698         }
1699
1700         switch (drv_type) {
1701         case DRV_TYPE_IO_1V8_3V0_AUTO:
1702         case DRV_TYPE_IO_3V3_ONLY:
1703                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1704                 switch (bit) {
1705                 case 0 ... 12:
1706                         /* regular case, nothing to do */
1707                         break;
1708                 case 15:
1709                         /*
1710                          * drive-strength offset is special, as it is spread
1711                          * over 2 registers, the bit data[15] contains bit 0
1712                          * of the value while temp[1:0] contains bits 2 and 1
1713                          */
1714                         data = (ret & 0x1) << 15;
1715                         temp = (ret >> 0x1) & 0x3;
1716
1717                         rmask = BIT(15) | BIT(31);
1718                         data |= BIT(31);
1719                         ret = regmap_update_bits(regmap, reg, rmask, data);
1720                         if (ret)
1721                                 return ret;
1722
1723                         rmask = 0x3 | (0x3 << 16);
1724                         temp |= (0x3 << 16);
1725                         reg += 0x4;
1726                         ret = regmap_update_bits(regmap, reg, rmask, temp);
1727
1728                         return ret;
1729                 case 18 ... 21:
1730                         /* setting fully enclosed in the second register */
1731                         reg += 4;
1732                         bit -= 16;
1733                         break;
1734                 default:
1735                         dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1736                                 bit, drv_type);
1737                         return -EINVAL;
1738                 }
1739                 break;
1740         case DRV_TYPE_IO_DEFAULT:
1741         case DRV_TYPE_IO_1V8_OR_3V0:
1742         case DRV_TYPE_IO_1V8_ONLY:
1743                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1744                 break;
1745         default:
1746                 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1747                         drv_type);
1748                 return -EINVAL;
1749         }
1750
1751         /* enable the write to the equivalent lower bits */
1752         data = ((1 << rmask_bits) - 1) << (bit + 16);
1753         rmask = data | (data >> 16);
1754         data |= (ret << bit);
1755
1756         ret = regmap_update_bits(regmap, reg, rmask, data);
1757
1758         return ret;
1759 }
1760
1761 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1762         {
1763                 PIN_CONFIG_BIAS_DISABLE,
1764                 PIN_CONFIG_BIAS_PULL_UP,
1765                 PIN_CONFIG_BIAS_PULL_DOWN,
1766                 PIN_CONFIG_BIAS_BUS_HOLD
1767         },
1768         {
1769                 PIN_CONFIG_BIAS_DISABLE,
1770                 PIN_CONFIG_BIAS_PULL_DOWN,
1771                 PIN_CONFIG_BIAS_DISABLE,
1772                 PIN_CONFIG_BIAS_PULL_UP
1773         },
1774 };
1775
1776 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1777 {
1778         struct rockchip_pinctrl *info = bank->drvdata;
1779         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1780         struct regmap *regmap;
1781         int reg, ret, pull_type;
1782         u8 bit;
1783         u32 data;
1784
1785         /* rk3066b does support any pulls */
1786         if (ctrl->type == RK3066B)
1787                 return PIN_CONFIG_BIAS_DISABLE;
1788
1789         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1790
1791         ret = regmap_read(regmap, reg, &data);
1792         if (ret)
1793                 return ret;
1794
1795         switch (ctrl->type) {
1796         case RK2928:
1797         case RK3128:
1798                 return !(data & BIT(bit))
1799                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1800                                 : PIN_CONFIG_BIAS_DISABLE;
1801         case RV1108:
1802         case RK3188:
1803         case RK3288:
1804         case RK3368:
1805         case RK3399:
1806                 pull_type = bank->pull_type[pin_num / 8];
1807                 data >>= bit;
1808                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1809
1810                 return rockchip_pull_list[pull_type][data];
1811         default:
1812                 dev_err(info->dev, "unsupported pinctrl type\n");
1813                 return -EINVAL;
1814         };
1815 }
1816
1817 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1818                                         int pin_num, int pull)
1819 {
1820         struct rockchip_pinctrl *info = bank->drvdata;
1821         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1822         struct regmap *regmap;
1823         int reg, ret, i, pull_type;
1824         u8 bit;
1825         u32 data, rmask;
1826
1827         dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
1828                  bank->bank_num, pin_num, pull);
1829
1830         /* rk3066b does support any pulls */
1831         if (ctrl->type == RK3066B)
1832                 return pull ? -EINVAL : 0;
1833
1834         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1835
1836         switch (ctrl->type) {
1837         case RK2928:
1838         case RK3128:
1839                 data = BIT(bit + 16);
1840                 if (pull == PIN_CONFIG_BIAS_DISABLE)
1841                         data |= BIT(bit);
1842                 ret = regmap_write(regmap, reg, data);
1843                 break;
1844         case RV1108:
1845         case RK3188:
1846         case RK3288:
1847         case RK3368:
1848         case RK3399:
1849                 pull_type = bank->pull_type[pin_num / 8];
1850                 ret = -EINVAL;
1851                 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
1852                         i++) {
1853                         if (rockchip_pull_list[pull_type][i] == pull) {
1854                                 ret = i;
1855                                 break;
1856                         }
1857                 }
1858
1859                 if (ret < 0) {
1860                         dev_err(info->dev, "unsupported pull setting %d\n",
1861                                 pull);
1862                         return ret;
1863                 }
1864
1865                 /* enable the write to the equivalent lower bits */
1866                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
1867                 rmask = data | (data >> 16);
1868                 data |= (ret << bit);
1869
1870                 ret = regmap_update_bits(regmap, reg, rmask, data);
1871                 break;
1872         default:
1873                 dev_err(info->dev, "unsupported pinctrl type\n");
1874                 return -EINVAL;
1875         }
1876
1877         return ret;
1878 }
1879
1880 #define RK3328_SCHMITT_BITS_PER_PIN             1
1881 #define RK3328_SCHMITT_PINS_PER_REG             16
1882 #define RK3328_SCHMITT_BANK_STRIDE              8
1883 #define RK3328_SCHMITT_GRF_OFFSET               0x380
1884
1885 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1886                                            int pin_num,
1887                                            struct regmap **regmap,
1888                                            int *reg, u8 *bit)
1889 {
1890         struct rockchip_pinctrl *info = bank->drvdata;
1891
1892         *regmap = info->regmap_base;
1893         *reg = RK3328_SCHMITT_GRF_OFFSET;
1894
1895         *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
1896         *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
1897         *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
1898
1899         return 0;
1900 }
1901
1902 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
1903 {
1904         struct rockchip_pinctrl *info = bank->drvdata;
1905         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1906         struct regmap *regmap;
1907         int reg, ret;
1908         u8 bit;
1909         u32 data;
1910
1911         ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1912         if (ret)
1913                 return ret;
1914
1915         ret = regmap_read(regmap, reg, &data);
1916         if (ret)
1917                 return ret;
1918
1919         data >>= bit;
1920         return data & 0x1;
1921 }
1922
1923 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
1924                                 int pin_num, int enable)
1925 {
1926         struct rockchip_pinctrl *info = bank->drvdata;
1927         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1928         struct regmap *regmap;
1929         int reg, ret;
1930         u8 bit;
1931         u32 data, rmask;
1932
1933         dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
1934                 bank->bank_num, pin_num, enable);
1935
1936         ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1937         if (ret)
1938                 return ret;
1939
1940         /* enable the write to the equivalent lower bits */
1941         data = BIT(bit + 16) | (enable << bit);
1942         rmask = BIT(bit + 16) | BIT(bit);
1943
1944         return regmap_update_bits(regmap, reg, rmask, data);
1945 }
1946
1947 /*
1948  * Pinmux_ops handling
1949  */
1950
1951 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
1952 {
1953         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1954
1955         return info->nfunctions;
1956 }
1957
1958 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
1959                                           unsigned selector)
1960 {
1961         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1962
1963         return info->functions[selector].name;
1964 }
1965
1966 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
1967                                 unsigned selector, const char * const **groups,
1968                                 unsigned * const num_groups)
1969 {
1970         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1971
1972         *groups = info->functions[selector].groups;
1973         *num_groups = info->functions[selector].ngroups;
1974
1975         return 0;
1976 }
1977
1978 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
1979                             unsigned group)
1980 {
1981         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1982         const unsigned int *pins = info->groups[group].pins;
1983         const struct rockchip_pin_config *data = info->groups[group].data;
1984         struct rockchip_pin_bank *bank;
1985         int cnt, ret = 0;
1986
1987         dev_dbg(info->dev, "enable function %s group %s\n",
1988                 info->functions[selector].name, info->groups[group].name);
1989
1990         /*
1991          * for each pin in the pin group selected, program the corresponding
1992          * pin function number in the config register.
1993          */
1994         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
1995                 bank = pin_to_bank(info, pins[cnt]);
1996                 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
1997                                        data[cnt].func);
1998                 if (ret)
1999                         break;
2000         }
2001
2002         if (ret) {
2003                 /* revert the already done pin settings */
2004                 for (cnt--; cnt >= 0; cnt--)
2005                         rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
2006
2007                 return ret;
2008         }
2009
2010         return 0;
2011 }
2012
2013 static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
2014 {
2015         struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
2016         u32 data;
2017         int ret;
2018
2019         ret = clk_enable(bank->clk);
2020         if (ret < 0) {
2021                 dev_err(bank->drvdata->dev,
2022                         "failed to enable clock for bank %s\n", bank->name);
2023                 return ret;
2024         }
2025         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2026         clk_disable(bank->clk);
2027
2028         return !(data & BIT(offset));
2029 }
2030
2031 /*
2032  * The calls to gpio_direction_output() and gpio_direction_input()
2033  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
2034  * function called from the gpiolib interface).
2035  */
2036 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
2037                                             int pin, bool input)
2038 {
2039         struct rockchip_pin_bank *bank;
2040         int ret;
2041         unsigned long flags;
2042         u32 data;
2043
2044         bank = gpiochip_get_data(chip);
2045
2046         ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
2047         if (ret < 0)
2048                 return ret;
2049
2050         clk_enable(bank->clk);
2051         raw_spin_lock_irqsave(&bank->slock, flags);
2052
2053         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2054         /* set bit to 1 for output, 0 for input */
2055         if (!input)
2056                 data |= BIT(pin);
2057         else
2058                 data &= ~BIT(pin);
2059         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2060
2061         raw_spin_unlock_irqrestore(&bank->slock, flags);
2062         clk_disable(bank->clk);
2063
2064         return 0;
2065 }
2066
2067 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
2068                                               struct pinctrl_gpio_range *range,
2069                                               unsigned offset, bool input)
2070 {
2071         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2072         struct gpio_chip *chip;
2073         int pin;
2074
2075         chip = range->gc;
2076         pin = offset - chip->base;
2077         dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
2078                  offset, range->name, pin, input ? "input" : "output");
2079
2080         return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
2081                                                 input);
2082 }
2083
2084 static const struct pinmux_ops rockchip_pmx_ops = {
2085         .get_functions_count    = rockchip_pmx_get_funcs_count,
2086         .get_function_name      = rockchip_pmx_get_func_name,
2087         .get_function_groups    = rockchip_pmx_get_groups,
2088         .set_mux                = rockchip_pmx_set,
2089         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
2090 };
2091
2092 /*
2093  * Pinconf_ops handling
2094  */
2095
2096 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2097                                         enum pin_config_param pull)
2098 {
2099         switch (ctrl->type) {
2100         case RK2928:
2101         case RK3128:
2102                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2103                                         pull == PIN_CONFIG_BIAS_DISABLE);
2104         case RK3066B:
2105                 return pull ? false : true;
2106         case RV1108:
2107         case RK3188:
2108         case RK3288:
2109         case RK3368:
2110         case RK3399:
2111                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2112         }
2113
2114         return false;
2115 }
2116
2117 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
2118 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
2119
2120 /* set the pin config settings for a specified pin */
2121 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2122                                 unsigned long *configs, unsigned num_configs)
2123 {
2124         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2125         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2126         enum pin_config_param param;
2127         u32 arg;
2128         int i;
2129         int rc;
2130
2131         for (i = 0; i < num_configs; i++) {
2132                 param = pinconf_to_config_param(configs[i]);
2133                 arg = pinconf_to_config_argument(configs[i]);
2134
2135                 switch (param) {
2136                 case PIN_CONFIG_BIAS_DISABLE:
2137                         rc =  rockchip_set_pull(bank, pin - bank->pin_base,
2138                                 param);
2139                         if (rc)
2140                                 return rc;
2141                         break;
2142                 case PIN_CONFIG_BIAS_PULL_UP:
2143                 case PIN_CONFIG_BIAS_PULL_DOWN:
2144                 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2145                 case PIN_CONFIG_BIAS_BUS_HOLD:
2146                         if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2147                                 return -ENOTSUPP;
2148
2149                         if (!arg)
2150                                 return -EINVAL;
2151
2152                         rc = rockchip_set_pull(bank, pin - bank->pin_base,
2153                                 param);
2154                         if (rc)
2155                                 return rc;
2156                         break;
2157                 case PIN_CONFIG_OUTPUT:
2158                         rockchip_gpio_set(&bank->gpio_chip,
2159                                           pin - bank->pin_base, arg);
2160                         rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
2161                                           pin - bank->pin_base, false);
2162                         if (rc)
2163                                 return rc;
2164                         break;
2165                 case PIN_CONFIG_DRIVE_STRENGTH:
2166                         /* rk3288 is the first with per-pin drive-strength */
2167                         if (!info->ctrl->drv_calc_reg)
2168                                 return -ENOTSUPP;
2169
2170                         rc = rockchip_set_drive_perpin(bank,
2171                                                 pin - bank->pin_base, arg);
2172                         if (rc < 0)
2173                                 return rc;
2174                         break;
2175                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2176                         if (!info->ctrl->schmitt_calc_reg)
2177                                 return -ENOTSUPP;
2178
2179                         rc = rockchip_set_schmitt(bank,
2180                                                   pin - bank->pin_base, arg);
2181                         if (rc < 0)
2182                                 return rc;
2183                         break;
2184                 default:
2185                         return -ENOTSUPP;
2186                         break;
2187                 }
2188         } /* for each config */
2189
2190         return 0;
2191 }
2192
2193 /* get the pin config settings for a specified pin */
2194 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2195                                                         unsigned long *config)
2196 {
2197         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2198         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2199         enum pin_config_param param = pinconf_to_config_param(*config);
2200         u16 arg;
2201         int rc;
2202
2203         switch (param) {
2204         case PIN_CONFIG_BIAS_DISABLE:
2205                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2206                         return -EINVAL;
2207
2208                 arg = 0;
2209                 break;
2210         case PIN_CONFIG_BIAS_PULL_UP:
2211         case PIN_CONFIG_BIAS_PULL_DOWN:
2212         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2213         case PIN_CONFIG_BIAS_BUS_HOLD:
2214                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2215                         return -ENOTSUPP;
2216
2217                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2218                         return -EINVAL;
2219
2220                 arg = 1;
2221                 break;
2222         case PIN_CONFIG_OUTPUT:
2223                 rc = rockchip_get_mux(bank, pin - bank->pin_base);
2224                 if (rc != RK_FUNC_GPIO)
2225                         return -EINVAL;
2226
2227                 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
2228                 if (rc < 0)
2229                         return rc;
2230
2231                 arg = rc ? 1 : 0;
2232                 break;
2233         case PIN_CONFIG_DRIVE_STRENGTH:
2234                 /* rk3288 is the first with per-pin drive-strength */
2235                 if (!info->ctrl->drv_calc_reg)
2236                         return -ENOTSUPP;
2237
2238                 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
2239                 if (rc < 0)
2240                         return rc;
2241
2242                 arg = rc;
2243                 break;
2244         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2245                 if (!info->ctrl->schmitt_calc_reg)
2246                         return -ENOTSUPP;
2247
2248                 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
2249                 if (rc < 0)
2250                         return rc;
2251
2252                 arg = rc;
2253                 break;
2254         default:
2255                 return -ENOTSUPP;
2256                 break;
2257         }
2258
2259         *config = pinconf_to_config_packed(param, arg);
2260
2261         return 0;
2262 }
2263
2264 static const struct pinconf_ops rockchip_pinconf_ops = {
2265         .pin_config_get                 = rockchip_pinconf_get,
2266         .pin_config_set                 = rockchip_pinconf_set,
2267         .is_generic                     = true,
2268 };
2269
2270 static const struct of_device_id rockchip_bank_match[] = {
2271         { .compatible = "rockchip,gpio-bank" },
2272         { .compatible = "rockchip,rk3188-gpio-bank0" },
2273         {},
2274 };
2275
2276 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2277                                                 struct device_node *np)
2278 {
2279         struct device_node *child;
2280
2281         for_each_child_of_node(np, child) {
2282                 if (of_match_node(rockchip_bank_match, child))
2283                         continue;
2284
2285                 info->nfunctions++;
2286                 info->ngroups += of_get_child_count(child);
2287         }
2288 }
2289
2290 static int rockchip_pinctrl_parse_groups(struct device_node *np,
2291                                               struct rockchip_pin_group *grp,
2292                                               struct rockchip_pinctrl *info,
2293                                               u32 index)
2294 {
2295         struct rockchip_pin_bank *bank;
2296         int size;
2297         const __be32 *list;
2298         int num;
2299         int i, j;
2300         int ret;
2301
2302         dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
2303
2304         /* Initialise group */
2305         grp->name = np->name;
2306
2307         /*
2308          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
2309          * do sanity check and calculate pins number
2310          */
2311         list = of_get_property(np, "rockchip,pins", &size);
2312         /* we do not check return since it's safe node passed down */
2313         size /= sizeof(*list);
2314         if (!size || size % 4) {
2315                 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
2316                 return -EINVAL;
2317         }
2318
2319         grp->npins = size / 4;
2320
2321         grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
2322                                                 GFP_KERNEL);
2323         grp->data = devm_kzalloc(info->dev, grp->npins *
2324                                           sizeof(struct rockchip_pin_config),
2325                                         GFP_KERNEL);
2326         if (!grp->pins || !grp->data)
2327                 return -ENOMEM;
2328
2329         for (i = 0, j = 0; i < size; i += 4, j++) {
2330                 const __be32 *phandle;
2331                 struct device_node *np_config;
2332
2333                 num = be32_to_cpu(*list++);
2334                 bank = bank_num_to_bank(info, num);
2335                 if (IS_ERR(bank))
2336                         return PTR_ERR(bank);
2337
2338                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
2339                 grp->data[j].func = be32_to_cpu(*list++);
2340
2341                 phandle = list++;
2342                 if (!phandle)
2343                         return -EINVAL;
2344
2345                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
2346                 ret = pinconf_generic_parse_dt_config(np_config, NULL,
2347                                 &grp->data[j].configs, &grp->data[j].nconfigs);
2348                 if (ret)
2349                         return ret;
2350         }
2351
2352         return 0;
2353 }
2354
2355 static int rockchip_pinctrl_parse_functions(struct device_node *np,
2356                                                 struct rockchip_pinctrl *info,
2357                                                 u32 index)
2358 {
2359         struct device_node *child;
2360         struct rockchip_pmx_func *func;
2361         struct rockchip_pin_group *grp;
2362         int ret;
2363         static u32 grp_index;
2364         u32 i = 0;
2365
2366         dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
2367
2368         func = &info->functions[index];
2369
2370         /* Initialise function */
2371         func->name = np->name;
2372         func->ngroups = of_get_child_count(np);
2373         if (func->ngroups <= 0)
2374                 return 0;
2375
2376         func->groups = devm_kzalloc(info->dev,
2377                         func->ngroups * sizeof(char *), GFP_KERNEL);
2378         if (!func->groups)
2379                 return -ENOMEM;
2380
2381         for_each_child_of_node(np, child) {
2382                 func->groups[i] = child->name;
2383                 grp = &info->groups[grp_index++];
2384                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
2385                 if (ret) {
2386                         of_node_put(child);
2387                         return ret;
2388                 }
2389         }
2390
2391         return 0;
2392 }
2393
2394 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2395                                               struct rockchip_pinctrl *info)
2396 {
2397         struct device *dev = &pdev->dev;
2398         struct device_node *np = dev->of_node;
2399         struct device_node *child;
2400         int ret;
2401         int i;
2402
2403         rockchip_pinctrl_child_count(info, np);
2404
2405         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
2406         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
2407
2408         info->functions = devm_kzalloc(dev, info->nfunctions *
2409                                               sizeof(struct rockchip_pmx_func),
2410                                               GFP_KERNEL);
2411         if (!info->functions)
2412                 return -EINVAL;
2413
2414         info->groups = devm_kzalloc(dev, info->ngroups *
2415                                             sizeof(struct rockchip_pin_group),
2416                                             GFP_KERNEL);
2417         if (!info->groups)
2418                 return -EINVAL;
2419
2420         i = 0;
2421
2422         for_each_child_of_node(np, child) {
2423                 if (of_match_node(rockchip_bank_match, child))
2424                         continue;
2425
2426                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2427                 if (ret) {
2428                         dev_err(&pdev->dev, "failed to parse function\n");
2429                         of_node_put(child);
2430                         return ret;
2431                 }
2432         }
2433
2434         return 0;
2435 }
2436
2437 static int rockchip_pinctrl_register(struct platform_device *pdev,
2438                                         struct rockchip_pinctrl *info)
2439 {
2440         struct pinctrl_desc *ctrldesc = &info->pctl;
2441         struct pinctrl_pin_desc *pindesc, *pdesc;
2442         struct rockchip_pin_bank *pin_bank;
2443         int pin, bank, ret;
2444         int k;
2445
2446         ctrldesc->name = "rockchip-pinctrl";
2447         ctrldesc->owner = THIS_MODULE;
2448         ctrldesc->pctlops = &rockchip_pctrl_ops;
2449         ctrldesc->pmxops = &rockchip_pmx_ops;
2450         ctrldesc->confops = &rockchip_pinconf_ops;
2451
2452         pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
2453                         info->ctrl->nr_pins, GFP_KERNEL);
2454         if (!pindesc)
2455                 return -ENOMEM;
2456
2457         ctrldesc->pins = pindesc;
2458         ctrldesc->npins = info->ctrl->nr_pins;
2459
2460         pdesc = pindesc;
2461         for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
2462                 pin_bank = &info->ctrl->pin_banks[bank];
2463                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
2464                         pdesc->number = k;
2465                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
2466                                                 pin_bank->name, pin);
2467                         pdesc++;
2468                 }
2469         }
2470
2471         ret = rockchip_pinctrl_parse_dt(pdev, info);
2472         if (ret)
2473                 return ret;
2474
2475         info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
2476         if (IS_ERR(info->pctl_dev)) {
2477                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
2478                 return PTR_ERR(info->pctl_dev);
2479         }
2480
2481         for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
2482                 pin_bank = &info->ctrl->pin_banks[bank];
2483                 pin_bank->grange.name = pin_bank->name;
2484                 pin_bank->grange.id = bank;
2485                 pin_bank->grange.pin_base = pin_bank->pin_base;
2486                 pin_bank->grange.base = pin_bank->gpio_chip.base;
2487                 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
2488                 pin_bank->grange.gc = &pin_bank->gpio_chip;
2489                 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
2490         }
2491
2492         return 0;
2493 }
2494
2495 /*
2496  * GPIO handling
2497  */
2498
2499 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
2500 {
2501         struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2502         void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
2503         unsigned long flags;
2504         u32 data;
2505
2506         clk_enable(bank->clk);
2507         raw_spin_lock_irqsave(&bank->slock, flags);
2508
2509         data = readl(reg);
2510         data &= ~BIT(offset);
2511         if (value)
2512                 data |= BIT(offset);
2513         writel(data, reg);
2514
2515         raw_spin_unlock_irqrestore(&bank->slock, flags);
2516         clk_disable(bank->clk);
2517 }
2518
2519 /*
2520  * Returns the level of the pin for input direction and setting of the DR
2521  * register for output gpios.
2522  */
2523 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
2524 {
2525         struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2526         u32 data;
2527
2528         clk_enable(bank->clk);
2529         data = readl(bank->reg_base + GPIO_EXT_PORT);
2530         clk_disable(bank->clk);
2531         data >>= offset;
2532         data &= 1;
2533         return data;
2534 }
2535
2536 /*
2537  * gpiolib gpio_direction_input callback function. The setting of the pin
2538  * mux function as 'gpio input' will be handled by the pinctrl subsystem
2539  * interface.
2540  */
2541 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
2542 {
2543         return pinctrl_gpio_direction_input(gc->base + offset);
2544 }
2545
2546 /*
2547  * gpiolib gpio_direction_output callback function. The setting of the pin
2548  * mux function as 'gpio output' will be handled by the pinctrl subsystem
2549  * interface.
2550  */
2551 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
2552                                           unsigned offset, int value)
2553 {
2554         rockchip_gpio_set(gc, offset, value);
2555         return pinctrl_gpio_direction_output(gc->base + offset);
2556 }
2557
2558 /*
2559  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
2560  * and a virtual IRQ, if not already present.
2561  */
2562 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
2563 {
2564         struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2565         unsigned int virq;
2566
2567         if (!bank->domain)
2568                 return -ENXIO;
2569
2570         virq = irq_create_mapping(bank->domain, offset);
2571
2572         return (virq) ? : -ENXIO;
2573 }
2574
2575 static const struct gpio_chip rockchip_gpiolib_chip = {
2576         .request = gpiochip_generic_request,
2577         .free = gpiochip_generic_free,
2578         .set = rockchip_gpio_set,
2579         .get = rockchip_gpio_get,
2580         .get_direction  = rockchip_gpio_get_direction,
2581         .direction_input = rockchip_gpio_direction_input,
2582         .direction_output = rockchip_gpio_direction_output,
2583         .to_irq = rockchip_gpio_to_irq,
2584         .owner = THIS_MODULE,
2585 };
2586
2587 /*
2588  * Interrupt handling
2589  */
2590
2591 static void rockchip_irq_demux(struct irq_desc *desc)
2592 {
2593         struct irq_chip *chip = irq_desc_get_chip(desc);
2594         struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
2595         u32 pend;
2596
2597         dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
2598
2599         chained_irq_enter(chip, desc);
2600
2601         pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
2602
2603         while (pend) {
2604                 unsigned int irq, virq;
2605
2606                 irq = __ffs(pend);
2607                 pend &= ~BIT(irq);
2608                 virq = irq_linear_revmap(bank->domain, irq);
2609
2610                 if (!virq) {
2611                         dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
2612                         continue;
2613                 }
2614
2615                 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
2616
2617                 /*
2618                  * Triggering IRQ on both rising and falling edge
2619                  * needs manual intervention.
2620                  */
2621                 if (bank->toggle_edge_mode & BIT(irq)) {
2622                         u32 data, data_old, polarity;
2623                         unsigned long flags;
2624
2625                         data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
2626                         do {
2627                                 raw_spin_lock_irqsave(&bank->slock, flags);
2628
2629                                 polarity = readl_relaxed(bank->reg_base +
2630                                                          GPIO_INT_POLARITY);
2631                                 if (data & BIT(irq))
2632                                         polarity &= ~BIT(irq);
2633                                 else
2634                                         polarity |= BIT(irq);
2635                                 writel(polarity,
2636                                        bank->reg_base + GPIO_INT_POLARITY);
2637
2638                                 raw_spin_unlock_irqrestore(&bank->slock, flags);
2639
2640                                 data_old = data;
2641                                 data = readl_relaxed(bank->reg_base +
2642                                                      GPIO_EXT_PORT);
2643                         } while ((data & BIT(irq)) != (data_old & BIT(irq)));
2644                 }
2645
2646                 generic_handle_irq(virq);
2647         }
2648
2649         chained_irq_exit(chip, desc);
2650 }
2651
2652 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
2653 {
2654         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2655         struct rockchip_pin_bank *bank = gc->private;
2656         u32 mask = BIT(d->hwirq);
2657         u32 polarity;
2658         u32 level;
2659         u32 data;
2660         unsigned long flags;
2661         int ret;
2662
2663         /* make sure the pin is configured as gpio input */
2664         ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
2665         if (ret < 0)
2666                 return ret;
2667
2668         clk_enable(bank->clk);
2669         raw_spin_lock_irqsave(&bank->slock, flags);
2670
2671         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2672         data &= ~mask;
2673         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2674
2675         raw_spin_unlock_irqrestore(&bank->slock, flags);
2676
2677         if (type & IRQ_TYPE_EDGE_BOTH)
2678                 irq_set_handler_locked(d, handle_edge_irq);
2679         else
2680                 irq_set_handler_locked(d, handle_level_irq);
2681
2682         raw_spin_lock_irqsave(&bank->slock, flags);
2683         irq_gc_lock(gc);
2684
2685         level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
2686         polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
2687
2688         switch (type) {
2689         case IRQ_TYPE_EDGE_BOTH:
2690                 bank->toggle_edge_mode |= mask;
2691                 level |= mask;
2692
2693                 /*
2694                  * Determine gpio state. If 1 next interrupt should be falling
2695                  * otherwise rising.
2696                  */
2697                 data = readl(bank->reg_base + GPIO_EXT_PORT);
2698                 if (data & mask)
2699                         polarity &= ~mask;
2700                 else
2701                         polarity |= mask;
2702                 break;
2703         case IRQ_TYPE_EDGE_RISING:
2704                 bank->toggle_edge_mode &= ~mask;
2705                 level |= mask;
2706                 polarity |= mask;
2707                 break;
2708         case IRQ_TYPE_EDGE_FALLING:
2709                 bank->toggle_edge_mode &= ~mask;
2710                 level |= mask;
2711                 polarity &= ~mask;
2712                 break;
2713         case IRQ_TYPE_LEVEL_HIGH:
2714                 bank->toggle_edge_mode &= ~mask;
2715                 level &= ~mask;
2716                 polarity |= mask;
2717                 break;
2718         case IRQ_TYPE_LEVEL_LOW:
2719                 bank->toggle_edge_mode &= ~mask;
2720                 level &= ~mask;
2721                 polarity &= ~mask;
2722                 break;
2723         default:
2724                 irq_gc_unlock(gc);
2725                 raw_spin_unlock_irqrestore(&bank->slock, flags);
2726                 clk_disable(bank->clk);
2727                 return -EINVAL;
2728         }
2729
2730         writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
2731         writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
2732
2733         irq_gc_unlock(gc);
2734         raw_spin_unlock_irqrestore(&bank->slock, flags);
2735         clk_disable(bank->clk);
2736
2737         return 0;
2738 }
2739
2740 static void rockchip_irq_suspend(struct irq_data *d)
2741 {
2742         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2743         struct rockchip_pin_bank *bank = gc->private;
2744
2745         clk_enable(bank->clk);
2746         bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
2747         irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
2748         clk_disable(bank->clk);
2749 }
2750
2751 static void rockchip_irq_resume(struct irq_data *d)
2752 {
2753         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2754         struct rockchip_pin_bank *bank = gc->private;
2755
2756         clk_enable(bank->clk);
2757         irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
2758         clk_disable(bank->clk);
2759 }
2760
2761 static void rockchip_irq_enable(struct irq_data *d)
2762 {
2763         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2764         struct rockchip_pin_bank *bank = gc->private;
2765
2766         clk_enable(bank->clk);
2767         irq_gc_mask_clr_bit(d);
2768 }
2769
2770 static void rockchip_irq_disable(struct irq_data *d)
2771 {
2772         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2773         struct rockchip_pin_bank *bank = gc->private;
2774
2775         irq_gc_mask_set_bit(d);
2776         clk_disable(bank->clk);
2777 }
2778
2779 static int rockchip_interrupts_register(struct platform_device *pdev,
2780                                                 struct rockchip_pinctrl *info)
2781 {
2782         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2783         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2784         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
2785         struct irq_chip_generic *gc;
2786         int ret;
2787         int i, j;
2788
2789         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2790                 if (!bank->valid) {
2791                         dev_warn(&pdev->dev, "bank %s is not valid\n",
2792                                  bank->name);
2793                         continue;
2794                 }
2795
2796                 ret = clk_enable(bank->clk);
2797                 if (ret) {
2798                         dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
2799                                 bank->name);
2800                         continue;
2801                 }
2802
2803                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
2804                                                 &irq_generic_chip_ops, NULL);
2805                 if (!bank->domain) {
2806                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
2807                                  bank->name);
2808                         clk_disable(bank->clk);
2809                         continue;
2810                 }
2811
2812                 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
2813                                          "rockchip_gpio_irq", handle_level_irq,
2814                                          clr, 0, IRQ_GC_INIT_MASK_CACHE);
2815                 if (ret) {
2816                         dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
2817                                 bank->name);
2818                         irq_domain_remove(bank->domain);
2819                         clk_disable(bank->clk);
2820                         continue;
2821                 }
2822
2823                 /*
2824                  * Linux assumes that all interrupts start out disabled/masked.
2825                  * Our driver only uses the concept of masked and always keeps
2826                  * things enabled, so for us that's all masked and all enabled.
2827                  */
2828                 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
2829                 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
2830
2831                 gc = irq_get_domain_generic_chip(bank->domain, 0);
2832                 gc->reg_base = bank->reg_base;
2833                 gc->private = bank;
2834                 gc->chip_types[0].regs.mask = GPIO_INTMASK;
2835                 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
2836                 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
2837                 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
2838                 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
2839                 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
2840                 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
2841                 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
2842                 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
2843                 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
2844                 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
2845                 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
2846
2847                 irq_set_chained_handler_and_data(bank->irq,
2848                                                  rockchip_irq_demux, bank);
2849
2850                 /* map the gpio irqs here, when the clock is still running */
2851                 for (j = 0 ; j < 32 ; j++)
2852                         irq_create_mapping(bank->domain, j);
2853
2854                 clk_disable(bank->clk);
2855         }
2856
2857         return 0;
2858 }
2859
2860 static int rockchip_gpiolib_register(struct platform_device *pdev,
2861                                                 struct rockchip_pinctrl *info)
2862 {
2863         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2864         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2865         struct gpio_chip *gc;
2866         int ret;
2867         int i;
2868
2869         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2870                 if (!bank->valid) {
2871                         dev_warn(&pdev->dev, "bank %s is not valid\n",
2872                                  bank->name);
2873                         continue;
2874                 }
2875
2876                 bank->gpio_chip = rockchip_gpiolib_chip;
2877
2878                 gc = &bank->gpio_chip;
2879                 gc->base = bank->pin_base;
2880                 gc->ngpio = bank->nr_pins;
2881                 gc->parent = &pdev->dev;
2882                 gc->of_node = bank->of_node;
2883                 gc->label = bank->name;
2884
2885                 ret = gpiochip_add_data(gc, bank);
2886                 if (ret) {
2887                         dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
2888                                                         gc->label, ret);
2889                         goto fail;
2890                 }
2891         }
2892
2893         rockchip_interrupts_register(pdev, info);
2894
2895         return 0;
2896
2897 fail:
2898         for (--i, --bank; i >= 0; --i, --bank) {
2899                 if (!bank->valid)
2900                         continue;
2901                 gpiochip_remove(&bank->gpio_chip);
2902         }
2903         return ret;
2904 }
2905
2906 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
2907                                                 struct rockchip_pinctrl *info)
2908 {
2909         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2910         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2911         int i;
2912
2913         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2914                 if (!bank->valid)
2915                         continue;
2916                 gpiochip_remove(&bank->gpio_chip);
2917         }
2918
2919         return 0;
2920 }
2921
2922 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
2923                                   struct rockchip_pinctrl *info)
2924 {
2925         struct resource res;
2926         void __iomem *base;
2927
2928         if (of_address_to_resource(bank->of_node, 0, &res)) {
2929                 dev_err(info->dev, "cannot find IO resource for bank\n");
2930                 return -ENOENT;
2931         }
2932
2933         bank->reg_base = devm_ioremap_resource(info->dev, &res);
2934         if (IS_ERR(bank->reg_base))
2935                 return PTR_ERR(bank->reg_base);
2936
2937         /*
2938          * special case, where parts of the pull setting-registers are
2939          * part of the PMU register space
2940          */
2941         if (of_device_is_compatible(bank->of_node,
2942                                     "rockchip,rk3188-gpio-bank0")) {
2943                 struct device_node *node;
2944
2945                 node = of_parse_phandle(bank->of_node->parent,
2946                                         "rockchip,pmu", 0);
2947                 if (!node) {
2948                         if (of_address_to_resource(bank->of_node, 1, &res)) {
2949                                 dev_err(info->dev, "cannot find IO resource for bank\n");
2950                                 return -ENOENT;
2951                         }
2952
2953                         base = devm_ioremap_resource(info->dev, &res);
2954                         if (IS_ERR(base))
2955                                 return PTR_ERR(base);
2956                         rockchip_regmap_config.max_register =
2957                                                     resource_size(&res) - 4;
2958                         rockchip_regmap_config.name =
2959                                             "rockchip,rk3188-gpio-bank0-pull";
2960                         bank->regmap_pull = devm_regmap_init_mmio(info->dev,
2961                                                     base,
2962                                                     &rockchip_regmap_config);
2963                 }
2964         }
2965
2966         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
2967
2968         bank->clk = of_clk_get(bank->of_node, 0);
2969         if (IS_ERR(bank->clk))
2970                 return PTR_ERR(bank->clk);
2971
2972         return clk_prepare(bank->clk);
2973 }
2974
2975 static const struct of_device_id rockchip_pinctrl_dt_match[];
2976
2977 /* retrieve the soc specific data */
2978 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
2979                                                 struct rockchip_pinctrl *d,
2980                                                 struct platform_device *pdev)
2981 {
2982         const struct of_device_id *match;
2983         struct device_node *node = pdev->dev.of_node;
2984         struct device_node *np;
2985         struct rockchip_pin_ctrl *ctrl;
2986         struct rockchip_pin_bank *bank;
2987         int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
2988
2989         match = of_match_node(rockchip_pinctrl_dt_match, node);
2990         ctrl = (struct rockchip_pin_ctrl *)match->data;
2991
2992         for_each_child_of_node(node, np) {
2993                 if (!of_find_property(np, "gpio-controller", NULL))
2994                         continue;
2995
2996                 bank = ctrl->pin_banks;
2997                 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2998                         if (!strcmp(bank->name, np->name)) {
2999                                 bank->of_node = np;
3000
3001                                 if (!rockchip_get_bank_data(bank, d))
3002                                         bank->valid = true;
3003
3004                                 break;
3005                         }
3006                 }
3007         }
3008
3009         grf_offs = ctrl->grf_mux_offset;
3010         pmu_offs = ctrl->pmu_mux_offset;
3011         drv_pmu_offs = ctrl->pmu_drv_offset;
3012         drv_grf_offs = ctrl->grf_drv_offset;
3013         bank = ctrl->pin_banks;
3014         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3015                 int bank_pins = 0;
3016
3017                 raw_spin_lock_init(&bank->slock);
3018                 bank->drvdata = d;
3019                 bank->pin_base = ctrl->nr_pins;
3020                 ctrl->nr_pins += bank->nr_pins;
3021
3022                 /* calculate iomux and drv offsets */
3023                 for (j = 0; j < 4; j++) {
3024                         struct rockchip_iomux *iom = &bank->iomux[j];
3025                         struct rockchip_drv *drv = &bank->drv[j];
3026                         int inc;
3027
3028                         if (bank_pins >= bank->nr_pins)
3029                                 break;
3030
3031                         /* preset iomux offset value, set new start value */
3032                         if (iom->offset >= 0) {
3033                                 if (iom->type & IOMUX_SOURCE_PMU)
3034                                         pmu_offs = iom->offset;
3035                                 else
3036                                         grf_offs = iom->offset;
3037                         } else { /* set current iomux offset */
3038                                 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3039                                                         pmu_offs : grf_offs;
3040                         }
3041
3042                         /* preset drv offset value, set new start value */
3043                         if (drv->offset >= 0) {
3044                                 if (iom->type & IOMUX_SOURCE_PMU)
3045                                         drv_pmu_offs = drv->offset;
3046                                 else
3047                                         drv_grf_offs = drv->offset;
3048                         } else { /* set current drv offset */
3049                                 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3050                                                 drv_pmu_offs : drv_grf_offs;
3051                         }
3052
3053                         dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
3054                                 i, j, iom->offset, drv->offset);
3055
3056                         /*
3057                          * Increase offset according to iomux width.
3058                          * 4bit iomux'es are spread over two registers.
3059                          */
3060                         inc = (iom->type & (IOMUX_WIDTH_4BIT |
3061                                             IOMUX_WIDTH_3BIT)) ? 8 : 4;
3062                         if (iom->type & IOMUX_SOURCE_PMU)
3063                                 pmu_offs += inc;
3064                         else
3065                                 grf_offs += inc;
3066
3067                         /*
3068                          * Increase offset according to drv width.
3069                          * 3bit drive-strenth'es are spread over two registers.
3070                          */
3071                         if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
3072                             (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
3073                                 inc = 8;
3074                         else
3075                                 inc = 4;
3076
3077                         if (iom->type & IOMUX_SOURCE_PMU)
3078                                 drv_pmu_offs += inc;
3079                         else
3080                                 drv_grf_offs += inc;
3081
3082                         bank_pins += 8;
3083                 }
3084
3085                 /* calculate the per-bank recalced_mask */
3086                 for (j = 0; j < ctrl->niomux_recalced; j++) {
3087                         int pin = 0;
3088
3089                         if (ctrl->iomux_recalced[j].num == bank->bank_num) {
3090                                 pin = ctrl->iomux_recalced[j].pin;
3091                                 bank->recalced_mask |= BIT(pin);
3092                         }
3093                 }
3094
3095                 /* calculate the per-bank route_mask */
3096                 for (j = 0; j < ctrl->niomux_routes; j++) {
3097                         int pin = 0;
3098
3099                         if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
3100                                 pin = ctrl->iomux_routes[j].pin;
3101                                 bank->route_mask |= BIT(pin);
3102                         }
3103                 }
3104         }
3105
3106         return ctrl;
3107 }
3108
3109 #define RK3288_GRF_GPIO6C_IOMUX         0x64
3110 #define GPIO6C6_SEL_WRITE_ENABLE        BIT(28)
3111
3112 static u32 rk3288_grf_gpio6c_iomux;
3113
3114 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
3115 {
3116         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3117         int ret = pinctrl_force_sleep(info->pctl_dev);
3118
3119         if (ret)
3120                 return ret;
3121
3122         /*
3123          * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
3124          * the setting here, and restore it at resume.
3125          */
3126         if (info->ctrl->type == RK3288) {
3127                 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3128                                   &rk3288_grf_gpio6c_iomux);
3129                 if (ret) {
3130                         pinctrl_force_default(info->pctl_dev);
3131                         return ret;
3132                 }
3133         }
3134
3135         return 0;
3136 }
3137
3138 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
3139 {
3140         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3141         int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3142                                rk3288_grf_gpio6c_iomux |
3143                                GPIO6C6_SEL_WRITE_ENABLE);
3144
3145         if (ret)
3146                 return ret;
3147
3148         return pinctrl_force_default(info->pctl_dev);
3149 }
3150
3151 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
3152                          rockchip_pinctrl_resume);
3153
3154 static int rockchip_pinctrl_probe(struct platform_device *pdev)
3155 {
3156         struct rockchip_pinctrl *info;
3157         struct device *dev = &pdev->dev;
3158         struct rockchip_pin_ctrl *ctrl;
3159         struct device_node *np = pdev->dev.of_node, *node;
3160         struct resource *res;
3161         void __iomem *base;
3162         int ret;
3163
3164         if (!dev->of_node) {
3165                 dev_err(dev, "device tree node not found\n");
3166                 return -ENODEV;
3167         }
3168
3169         info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
3170         if (!info)
3171                 return -ENOMEM;
3172
3173         info->dev = dev;
3174
3175         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
3176         if (!ctrl) {
3177                 dev_err(dev, "driver data not available\n");
3178                 return -EINVAL;
3179         }
3180         info->ctrl = ctrl;
3181
3182         node = of_parse_phandle(np, "rockchip,grf", 0);
3183         if (node) {
3184                 info->regmap_base = syscon_node_to_regmap(node);
3185                 if (IS_ERR(info->regmap_base))
3186                         return PTR_ERR(info->regmap_base);
3187         } else {
3188                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3189                 base = devm_ioremap_resource(&pdev->dev, res);
3190                 if (IS_ERR(base))
3191                         return PTR_ERR(base);
3192
3193                 rockchip_regmap_config.max_register = resource_size(res) - 4;
3194                 rockchip_regmap_config.name = "rockchip,pinctrl";
3195                 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
3196                                                     &rockchip_regmap_config);
3197
3198                 /* to check for the old dt-bindings */
3199                 info->reg_size = resource_size(res);
3200
3201                 /* Honor the old binding, with pull registers as 2nd resource */
3202                 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
3203                         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3204                         base = devm_ioremap_resource(&pdev->dev, res);
3205                         if (IS_ERR(base))
3206                                 return PTR_ERR(base);
3207
3208                         rockchip_regmap_config.max_register =
3209                                                         resource_size(res) - 4;
3210                         rockchip_regmap_config.name = "rockchip,pinctrl-pull";
3211                         info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
3212                                                     base,
3213                                                     &rockchip_regmap_config);
3214                 }
3215         }
3216
3217         /* try to find the optional reference to the pmu syscon */
3218         node = of_parse_phandle(np, "rockchip,pmu", 0);
3219         if (node) {
3220                 info->regmap_pmu = syscon_node_to_regmap(node);
3221                 if (IS_ERR(info->regmap_pmu))
3222                         return PTR_ERR(info->regmap_pmu);
3223         }
3224
3225         ret = rockchip_gpiolib_register(pdev, info);
3226         if (ret)
3227                 return ret;
3228
3229         ret = rockchip_pinctrl_register(pdev, info);
3230         if (ret) {
3231                 rockchip_gpiolib_unregister(pdev, info);
3232                 return ret;
3233         }
3234
3235         platform_set_drvdata(pdev, info);
3236
3237         return 0;
3238 }
3239
3240 static struct rockchip_pin_bank rv1108_pin_banks[] = {
3241         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3242                                              IOMUX_SOURCE_PMU,
3243                                              IOMUX_SOURCE_PMU,
3244                                              IOMUX_SOURCE_PMU),
3245         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3246         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
3247         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
3248 };
3249
3250 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
3251         .pin_banks              = rv1108_pin_banks,
3252         .nr_banks               = ARRAY_SIZE(rv1108_pin_banks),
3253         .label                  = "RV1108-GPIO",
3254         .type                   = RV1108,
3255         .grf_mux_offset         = 0x10,
3256         .pmu_mux_offset         = 0x0,
3257         .iomux_recalced         = rv1108_mux_recalced_data,
3258         .niomux_recalced        = ARRAY_SIZE(rv1108_mux_recalced_data),
3259         .pull_calc_reg          = rv1108_calc_pull_reg_and_bit,
3260         .drv_calc_reg           = rv1108_calc_drv_reg_and_bit,
3261         .schmitt_calc_reg       = rv1108_calc_schmitt_reg_and_bit,
3262 };
3263
3264 static struct rockchip_pin_bank rk2928_pin_banks[] = {
3265         PIN_BANK(0, 32, "gpio0"),
3266         PIN_BANK(1, 32, "gpio1"),
3267         PIN_BANK(2, 32, "gpio2"),
3268         PIN_BANK(3, 32, "gpio3"),
3269 };
3270
3271 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
3272                 .pin_banks              = rk2928_pin_banks,
3273                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
3274                 .label                  = "RK2928-GPIO",
3275                 .type                   = RK2928,
3276                 .grf_mux_offset         = 0xa8,
3277                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3278 };
3279
3280 static struct rockchip_pin_bank rk3036_pin_banks[] = {
3281         PIN_BANK(0, 32, "gpio0"),
3282         PIN_BANK(1, 32, "gpio1"),
3283         PIN_BANK(2, 32, "gpio2"),
3284 };
3285
3286 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
3287                 .pin_banks              = rk3036_pin_banks,
3288                 .nr_banks               = ARRAY_SIZE(rk3036_pin_banks),
3289                 .label                  = "RK3036-GPIO",
3290                 .type                   = RK2928,
3291                 .grf_mux_offset         = 0xa8,
3292                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3293 };
3294
3295 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
3296         PIN_BANK(0, 32, "gpio0"),
3297         PIN_BANK(1, 32, "gpio1"),
3298         PIN_BANK(2, 32, "gpio2"),
3299         PIN_BANK(3, 32, "gpio3"),
3300         PIN_BANK(4, 32, "gpio4"),
3301         PIN_BANK(6, 16, "gpio6"),
3302 };
3303
3304 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
3305                 .pin_banks              = rk3066a_pin_banks,
3306                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
3307                 .label                  = "RK3066a-GPIO",
3308                 .type                   = RK2928,
3309                 .grf_mux_offset         = 0xa8,
3310                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3311 };
3312
3313 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
3314         PIN_BANK(0, 32, "gpio0"),
3315         PIN_BANK(1, 32, "gpio1"),
3316         PIN_BANK(2, 32, "gpio2"),
3317         PIN_BANK(3, 32, "gpio3"),
3318 };
3319
3320 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
3321                 .pin_banks      = rk3066b_pin_banks,
3322                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
3323                 .label          = "RK3066b-GPIO",
3324                 .type           = RK3066B,
3325                 .grf_mux_offset = 0x60,
3326 };
3327
3328 static struct rockchip_pin_bank rk3128_pin_banks[] = {
3329         PIN_BANK(0, 32, "gpio0"),
3330         PIN_BANK(1, 32, "gpio1"),
3331         PIN_BANK(2, 32, "gpio2"),
3332         PIN_BANK(3, 32, "gpio3"),
3333 };
3334
3335 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
3336                 .pin_banks              = rk3128_pin_banks,
3337                 .nr_banks               = ARRAY_SIZE(rk3128_pin_banks),
3338                 .label                  = "RK3128-GPIO",
3339                 .type                   = RK3128,
3340                 .grf_mux_offset         = 0xa8,
3341                 .iomux_recalced         = rk3128_mux_recalced_data,
3342                 .niomux_recalced        = ARRAY_SIZE(rk3128_mux_recalced_data),
3343                 .iomux_routes           = rk3128_mux_route_data,
3344                 .niomux_routes          = ARRAY_SIZE(rk3128_mux_route_data),
3345                 .pull_calc_reg          = rk3128_calc_pull_reg_and_bit,
3346 };
3347
3348 static struct rockchip_pin_bank rk3188_pin_banks[] = {
3349         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
3350         PIN_BANK(1, 32, "gpio1"),
3351         PIN_BANK(2, 32, "gpio2"),
3352         PIN_BANK(3, 32, "gpio3"),
3353 };
3354
3355 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
3356                 .pin_banks              = rk3188_pin_banks,
3357                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
3358                 .label                  = "RK3188-GPIO",
3359                 .type                   = RK3188,
3360                 .grf_mux_offset         = 0x60,
3361                 .pull_calc_reg          = rk3188_calc_pull_reg_and_bit,
3362 };
3363
3364 static struct rockchip_pin_bank rk3228_pin_banks[] = {
3365         PIN_BANK(0, 32, "gpio0"),
3366         PIN_BANK(1, 32, "gpio1"),
3367         PIN_BANK(2, 32, "gpio2"),
3368         PIN_BANK(3, 32, "gpio3"),
3369 };
3370
3371 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
3372                 .pin_banks              = rk3228_pin_banks,
3373                 .nr_banks               = ARRAY_SIZE(rk3228_pin_banks),
3374                 .label                  = "RK3228-GPIO",
3375                 .type                   = RK3288,
3376                 .grf_mux_offset         = 0x0,
3377                 .iomux_routes           = rk3228_mux_route_data,
3378                 .niomux_routes          = ARRAY_SIZE(rk3228_mux_route_data),
3379                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
3380                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
3381 };
3382
3383 static struct rockchip_pin_bank rk3288_pin_banks[] = {
3384         PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
3385                                              IOMUX_SOURCE_PMU,
3386                                              IOMUX_SOURCE_PMU,
3387                                              IOMUX_UNROUTED
3388                             ),
3389         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
3390                                              IOMUX_UNROUTED,
3391                                              IOMUX_UNROUTED,
3392                                              0
3393                             ),
3394         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
3395         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
3396         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3397                                              IOMUX_WIDTH_4BIT,
3398                                              0,
3399                                              0
3400                             ),
3401         PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
3402                                              0,
3403                                              0,
3404                                              IOMUX_UNROUTED
3405                             ),
3406         PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
3407         PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
3408                                              0,
3409                                              IOMUX_WIDTH_4BIT,
3410                                              IOMUX_UNROUTED
3411                             ),
3412         PIN_BANK(8, 16, "gpio8"),
3413 };
3414
3415 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3416                 .pin_banks              = rk3288_pin_banks,
3417                 .nr_banks               = ARRAY_SIZE(rk3288_pin_banks),
3418                 .label                  = "RK3288-GPIO",
3419                 .type                   = RK3288,
3420                 .grf_mux_offset         = 0x0,
3421                 .pmu_mux_offset         = 0x84,
3422                 .iomux_routes           = rk3288_mux_route_data,
3423                 .niomux_routes          = ARRAY_SIZE(rk3288_mux_route_data),
3424                 .pull_calc_reg          = rk3288_calc_pull_reg_and_bit,
3425                 .drv_calc_reg           = rk3288_calc_drv_reg_and_bit,
3426 };
3427
3428 static struct rockchip_pin_bank rk3328_pin_banks[] = {
3429         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3430         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3431         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
3432                              IOMUX_WIDTH_3BIT,
3433                              IOMUX_WIDTH_3BIT,
3434                              0),
3435         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3436                              IOMUX_WIDTH_3BIT,
3437                              IOMUX_WIDTH_3BIT,
3438                              0,
3439                              0),
3440 };
3441
3442 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
3443                 .pin_banks              = rk3328_pin_banks,
3444                 .nr_banks               = ARRAY_SIZE(rk3328_pin_banks),
3445                 .label                  = "RK3328-GPIO",
3446                 .type                   = RK3288,
3447                 .grf_mux_offset         = 0x0,
3448                 .iomux_recalced         = rk3328_mux_recalced_data,
3449                 .niomux_recalced        = ARRAY_SIZE(rk3328_mux_recalced_data),
3450                 .iomux_routes           = rk3328_mux_route_data,
3451                 .niomux_routes          = ARRAY_SIZE(rk3328_mux_route_data),
3452                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
3453                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
3454                 .schmitt_calc_reg       = rk3328_calc_schmitt_reg_and_bit,
3455 };
3456
3457 static struct rockchip_pin_bank rk3368_pin_banks[] = {
3458         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3459                                              IOMUX_SOURCE_PMU,
3460                                              IOMUX_SOURCE_PMU,
3461                                              IOMUX_SOURCE_PMU
3462                             ),
3463         PIN_BANK(1, 32, "gpio1"),
3464         PIN_BANK(2, 32, "gpio2"),
3465         PIN_BANK(3, 32, "gpio3"),
3466 };
3467
3468 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
3469                 .pin_banks              = rk3368_pin_banks,
3470                 .nr_banks               = ARRAY_SIZE(rk3368_pin_banks),
3471                 .label                  = "RK3368-GPIO",
3472                 .type                   = RK3368,
3473                 .grf_mux_offset         = 0x0,
3474                 .pmu_mux_offset         = 0x0,
3475                 .pull_calc_reg          = rk3368_calc_pull_reg_and_bit,
3476                 .drv_calc_reg           = rk3368_calc_drv_reg_and_bit,
3477 };
3478
3479 static struct rockchip_pin_bank rk3399_pin_banks[] = {
3480         PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
3481                                                          IOMUX_SOURCE_PMU,
3482                                                          IOMUX_SOURCE_PMU,
3483                                                          IOMUX_SOURCE_PMU,
3484                                                          IOMUX_SOURCE_PMU,
3485                                                          DRV_TYPE_IO_1V8_ONLY,
3486                                                          DRV_TYPE_IO_1V8_ONLY,
3487                                                          DRV_TYPE_IO_DEFAULT,
3488                                                          DRV_TYPE_IO_DEFAULT,
3489                                                          0x80,
3490                                                          0x88,
3491                                                          -1,
3492                                                          -1,
3493                                                          PULL_TYPE_IO_1V8_ONLY,
3494                                                          PULL_TYPE_IO_1V8_ONLY,
3495                                                          PULL_TYPE_IO_DEFAULT,
3496                                                          PULL_TYPE_IO_DEFAULT
3497                                                         ),
3498         PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
3499                                         IOMUX_SOURCE_PMU,
3500                                         IOMUX_SOURCE_PMU,
3501                                         IOMUX_SOURCE_PMU,
3502                                         DRV_TYPE_IO_1V8_OR_3V0,
3503                                         DRV_TYPE_IO_1V8_OR_3V0,
3504                                         DRV_TYPE_IO_1V8_OR_3V0,
3505                                         DRV_TYPE_IO_1V8_OR_3V0,
3506                                         0xa0,
3507                                         0xa8,
3508                                         0xb0,
3509                                         0xb8
3510                                         ),
3511         PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
3512                                       DRV_TYPE_IO_1V8_OR_3V0,
3513                                       DRV_TYPE_IO_1V8_ONLY,
3514                                       DRV_TYPE_IO_1V8_ONLY,
3515                                       PULL_TYPE_IO_DEFAULT,
3516                                       PULL_TYPE_IO_DEFAULT,
3517                                       PULL_TYPE_IO_1V8_ONLY,
3518                                       PULL_TYPE_IO_1V8_ONLY
3519                                       ),
3520         PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
3521                            DRV_TYPE_IO_3V3_ONLY,
3522                            DRV_TYPE_IO_3V3_ONLY,
3523                            DRV_TYPE_IO_1V8_OR_3V0
3524                            ),
3525         PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
3526                            DRV_TYPE_IO_1V8_3V0_AUTO,
3527                            DRV_TYPE_IO_1V8_OR_3V0,
3528                            DRV_TYPE_IO_1V8_OR_3V0
3529                            ),
3530 };
3531
3532 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
3533                 .pin_banks              = rk3399_pin_banks,
3534                 .nr_banks               = ARRAY_SIZE(rk3399_pin_banks),
3535                 .label                  = "RK3399-GPIO",
3536                 .type                   = RK3399,
3537                 .grf_mux_offset         = 0xe000,
3538                 .pmu_mux_offset         = 0x0,
3539                 .grf_drv_offset         = 0xe100,
3540                 .pmu_drv_offset         = 0x80,
3541                 .iomux_routes           = rk3399_mux_route_data,
3542                 .niomux_routes          = ARRAY_SIZE(rk3399_mux_route_data),
3543                 .pull_calc_reg          = rk3399_calc_pull_reg_and_bit,
3544                 .drv_calc_reg           = rk3399_calc_drv_reg_and_bit,
3545 };
3546
3547 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
3548         { .compatible = "rockchip,rv1108-pinctrl",
3549                 .data = &rv1108_pin_ctrl },
3550         { .compatible = "rockchip,rk2928-pinctrl",
3551                 .data = &rk2928_pin_ctrl },
3552         { .compatible = "rockchip,rk3036-pinctrl",
3553                 .data = &rk3036_pin_ctrl },
3554         { .compatible = "rockchip,rk3066a-pinctrl",
3555                 .data = &rk3066a_pin_ctrl },
3556         { .compatible = "rockchip,rk3066b-pinctrl",
3557                 .data = &rk3066b_pin_ctrl },
3558         { .compatible = "rockchip,rk3128-pinctrl",
3559                 .data = (void *)&rk3128_pin_ctrl },
3560         { .compatible = "rockchip,rk3188-pinctrl",
3561                 .data = &rk3188_pin_ctrl },
3562         { .compatible = "rockchip,rk3228-pinctrl",
3563                 .data = &rk3228_pin_ctrl },
3564         { .compatible = "rockchip,rk3288-pinctrl",
3565                 .data = &rk3288_pin_ctrl },
3566         { .compatible = "rockchip,rk3328-pinctrl",
3567                 .data = &rk3328_pin_ctrl },
3568         { .compatible = "rockchip,rk3368-pinctrl",
3569                 .data = &rk3368_pin_ctrl },
3570         { .compatible = "rockchip,rk3399-pinctrl",
3571                 .data = &rk3399_pin_ctrl },
3572         {},
3573 };
3574
3575 static struct platform_driver rockchip_pinctrl_driver = {
3576         .probe          = rockchip_pinctrl_probe,
3577         .driver = {
3578                 .name   = "rockchip-pinctrl",
3579                 .pm = &rockchip_pinctrl_dev_pm_ops,
3580                 .of_match_table = rockchip_pinctrl_dt_match,
3581         },
3582 };
3583
3584 static int __init rockchip_pinctrl_drv_register(void)
3585 {
3586         return platform_driver_register(&rockchip_pinctrl_driver);
3587 }
3588 postcore_initcall(rockchip_pinctrl_drv_register);