2 * Generic device tree based pinctrl driver for one register per pin
3 * type pinmux controllers
5 * Copyright (C) 2012 Texas Instruments, Inc.
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
12 #include <linux/init.h>
13 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
17 #include <linux/list.h>
18 #include <linux/interrupt.h>
20 #include <linux/irqchip/chained_irq.h>
23 #include <linux/of_device.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinmux.h>
29 #include <linux/pinctrl/pinconf-generic.h>
31 #include <linux/platform_data/pinctrl-single.h>
34 #include "devicetree.h"
38 #define DRIVER_NAME "pinctrl-single"
39 #define PCS_OFF_DISABLED ~0U
42 * struct pcs_func_vals - mux function register offset and value pair
43 * @reg: register virtual address
44 * @val: register value
46 struct pcs_func_vals {
53 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
54 * and value, enable, disable, mask
55 * @param: config parameter
56 * @val: user input bits in the pinconf register
57 * @enable: enable bits in the pinconf register
58 * @disable: disable bits in the pinconf register
59 * @mask: mask bits in the register value
61 struct pcs_conf_vals {
62 enum pin_config_param param;
70 * struct pcs_conf_type - pinconf property name, pinconf param pair
71 * @name: property name in DTS file
72 * @param: config parameter
74 struct pcs_conf_type {
76 enum pin_config_param param;
80 * struct pcs_function - pinctrl function
81 * @name: pinctrl function name
82 * @vals: register and vals array
83 * @nvals: number of entries in vals array
84 * @pgnames: array of pingroup names the function uses
85 * @npgnames: number of pingroup names the function uses
90 struct pcs_func_vals *vals;
94 struct pcs_conf_vals *conf;
96 struct list_head node;
100 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
101 * @offset: offset base of pins
102 * @npins: number pins with the same mux value of gpio function
103 * @gpiofunc: mux value of gpio function
106 struct pcs_gpiofunc_range {
110 struct list_head node;
114 * struct pcs_data - wrapper for data needed by pinctrl framework
116 * @cur: index to current element
118 * REVISIT: We should be able to drop this eventually by adding
119 * support for registering pins individually in the pinctrl
120 * framework for those drivers that don't need a static array.
123 struct pinctrl_pin_desc *pa;
128 * struct pcs_soc_data - SoC specific settings
129 * @flags: initial SoC specific PCS_FEAT_xxx values
130 * @irq: optional interrupt for the controller
131 * @irq_enable_mask: optional SoC specific interrupt enable mask
132 * @irq_status_mask: optional SoC specific interrupt status mask
133 * @rearm: optional SoC specific wake-up rearm function
135 struct pcs_soc_data {
138 unsigned irq_enable_mask;
139 unsigned irq_status_mask;
144 * struct pcs_device - pinctrl device instance
146 * @base: virtual address of the controller
147 * @size: size of the ioremapped area
149 * @np: device tree node
150 * @pctl: pin controller device
151 * @flags: mask of PCS_FEAT_xxx values
152 * @missing_nr_pinctrl_cells: for legacy binding, may go away
153 * @socdata: soc specific data
154 * @lock: spinlock for register access
155 * @mutex: mutex protecting the lists
156 * @width: bits per mux register
157 * @fmask: function register mask
158 * @fshift: function register shift
159 * @foff: value to turn mux off
160 * @fmax: max number of functions in fmask
161 * @bits_per_mux: number of bits per mux
162 * @bits_per_pin: number of bits per pin
163 * @pins: physical pins on the SoC
164 * @gpiofuncs: list of gpio functions
165 * @irqs: list of interrupt registers
166 * @chip: chip container for this instance
167 * @domain: IRQ domain for this instance
168 * @desc: pin controller descriptor
169 * @read: register read function to use
170 * @write: register write function to use
173 struct resource *res;
177 struct device_node *np;
178 struct pinctrl_dev *pctl;
180 #define PCS_QUIRK_SHARED_IRQ (1 << 2)
181 #define PCS_FEAT_IRQ (1 << 1)
182 #define PCS_FEAT_PINCONF (1 << 0)
183 struct property *missing_nr_pinctrl_cells;
184 struct pcs_soc_data socdata;
193 unsigned bits_per_pin;
194 struct pcs_data pins;
195 struct list_head gpiofuncs;
196 struct list_head irqs;
197 struct irq_chip chip;
198 struct irq_domain *domain;
199 struct pinctrl_desc desc;
200 unsigned (*read)(void __iomem *reg);
201 void (*write)(unsigned val, void __iomem *reg);
204 #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
205 #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
206 #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
208 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
209 unsigned long *config);
210 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
211 unsigned long *configs, unsigned num_configs);
213 static enum pin_config_param pcs_bias[] = {
214 PIN_CONFIG_BIAS_PULL_DOWN,
215 PIN_CONFIG_BIAS_PULL_UP,
219 * This lock class tells lockdep that irqchip core that this single
220 * pinctrl can be in a different category than its parents, so it won't
221 * report false recursion.
223 static struct lock_class_key pcs_lock_class;
225 /* Class for the IRQ request mutex */
226 static struct lock_class_key pcs_request_class;
229 * REVISIT: Reads and writes could eventually use regmap or something
230 * generic. But at least on omaps, some mux registers are performance
231 * critical as they may need to be remuxed every time before and after
232 * idle. Adding tests for register access width for every read and
233 * write like regmap is doing is not desired, and caching the registers
234 * does not help in this case.
237 static unsigned __maybe_unused pcs_readb(void __iomem *reg)
242 static unsigned __maybe_unused pcs_readw(void __iomem *reg)
247 static unsigned __maybe_unused pcs_readl(void __iomem *reg)
252 static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
257 static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
262 static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
267 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
271 struct pcs_device *pcs;
272 unsigned val, mux_bytes;
273 unsigned long offset;
276 pcs = pinctrl_dev_get_drvdata(pctldev);
278 mux_bytes = pcs->width / BITS_PER_BYTE;
279 offset = pin * mux_bytes;
280 val = pcs->read(pcs->base + offset);
281 pa = pcs->res->start + offset;
283 seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME);
286 static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
287 struct pinctrl_map *map, unsigned num_maps)
289 struct pcs_device *pcs;
291 pcs = pinctrl_dev_get_drvdata(pctldev);
292 devm_kfree(pcs->dev, map);
295 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
296 struct device_node *np_config,
297 struct pinctrl_map **map, unsigned *num_maps);
299 static const struct pinctrl_ops pcs_pinctrl_ops = {
300 .get_groups_count = pinctrl_generic_get_group_count,
301 .get_group_name = pinctrl_generic_get_group_name,
302 .get_group_pins = pinctrl_generic_get_group_pins,
303 .pin_dbg_show = pcs_pin_dbg_show,
304 .dt_node_to_map = pcs_dt_node_to_map,
305 .dt_free_map = pcs_dt_free_map,
308 static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
309 struct pcs_function **func)
311 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
312 struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
313 const struct pinctrl_setting_mux *setting;
314 struct function_desc *function;
317 /* If pin is not described in DTS & enabled, mux_setting is NULL. */
318 setting = pdesc->mux_setting;
321 fselector = setting->func;
322 function = pinmux_generic_get_function(pctldev, fselector);
323 *func = function->data;
325 dev_err(pcs->dev, "%s could not find function%i\n",
326 __func__, fselector);
332 static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
335 struct pcs_device *pcs;
336 struct function_desc *function;
337 struct pcs_function *func;
340 pcs = pinctrl_dev_get_drvdata(pctldev);
341 /* If function mask is null, needn't enable it. */
344 function = pinmux_generic_get_function(pctldev, fselector);
345 func = function->data;
349 dev_dbg(pcs->dev, "enabling %s function%i\n",
350 func->name, fselector);
352 for (i = 0; i < func->nvals; i++) {
353 struct pcs_func_vals *vals;
357 vals = &func->vals[i];
358 raw_spin_lock_irqsave(&pcs->lock, flags);
359 val = pcs->read(vals->reg);
361 if (pcs->bits_per_mux)
367 val |= (vals->val & mask);
368 pcs->write(val, vals->reg);
369 raw_spin_unlock_irqrestore(&pcs->lock, flags);
375 static int pcs_request_gpio(struct pinctrl_dev *pctldev,
376 struct pinctrl_gpio_range *range, unsigned pin)
378 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
379 struct pcs_gpiofunc_range *frange = NULL;
380 struct list_head *pos, *tmp;
384 /* If function mask is null, return directly. */
388 list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
389 frange = list_entry(pos, struct pcs_gpiofunc_range, node);
390 if (pin >= frange->offset + frange->npins
391 || pin < frange->offset)
393 mux_bytes = pcs->width / BITS_PER_BYTE;
394 data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask;
395 data |= frange->gpiofunc;
396 pcs->write(data, pcs->base + pin * mux_bytes);
402 static const struct pinmux_ops pcs_pinmux_ops = {
403 .get_functions_count = pinmux_generic_get_function_count,
404 .get_function_name = pinmux_generic_get_function_name,
405 .get_function_groups = pinmux_generic_get_function_groups,
406 .set_mux = pcs_set_mux,
407 .gpio_request_enable = pcs_request_gpio,
410 /* Clear BIAS value */
411 static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
413 unsigned long config;
415 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
416 config = pinconf_to_config_packed(pcs_bias[i], 0);
417 pcs_pinconf_set(pctldev, pin, &config, 1);
422 * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
423 * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
425 static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
427 unsigned long config;
430 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
431 config = pinconf_to_config_packed(pcs_bias[i], 0);
432 if (!pcs_pinconf_get(pctldev, pin, &config))
440 static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
441 unsigned pin, unsigned long *config)
443 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
444 struct pcs_function *func;
445 enum pin_config_param param;
446 unsigned offset = 0, data = 0, i, j, ret;
448 ret = pcs_get_function(pctldev, pin, &func);
452 for (i = 0; i < func->nconfs; i++) {
453 param = pinconf_to_config_param(*config);
454 if (param == PIN_CONFIG_BIAS_DISABLE) {
455 if (pcs_pinconf_bias_disable(pctldev, pin)) {
461 } else if (param != func->conf[i].param) {
465 offset = pin * (pcs->width / BITS_PER_BYTE);
466 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
467 switch (func->conf[i].param) {
469 case PIN_CONFIG_BIAS_PULL_DOWN:
470 case PIN_CONFIG_BIAS_PULL_UP:
471 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
472 if ((data != func->conf[i].enable) ||
473 (data == func->conf[i].disable))
478 case PIN_CONFIG_INPUT_SCHMITT:
479 for (j = 0; j < func->nconfs; j++) {
480 switch (func->conf[j].param) {
481 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
482 if (data != func->conf[j].enable)
491 case PIN_CONFIG_DRIVE_STRENGTH:
492 case PIN_CONFIG_SLEW_RATE:
493 case PIN_CONFIG_LOW_POWER_MODE:
503 static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
504 unsigned pin, unsigned long *configs,
505 unsigned num_configs)
507 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
508 struct pcs_function *func;
509 unsigned offset = 0, shift = 0, i, data, ret;
513 ret = pcs_get_function(pctldev, pin, &func);
517 for (j = 0; j < num_configs; j++) {
518 for (i = 0; i < func->nconfs; i++) {
519 if (pinconf_to_config_param(configs[j])
520 != func->conf[i].param)
523 offset = pin * (pcs->width / BITS_PER_BYTE);
524 data = pcs->read(pcs->base + offset);
525 arg = pinconf_to_config_argument(configs[j]);
526 switch (func->conf[i].param) {
528 case PIN_CONFIG_INPUT_SCHMITT:
529 case PIN_CONFIG_DRIVE_STRENGTH:
530 case PIN_CONFIG_SLEW_RATE:
531 case PIN_CONFIG_LOW_POWER_MODE:
532 shift = ffs(func->conf[i].mask) - 1;
533 data &= ~func->conf[i].mask;
534 data |= (arg << shift) & func->conf[i].mask;
537 case PIN_CONFIG_BIAS_DISABLE:
538 pcs_pinconf_clear_bias(pctldev, pin);
540 case PIN_CONFIG_BIAS_PULL_DOWN:
541 case PIN_CONFIG_BIAS_PULL_UP:
543 pcs_pinconf_clear_bias(pctldev, pin);
545 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
546 data &= ~func->conf[i].mask;
548 data |= func->conf[i].enable;
550 data |= func->conf[i].disable;
555 pcs->write(data, pcs->base + offset);
559 if (i >= func->nconfs)
561 } /* for each config */
566 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
567 unsigned group, unsigned long *config)
569 const unsigned *pins;
570 unsigned npins, old = 0;
573 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
576 for (i = 0; i < npins; i++) {
577 if (pcs_pinconf_get(pctldev, pins[i], config))
579 /* configs do not match between two pins */
580 if (i && (old != *config))
587 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
588 unsigned group, unsigned long *configs,
589 unsigned num_configs)
591 const unsigned *pins;
595 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
598 for (i = 0; i < npins; i++) {
599 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
605 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
606 struct seq_file *s, unsigned pin)
610 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
611 struct seq_file *s, unsigned selector)
615 static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
617 unsigned long config)
619 pinconf_generic_dump_config(pctldev, s, config);
622 static const struct pinconf_ops pcs_pinconf_ops = {
623 .pin_config_get = pcs_pinconf_get,
624 .pin_config_set = pcs_pinconf_set,
625 .pin_config_group_get = pcs_pinconf_group_get,
626 .pin_config_group_set = pcs_pinconf_group_set,
627 .pin_config_dbg_show = pcs_pinconf_dbg_show,
628 .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
629 .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
634 * pcs_add_pin() - add a pin to the static per controller pin array
635 * @pcs: pcs driver instance
636 * @offset: register offset from base
638 static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
641 struct pcs_soc_data *pcs_soc = &pcs->socdata;
642 struct pinctrl_pin_desc *pin;
646 if (i >= pcs->desc.npins) {
647 dev_err(pcs->dev, "too many pins, max %i\n",
652 if (pcs_soc->irq_enable_mask) {
655 val = pcs->read(pcs->base + offset);
656 if (val & pcs_soc->irq_enable_mask) {
657 dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
658 (unsigned long)pcs->res->start + offset, val);
659 val &= ~pcs_soc->irq_enable_mask;
660 pcs->write(val, pcs->base + offset);
664 pin = &pcs->pins.pa[i];
672 * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
673 * @pcs: pcs driver instance
675 * In case of errors, resources are freed in pcs_free_resources.
677 * If your hardware needs holes in the address space, then just set
678 * up multiple driver instances.
680 static int pcs_allocate_pin_table(struct pcs_device *pcs)
682 int mux_bytes, nr_pins, i;
683 int num_pins_in_register = 0;
685 mux_bytes = pcs->width / BITS_PER_BYTE;
687 if (pcs->bits_per_mux) {
688 pcs->bits_per_pin = fls(pcs->fmask);
689 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
690 num_pins_in_register = pcs->width / pcs->bits_per_pin;
692 nr_pins = pcs->size / mux_bytes;
695 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
696 pcs->pins.pa = devm_kzalloc(pcs->dev,
697 sizeof(*pcs->pins.pa) * nr_pins,
702 pcs->desc.pins = pcs->pins.pa;
703 pcs->desc.npins = nr_pins;
705 for (i = 0; i < pcs->desc.npins; i++) {
711 if (pcs->bits_per_mux) {
712 byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE;
713 offset = (byte_num / mux_bytes) * mux_bytes;
714 pin_pos = i % num_pins_in_register;
716 offset = i * mux_bytes;
718 res = pcs_add_pin(pcs, offset, pin_pos);
720 dev_err(pcs->dev, "error adding pins: %i\n", res);
729 * pcs_add_function() - adds a new function to the function list
730 * @pcs: pcs driver instance
731 * @np: device node of the mux entry
732 * @name: name of the function
733 * @vals: array of mux register value pairs used by the function
734 * @nvals: number of mux register value pairs
735 * @pgnames: array of pingroup names for the function
736 * @npgnames: number of pingroup names
738 static struct pcs_function *pcs_add_function(struct pcs_device *pcs,
739 struct device_node *np,
741 struct pcs_func_vals *vals,
743 const char **pgnames,
746 struct pcs_function *function;
749 function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
753 function->vals = vals;
754 function->nvals = nvals;
756 res = pinmux_generic_add_function(pcs->pctl, name,
766 * pcs_get_pin_by_offset() - get a pin index based on the register offset
767 * @pcs: pcs driver instance
768 * @offset: register offset from the base
770 * Note that this is OK as long as the pins are in a static array.
772 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
776 if (offset >= pcs->size) {
777 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
782 if (pcs->bits_per_mux)
783 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
785 index = offset / (pcs->width / BITS_PER_BYTE);
791 * check whether data matches enable bits or disable bits
792 * Return value: 1 for matching enable bits, 0 for matching disable bits,
793 * and negative value for matching failure.
795 static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
801 else if (data == disable)
806 static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
807 unsigned value, unsigned enable, unsigned disable,
810 (*conf)->param = param;
811 (*conf)->val = value;
812 (*conf)->enable = enable;
813 (*conf)->disable = disable;
814 (*conf)->mask = mask;
818 static void add_setting(unsigned long **setting, enum pin_config_param param,
821 **setting = pinconf_to_config_packed(param, arg);
825 /* add pinconf setting with 2 parameters */
826 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
827 const char *name, enum pin_config_param param,
828 struct pcs_conf_vals **conf, unsigned long **settings)
830 unsigned value[2], shift;
833 ret = of_property_read_u32_array(np, name, value, 2);
836 /* set value & mask */
837 value[0] &= value[1];
838 shift = ffs(value[1]) - 1;
839 /* skip enable & disable */
840 add_config(conf, param, value[0], 0, 0, value[1]);
841 add_setting(settings, param, value[0] >> shift);
844 /* add pinconf setting with 4 parameters */
845 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
846 const char *name, enum pin_config_param param,
847 struct pcs_conf_vals **conf, unsigned long **settings)
852 /* value to set, enable, disable, mask */
853 ret = of_property_read_u32_array(np, name, value, 4);
857 dev_err(pcs->dev, "mask field of the property can't be 0\n");
860 value[0] &= value[3];
861 value[1] &= value[3];
862 value[2] &= value[3];
863 ret = pcs_config_match(value[0], value[1], value[2]);
865 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
866 add_config(conf, param, value[0], value[1], value[2], value[3]);
867 add_setting(settings, param, ret);
870 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
871 struct pcs_function *func,
872 struct pinctrl_map **map)
875 struct pinctrl_map *m = *map;
876 int i = 0, nconfs = 0;
877 unsigned long *settings = NULL, *s = NULL;
878 struct pcs_conf_vals *conf = NULL;
879 static const struct pcs_conf_type prop2[] = {
880 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
881 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
882 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
883 { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, },
885 static const struct pcs_conf_type prop4[] = {
886 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
887 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
888 { "pinctrl-single,input-schmitt-enable",
889 PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
892 /* If pinconf isn't supported, don't parse properties in below. */
893 if (!PCS_HAS_PINCONF)
896 /* cacluate how much properties are supported in current node */
897 for (i = 0; i < ARRAY_SIZE(prop2); i++) {
898 if (of_find_property(np, prop2[i].name, NULL))
901 for (i = 0; i < ARRAY_SIZE(prop4); i++) {
902 if (of_find_property(np, prop4[i].name, NULL))
908 func->conf = devm_kzalloc(pcs->dev,
909 sizeof(struct pcs_conf_vals) * nconfs,
913 func->nconfs = nconfs;
914 conf = &(func->conf[0]);
916 settings = devm_kzalloc(pcs->dev, sizeof(unsigned long) * nconfs,
922 for (i = 0; i < ARRAY_SIZE(prop2); i++)
923 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
925 for (i = 0; i < ARRAY_SIZE(prop4); i++)
926 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
928 m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
929 m->data.configs.group_or_pin = np->name;
930 m->data.configs.configs = settings;
931 m->data.configs.num_configs = nconfs;
936 * smux_parse_one_pinctrl_entry() - parses a device tree mux entry
937 * @pctldev: pin controller device
938 * @pcs: pinctrl driver instance
939 * @np: device node of the mux entry
941 * @num_maps: number of map
942 * @pgnames: pingroup names
944 * Note that this binding currently supports only sets of one register + value.
946 * Also note that this driver tries to avoid understanding pin and function
947 * names because of the extra bloat they would cause especially in the case of
948 * a large number of pins. This driver just sets what is specified for the board
949 * in the .dts file. Further user space debugging tools can be developed to
950 * decipher the pin and function names using debugfs.
952 * If you are concerned about the boot time, set up the static pins in
953 * the bootloader, and only set up selected pins as device tree entries.
955 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
956 struct device_node *np,
957 struct pinctrl_map **map,
959 const char **pgnames)
961 const char *name = "pinctrl-single,pins";
962 struct pcs_func_vals *vals;
963 int rows, *pins, found = 0, res = -ENOMEM, i;
964 struct pcs_function *function;
966 rows = pinctrl_count_index_with_args(np, name);
968 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
972 vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL);
976 pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows, GFP_KERNEL);
980 for (i = 0; i < rows; i++) {
981 struct of_phandle_args pinctrl_spec;
985 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
989 if (pinctrl_spec.args_count < 2) {
990 dev_err(pcs->dev, "invalid args_count for spec: %i\n",
991 pinctrl_spec.args_count);
995 /* Index plus one value cell */
996 offset = pinctrl_spec.args[0];
997 vals[found].reg = pcs->base + offset;
998 vals[found].val = pinctrl_spec.args[1];
1000 dev_dbg(pcs->dev, "%s index: 0x%x value: 0x%x\n",
1001 pinctrl_spec.np->name, offset, pinctrl_spec.args[1]);
1003 pin = pcs_get_pin_by_offset(pcs, offset);
1006 "could not add functions for %s %ux\n",
1010 pins[found++] = pin;
1013 pgnames[0] = np->name;
1014 function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1020 res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1024 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1025 (*map)->data.mux.group = np->name;
1026 (*map)->data.mux.function = np->name;
1028 if (PCS_HAS_PINCONF) {
1029 res = pcs_parse_pinconf(pcs, np, function, map);
1031 goto free_pingroups;
1039 pinctrl_generic_remove_last_group(pcs->pctl);
1042 pinmux_generic_remove_last_function(pcs->pctl);
1045 devm_kfree(pcs->dev, pins);
1048 devm_kfree(pcs->dev, vals);
1053 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1054 struct device_node *np,
1055 struct pinctrl_map **map,
1057 const char **pgnames)
1059 const char *name = "pinctrl-single,bits";
1060 struct pcs_func_vals *vals;
1061 int rows, *pins, found = 0, res = -ENOMEM, i;
1063 struct pcs_function *function;
1065 rows = pinctrl_count_index_with_args(np, name);
1067 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1071 npins_in_row = pcs->width / pcs->bits_per_pin;
1073 vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows * npins_in_row,
1078 pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows * npins_in_row,
1083 for (i = 0; i < rows; i++) {
1084 struct of_phandle_args pinctrl_spec;
1085 unsigned offset, val;
1086 unsigned mask, bit_pos, val_pos, mask_pos, submask;
1087 unsigned pin_num_from_lsb;
1090 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1094 if (pinctrl_spec.args_count < 3) {
1095 dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1096 pinctrl_spec.args_count);
1100 /* Index plus two value cells */
1101 offset = pinctrl_spec.args[0];
1102 val = pinctrl_spec.args[1];
1103 mask = pinctrl_spec.args[2];
1105 dev_dbg(pcs->dev, "%s index: 0x%x value: 0x%x mask: 0x%x\n",
1106 pinctrl_spec.np->name, offset, val, mask);
1108 /* Parse pins in each row from LSB */
1110 bit_pos = __ffs(mask);
1111 pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1112 mask_pos = ((pcs->fmask) << bit_pos);
1113 val_pos = val & mask_pos;
1114 submask = mask & mask_pos;
1116 if ((mask & mask_pos) == 0) {
1118 "Invalid mask for %s at 0x%x\n",
1125 if (submask != mask_pos) {
1127 "Invalid submask 0x%x for %s at 0x%x\n",
1128 submask, np->name, offset);
1132 vals[found].mask = submask;
1133 vals[found].reg = pcs->base + offset;
1134 vals[found].val = val_pos;
1136 pin = pcs_get_pin_by_offset(pcs, offset);
1139 "could not add functions for %s %ux\n",
1143 pins[found++] = pin + pin_num_from_lsb;
1147 pgnames[0] = np->name;
1148 function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1154 res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1158 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1159 (*map)->data.mux.group = np->name;
1160 (*map)->data.mux.function = np->name;
1162 if (PCS_HAS_PINCONF) {
1163 dev_err(pcs->dev, "pinconf not supported\n");
1164 goto free_pingroups;
1171 pinctrl_generic_remove_last_group(pcs->pctl);
1174 pinmux_generic_remove_last_function(pcs->pctl);
1176 devm_kfree(pcs->dev, pins);
1179 devm_kfree(pcs->dev, vals);
1184 * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1185 * @pctldev: pinctrl instance
1186 * @np_config: device tree pinmux entry
1187 * @map: array of map entries
1188 * @num_maps: number of maps
1190 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1191 struct device_node *np_config,
1192 struct pinctrl_map **map, unsigned *num_maps)
1194 struct pcs_device *pcs;
1195 const char **pgnames;
1198 pcs = pinctrl_dev_get_drvdata(pctldev);
1200 /* create 2 maps. One is for pinmux, and the other is for pinconf. */
1201 *map = devm_kzalloc(pcs->dev, sizeof(**map) * 2, GFP_KERNEL);
1207 pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1213 if (pcs->bits_per_mux) {
1214 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1217 dev_err(pcs->dev, "no pins entries for %s\n",
1222 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1225 dev_err(pcs->dev, "no pins entries for %s\n",
1234 devm_kfree(pcs->dev, pgnames);
1236 devm_kfree(pcs->dev, *map);
1242 * pcs_irq_free() - free interrupt
1243 * @pcs: pcs driver instance
1245 static void pcs_irq_free(struct pcs_device *pcs)
1247 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1249 if (pcs_soc->irq < 0)
1253 irq_domain_remove(pcs->domain);
1255 if (PCS_QUIRK_HAS_SHARED_IRQ)
1256 free_irq(pcs_soc->irq, pcs_soc);
1258 irq_set_chained_handler(pcs_soc->irq, NULL);
1262 * pcs_free_resources() - free memory used by this driver
1263 * @pcs: pcs driver instance
1265 static void pcs_free_resources(struct pcs_device *pcs)
1268 pinctrl_unregister(pcs->pctl);
1270 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1271 if (pcs->missing_nr_pinctrl_cells)
1272 of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells);
1276 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1278 const char *propname = "pinctrl-single,gpio-range";
1279 const char *cellname = "#pinctrl-single,gpio-range-cells";
1280 struct of_phandle_args gpiospec;
1281 struct pcs_gpiofunc_range *range;
1284 for (i = 0; ; i++) {
1285 ret = of_parse_phandle_with_args(node, propname, cellname,
1287 /* Do not treat it as error. Only treat it as end condition. */
1292 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1297 range->offset = gpiospec.args[0];
1298 range->npins = gpiospec.args[1];
1299 range->gpiofunc = gpiospec.args[2];
1300 mutex_lock(&pcs->mutex);
1301 list_add_tail(&range->node, &pcs->gpiofuncs);
1302 mutex_unlock(&pcs->mutex);
1307 * @reg: virtual address of interrupt register
1308 * @hwirq: hardware irq number
1309 * @irq: virtual irq number
1312 struct pcs_interrupt {
1314 irq_hw_number_t hwirq;
1316 struct list_head node;
1320 * pcs_irq_set() - enables or disables an interrupt
1322 * Note that this currently assumes one interrupt per pinctrl
1323 * register that is typically used for wake-up events.
1325 static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1326 int irq, const bool enable)
1328 struct pcs_device *pcs;
1329 struct list_head *pos;
1332 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1333 list_for_each(pos, &pcs->irqs) {
1334 struct pcs_interrupt *pcswi;
1337 pcswi = list_entry(pos, struct pcs_interrupt, node);
1338 if (irq != pcswi->irq)
1341 soc_mask = pcs_soc->irq_enable_mask;
1342 raw_spin_lock(&pcs->lock);
1343 mask = pcs->read(pcswi->reg);
1348 pcs->write(mask, pcswi->reg);
1350 /* flush posted write */
1351 mask = pcs->read(pcswi->reg);
1352 raw_spin_unlock(&pcs->lock);
1360 * pcs_irq_mask() - mask pinctrl interrupt
1361 * @d: interrupt data
1363 static void pcs_irq_mask(struct irq_data *d)
1365 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1367 pcs_irq_set(pcs_soc, d->irq, false);
1371 * pcs_irq_unmask() - unmask pinctrl interrupt
1372 * @d: interrupt data
1374 static void pcs_irq_unmask(struct irq_data *d)
1376 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1378 pcs_irq_set(pcs_soc, d->irq, true);
1382 * pcs_irq_set_wake() - toggle the suspend and resume wake up
1383 * @d: interrupt data
1384 * @state: wake-up state
1386 * Note that this should be called only for suspend and resume.
1387 * For runtime PM, the wake-up events should be enabled by default.
1389 static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1400 * pcs_irq_handle() - common interrupt handler
1401 * @pcs_irq: interrupt data
1403 * Note that this currently assumes we have one interrupt bit per
1404 * mux register. This interrupt is typically used for wake-up events.
1405 * For more complex interrupts different handlers can be specified.
1407 static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1409 struct pcs_device *pcs;
1410 struct list_head *pos;
1413 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1414 list_for_each(pos, &pcs->irqs) {
1415 struct pcs_interrupt *pcswi;
1418 pcswi = list_entry(pos, struct pcs_interrupt, node);
1419 raw_spin_lock(&pcs->lock);
1420 mask = pcs->read(pcswi->reg);
1421 raw_spin_unlock(&pcs->lock);
1422 if (mask & pcs_soc->irq_status_mask) {
1423 generic_handle_irq(irq_find_mapping(pcs->domain,
1433 * pcs_irq_handler() - handler for the shared interrupt case
1437 * Use this for cases where multiple instances of
1438 * pinctrl-single share a single interrupt like on omaps.
1440 static irqreturn_t pcs_irq_handler(int irq, void *d)
1442 struct pcs_soc_data *pcs_soc = d;
1444 return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1448 * pcs_irq_handle() - handler for the dedicated chained interrupt case
1450 * @desc: interrupt descriptor
1452 * Use this if you have a separate interrupt for each
1453 * pinctrl-single instance.
1455 static void pcs_irq_chain_handler(struct irq_desc *desc)
1457 struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1458 struct irq_chip *chip;
1460 chip = irq_desc_get_chip(desc);
1461 chained_irq_enter(chip, desc);
1462 pcs_irq_handle(pcs_soc);
1463 /* REVISIT: export and add handle_bad_irq(irq, desc)? */
1464 chained_irq_exit(chip, desc);
1467 static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1468 irq_hw_number_t hwirq)
1470 struct pcs_soc_data *pcs_soc = d->host_data;
1471 struct pcs_device *pcs;
1472 struct pcs_interrupt *pcswi;
1474 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1475 pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1479 pcswi->reg = pcs->base + hwirq;
1480 pcswi->hwirq = hwirq;
1483 mutex_lock(&pcs->mutex);
1484 list_add_tail(&pcswi->node, &pcs->irqs);
1485 mutex_unlock(&pcs->mutex);
1487 irq_set_chip_data(irq, pcs_soc);
1488 irq_set_chip_and_handler(irq, &pcs->chip,
1490 irq_set_lockdep_class(irq, &pcs_lock_class, &pcs_request_class);
1491 irq_set_noprobe(irq);
1496 static const struct irq_domain_ops pcs_irqdomain_ops = {
1497 .map = pcs_irqdomain_map,
1498 .xlate = irq_domain_xlate_onecell,
1502 * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1503 * @pcs: pcs driver instance
1504 * @np: device node pointer
1506 static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1507 struct device_node *np)
1509 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1510 const char *name = "pinctrl";
1513 if (!pcs_soc->irq_enable_mask ||
1514 !pcs_soc->irq_status_mask) {
1519 INIT_LIST_HEAD(&pcs->irqs);
1520 pcs->chip.name = name;
1521 pcs->chip.irq_ack = pcs_irq_mask;
1522 pcs->chip.irq_mask = pcs_irq_mask;
1523 pcs->chip.irq_unmask = pcs_irq_unmask;
1524 pcs->chip.irq_set_wake = pcs_irq_set_wake;
1526 if (PCS_QUIRK_HAS_SHARED_IRQ) {
1529 res = request_irq(pcs_soc->irq, pcs_irq_handler,
1530 IRQF_SHARED | IRQF_NO_SUSPEND |
1538 irq_set_chained_handler_and_data(pcs_soc->irq,
1539 pcs_irq_chain_handler,
1544 * We can use the register offset as the hardirq
1545 * number as irq_domain_add_simple maps them lazily.
1546 * This way we can easily support more than one
1547 * interrupt per function if needed.
1549 num_irqs = pcs->size;
1551 pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
1555 irq_set_chained_handler(pcs_soc->irq, NULL);
1563 static int pinctrl_single_suspend(struct platform_device *pdev,
1566 struct pcs_device *pcs;
1568 pcs = platform_get_drvdata(pdev);
1572 return pinctrl_force_sleep(pcs->pctl);
1575 static int pinctrl_single_resume(struct platform_device *pdev)
1577 struct pcs_device *pcs;
1579 pcs = platform_get_drvdata(pdev);
1583 return pinctrl_force_default(pcs->pctl);
1588 * pcs_quirk_missing_pinctrl_cells - handle legacy binding
1589 * @pcs: pinctrl driver instance
1590 * @np: device tree node
1591 * @cells: number of cells
1593 * Handle legacy binding with no #pinctrl-cells. This should be
1594 * always two pinctrl-single,bit-per-mux and one for others.
1595 * At some point we may want to consider removing this.
1597 static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs,
1598 struct device_node *np,
1602 const char *name = "#pinctrl-cells";
1606 error = of_property_read_u32(np, name, &val);
1610 dev_warn(pcs->dev, "please update dts to use %s = <%i>\n",
1613 p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL);
1617 p->length = sizeof(__be32);
1618 p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL);
1621 *(__be32 *)p->value = cpu_to_be32(cells);
1623 p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL);
1627 pcs->missing_nr_pinctrl_cells = p;
1629 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1630 error = of_add_property(np, pcs->missing_nr_pinctrl_cells);
1636 static int pcs_probe(struct platform_device *pdev)
1638 struct device_node *np = pdev->dev.of_node;
1639 struct pcs_pdata *pdata;
1640 struct resource *res;
1641 struct pcs_device *pcs;
1642 const struct pcs_soc_data *soc;
1645 soc = of_device_get_match_data(&pdev->dev);
1649 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1653 pcs->dev = &pdev->dev;
1655 raw_spin_lock_init(&pcs->lock);
1656 mutex_init(&pcs->mutex);
1657 INIT_LIST_HEAD(&pcs->gpiofuncs);
1658 pcs->flags = soc->flags;
1659 memcpy(&pcs->socdata, soc, sizeof(*soc));
1661 ret = of_property_read_u32(np, "pinctrl-single,register-width",
1664 dev_err(pcs->dev, "register width not specified\n");
1669 ret = of_property_read_u32(np, "pinctrl-single,function-mask",
1672 pcs->fshift = __ffs(pcs->fmask);
1673 pcs->fmax = pcs->fmask >> pcs->fshift;
1675 /* If mask property doesn't exist, function mux is invalid. */
1681 ret = of_property_read_u32(np, "pinctrl-single,function-off",
1684 pcs->foff = PCS_OFF_DISABLED;
1686 pcs->bits_per_mux = of_property_read_bool(np,
1687 "pinctrl-single,bit-per-mux");
1688 ret = pcs_quirk_missing_pinctrl_cells(pcs, np,
1689 pcs->bits_per_mux ? 2 : 1);
1691 dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n");
1696 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1698 dev_err(pcs->dev, "could not get resource\n");
1702 pcs->res = devm_request_mem_region(pcs->dev, res->start,
1703 resource_size(res), DRIVER_NAME);
1705 dev_err(pcs->dev, "could not get mem_region\n");
1709 pcs->size = resource_size(pcs->res);
1710 pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1712 dev_err(pcs->dev, "could not ioremap\n");
1716 platform_set_drvdata(pdev, pcs);
1718 switch (pcs->width) {
1720 pcs->read = pcs_readb;
1721 pcs->write = pcs_writeb;
1724 pcs->read = pcs_readw;
1725 pcs->write = pcs_writew;
1728 pcs->read = pcs_readl;
1729 pcs->write = pcs_writel;
1735 pcs->desc.name = DRIVER_NAME;
1736 pcs->desc.pctlops = &pcs_pinctrl_ops;
1737 pcs->desc.pmxops = &pcs_pinmux_ops;
1738 if (PCS_HAS_PINCONF)
1739 pcs->desc.confops = &pcs_pinconf_ops;
1740 pcs->desc.owner = THIS_MODULE;
1742 ret = pcs_allocate_pin_table(pcs);
1746 ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl);
1748 dev_err(pcs->dev, "could not register single pinctrl driver\n");
1752 ret = pcs_add_gpio_func(np, pcs);
1756 pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1757 if (pcs->socdata.irq)
1758 pcs->flags |= PCS_FEAT_IRQ;
1760 /* We still need auxdata for some omaps for PRM interrupts */
1761 pdata = dev_get_platdata(&pdev->dev);
1764 pcs->socdata.rearm = pdata->rearm;
1766 pcs->socdata.irq = pdata->irq;
1767 pcs->flags |= PCS_FEAT_IRQ;
1772 ret = pcs_irq_init_chained_handler(pcs, np);
1774 dev_warn(pcs->dev, "initialized with no interrupts\n");
1777 dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size);
1779 return pinctrl_enable(pcs->pctl);
1782 pcs_free_resources(pcs);
1787 static int pcs_remove(struct platform_device *pdev)
1789 struct pcs_device *pcs = platform_get_drvdata(pdev);
1794 pcs_free_resources(pcs);
1799 static const struct pcs_soc_data pinctrl_single_omap_wkup = {
1800 .flags = PCS_QUIRK_SHARED_IRQ,
1801 .irq_enable_mask = (1 << 14), /* OMAP_WAKEUP_EN */
1802 .irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */
1805 static const struct pcs_soc_data pinctrl_single_dra7 = {
1806 .irq_enable_mask = (1 << 24), /* WAKEUPENABLE */
1807 .irq_status_mask = (1 << 25), /* WAKEUPEVENT */
1810 static const struct pcs_soc_data pinctrl_single_am437x = {
1811 .flags = PCS_QUIRK_SHARED_IRQ,
1812 .irq_enable_mask = (1 << 29), /* OMAP_WAKEUP_EN */
1813 .irq_status_mask = (1 << 30), /* OMAP_WAKEUP_EVENT */
1816 static const struct pcs_soc_data pinctrl_single = {
1819 static const struct pcs_soc_data pinconf_single = {
1820 .flags = PCS_FEAT_PINCONF,
1823 static const struct of_device_id pcs_of_match[] = {
1824 { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1825 { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1826 { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1827 { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
1828 { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
1829 { .compatible = "pinctrl-single", .data = &pinctrl_single },
1830 { .compatible = "pinconf-single", .data = &pinconf_single },
1833 MODULE_DEVICE_TABLE(of, pcs_of_match);
1835 static struct platform_driver pcs_driver = {
1837 .remove = pcs_remove,
1839 .name = DRIVER_NAME,
1840 .of_match_table = pcs_of_match,
1843 .suspend = pinctrl_single_suspend,
1844 .resume = pinctrl_single_resume,
1848 module_platform_driver(pcs_driver);
1850 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
1851 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
1852 MODULE_LICENSE("GPL v2");