1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander
5 * Copyright (C) 2019 STMicroelectronics
6 * Author(s): Amelie Delaunay <amelie.delaunay@st.com>.
8 #include <linux/gpio/driver.h>
9 #include <linux/interrupt.h>
10 #include <linux/mfd/stmfx.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/pinctrl/pinconf.h>
14 #include <linux/pinctrl/pinmux.h>
17 #include "pinctrl-utils.h"
20 /* GPIO_STATE1 0x10, GPIO_STATE2 0x11, GPIO_STATE3 0x12 */
21 #define STMFX_REG_GPIO_STATE STMFX_REG_GPIO_STATE1 /* R */
22 /* GPIO_DIR1 0x60, GPIO_DIR2 0x61, GPIO_DIR3 0x63 */
23 #define STMFX_REG_GPIO_DIR STMFX_REG_GPIO_DIR1 /* RW */
24 /* GPIO_TYPE1 0x64, GPIO_TYPE2 0x65, GPIO_TYPE3 0x66 */
25 #define STMFX_REG_GPIO_TYPE STMFX_REG_GPIO_TYPE1 /* RW */
26 /* GPIO_PUPD1 0x68, GPIO_PUPD2 0x69, GPIO_PUPD3 0x6A */
27 #define STMFX_REG_GPIO_PUPD STMFX_REG_GPIO_PUPD1 /* RW */
28 /* GPO_SET1 0x6C, GPO_SET2 0x6D, GPO_SET3 0x6E */
29 #define STMFX_REG_GPO_SET STMFX_REG_GPO_SET1 /* RW */
30 /* GPO_CLR1 0x70, GPO_CLR2 0x71, GPO_CLR3 0x72 */
31 #define STMFX_REG_GPO_CLR STMFX_REG_GPO_CLR1 /* RW */
32 /* IRQ_GPI_SRC1 0x48, IRQ_GPI_SRC2 0x49, IRQ_GPI_SRC3 0x4A */
33 #define STMFX_REG_IRQ_GPI_SRC STMFX_REG_IRQ_GPI_SRC1 /* RW */
34 /* IRQ_GPI_EVT1 0x4C, IRQ_GPI_EVT2 0x4D, IRQ_GPI_EVT3 0x4E */
35 #define STMFX_REG_IRQ_GPI_EVT STMFX_REG_IRQ_GPI_EVT1 /* RW */
36 /* IRQ_GPI_TYPE1 0x50, IRQ_GPI_TYPE2 0x51, IRQ_GPI_TYPE3 0x52 */
37 #define STMFX_REG_IRQ_GPI_TYPE STMFX_REG_IRQ_GPI_TYPE1 /* RW */
38 /* IRQ_GPI_PENDING1 0x0C, IRQ_GPI_PENDING2 0x0D, IRQ_GPI_PENDING3 0x0E*/
39 #define STMFX_REG_IRQ_GPI_PENDING STMFX_REG_IRQ_GPI_PENDING1 /* R */
40 /* IRQ_GPI_ACK1 0x54, IRQ_GPI_ACK2 0x55, IRQ_GPI_ACK3 0x56 */
41 #define STMFX_REG_IRQ_GPI_ACK STMFX_REG_IRQ_GPI_ACK1 /* RW */
43 #define NR_GPIO_REGS 3
44 #define NR_GPIOS_PER_REG 8
45 #define get_reg(offset) ((offset) / NR_GPIOS_PER_REG)
46 #define get_shift(offset) ((offset) % NR_GPIOS_PER_REG)
47 #define get_mask(offset) (BIT(get_shift(offset)))
50 * STMFX pinctrl can have up to 24 pins if STMFX other functions are not used.
51 * Pins availability is managed thanks to gpio-ranges property.
53 static const struct pinctrl_pin_desc stmfx_pins[] = {
54 PINCTRL_PIN(0, "gpio0"),
55 PINCTRL_PIN(1, "gpio1"),
56 PINCTRL_PIN(2, "gpio2"),
57 PINCTRL_PIN(3, "gpio3"),
58 PINCTRL_PIN(4, "gpio4"),
59 PINCTRL_PIN(5, "gpio5"),
60 PINCTRL_PIN(6, "gpio6"),
61 PINCTRL_PIN(7, "gpio7"),
62 PINCTRL_PIN(8, "gpio8"),
63 PINCTRL_PIN(9, "gpio9"),
64 PINCTRL_PIN(10, "gpio10"),
65 PINCTRL_PIN(11, "gpio11"),
66 PINCTRL_PIN(12, "gpio12"),
67 PINCTRL_PIN(13, "gpio13"),
68 PINCTRL_PIN(14, "gpio14"),
69 PINCTRL_PIN(15, "gpio15"),
70 PINCTRL_PIN(16, "agpio0"),
71 PINCTRL_PIN(17, "agpio1"),
72 PINCTRL_PIN(18, "agpio2"),
73 PINCTRL_PIN(19, "agpio3"),
74 PINCTRL_PIN(20, "agpio4"),
75 PINCTRL_PIN(21, "agpio5"),
76 PINCTRL_PIN(22, "agpio6"),
77 PINCTRL_PIN(23, "agpio7"),
80 struct stmfx_pinctrl {
83 struct pinctrl_dev *pctl_dev;
84 struct pinctrl_desc pctl_desc;
85 struct gpio_chip gpio_chip;
86 struct irq_chip irq_chip;
87 struct mutex lock; /* IRQ bus lock */
88 unsigned long gpio_valid_mask;
89 /* Cache of IRQ_GPI_* registers for bus_lock */
90 u8 irq_gpi_src[NR_GPIO_REGS];
91 u8 irq_gpi_type[NR_GPIO_REGS];
92 u8 irq_gpi_evt[NR_GPIO_REGS];
93 u8 irq_toggle_edge[NR_GPIO_REGS];
95 /* Backup of GPIO_* registers for suspend/resume */
96 u8 bkp_gpio_state[NR_GPIO_REGS];
97 u8 bkp_gpio_dir[NR_GPIO_REGS];
98 u8 bkp_gpio_type[NR_GPIO_REGS];
99 u8 bkp_gpio_pupd[NR_GPIO_REGS];
103 static int stmfx_gpio_get(struct gpio_chip *gc, unsigned int offset)
105 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
106 u32 reg = STMFX_REG_GPIO_STATE + get_reg(offset);
107 u32 mask = get_mask(offset);
111 ret = regmap_read(pctl->stmfx->map, reg, &value);
113 return ret ? ret : !!(value & mask);
116 static void stmfx_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
118 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
119 u32 reg = value ? STMFX_REG_GPO_SET : STMFX_REG_GPO_CLR;
120 u32 mask = get_mask(offset);
122 regmap_write_bits(pctl->stmfx->map, reg + get_reg(offset),
126 static int stmfx_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
128 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
129 u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
130 u32 mask = get_mask(offset);
134 ret = regmap_read(pctl->stmfx->map, reg, &val);
136 * On stmfx, gpio pins direction is (0)input, (1)output.
137 * .get_direction returns 0=out, 1=in
140 return ret ? ret : !(val & mask);
143 static int stmfx_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
145 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
146 u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
147 u32 mask = get_mask(offset);
149 return regmap_write_bits(pctl->stmfx->map, reg, mask, 0);
152 static int stmfx_gpio_direction_output(struct gpio_chip *gc,
153 unsigned int offset, int value)
155 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
156 u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
157 u32 mask = get_mask(offset);
159 stmfx_gpio_set(gc, offset, value);
161 return regmap_write_bits(pctl->stmfx->map, reg, mask, mask);
164 static int stmfx_pinconf_get_pupd(struct stmfx_pinctrl *pctl,
167 u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset);
168 u32 pupd, mask = get_mask(offset);
171 ret = regmap_read(pctl->stmfx->map, reg, &pupd);
175 return !!(pupd & mask);
178 static int stmfx_pinconf_set_pupd(struct stmfx_pinctrl *pctl,
179 unsigned int offset, u32 pupd)
181 u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset);
182 u32 mask = get_mask(offset);
184 return regmap_write_bits(pctl->stmfx->map, reg, mask, pupd ? mask : 0);
187 static int stmfx_pinconf_get_type(struct stmfx_pinctrl *pctl,
190 u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset);
191 u32 type, mask = get_mask(offset);
194 ret = regmap_read(pctl->stmfx->map, reg, &type);
198 return !!(type & mask);
201 static int stmfx_pinconf_set_type(struct stmfx_pinctrl *pctl,
202 unsigned int offset, u32 type)
204 u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset);
205 u32 mask = get_mask(offset);
207 return regmap_write_bits(pctl->stmfx->map, reg, mask, type ? mask : 0);
210 static int stmfx_pinconf_get(struct pinctrl_dev *pctldev,
211 unsigned int pin, unsigned long *config)
213 struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
214 u32 param = pinconf_to_config_param(*config);
215 struct pinctrl_gpio_range *range;
217 int ret, dir, type, pupd;
219 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
223 dir = stmfx_gpio_get_direction(&pctl->gpio_chip, pin);
226 type = stmfx_pinconf_get_type(pctl, pin);
229 pupd = stmfx_pinconf_get_pupd(pctl, pin);
234 case PIN_CONFIG_BIAS_DISABLE:
235 if ((!dir && (!type || !pupd)) || (dir && !type))
238 case PIN_CONFIG_BIAS_PULL_DOWN:
239 if (dir && type && !pupd)
242 case PIN_CONFIG_BIAS_PULL_UP:
246 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
247 if ((!dir && type) || (dir && !type))
250 case PIN_CONFIG_DRIVE_PUSH_PULL:
251 if ((!dir && !type) || (dir && type))
254 case PIN_CONFIG_OUTPUT:
258 ret = stmfx_gpio_get(&pctl->gpio_chip, pin);
268 *config = pinconf_to_config_packed(param, arg);
273 static int stmfx_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
274 unsigned long *configs, unsigned int num_configs)
276 struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
277 struct pinctrl_gpio_range *range;
278 enum pin_config_param param;
282 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
284 dev_err(pctldev->dev, "pin %d is not available\n", pin);
288 dir = stmfx_gpio_get_direction(&pctl->gpio_chip, pin);
292 for (i = 0; i < num_configs; i++) {
293 param = pinconf_to_config_param(configs[i]);
294 arg = pinconf_to_config_argument(configs[i]);
297 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
298 case PIN_CONFIG_BIAS_DISABLE:
299 case PIN_CONFIG_DRIVE_PUSH_PULL:
300 ret = stmfx_pinconf_set_type(pctl, pin, 0);
304 case PIN_CONFIG_BIAS_PULL_DOWN:
305 ret = stmfx_pinconf_set_type(pctl, pin, 1);
308 ret = stmfx_pinconf_set_pupd(pctl, pin, 0);
312 case PIN_CONFIG_BIAS_PULL_UP:
313 ret = stmfx_pinconf_set_type(pctl, pin, 1);
316 ret = stmfx_pinconf_set_pupd(pctl, pin, 1);
320 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
321 ret = stmfx_pinconf_set_type(pctl, pin, 1);
325 case PIN_CONFIG_OUTPUT:
326 ret = stmfx_gpio_direction_output(&pctl->gpio_chip,
339 static void stmfx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
340 struct seq_file *s, unsigned int offset)
342 struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
343 struct pinctrl_gpio_range *range;
344 int dir, type, pupd, val;
346 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, offset);
350 dir = stmfx_gpio_get_direction(&pctl->gpio_chip, offset);
353 type = stmfx_pinconf_get_type(pctl, offset);
356 pupd = stmfx_pinconf_get_pupd(pctl, offset);
359 val = stmfx_gpio_get(&pctl->gpio_chip, offset);
364 seq_printf(s, "output %s ", val ? "high" : "low");
366 seq_printf(s, "open drain %s internal pull-up ",
367 pupd ? "with" : "without");
369 seq_puts(s, "push pull no pull ");
371 seq_printf(s, "input %s ", val ? "high" : "low");
373 seq_printf(s, "with internal pull-%s ",
374 pupd ? "up" : "down");
376 seq_printf(s, "%s ", pupd ? "floating" : "analog");
380 static const struct pinconf_ops stmfx_pinconf_ops = {
381 .pin_config_get = stmfx_pinconf_get,
382 .pin_config_set = stmfx_pinconf_set,
383 .pin_config_dbg_show = stmfx_pinconf_dbg_show,
386 static int stmfx_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
391 static const char *stmfx_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
392 unsigned int selector)
397 static int stmfx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
398 unsigned int selector,
399 const unsigned int **pins,
400 unsigned int *num_pins)
405 static const struct pinctrl_ops stmfx_pinctrl_ops = {
406 .get_groups_count = stmfx_pinctrl_get_groups_count,
407 .get_group_name = stmfx_pinctrl_get_group_name,
408 .get_group_pins = stmfx_pinctrl_get_group_pins,
409 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
410 .dt_free_map = pinctrl_utils_free_map,
413 static void stmfx_pinctrl_irq_mask(struct irq_data *data)
415 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
416 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
417 u32 reg = get_reg(data->hwirq);
418 u32 mask = get_mask(data->hwirq);
420 pctl->irq_gpi_src[reg] &= ~mask;
423 static void stmfx_pinctrl_irq_unmask(struct irq_data *data)
425 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
426 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
427 u32 reg = get_reg(data->hwirq);
428 u32 mask = get_mask(data->hwirq);
430 pctl->irq_gpi_src[reg] |= mask;
433 static int stmfx_pinctrl_irq_set_type(struct irq_data *data, unsigned int type)
435 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
436 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
437 u32 reg = get_reg(data->hwirq);
438 u32 mask = get_mask(data->hwirq);
440 if (type == IRQ_TYPE_NONE)
443 if (type & IRQ_TYPE_EDGE_BOTH) {
444 pctl->irq_gpi_evt[reg] |= mask;
445 irq_set_handler_locked(data, handle_edge_irq);
447 pctl->irq_gpi_evt[reg] &= ~mask;
448 irq_set_handler_locked(data, handle_level_irq);
451 if ((type & IRQ_TYPE_EDGE_RISING) || (type & IRQ_TYPE_LEVEL_HIGH))
452 pctl->irq_gpi_type[reg] |= mask;
454 pctl->irq_gpi_type[reg] &= ~mask;
457 * In case of (type & IRQ_TYPE_EDGE_BOTH), we need to know current
458 * GPIO value to set the right edge trigger. But in atomic context
459 * here we can't access registers over I2C. That's why (type &
460 * IRQ_TYPE_EDGE_BOTH) will be managed in .irq_sync_unlock.
463 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
464 pctl->irq_toggle_edge[reg] |= mask;
466 pctl->irq_toggle_edge[reg] &= mask;
471 static void stmfx_pinctrl_irq_bus_lock(struct irq_data *data)
473 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
474 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
476 mutex_lock(&pctl->lock);
479 static void stmfx_pinctrl_irq_bus_sync_unlock(struct irq_data *data)
481 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
482 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
483 u32 reg = get_reg(data->hwirq);
484 u32 mask = get_mask(data->hwirq);
487 * In case of IRQ_TYPE_EDGE_BOTH), read the current GPIO value
488 * (this couldn't be done in .irq_set_type because of atomic context)
489 * to set the right irq trigger type.
491 if (pctl->irq_toggle_edge[reg] & mask) {
492 if (stmfx_gpio_get(gpio_chip, data->hwirq))
493 pctl->irq_gpi_type[reg] &= ~mask;
495 pctl->irq_gpi_type[reg] |= mask;
498 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_EVT,
499 pctl->irq_gpi_evt, NR_GPIO_REGS);
500 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_TYPE,
501 pctl->irq_gpi_type, NR_GPIO_REGS);
502 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
503 pctl->irq_gpi_src, NR_GPIO_REGS);
505 mutex_unlock(&pctl->lock);
508 static int stmfx_gpio_irq_request_resources(struct irq_data *data)
510 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
513 ret = stmfx_gpio_direction_input(gpio_chip, data->hwirq);
517 return gpiochip_reqres_irq(gpio_chip, data->hwirq);
520 static void stmfx_gpio_irq_release_resources(struct irq_data *data)
522 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
524 return gpiochip_relres_irq(gpio_chip, data->hwirq);
527 static void stmfx_pinctrl_irq_toggle_trigger(struct stmfx_pinctrl *pctl,
530 u32 reg = get_reg(offset);
531 u32 mask = get_mask(offset);
534 if (!(pctl->irq_toggle_edge[reg] & mask))
537 val = stmfx_gpio_get(&pctl->gpio_chip, offset);
542 pctl->irq_gpi_type[reg] &= mask;
543 regmap_write_bits(pctl->stmfx->map,
544 STMFX_REG_IRQ_GPI_TYPE + reg,
548 pctl->irq_gpi_type[reg] |= mask;
549 regmap_write_bits(pctl->stmfx->map,
550 STMFX_REG_IRQ_GPI_TYPE + reg,
555 static irqreturn_t stmfx_pinctrl_irq_thread_fn(int irq, void *dev_id)
557 struct stmfx_pinctrl *pctl = (struct stmfx_pinctrl *)dev_id;
558 struct gpio_chip *gc = &pctl->gpio_chip;
559 u8 pending[NR_GPIO_REGS];
560 u8 src[NR_GPIO_REGS] = {0, 0, 0};
561 unsigned long n, status;
564 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_IRQ_GPI_PENDING,
565 &pending, NR_GPIO_REGS);
569 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
572 status = *(unsigned long *)pending;
573 for_each_set_bit(n, &status, gc->ngpio) {
574 handle_nested_irq(irq_find_mapping(gc->irq.domain, n));
575 stmfx_pinctrl_irq_toggle_trigger(pctl, n);
578 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
579 pctl->irq_gpi_src, NR_GPIO_REGS);
584 static int stmfx_pinctrl_gpio_function_enable(struct stmfx_pinctrl *pctl)
586 struct pinctrl_gpio_range *gpio_range;
587 struct pinctrl_dev *pctl_dev = pctl->pctl_dev;
588 u32 func = STMFX_FUNC_GPIO;
590 pctl->gpio_valid_mask = GENMASK(15, 0);
592 gpio_range = pinctrl_find_gpio_range_from_pin(pctl_dev, 16);
594 func |= STMFX_FUNC_ALTGPIO_LOW;
595 pctl->gpio_valid_mask |= GENMASK(19, 16);
598 gpio_range = pinctrl_find_gpio_range_from_pin(pctl_dev, 20);
600 func |= STMFX_FUNC_ALTGPIO_HIGH;
601 pctl->gpio_valid_mask |= GENMASK(23, 20);
604 return stmfx_function_enable(pctl->stmfx, func);
607 static int stmfx_pinctrl_probe(struct platform_device *pdev)
609 struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent);
610 struct device_node *np = pdev->dev.of_node;
611 struct stmfx_pinctrl *pctl;
614 pctl = devm_kzalloc(stmfx->dev, sizeof(*pctl), GFP_KERNEL);
618 platform_set_drvdata(pdev, pctl);
620 pctl->dev = &pdev->dev;
623 if (!of_find_property(np, "gpio-ranges", NULL)) {
624 dev_err(pctl->dev, "missing required gpio-ranges property\n");
628 irq = platform_get_irq(pdev, 0);
632 mutex_init(&pctl->lock);
634 /* Register pin controller */
635 pctl->pctl_desc.name = "stmfx-pinctrl";
636 pctl->pctl_desc.pctlops = &stmfx_pinctrl_ops;
637 pctl->pctl_desc.confops = &stmfx_pinconf_ops;
638 pctl->pctl_desc.pins = stmfx_pins;
639 pctl->pctl_desc.npins = ARRAY_SIZE(stmfx_pins);
640 pctl->pctl_desc.owner = THIS_MODULE;
641 pctl->pctl_desc.link_consumers = true;
643 ret = devm_pinctrl_register_and_init(pctl->dev, &pctl->pctl_desc,
644 pctl, &pctl->pctl_dev);
646 dev_err(pctl->dev, "pinctrl registration failed\n");
650 ret = pinctrl_enable(pctl->pctl_dev);
652 dev_err(pctl->dev, "pinctrl enable failed\n");
656 /* Register gpio controller */
657 pctl->gpio_chip.label = "stmfx-gpio";
658 pctl->gpio_chip.parent = pctl->dev;
659 pctl->gpio_chip.get_direction = stmfx_gpio_get_direction;
660 pctl->gpio_chip.direction_input = stmfx_gpio_direction_input;
661 pctl->gpio_chip.direction_output = stmfx_gpio_direction_output;
662 pctl->gpio_chip.get = stmfx_gpio_get;
663 pctl->gpio_chip.set = stmfx_gpio_set;
664 pctl->gpio_chip.set_config = gpiochip_generic_config;
665 pctl->gpio_chip.base = -1;
666 pctl->gpio_chip.ngpio = pctl->pctl_desc.npins;
667 pctl->gpio_chip.can_sleep = true;
668 pctl->gpio_chip.of_node = np;
670 ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl);
672 dev_err(pctl->dev, "gpio_chip registration failed\n");
676 ret = stmfx_pinctrl_gpio_function_enable(pctl);
680 pctl->irq_chip.name = dev_name(pctl->dev);
681 pctl->irq_chip.irq_mask = stmfx_pinctrl_irq_mask;
682 pctl->irq_chip.irq_unmask = stmfx_pinctrl_irq_unmask;
683 pctl->irq_chip.irq_set_type = stmfx_pinctrl_irq_set_type;
684 pctl->irq_chip.irq_bus_lock = stmfx_pinctrl_irq_bus_lock;
685 pctl->irq_chip.irq_bus_sync_unlock = stmfx_pinctrl_irq_bus_sync_unlock;
686 pctl->irq_chip.irq_request_resources = stmfx_gpio_irq_request_resources;
687 pctl->irq_chip.irq_release_resources = stmfx_gpio_irq_release_resources;
689 ret = gpiochip_irqchip_add_nested(&pctl->gpio_chip, &pctl->irq_chip,
690 0, handle_bad_irq, IRQ_TYPE_NONE);
692 dev_err(pctl->dev, "cannot add irqchip to gpiochip\n");
696 ret = devm_request_threaded_irq(pctl->dev, irq, NULL,
697 stmfx_pinctrl_irq_thread_fn,
699 pctl->irq_chip.name, pctl);
701 dev_err(pctl->dev, "cannot request irq%d\n", irq);
705 gpiochip_set_nested_irqchip(&pctl->gpio_chip, &pctl->irq_chip, irq);
708 "%ld GPIOs available\n", hweight_long(pctl->gpio_valid_mask));
713 static int stmfx_pinctrl_remove(struct platform_device *pdev)
715 struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent);
717 return stmfx_function_disable(stmfx,
719 STMFX_FUNC_ALTGPIO_LOW |
720 STMFX_FUNC_ALTGPIO_HIGH);
723 #ifdef CONFIG_PM_SLEEP
724 static int stmfx_pinctrl_backup_regs(struct stmfx_pinctrl *pctl)
728 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_STATE,
729 &pctl->bkp_gpio_state, NR_GPIO_REGS);
732 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_DIR,
733 &pctl->bkp_gpio_dir, NR_GPIO_REGS);
736 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_TYPE,
737 &pctl->bkp_gpio_type, NR_GPIO_REGS);
740 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_PUPD,
741 &pctl->bkp_gpio_pupd, NR_GPIO_REGS);
748 static int stmfx_pinctrl_restore_regs(struct stmfx_pinctrl *pctl)
752 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_DIR,
753 pctl->bkp_gpio_dir, NR_GPIO_REGS);
756 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_TYPE,
757 pctl->bkp_gpio_type, NR_GPIO_REGS);
760 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_PUPD,
761 pctl->bkp_gpio_pupd, NR_GPIO_REGS);
764 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPO_SET,
765 pctl->bkp_gpio_state, NR_GPIO_REGS);
768 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_EVT,
769 pctl->irq_gpi_evt, NR_GPIO_REGS);
772 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_TYPE,
773 pctl->irq_gpi_type, NR_GPIO_REGS);
776 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
777 pctl->irq_gpi_src, NR_GPIO_REGS);
784 static int stmfx_pinctrl_suspend(struct device *dev)
786 struct stmfx_pinctrl *pctl = dev_get_drvdata(dev);
789 ret = stmfx_pinctrl_backup_regs(pctl);
791 dev_err(pctl->dev, "registers backup failure\n");
798 static int stmfx_pinctrl_resume(struct device *dev)
800 struct stmfx_pinctrl *pctl = dev_get_drvdata(dev);
803 ret = stmfx_pinctrl_restore_regs(pctl);
805 dev_err(pctl->dev, "registers restoration failure\n");
813 static SIMPLE_DEV_PM_OPS(stmfx_pinctrl_dev_pm_ops,
814 stmfx_pinctrl_suspend, stmfx_pinctrl_resume);
816 static const struct of_device_id stmfx_pinctrl_of_match[] = {
817 { .compatible = "st,stmfx-0300-pinctrl", },
820 MODULE_DEVICE_TABLE(of, stmfx_pinctrl_of_match);
822 static struct platform_driver stmfx_pinctrl_driver = {
824 .name = "stmfx-pinctrl",
825 .of_match_table = stmfx_pinctrl_of_match,
826 .pm = &stmfx_pinctrl_dev_pm_ops,
828 .probe = stmfx_pinctrl_probe,
829 .remove = stmfx_pinctrl_remove,
831 module_platform_driver(stmfx_pinctrl_driver);
833 MODULE_DESCRIPTION("STMFX pinctrl/GPIO driver");
834 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
835 MODULE_LICENSE("GPL v2");