2 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/gpio.h>
15 #include <linux/module.h>
17 #include <linux/of_irq.h>
18 #include <linux/pinctrl/pinconf-generic.h>
19 #include <linux/pinctrl/pinconf.h>
20 #include <linux/pinctrl/pinmux.h>
21 #include <linux/platform_device.h>
22 #include <linux/regmap.h>
23 #include <linux/slab.h>
24 #include <linux/types.h>
26 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
29 #include "../pinctrl-utils.h"
31 #define PMIC_GPIO_ADDRESS_RANGE 0x100
33 /* type and subtype registers base address offsets */
34 #define PMIC_GPIO_REG_TYPE 0x4
35 #define PMIC_GPIO_REG_SUBTYPE 0x5
37 /* GPIO peripheral type and subtype out_values */
38 #define PMIC_GPIO_TYPE 0x10
39 #define PMIC_GPIO_SUBTYPE_GPIO_4CH 0x1
40 #define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5
41 #define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9
42 #define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd
44 #define PMIC_MPP_REG_RT_STS 0x10
45 #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1
47 /* control register base address offsets */
48 #define PMIC_GPIO_REG_MODE_CTL 0x40
49 #define PMIC_GPIO_REG_DIG_VIN_CTL 0x41
50 #define PMIC_GPIO_REG_DIG_PULL_CTL 0x42
51 #define PMIC_GPIO_REG_DIG_OUT_CTL 0x45
52 #define PMIC_GPIO_REG_EN_CTL 0x46
54 /* PMIC_GPIO_REG_MODE_CTL */
55 #define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1
56 #define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT 1
57 #define PMIC_GPIO_REG_MODE_FUNCTION_MASK 0x7
58 #define PMIC_GPIO_REG_MODE_DIR_SHIFT 4
59 #define PMIC_GPIO_REG_MODE_DIR_MASK 0x7
61 /* PMIC_GPIO_REG_DIG_VIN_CTL */
62 #define PMIC_GPIO_REG_VIN_SHIFT 0
63 #define PMIC_GPIO_REG_VIN_MASK 0x7
65 /* PMIC_GPIO_REG_DIG_PULL_CTL */
66 #define PMIC_GPIO_REG_PULL_SHIFT 0
67 #define PMIC_GPIO_REG_PULL_MASK 0x7
69 #define PMIC_GPIO_PULL_DOWN 4
70 #define PMIC_GPIO_PULL_DISABLE 5
72 /* PMIC_GPIO_REG_DIG_OUT_CTL */
73 #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0
74 #define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3
75 #define PMIC_GPIO_REG_OUT_TYPE_SHIFT 4
76 #define PMIC_GPIO_REG_OUT_TYPE_MASK 0x3
79 * Output type - indicates pin should be configured as push-pull,
80 * open drain or open source.
82 #define PMIC_GPIO_OUT_BUF_CMOS 0
83 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS 1
84 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS 2
86 /* PMIC_GPIO_REG_EN_CTL */
87 #define PMIC_GPIO_REG_MASTER_EN_SHIFT 7
89 #define PMIC_GPIO_PHYSICAL_OFFSET 1
91 /* Qualcomm specific pin configurations */
92 #define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1)
93 #define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2)
96 * struct pmic_gpio_pad - keep current GPIO settings
97 * @base: Address base in SPMI device.
98 * @irq: IRQ number which this GPIO generate.
99 * @is_enabled: Set to false when GPIO should be put in high Z state.
100 * @out_value: Cached pin output value
101 * @have_buffer: Set to true if GPIO output could be configured in push-pull,
102 * open-drain or open-source mode.
103 * @output_enabled: Set to true if GPIO output logic is enabled.
104 * @input_enabled: Set to true if GPIO input buffer logic is enabled.
105 * @num_sources: Number of power-sources supported by this GPIO.
106 * @power_source: Current power-source used.
107 * @buffer_type: Push-pull, open-drain or open-source.
108 * @pullup: Constant current which flow trough GPIO output buffer.
109 * @strength: No, Low, Medium, High
110 * @function: See pmic_gpio_functions[]
112 struct pmic_gpio_pad {
120 unsigned int num_sources;
121 unsigned int power_source;
122 unsigned int buffer_type;
124 unsigned int strength;
125 unsigned int function;
128 struct pmic_gpio_state {
131 struct pinctrl_dev *ctrl;
132 struct gpio_chip chip;
135 static const struct pinconf_generic_params pmic_gpio_bindings[] = {
136 {"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0},
137 {"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0},
140 #ifdef CONFIG_DEBUG_FS
141 static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
142 PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true),
143 PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true),
147 static const char *const pmic_gpio_groups[] = {
148 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
149 "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
150 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
151 "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
152 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
155 static const char *const pmic_gpio_functions[] = {
156 PMIC_GPIO_FUNC_NORMAL, PMIC_GPIO_FUNC_PAIRED,
157 PMIC_GPIO_FUNC_FUNC1, PMIC_GPIO_FUNC_FUNC2,
158 PMIC_GPIO_FUNC_DTEST1, PMIC_GPIO_FUNC_DTEST2,
159 PMIC_GPIO_FUNC_DTEST3, PMIC_GPIO_FUNC_DTEST4,
162 static inline struct pmic_gpio_state *to_gpio_state(struct gpio_chip *chip)
164 return container_of(chip, struct pmic_gpio_state, chip);
167 static int pmic_gpio_read(struct pmic_gpio_state *state,
168 struct pmic_gpio_pad *pad, unsigned int addr)
173 ret = regmap_read(state->map, pad->base + addr, &val);
175 dev_err(state->dev, "read 0x%x failed\n", addr);
182 static int pmic_gpio_write(struct pmic_gpio_state *state,
183 struct pmic_gpio_pad *pad, unsigned int addr,
188 ret = regmap_write(state->map, pad->base + addr, val);
190 dev_err(state->dev, "write 0x%x failed\n", addr);
195 static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev)
197 /* Every PIN is a group */
198 return pctldev->desc->npins;
201 static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev,
204 return pctldev->desc->pins[pin].name;
207 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin,
208 const unsigned **pins, unsigned *num_pins)
210 *pins = &pctldev->desc->pins[pin].number;
215 static const struct pinctrl_ops pmic_gpio_pinctrl_ops = {
216 .get_groups_count = pmic_gpio_get_groups_count,
217 .get_group_name = pmic_gpio_get_group_name,
218 .get_group_pins = pmic_gpio_get_group_pins,
219 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
220 .dt_free_map = pinctrl_utils_dt_free_map,
223 static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev)
225 return ARRAY_SIZE(pmic_gpio_functions);
228 static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev,
231 return pmic_gpio_functions[function];
234 static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev,
236 const char *const **groups,
237 unsigned *const num_qgroups)
239 *groups = pmic_gpio_groups;
240 *num_qgroups = pctldev->desc->npins;
244 static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
247 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
248 struct pmic_gpio_pad *pad;
252 pad = pctldev->desc->pins[pin].drv_data;
254 pad->function = function;
257 if (pad->output_enabled) {
258 if (pad->input_enabled)
264 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
265 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
266 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
268 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
272 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
274 return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
277 static const struct pinmux_ops pmic_gpio_pinmux_ops = {
278 .get_functions_count = pmic_gpio_get_functions_count,
279 .get_function_name = pmic_gpio_get_function_name,
280 .get_function_groups = pmic_gpio_get_function_groups,
281 .set_mux = pmic_gpio_set_mux,
284 static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
285 unsigned int pin, unsigned long *config)
287 unsigned param = pinconf_to_config_param(*config);
288 struct pmic_gpio_pad *pad;
291 pad = pctldev->desc->pins[pin].drv_data;
294 case PIN_CONFIG_DRIVE_PUSH_PULL:
295 arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_CMOS;
297 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
298 arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
300 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
301 arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
303 case PIN_CONFIG_BIAS_PULL_DOWN:
304 arg = pad->pullup == PMIC_GPIO_PULL_DOWN;
306 case PIN_CONFIG_BIAS_DISABLE:
307 arg = pad->pullup = PMIC_GPIO_PULL_DISABLE;
309 case PIN_CONFIG_BIAS_PULL_UP:
310 arg = pad->pullup == PMIC_GPIO_PULL_UP_30;
312 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
313 arg = !pad->is_enabled;
315 case PIN_CONFIG_POWER_SOURCE:
316 arg = pad->power_source;
318 case PIN_CONFIG_INPUT_ENABLE:
319 arg = pad->input_enabled;
321 case PIN_CONFIG_OUTPUT:
322 arg = pad->out_value;
324 case PMIC_GPIO_CONF_PULL_UP:
327 case PMIC_GPIO_CONF_STRENGTH:
334 *config = pinconf_to_config_packed(param, arg);
338 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
339 unsigned long *configs, unsigned nconfs)
341 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
342 struct pmic_gpio_pad *pad;
347 pad = pctldev->desc->pins[pin].drv_data;
349 for (i = 0; i < nconfs; i++) {
350 param = pinconf_to_config_param(configs[i]);
351 arg = pinconf_to_config_argument(configs[i]);
354 case PIN_CONFIG_DRIVE_PUSH_PULL:
355 pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS;
357 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
358 if (!pad->have_buffer)
360 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
362 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
363 if (!pad->have_buffer)
365 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
367 case PIN_CONFIG_BIAS_DISABLE:
368 pad->pullup = PMIC_GPIO_PULL_DISABLE;
370 case PIN_CONFIG_BIAS_PULL_UP:
371 pad->pullup = PMIC_GPIO_PULL_UP_30;
373 case PIN_CONFIG_BIAS_PULL_DOWN:
375 pad->pullup = PMIC_GPIO_PULL_DOWN;
377 pad->pullup = PMIC_GPIO_PULL_DISABLE;
379 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
380 pad->is_enabled = false;
382 case PIN_CONFIG_POWER_SOURCE:
383 if (arg > pad->num_sources)
385 pad->power_source = arg;
387 case PIN_CONFIG_INPUT_ENABLE:
388 pad->input_enabled = arg ? true : false;
390 case PIN_CONFIG_OUTPUT:
391 pad->output_enabled = true;
392 pad->out_value = arg;
394 case PMIC_GPIO_CONF_PULL_UP:
395 if (arg > PMIC_GPIO_PULL_UP_1P5_30)
399 case PMIC_GPIO_CONF_STRENGTH:
400 if (arg > PMIC_GPIO_STRENGTH_LOW)
409 val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT;
411 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val);
415 val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT;
417 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val);
421 val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT;
422 val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
424 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val);
429 if (pad->output_enabled) {
430 if (pad->input_enabled)
436 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
437 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
438 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
440 return pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
443 static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
444 struct seq_file *s, unsigned pin)
446 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
447 struct pmic_gpio_pad *pad;
450 static const char *const biases[] = {
451 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
452 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
454 static const char *const buffer_types[] = {
455 "push-pull", "open-drain", "open-source"
457 static const char *const strengths[] = {
458 "no", "high", "medium", "low"
461 pad = pctldev->desc->pins[pin].drv_data;
463 seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET);
465 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL);
467 if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) {
471 if (pad->input_enabled) {
472 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
476 ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
477 pad->out_value = ret;
480 seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in");
481 seq_printf(s, " %-7s", pmic_gpio_functions[pad->function]);
482 seq_printf(s, " vin-%d", pad->power_source);
483 seq_printf(s, " %-27s", biases[pad->pullup]);
484 seq_printf(s, " %-10s", buffer_types[pad->buffer_type]);
485 seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
486 seq_printf(s, " %-7s", strengths[pad->strength]);
490 static const struct pinconf_ops pmic_gpio_pinconf_ops = {
492 .pin_config_group_get = pmic_gpio_config_get,
493 .pin_config_group_set = pmic_gpio_config_set,
494 .pin_config_group_dbg_show = pmic_gpio_config_dbg_show,
497 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
499 struct pmic_gpio_state *state = to_gpio_state(chip);
500 unsigned long config;
502 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
504 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
507 static int pmic_gpio_direction_output(struct gpio_chip *chip,
508 unsigned pin, int val)
510 struct pmic_gpio_state *state = to_gpio_state(chip);
511 unsigned long config;
513 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
515 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
518 static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin)
520 struct pmic_gpio_state *state = to_gpio_state(chip);
521 struct pmic_gpio_pad *pad;
524 pad = state->ctrl->desc->pins[pin].drv_data;
526 if (!pad->is_enabled)
529 if (pad->input_enabled) {
530 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
534 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
537 return pad->out_value;
540 static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
542 struct pmic_gpio_state *state = to_gpio_state(chip);
543 unsigned long config;
545 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
547 pmic_gpio_config_set(state->ctrl, pin, &config, 1);
550 static int pmic_gpio_of_xlate(struct gpio_chip *chip,
551 const struct of_phandle_args *gpio_desc,
554 if (chip->of_gpio_n_cells < 2)
558 *flags = gpio_desc->args[1];
560 return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET;
563 static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
565 struct pmic_gpio_state *state = to_gpio_state(chip);
566 struct pmic_gpio_pad *pad;
568 pad = state->ctrl->desc->pins[pin].drv_data;
573 static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
575 struct pmic_gpio_state *state = to_gpio_state(chip);
578 for (i = 0; i < chip->ngpio; i++) {
579 pmic_gpio_config_dbg_show(state->ctrl, s, i);
584 static const struct gpio_chip pmic_gpio_gpio_template = {
585 .direction_input = pmic_gpio_direction_input,
586 .direction_output = pmic_gpio_direction_output,
587 .get = pmic_gpio_get,
588 .set = pmic_gpio_set,
589 .request = gpiochip_generic_request,
590 .free = gpiochip_generic_free,
591 .of_xlate = pmic_gpio_of_xlate,
592 .to_irq = pmic_gpio_to_irq,
593 .dbg_show = pmic_gpio_dbg_show,
596 static int pmic_gpio_populate(struct pmic_gpio_state *state,
597 struct pmic_gpio_pad *pad)
599 int type, subtype, val, dir;
601 type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE);
605 if (type != PMIC_GPIO_TYPE) {
606 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
611 subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE);
616 case PMIC_GPIO_SUBTYPE_GPIO_4CH:
617 pad->have_buffer = true;
618 case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
619 pad->num_sources = 4;
621 case PMIC_GPIO_SUBTYPE_GPIO_8CH:
622 pad->have_buffer = true;
623 case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
624 pad->num_sources = 8;
627 dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype);
631 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
635 pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
637 dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT;
638 dir &= PMIC_GPIO_REG_MODE_DIR_MASK;
641 pad->input_enabled = true;
642 pad->output_enabled = false;
645 pad->input_enabled = false;
646 pad->output_enabled = true;
649 pad->input_enabled = true;
650 pad->output_enabled = true;
653 dev_err(state->dev, "unknown GPIO direction\n");
657 pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
658 pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;
660 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL);
664 pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT;
665 pad->power_source &= PMIC_GPIO_REG_VIN_MASK;
667 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL);
671 pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT;
672 pad->pullup &= PMIC_GPIO_REG_PULL_MASK;
674 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL);
678 pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
679 pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK;
681 pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT;
682 pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK;
684 /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */
685 pad->is_enabled = true;
689 static int pmic_gpio_probe(struct platform_device *pdev)
691 struct device *dev = &pdev->dev;
692 struct pinctrl_pin_desc *pindesc;
693 struct pinctrl_desc *pctrldesc;
694 struct pmic_gpio_pad *pad, *pads;
695 struct pmic_gpio_state *state;
699 ret = of_property_read_u32(dev->of_node, "reg", ®);
701 dev_err(dev, "missing base address");
705 npins = of_irq_count(dev->of_node);
709 BUG_ON(npins > ARRAY_SIZE(pmic_gpio_groups));
711 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
715 platform_set_drvdata(pdev, state);
717 state->dev = &pdev->dev;
718 state->map = dev_get_regmap(dev->parent, NULL);
720 pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
724 pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
728 pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
732 pctrldesc->pctlops = &pmic_gpio_pinctrl_ops;
733 pctrldesc->pmxops = &pmic_gpio_pinmux_ops;
734 pctrldesc->confops = &pmic_gpio_pinconf_ops;
735 pctrldesc->owner = THIS_MODULE;
736 pctrldesc->name = dev_name(dev);
737 pctrldesc->pins = pindesc;
738 pctrldesc->npins = npins;
739 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings);
740 pctrldesc->custom_params = pmic_gpio_bindings;
741 #ifdef CONFIG_DEBUG_FS
742 pctrldesc->custom_conf_items = pmic_conf_items;
745 for (i = 0; i < npins; i++, pindesc++) {
747 pindesc->drv_data = pad;
749 pindesc->name = pmic_gpio_groups[i];
751 pad->irq = platform_get_irq(pdev, i);
755 pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE;
757 ret = pmic_gpio_populate(state, pad);
762 state->chip = pmic_gpio_gpio_template;
763 state->chip.dev = dev;
764 state->chip.base = -1;
765 state->chip.ngpio = npins;
766 state->chip.label = dev_name(dev);
767 state->chip.of_gpio_n_cells = 2;
768 state->chip.can_sleep = false;
770 state->ctrl = pinctrl_register(pctrldesc, dev, state);
771 if (IS_ERR(state->ctrl))
772 return PTR_ERR(state->ctrl);
774 ret = gpiochip_add(&state->chip);
776 dev_err(state->dev, "can't add gpio chip\n");
780 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins);
782 dev_err(dev, "failed to add pin range\n");
789 gpiochip_remove(&state->chip);
791 pinctrl_unregister(state->ctrl);
795 static int pmic_gpio_remove(struct platform_device *pdev)
797 struct pmic_gpio_state *state = platform_get_drvdata(pdev);
799 gpiochip_remove(&state->chip);
800 pinctrl_unregister(state->ctrl);
804 static const struct of_device_id pmic_gpio_of_match[] = {
805 { .compatible = "qcom,pm8916-gpio" }, /* 4 GPIO's */
806 { .compatible = "qcom,pm8941-gpio" }, /* 36 GPIO's */
807 { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */
808 { .compatible = "qcom,pma8084-gpio" }, /* 22 GPIO's */
812 MODULE_DEVICE_TABLE(of, pmic_gpio_of_match);
814 static struct platform_driver pmic_gpio_driver = {
816 .name = "qcom-spmi-gpio",
817 .of_match_table = pmic_gpio_of_match,
819 .probe = pmic_gpio_probe,
820 .remove = pmic_gpio_remove,
823 module_platform_driver(pmic_gpio_driver);
825 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
826 MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver");
827 MODULE_ALIAS("platform:qcom-spmi-gpio");
828 MODULE_LICENSE("GPL v2");