drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * R8A7795 ES1.x processor support - PFC hardware block.
   4  *
   5  * Copyright (C) 2015-2017  Renesas Electronics Corporation
   6  */
   7
   8 #include <linux/kernel.h>
   9
  10 #include "core.h"
  11 #include "sh_pfc.h"
  12
  13 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
  14                    SH_PFC_PIN_CFG_PULL_UP | \
  15                    SH_PFC_PIN_CFG_PULL_DOWN)
  16
  17 #define CPU_ALL_PORT(fn, sfx)                                           \
  18         PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),  \
  19         PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS),  \
  20         PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),  \
  21         PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  22         PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),       \
  23         PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),       \
  24         PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),       \
  25         PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),       \
  26         PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  27         PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),  \
  28         PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),  \
  29         PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
  30 /*
  31  * F_() : just information
  32  * FM() : macro for FN_xxx / xxx_MARK
  33  */
  34
  35 /* GPSR0 */
  36 #define GPSR0_15        F_(D15,                 IP7_11_8)
  37 #define GPSR0_14        F_(D14,                 IP7_7_4)
  38 #define GPSR0_13        F_(D13,                 IP7_3_0)
  39 #define GPSR0_12        F_(D12,                 IP6_31_28)
  40 #define GPSR0_11        F_(D11,                 IP6_27_24)
  41 #define GPSR0_10        F_(D10,                 IP6_23_20)
  42 #define GPSR0_9         F_(D9,                  IP6_19_16)
  43 #define GPSR0_8         F_(D8,                  IP6_15_12)
  44 #define GPSR0_7         F_(D7,                  IP6_11_8)
  45 #define GPSR0_6         F_(D6,                  IP6_7_4)
  46 #define GPSR0_5         F_(D5,                  IP6_3_0)
  47 #define GPSR0_4         F_(D4,                  IP5_31_28)
  48 #define GPSR0_3         F_(D3,                  IP5_27_24)
  49 #define GPSR0_2         F_(D2,                  IP5_23_20)
  50 #define GPSR0_1         F_(D1,                  IP5_19_16)
  51 #define GPSR0_0         F_(D0,                  IP5_15_12)
  52
  53 /* GPSR1 */
  54 #define GPSR1_27        F_(EX_WAIT0_A,          IP5_11_8)
  55 #define GPSR1_26        F_(WE1_N,               IP5_7_4)
  56 #define GPSR1_25        F_(WE0_N,               IP5_3_0)
  57 #define GPSR1_24        F_(RD_WR_N,             IP4_31_28)
  58 #define GPSR1_23        F_(RD_N,                IP4_27_24)
  59 #define GPSR1_22        F_(BS_N,                IP4_23_20)
  60 #define GPSR1_21        F_(CS1_N_A26,           IP4_19_16)
  61 #define GPSR1_20        F_(CS0_N,               IP4_15_12)
  62 #define GPSR1_19        F_(A19,                 IP4_11_8)
  63 #define GPSR1_18        F_(A18,                 IP4_7_4)
  64 #define GPSR1_17        F_(A17,                 IP4_3_0)
  65 #define GPSR1_16        F_(A16,                 IP3_31_28)
  66 #define GPSR1_15        F_(A15,                 IP3_27_24)
  67 #define GPSR1_14        F_(A14,                 IP3_23_20)
  68 #define GPSR1_13        F_(A13,                 IP3_19_16)
  69 #define GPSR1_12        F_(A12,                 IP3_15_12)
  70 #define GPSR1_11        F_(A11,                 IP3_11_8)
  71 #define GPSR1_10        F_(A10,                 IP3_7_4)
  72 #define GPSR1_9         F_(A9,                  IP3_3_0)
  73 #define GPSR1_8         F_(A8,                  IP2_31_28)
  74 #define GPSR1_7         F_(A7,                  IP2_27_24)
  75 #define GPSR1_6         F_(A6,                  IP2_23_20)
  76 #define GPSR1_5         F_(A5,                  IP2_19_16)
  77 #define GPSR1_4         F_(A4,                  IP2_15_12)
  78 #define GPSR1_3         F_(A3,                  IP2_11_8)
  79 #define GPSR1_2         F_(A2,                  IP2_7_4)
  80 #define GPSR1_1         F_(A1,                  IP2_3_0)
  81 #define GPSR1_0         F_(A0,                  IP1_31_28)
  82
  83 /* GPSR2 */
  84 #define GPSR2_14        F_(AVB_AVTP_CAPTURE_A,  IP0_23_20)
  85 #define GPSR2_13        F_(AVB_AVTP_MATCH_A,    IP0_19_16)
  86 #define GPSR2_12        F_(AVB_LINK,            IP0_15_12)
  87 #define GPSR2_11        F_(AVB_PHY_INT,         IP0_11_8)
  88 #define GPSR2_10        F_(AVB_MAGIC,           IP0_7_4)
  89 #define GPSR2_9         F_(AVB_MDC,             IP0_3_0)
  90 #define GPSR2_8         F_(PWM2_A,              IP1_27_24)
  91 #define GPSR2_7         F_(PWM1_A,              IP1_23_20)
  92 #define GPSR2_6         F_(PWM0,                IP1_19_16)
  93 #define GPSR2_5         F_(IRQ5,                IP1_15_12)
  94 #define GPSR2_4         F_(IRQ4,                IP1_11_8)
  95 #define GPSR2_3         F_(IRQ3,                IP1_7_4)
  96 #define GPSR2_2         F_(IRQ2,                IP1_3_0)
  97 #define GPSR2_1         F_(IRQ1,                IP0_31_28)
  98 #define GPSR2_0         F_(IRQ0,                IP0_27_24)
  99
 100 /* GPSR3 */
 101 #define GPSR3_15        F_(SD1_WP,              IP10_23_20)
 102 #define GPSR3_14        F_(SD1_CD,              IP10_19_16)
 103 #define GPSR3_13        F_(SD0_WP,              IP10_15_12)
 104 #define GPSR3_12        F_(SD0_CD,              IP10_11_8)
 105 #define GPSR3_11        F_(SD1_DAT3,            IP8_31_28)
 106 #define GPSR3_10        F_(SD1_DAT2,            IP8_27_24)
 107 #define GPSR3_9         F_(SD1_DAT1,            IP8_23_20)
 108 #define GPSR3_8         F_(SD1_DAT0,            IP8_19_16)
 109 #define GPSR3_7         F_(SD1_CMD,             IP8_15_12)
 110 #define GPSR3_6         F_(SD1_CLK,             IP8_11_8)
 111 #define GPSR3_5         F_(SD0_DAT3,            IP8_7_4)
 112 #define GPSR3_4         F_(SD0_DAT2,            IP8_3_0)
 113 #define GPSR3_3         F_(SD0_DAT1,            IP7_31_28)
 114 #define GPSR3_2         F_(SD0_DAT0,            IP7_27_24)
 115 #define GPSR3_1         F_(SD0_CMD,             IP7_23_20)
 116 #define GPSR3_0         F_(SD0_CLK,             IP7_19_16)
 117
 118 /* GPSR4 */
 119 #define GPSR4_17        FM(SD3_DS)
 120 #define GPSR4_16        F_(SD3_DAT7,            IP10_7_4)
 121 #define GPSR4_15        F_(SD3_DAT6,            IP10_3_0)
 122 #define GPSR4_14        F_(SD3_DAT5,            IP9_31_28)
 123 #define GPSR4_13        F_(SD3_DAT4,            IP9_27_24)
 124 #define GPSR4_12        FM(SD3_DAT3)
 125 #define GPSR4_11        FM(SD3_DAT2)
 126 #define GPSR4_10        FM(SD3_DAT1)
 127 #define GPSR4_9         FM(SD3_DAT0)
 128 #define GPSR4_8         FM(SD3_CMD)
 129 #define GPSR4_7         FM(SD3_CLK)
 130 #define GPSR4_6         F_(SD2_DS,              IP9_23_20)
 131 #define GPSR4_5         F_(SD2_DAT3,            IP9_19_16)
 132 #define GPSR4_4         F_(SD2_DAT2,            IP9_15_12)
 133 #define GPSR4_3         F_(SD2_DAT1,            IP9_11_8)
 134 #define GPSR4_2         F_(SD2_DAT0,            IP9_7_4)
 135 #define GPSR4_1         FM(SD2_CMD)
 136 #define GPSR4_0         F_(SD2_CLK,             IP9_3_0)
 137
 138 /* GPSR5 */
 139 #define GPSR5_25        F_(MLB_DAT,             IP13_19_16)
 140 #define GPSR5_24        F_(MLB_SIG,             IP13_15_12)
 141 #define GPSR5_23        F_(MLB_CLK,             IP13_11_8)
 142 #define GPSR5_22        FM(MSIOF0_RXD)
 143 #define GPSR5_21        F_(MSIOF0_SS2,          IP13_7_4)
 144 #define GPSR5_20        FM(MSIOF0_TXD)
 145 #define GPSR5_19        F_(MSIOF0_SS1,          IP13_3_0)
 146 #define GPSR5_18        F_(MSIOF0_SYNC,         IP12_31_28)
 147 #define GPSR5_17        FM(MSIOF0_SCK)
 148 #define GPSR5_16        F_(HRTS0_N,             IP12_27_24)
 149 #define GPSR5_15        F_(HCTS0_N,             IP12_23_20)
 150 #define GPSR5_14        F_(HTX0,                IP12_19_16)
 151 #define GPSR5_13        F_(HRX0,                IP12_15_12)
 152 #define GPSR5_12        F_(HSCK0,               IP12_11_8)
 153 #define GPSR5_11        F_(RX2_A,               IP12_7_4)
 154 #define GPSR5_10        F_(TX2_A,               IP12_3_0)
 155 #define GPSR5_9         F_(SCK2,                IP11_31_28)
 156 #define GPSR5_8         F_(RTS1_N_TANS,         IP11_27_24)
 157 #define GPSR5_7         F_(CTS1_N,              IP11_23_20)
 158 #define GPSR5_6         F_(TX1_A,               IP11_19_16)
 159 #define GPSR5_5         F_(RX1_A,               IP11_15_12)
 160 #define GPSR5_4         F_(RTS0_N_TANS,         IP11_11_8)
 161 #define GPSR5_3         F_(CTS0_N,              IP11_7_4)
 162 #define GPSR5_2         F_(TX0,                 IP11_3_0)
 163 #define GPSR5_1         F_(RX0,                 IP10_31_28)
 164 #define GPSR5_0         F_(SCK0,                IP10_27_24)
 165
 166 /* GPSR6 */
 167 #define GPSR6_31        F_(USB31_OVC,           IP17_7_4)
 168 #define GPSR6_30        F_(USB31_PWEN,          IP17_3_0)
 169 #define GPSR6_29        F_(USB30_OVC,           IP16_31_28)
 170 #define GPSR6_28        F_(USB30_PWEN,          IP16_27_24)
 171 #define GPSR6_27        F_(USB1_OVC,            IP16_23_20)
 172 #define GPSR6_26        F_(USB1_PWEN,           IP16_19_16)
 173 #define GPSR6_25        F_(USB0_OVC,            IP16_15_12)
 174 #define GPSR6_24        F_(USB0_PWEN,           IP16_11_8)
 175 #define GPSR6_23        F_(AUDIO_CLKB_B,        IP16_7_4)
 176 #define GPSR6_22        F_(AUDIO_CLKA_A,        IP16_3_0)
 177 #define GPSR6_21        F_(SSI_SDATA9_A,        IP15_31_28)
 178 #define GPSR6_20        F_(SSI_SDATA8,          IP15_27_24)
 179 #define GPSR6_19        F_(SSI_SDATA7,          IP15_23_20)
 180 #define GPSR6_18        F_(SSI_WS78,            IP15_19_16)
 181 #define GPSR6_17        F_(SSI_SCK78,           IP15_15_12)
 182 #define GPSR6_16        F_(SSI_SDATA6,          IP15_11_8)
 183 #define GPSR6_15        F_(SSI_WS6,             IP15_7_4)
 184 #define GPSR6_14        F_(SSI_SCK6,            IP15_3_0)
 185 #define GPSR6_13        FM(SSI_SDATA5)
 186 #define GPSR6_12        FM(SSI_WS5)
 187 #define GPSR6_11        FM(SSI_SCK5)
 188 #define GPSR6_10        F_(SSI_SDATA4,          IP14_31_28)
 189 #define GPSR6_9         F_(SSI_WS4,             IP14_27_24)
 190 #define GPSR6_8         F_(SSI_SCK4,            IP14_23_20)
 191 #define GPSR6_7         F_(SSI_SDATA3,          IP14_19_16)
 192 #define GPSR6_6         F_(SSI_WS349,           IP14_15_12)
 193 #define GPSR6_5         F_(SSI_SCK349,          IP14_11_8)
 194 #define GPSR6_4         F_(SSI_SDATA2_A,        IP14_7_4)
 195 #define GPSR6_3         F_(SSI_SDATA1_A,        IP14_3_0)
 196 #define GPSR6_2         F_(SSI_SDATA0,          IP13_31_28)
 197 #define GPSR6_1         F_(SSI_WS01239,         IP13_27_24)
 198 #define GPSR6_0         F_(SSI_SCK01239,        IP13_23_20)
 199
 200 /* GPSR7 */
 201 #define GPSR7_3         FM(HDMI1_CEC)
 202 #define GPSR7_2         FM(HDMI0_CEC)
 203 #define GPSR7_1         FM(AVS2)
 204 #define GPSR7_0         FM(AVS1)
 205
 206
 207 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 208 #define IP0_3_0         FM(AVB_MDC)             F_(0, 0)        FM(MSIOF2_SS2_C)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 209 #define IP0_7_4         FM(AVB_MAGIC)           F_(0, 0)        FM(MSIOF2_SS1_C)        FM(SCK4_A)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 210 #define IP0_11_8        FM(AVB_PHY_INT)         F_(0, 0)        FM(MSIOF2_SYNC_C)       FM(RX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 211 #define IP0_15_12       FM(AVB_LINK)            F_(0, 0)        FM(MSIOF2_SCK_C)        FM(TX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 212 #define IP0_19_16       FM(AVB_AVTP_MATCH_A)    F_(0, 0)        FM(MSIOF2_RXD_C)        FM(CTS4_N_A)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 213 #define IP0_23_20       FM(AVB_AVTP_CAPTURE_A)  F_(0, 0)        FM(MSIOF2_TXD_C)        FM(RTS4_N_TANS_A)               F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 214 #define IP0_27_24       FM(IRQ0)                FM(QPOLB)       F_(0, 0)                FM(DU_CDE)                      FM(VI4_DATA0_B) FM(CAN0_TX_B)   FM(CANFD0_TX_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 215 #define IP0_31_28       FM(IRQ1)                FM(QPOLA)       F_(0, 0)                FM(DU_DISP)                     FM(VI4_DATA1_B) FM(CAN0_RX_B)   FM(CANFD0_RX_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 216 #define IP1_3_0         FM(IRQ2)                FM(QCPV_QDE)    F_(0, 0)                FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(VI4_DATA2_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(PWM3_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 217 #define IP1_7_4         FM(IRQ3)                FM(QSTVB_QVE)   FM(A25)                 FM(DU_DOTCLKOUT1)               FM(VI4_DATA3_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(PWM4_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 218 #define IP1_11_8        FM(IRQ4)                FM(QSTH_QHS)    FM(A24)                 FM(DU_EXHSYNC_DU_HSYNC)         FM(VI4_DATA4_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(PWM5_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 219 #define IP1_15_12       FM(IRQ5)                FM(QSTB_QHE)    FM(A23)                 FM(DU_EXVSYNC_DU_VSYNC)         FM(VI4_DATA5_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(PWM6_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 220 #define IP1_19_16       FM(PWM0)                FM(AVB_AVTP_PPS)FM(A22)                 F_(0, 0)                        FM(VI4_DATA6_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IECLK_B)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 221 #define IP1_23_20       FM(PWM1_A)              F_(0, 0)        FM(A21)                 FM(HRX3_D)                      FM(VI4_DATA7_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IERX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 222 #define IP1_27_24       FM(PWM2_A)              F_(0, 0)        FM(A20)                 FM(HTX3_D)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IETX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 223 #define IP1_31_28       FM(A0)                  FM(LCDOUT16)    FM(MSIOF3_SYNC_B)       F_(0, 0)                        FM(VI4_DATA8)   F_(0, 0)        FM(DU_DB0)              F_(0, 0)        F_(0, 0)                FM(PWM3_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 224 #define IP2_3_0         FM(A1)                  FM(LCDOUT17)    FM(MSIOF3_TXD_B)        F_(0, 0)                        FM(VI4_DATA9)   F_(0, 0)        FM(DU_DB1)              F_(0, 0)        F_(0, 0)                FM(PWM4_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 225 #define IP2_7_4         FM(A2)                  FM(LCDOUT18)    FM(MSIOF3_SCK_B)        F_(0, 0)                        FM(VI4_DATA10)  F_(0, 0)        FM(DU_DB2)              F_(0, 0)        F_(0, 0)                FM(PWM5_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 226 #define IP2_11_8        FM(A3)                  FM(LCDOUT19)    FM(MSIOF3_RXD_B)        F_(0, 0)                        FM(VI4_DATA11)  F_(0, 0)        FM(DU_DB3)              F_(0, 0)        F_(0, 0)                FM(PWM6_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 227
 228 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 229 #define IP2_15_12       FM(A4)                  FM(LCDOUT20)    FM(MSIOF3_SS1_B)        F_(0, 0)                        FM(VI4_DATA12)  FM(VI5_DATA12)  FM(DU_DB4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 230 #define IP2_19_16       FM(A5)                  FM(LCDOUT21)    FM(MSIOF3_SS2_B)        FM(SCK4_B)                      FM(VI4_DATA13)  FM(VI5_DATA13)  FM(DU_DB5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 231 #define IP2_23_20       FM(A6)                  FM(LCDOUT22)    FM(MSIOF2_SS1_A)        FM(RX4_B)                       FM(VI4_DATA14)  FM(VI5_DATA14)  FM(DU_DB6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 232 #define IP2_27_24       FM(A7)                  FM(LCDOUT23)    FM(MSIOF2_SS2_A)        FM(TX4_B)                       FM(VI4_DATA15)  FM(VI5_DATA15)  FM(DU_DB7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 233 #define IP2_31_28       FM(A8)                  FM(RX3_B)       FM(MSIOF2_SYNC_A)       FM(HRX4_B)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                FM(SDA6_A)      FM(AVB_AVTP_MATCH_B)    FM(PWM1_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 234 #define IP3_3_0         FM(A9)                  F_(0, 0)        FM(MSIOF2_SCK_A)        FM(CTS4_N_B)                    F_(0, 0)        FM(VI5_VSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 235 #define IP3_7_4         FM(A10)                 F_(0, 0)        FM(MSIOF2_RXD_A)        FM(RTS4_N_TANS_B)               F_(0, 0)        FM(VI5_HSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 236 #define IP3_11_8        FM(A11)                 FM(TX3_B)       FM(MSIOF2_TXD_A)        FM(HTX4_B)                      FM(HSCK4)       FM(VI5_FIELD)   F_(0, 0)                FM(SCL6_A)      FM(AVB_AVTP_CAPTURE_B)  FM(PWM2_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 237 #define IP3_15_12       FM(A12)                 FM(LCDOUT12)    FM(MSIOF3_SCK_C)        F_(0, 0)                        FM(HRX4_A)      FM(VI5_DATA8)   FM(DU_DG4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 238 #define IP3_19_16       FM(A13)                 FM(LCDOUT13)    FM(MSIOF3_SYNC_C)       F_(0, 0)                        FM(HTX4_A)      FM(VI5_DATA9)   FM(DU_DG5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 239 #define IP3_23_20       FM(A14)                 FM(LCDOUT14)    FM(MSIOF3_RXD_C)        F_(0, 0)                        FM(HCTS4_N)     FM(VI5_DATA10)  FM(DU_DG6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 240 #define IP3_27_24       FM(A15)                 FM(LCDOUT15)    FM(MSIOF3_TXD_C)        F_(0, 0)                        FM(HRTS4_N)     FM(VI5_DATA11)  FM(DU_DG7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 241 #define IP3_31_28       FM(A16)                 FM(LCDOUT8)     F_(0, 0)                F_(0, 0)                        FM(VI4_FIELD)   F_(0, 0)        FM(DU_DG0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 242 #define IP4_3_0         FM(A17)                 FM(LCDOUT9)     F_(0, 0)                F_(0, 0)                        FM(VI4_VSYNC_N) F_(0, 0)        FM(DU_DG1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 243 #define IP4_7_4         FM(A18)                 FM(LCDOUT10)    F_(0, 0)                F_(0, 0)                        FM(VI4_HSYNC_N) F_(0, 0)        FM(DU_DG2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 244 #define IP4_11_8        FM(A19)                 FM(LCDOUT11)    F_(0, 0)                F_(0, 0)                        FM(VI4_CLKENB)  F_(0, 0)        FM(DU_DG3)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 245 #define IP4_15_12       FM(CS0_N)               F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLKENB)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 246 #define IP4_19_16       FM(CS1_N_A26)           F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLK)     F_(0, 0)                FM(EX_WAIT0_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 247 #define IP4_23_20       FM(BS_N)                FM(QSTVA_QVS)   FM(MSIOF3_SCK_D)        FM(SCK3)                        FM(HSCK3)       F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN1_TX)             FM(CANFD1_TX)   FM(IETX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 248 #define IP4_27_24       FM(RD_N)                F_(0, 0)        FM(MSIOF3_SYNC_D)       FM(RX3_A)                       FM(HRX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_TX_A)           FM(CANFD0_TX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 249 #define IP4_31_28       FM(RD_WR_N)             F_(0, 0)        FM(MSIOF3_RXD_D)        FM(TX3_A)                       FM(HTX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_RX_A)           FM(CANFD0_RX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 250 #define IP5_3_0         FM(WE0_N)               F_(0, 0)        FM(MSIOF3_TXD_D)        FM(CTS3_N)                      FM(HCTS3_N)     F_(0, 0)        F_(0, 0)                FM(SCL6_B)      FM(CAN_CLK)             F_(0, 0)        FM(IECLK_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 251 #define IP5_7_4         FM(WE1_N)               F_(0, 0)        FM(MSIOF3_SS1_D)        FM(RTS3_N_TANS)                 FM(HRTS3_N)     F_(0, 0)        F_(0, 0)                FM(SDA6_B)      FM(CAN1_RX)             FM(CANFD1_RX)   FM(IERX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 252 #define IP5_11_8        FM(EX_WAIT0_A)          FM(QCLK)        F_(0, 0)                F_(0, 0)                        FM(VI4_CLK)     F_(0, 0)        FM(DU_DOTCLKOUT0)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 253 #define IP5_15_12       FM(D0)                  FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)        F_(0, 0)                        FM(VI4_DATA16)  FM(VI5_DATA0)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 254 #define IP5_19_16       FM(D1)                  FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)       F_(0, 0)                        FM(VI4_DATA17)  FM(VI5_DATA1)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 255 #define IP5_23_20       FM(D2)                  F_(0, 0)        FM(MSIOF3_RXD_A)        F_(0, 0)                        FM(VI4_DATA18)  FM(VI5_DATA2)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 256 #define IP5_27_24       FM(D3)                  F_(0, 0)        FM(MSIOF3_TXD_A)        F_(0, 0)                        FM(VI4_DATA19)  FM(VI5_DATA3)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 257 #define IP5_31_28       FM(D4)                  FM(MSIOF2_SCK_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA20)  FM(VI5_DATA4)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 258 #define IP6_3_0         FM(D5)                  FM(MSIOF2_SYNC_B)F_(0, 0)               F_(0, 0)                        FM(VI4_DATA21)  FM(VI5_DATA5)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 259 #define IP6_7_4         FM(D6)                  FM(MSIOF2_RXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA22)  FM(VI5_DATA6)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 260 #define IP6_11_8        FM(D7)                  FM(MSIOF2_TXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA23)  FM(VI5_DATA7)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 261 #define IP6_15_12       FM(D8)                  FM(LCDOUT0)     FM(MSIOF2_SCK_D)        FM(SCK4_C)                      FM(VI4_DATA0_A) F_(0, 0)        FM(DU_DR0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 262 #define IP6_19_16       FM(D9)                  FM(LCDOUT1)     FM(MSIOF2_SYNC_D)       F_(0, 0)                        FM(VI4_DATA1_A) F_(0, 0)        FM(DU_DR1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 263 #define IP6_23_20       FM(D10)                 FM(LCDOUT2)     FM(MSIOF2_RXD_D)        FM(HRX3_B)                      FM(VI4_DATA2_A) FM(CTS4_N_C)    FM(DU_DR2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 264 #define IP6_27_24       FM(D11)                 FM(LCDOUT3)     FM(MSIOF2_TXD_D)        FM(HTX3_B)                      FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3)             F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 265 #define IP6_31_28       FM(D12)                 FM(LCDOUT4)     FM(MSIOF2_SS1_D)        FM(RX4_C)                       FM(VI4_DATA4_A) F_(0, 0)        FM(DU_DR4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 266 #define IP7_3_0         FM(D13)                 FM(LCDOUT5)     FM(MSIOF2_SS2_D)        FM(TX4_C)                       FM(VI4_DATA5_A) F_(0, 0)        FM(DU_DR5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 267 #define IP7_7_4         FM(D14)                 FM(LCDOUT6)     FM(MSIOF3_SS1_A)        FM(HRX3_C)                      FM(VI4_DATA6_A) F_(0, 0)        FM(DU_DR6)              FM(SCL6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 268 #define IP7_11_8        FM(D15)                 FM(LCDOUT7)     FM(MSIOF3_SS2_A)        FM(HTX3_C)                      FM(VI4_DATA7_A) F_(0, 0)        FM(DU_DR7)              FM(SDA6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 269 #define IP7_15_12       FM(FSCLKST)             F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 270 #define IP7_19_16       FM(SD0_CLK)             F_(0, 0)        FM(MSIOF1_SCK_E)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 271
 272 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 273 #define IP7_23_20       FM(SD0_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_E)       F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 274 #define IP7_27_24       FM(SD0_DAT0)            F_(0, 0)        FM(MSIOF1_RXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_B)   FM(STP_ISCLK_0_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 275 #define IP7_31_28       FM(SD0_DAT1)            F_(0, 0)        FM(MSIOF1_TXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 276 #define IP8_3_0         FM(SD0_DAT2)            F_(0, 0)        FM(MSIOF1_SS1_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_B)  FM(STP_ISD_0_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 277 #define IP8_7_4         FM(SD0_DAT3)            F_(0, 0)        FM(MSIOF1_SS2_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_B)  FM(STP_ISEN_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 278 #define IP8_11_8        FM(SD1_CLK)             F_(0, 0)        FM(MSIOF1_SCK_G)        F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 279 #define IP8_15_12       FM(SD1_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_G)       F_(0, 0)                        F_(0, 0)        FM(SIM0_D_A)    FM(STP_IVCXO27_1_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 280 #define IP8_19_16       FM(SD1_DAT0)            FM(SD2_DAT4)    FM(MSIOF1_RXD_G)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_B)   FM(STP_ISCLK_1_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 281 #define IP8_23_20       FM(SD1_DAT1)            FM(SD2_DAT5)    FM(MSIOF1_TXD_G)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 282 #define IP8_27_24       FM(SD1_DAT2)            FM(SD2_DAT6)    FM(MSIOF1_SS1_G)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_B)  FM(STP_ISD_1_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 283 #define IP8_31_28       FM(SD1_DAT3)            FM(SD2_DAT7)    FM(MSIOF1_SS2_G)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_B)  FM(STP_ISEN_1_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 284 #define IP9_3_0         FM(SD2_CLK)             F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 285 #define IP9_7_4         FM(SD2_DAT0)            F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 286 #define IP9_11_8        FM(SD2_DAT1)            F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 287 #define IP9_15_12       FM(SD2_DAT2)            F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 288 #define IP9_19_16       FM(SD2_DAT3)            F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 289 #define IP9_23_20       FM(SD2_DS)              F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(SATA_DEVSLP_B)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 290 #define IP9_27_24       FM(SD3_DAT4)            FM(SD2_CD_A)    F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 291 #define IP9_31_28       FM(SD3_DAT5)            FM(SD2_WP_A)    F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 292 #define IP10_3_0        FM(SD3_DAT6)            FM(SD3_CD)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 293 #define IP10_7_4        FM(SD3_DAT7)            FM(SD3_WP)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 294 #define IP10_11_8       FM(SD0_CD)              F_(0, 0)        F_(0, 0)                F_(0, 0)                        FM(SCL2_B)      FM(SIM0_RST_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 295 #define IP10_15_12      FM(SD0_WP)              F_(0, 0)        F_(0, 0)                F_(0, 0)                        FM(SDA2_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 296 #define IP10_19_16      FM(SD1_CD)              F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 297 #define IP10_23_20      FM(SD1_WP)              F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(SIM0_D_B)    F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 298 #define IP10_27_24      FM(SCK0)                FM(HSCK1_B)     FM(MSIOF1_SS2_B)        FM(AUDIO_CLKC_B)                FM(SDA2_A)      FM(SIM0_RST_B)  FM(STP_OPWM_0_C)        FM(RIF0_CLK_B)  F_(0, 0)                FM(ADICHS2)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 299 #define IP10_31_28      FM(RX0)                 FM(HRX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_C)   FM(STP_ISCLK_0_C)       FM(RIF0_D0_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 300 #define IP11_3_0        FM(TX0)                 FM(HTX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)      FM(RIF0_D1_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 301 #define IP11_7_4        FM(CTS0_N)              FM(HCTS1_N_B)   FM(MSIOF1_SYNC_B)       F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)      FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C)      FM(ADICS_SAMP)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 302 #define IP11_11_8       FM(RTS0_N_TANS)         FM(HRTS1_N_B)   FM(MSIOF1_SS1_B)        FM(AUDIO_CLKA_B)                FM(SCL2_A)      F_(0, 0)        FM(STP_IVCXO27_1_C)     FM(RIF0_SYNC_B) F_(0, 0)                FM(ADICHS1)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 303 #define IP11_15_12      FM(RX1_A)               FM(HRX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_C)  FM(STP_ISD_0_C)         FM(RIF1_CLK_C)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 304 #define IP11_19_16      FM(TX1_A)               FM(HTX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_C)  FM(STP_ISEN_0_C)        FM(RIF1_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 305 #define IP11_23_20      FM(CTS1_N)              FM(HCTS1_N_A)   FM(MSIOF1_RXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_C)  FM(STP_ISEN_1_C)        FM(RIF1_D0_B)   F_(0, 0)                FM(ADIDATA)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 306 #define IP11_27_24      FM(RTS1_N_TANS)         FM(HRTS1_N_A)   FM(MSIOF1_TXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_C)  FM(STP_ISD_1_C)         FM(RIF1_D1_B)   F_(0, 0)                FM(ADICHS0)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 307 #define IP11_31_28      FM(SCK2)                FM(SCIF_CLK_B)  FM(MSIOF1_SCK_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_C)   FM(STP_ISCLK_1_C)       FM(RIF1_CLK_B)  F_(0, 0)                FM(ADICLK)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 308 #define IP12_3_0        FM(TX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_CD_B)                    FM(SCL1_A)      F_(0, 0)        FM(FMCLK_A)             FM(RIF1_D1_C)   F_(0, 0)                FM(FSO_CFE_0_B) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 309 #define IP12_7_4        FM(RX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_WP_B)                    FM(SDA1_A)      F_(0, 0)        FM(FMIN_A)              FM(RIF1_SYNC_C) F_(0, 0)                FM(FSO_CFE_1_B) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 310 #define IP12_11_8       FM(HSCK0)               F_(0, 0)        FM(MSIOF1_SCK_D)        FM(AUDIO_CLKB_A)                FM(SSI_SDATA1_B)FM(TS_SCK0_D)   FM(STP_ISCLK_0_D)       FM(RIF0_CLK_C)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 311 #define IP12_15_12      FM(HRX0)                F_(0, 0)        FM(MSIOF1_RXD_D)        F_(0, 0)                        FM(SSI_SDATA2_B)FM(TS_SDEN0_D)  FM(STP_ISEN_0_D)        FM(RIF0_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 312 #define IP12_19_16      FM(HTX0)                F_(0, 0)        FM(MSIOF1_TXD_D)        F_(0, 0)                        FM(SSI_SDATA9_B)FM(TS_SDAT0_D)  FM(STP_ISD_0_D)         FM(RIF0_D1_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 313 #define IP12_23_20      FM(HCTS0_N)             FM(RX2_B)       FM(MSIOF1_SYNC_D)       F_(0, 0)                        FM(SSI_SCK9_A)  FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D)      FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 314 #define IP12_27_24      FM(HRTS0_N)             FM(TX2_B)       FM(MSIOF1_SS1_D)        F_(0, 0)                        FM(SSI_WS9_A)   F_(0, 0)        FM(STP_IVCXO27_0_D)     FM(BPFCLK_A)    FM(AUDIO_CLKOUT2_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 315
 316 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 317 #define IP12_31_28      FM(MSIOF0_SYNC)         F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(AUDIO_CLKOUT_A)      F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 318 #define IP13_3_0        FM(MSIOF0_SS1)          FM(RX5)         F_(0, 0)                FM(AUDIO_CLKA_C)                FM(SSI_SCK2_A)  F_(0, 0)        FM(STP_IVCXO27_0_C)     F_(0, 0)        FM(AUDIO_CLKOUT3_A)     F_(0, 0)        FM(TCLK1_B)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 319 #define IP13_7_4        FM(MSIOF0_SS2)          FM(TX5)         FM(MSIOF1_SS2_D)        FM(AUDIO_CLKC_A)                FM(SSI_WS2_A)   F_(0, 0)        FM(STP_OPWM_0_D)        F_(0, 0)        FM(AUDIO_CLKOUT_D)      F_(0, 0)        FM(SPEEDIN_B)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 320 #define IP13_11_8       FM(MLB_CLK)             F_(0, 0)        FM(MSIOF1_SCK_F)        F_(0, 0)                        FM(SCL1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 321 #define IP13_15_12      FM(MLB_SIG)             FM(RX1_B)       FM(MSIOF1_SYNC_F)       F_(0, 0)                        FM(SDA1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 322 #define IP13_19_16      FM(MLB_DAT)             FM(TX1_B)       FM(MSIOF1_RXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 323 #define IP13_23_20      FM(SSI_SCK01239)        F_(0, 0)        FM(MSIOF1_TXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 324 #define IP13_27_24      FM(SSI_WS01239)         F_(0, 0)        FM(MSIOF1_SS1_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 325 #define IP13_31_28      FM(SSI_SDATA0)          F_(0, 0)        FM(MSIOF1_SS2_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 326 #define IP14_3_0        FM(SSI_SDATA1_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 327 #define IP14_7_4        FM(SSI_SDATA2_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        FM(SSI_SCK1_B)  F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 328 #define IP14_11_8       FM(SSI_SCK349)          F_(0, 0)        FM(MSIOF1_SS1_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 329 #define IP14_15_12      FM(SSI_WS349)           FM(HCTS2_N_A)   FM(MSIOF1_SS2_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_A)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 330 #define IP14_19_16      FM(SSI_SDATA3)          FM(HRTS2_N_A)   FM(MSIOF1_TXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_A)   FM(STP_ISCLK_0_A)       FM(RIF0_D1_A)   FM(RIF2_D0_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 331 #define IP14_23_20      FM(SSI_SCK4)            FM(HRX2_A)      FM(MSIOF1_SCK_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_A)  FM(STP_ISD_0_A)         FM(RIF0_CLK_A)  FM(RIF2_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 332 #define IP14_27_24      FM(SSI_WS4)             FM(HTX2_A)      FM(MSIOF1_SYNC_A)       F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_A)  FM(STP_ISEN_0_A)        FM(RIF0_SYNC_A) FM(RIF2_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 333 #define IP14_31_28      FM(SSI_SDATA4)          FM(HSCK2_A)     FM(MSIOF1_RXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)      FM(RIF0_D0_A)   FM(RIF2_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 334 #define IP15_3_0        FM(SSI_SCK6)            FM(USB2_PWEN)   F_(0, 0)                FM(SIM0_RST_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 335 #define IP15_7_4        FM(SSI_WS6)             FM(USB2_OVC)    F_(0, 0)                FM(SIM0_D_D)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 336 #define IP15_11_8       FM(SSI_SDATA6)          F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(SATA_DEVSLP_A)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 337 #define IP15_15_12      FM(SSI_SCK78)           FM(HRX2_B)      FM(MSIOF1_SCK_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_A)   FM(STP_ISCLK_1_A)       FM(RIF1_CLK_A)  FM(RIF3_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 338 #define IP15_19_16      FM(SSI_WS78)            FM(HTX2_B)      FM(MSIOF1_SYNC_C)       F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_A)  FM(STP_ISD_1_A)         FM(RIF1_SYNC_A) FM(RIF3_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 339 #define IP15_23_20      FM(SSI_SDATA7)          FM(HCTS2_N_B)   FM(MSIOF1_RXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_A)  FM(STP_ISEN_1_A)        FM(RIF1_D0_A)   FM(RIF3_D0_A)           F_(0, 0)        FM(TCLK2_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 340 #define IP15_27_24      FM(SSI_SDATA8)          FM(HRTS2_N_B)   FM(MSIOF1_TXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A)      FM(RIF1_D1_A)   FM(RIF3_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 341 #define IP15_31_28      FM(SSI_SDATA9_A)        FM(HSCK2_B)     FM(MSIOF1_SS1_C)        FM(HSCK1_A)                     FM(SSI_WS1_B)   FM(SCK1)        FM(STP_IVCXO27_1_A)     FM(SCK5)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 342 #define IP16_3_0        FM(AUDIO_CLKA_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        FM(CC5_OSCOUT)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 343 #define IP16_7_4        FM(AUDIO_CLKB_B)        FM(SCIF_CLK_A)  F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_1_D)     FM(REMOCON_A)   F_(0, 0)                F_(0, 0)        FM(TCLK1_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 344 #define IP16_11_8       FM(USB0_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_RST_C)                  F_(0, 0)        FM(TS_SCK1_D)   FM(STP_ISCLK_1_D)       FM(BPFCLK_B)    FM(RIF3_CLK_B)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 345 #define IP16_15_12      FM(USB0_OVC)            F_(0, 0)        F_(0, 0)                FM(SIM0_D_C)                    F_(0, 0)        FM(TS_SDAT1_D)  FM(STP_ISD_1_D)         F_(0, 0)        FM(RIF3_SYNC_B)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 346 #define IP16_19_16      FM(USB1_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_C)                  FM(SSI_SCK1_A)  FM(TS_SCK0_E)   FM(STP_ISCLK_0_E)       FM(FMCLK_B)     FM(RIF2_CLK_B)          F_(0, 0)        FM(SPEEDIN_A)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 347 #define IP16_23_20      FM(USB1_OVC)            F_(0, 0)        FM(MSIOF1_SS2_C)        F_(0, 0)                        FM(SSI_WS1_A)   FM(TS_SDAT0_E)  FM(STP_ISD_0_E)         FM(FMIN_B)      FM(RIF2_SYNC_B)         F_(0, 0)        FM(REMOCON_B)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 348 #define IP16_27_24      FM(USB30_PWEN)          F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT_B)              FM(SSI_SCK2_B)  FM(TS_SDEN1_D)  FM(STP_ISEN_1_D)        FM(STP_OPWM_0_E)FM(RIF3_D0_B)           F_(0, 0)        FM(TCLK2_B)     FM(TPU0TO0)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 349 #define IP16_31_28      FM(USB30_OVC)           F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT1_B)             FM(SSI_WS2_B)   FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)      FM(STP_IVCXO27_0_E)FM(RIF3_D1_B)        F_(0, 0)        FM(FSO_TOE_B)   FM(TPU0TO1)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 350 #define IP17_3_0        FM(USB31_PWEN)          F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT2_B)             FM(SSI_SCK9_B)  FM(TS_SDEN0_E)  FM(STP_ISEN_0_E)        F_(0, 0)        FM(RIF2_D0_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO2)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 351 #define IP17_7_4        FM(USB31_OVC)           F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT3_B)             FM(SSI_WS9_B)   FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)      F_(0, 0)        FM(RIF2_D1_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO3)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 352
 353 #define PINMUX_GPSR     \
 354 \
 355                                                                                                 GPSR6_31 \
 356                                                                                                 GPSR6_30 \
 357                                                                                                 GPSR6_29 \
 358                                                                                                 GPSR6_28 \
 359                 GPSR1_27                                                                        GPSR6_27 \
 360                 GPSR1_26                                                                        GPSR6_26 \
 361                 GPSR1_25                                                        GPSR5_25        GPSR6_25 \
 362                 GPSR1_24                                                        GPSR5_24        GPSR6_24 \
 363                 GPSR1_23                                                        GPSR5_23        GPSR6_23 \
 364                 GPSR1_22                                                        GPSR5_22        GPSR6_22 \
 365                 GPSR1_21                                                        GPSR5_21        GPSR6_21 \
 366                 GPSR1_20                                                        GPSR5_20        GPSR6_20 \
 367                 GPSR1_19                                                        GPSR5_19        GPSR6_19 \
 368                 GPSR1_18                                                        GPSR5_18        GPSR6_18 \
 369                 GPSR1_17                                        GPSR4_17        GPSR5_17        GPSR6_17 \
 370                 GPSR1_16                                        GPSR4_16        GPSR5_16        GPSR6_16 \
 371 GPSR0_15        GPSR1_15                        GPSR3_15        GPSR4_15        GPSR5_15        GPSR6_15 \
 372 GPSR0_14        GPSR1_14        GPSR2_14        GPSR3_14        GPSR4_14        GPSR5_14        GPSR6_14 \
 373 GPSR0_13        GPSR1_13        GPSR2_13        GPSR3_13        GPSR4_13        GPSR5_13        GPSR6_13 \
 374 GPSR0_12        GPSR1_12        GPSR2_12        GPSR3_12        GPSR4_12        GPSR5_12        GPSR6_12 \
 375 GPSR0_11        GPSR1_11        GPSR2_11        GPSR3_11        GPSR4_11        GPSR5_11        GPSR6_11 \
 376 GPSR0_10        GPSR1_10        GPSR2_10        GPSR3_10        GPSR4_10        GPSR5_10        GPSR6_10 \
 377 GPSR0_9         GPSR1_9         GPSR2_9         GPSR3_9         GPSR4_9         GPSR5_9         GPSR6_9 \
 378 GPSR0_8         GPSR1_8         GPSR2_8         GPSR3_8         GPSR4_8         GPSR5_8         GPSR6_8 \
 379 GPSR0_7         GPSR1_7         GPSR2_7         GPSR3_7         GPSR4_7         GPSR5_7         GPSR6_7 \
 380 GPSR0_6         GPSR1_6         GPSR2_6         GPSR3_6         GPSR4_6         GPSR5_6         GPSR6_6 \
 381 GPSR0_5         GPSR1_5         GPSR2_5         GPSR3_5         GPSR4_5         GPSR5_5         GPSR6_5 \
 382 GPSR0_4         GPSR1_4         GPSR2_4         GPSR3_4         GPSR4_4         GPSR5_4         GPSR6_4 \
 383 GPSR0_3         GPSR1_3         GPSR2_3         GPSR3_3         GPSR4_3         GPSR5_3         GPSR6_3         GPSR7_3 \
 384 GPSR0_2         GPSR1_2         GPSR2_2         GPSR3_2         GPSR4_2         GPSR5_2         GPSR6_2         GPSR7_2 \
 385 GPSR0_1         GPSR1_1         GPSR2_1         GPSR3_1         GPSR4_1         GPSR5_1         GPSR6_1         GPSR7_1 \
 386 GPSR0_0         GPSR1_0         GPSR2_0         GPSR3_0         GPSR4_0         GPSR5_0         GPSR6_0         GPSR7_0
 387
 388 #define PINMUX_IPSR                             \
 389 \
 390 FM(IP0_3_0)     IP0_3_0         FM(IP1_3_0)     IP1_3_0         FM(IP2_3_0)     IP2_3_0         FM(IP3_3_0)     IP3_3_0 \
 391 FM(IP0_7_4)     IP0_7_4         FM(IP1_7_4)     IP1_7_4         FM(IP2_7_4)     IP2_7_4         FM(IP3_7_4)     IP3_7_4 \
 392 FM(IP0_11_8)    IP0_11_8        FM(IP1_11_8)    IP1_11_8        FM(IP2_11_8)    IP2_11_8        FM(IP3_11_8)    IP3_11_8 \
 393 FM(IP0_15_12)   IP0_15_12       FM(IP1_15_12)   IP1_15_12       FM(IP2_15_12)   IP2_15_12       FM(IP3_15_12)   IP3_15_12 \
 394 FM(IP0_19_16)   IP0_19_16       FM(IP1_19_16)   IP1_19_16       FM(IP2_19_16)   IP2_19_16       FM(IP3_19_16)   IP3_19_16 \
 395 FM(IP0_23_20)   IP0_23_20       FM(IP1_23_20)   IP1_23_20       FM(IP2_23_20)   IP2_23_20       FM(IP3_23_20)   IP3_23_20 \
 396 FM(IP0_27_24)   IP0_27_24       FM(IP1_27_24)   IP1_27_24       FM(IP2_27_24)   IP2_27_24       FM(IP3_27_24)   IP3_27_24 \
 397 FM(IP0_31_28)   IP0_31_28       FM(IP1_31_28)   IP1_31_28       FM(IP2_31_28)   IP2_31_28       FM(IP3_31_28)   IP3_31_28 \
 398 \
 399 FM(IP4_3_0)     IP4_3_0         FM(IP5_3_0)     IP5_3_0         FM(IP6_3_0)     IP6_3_0         FM(IP7_3_0)     IP7_3_0 \
 400 FM(IP4_7_4)     IP4_7_4         FM(IP5_7_4)     IP5_7_4         FM(IP6_7_4)     IP6_7_4         FM(IP7_7_4)     IP7_7_4 \
 401 FM(IP4_11_8)    IP4_11_8        FM(IP5_11_8)    IP5_11_8        FM(IP6_11_8)    IP6_11_8        FM(IP7_11_8)    IP7_11_8 \
 402 FM(IP4_15_12)   IP4_15_12       FM(IP5_15_12)   IP5_15_12       FM(IP6_15_12)   IP6_15_12       FM(IP7_15_12)   IP7_15_12 \
 403 FM(IP4_19_16)   IP4_19_16       FM(IP5_19_16)   IP5_19_16       FM(IP6_19_16)   IP6_19_16       FM(IP7_19_16)   IP7_19_16 \
 404 FM(IP4_23_20)   IP4_23_20       FM(IP5_23_20)   IP5_23_20       FM(IP6_23_20)   IP6_23_20       FM(IP7_23_20)   IP7_23_20 \
 405 FM(IP4_27_24)   IP4_27_24       FM(IP5_27_24)   IP5_27_24       FM(IP6_27_24)   IP6_27_24       FM(IP7_27_24)   IP7_27_24 \
 406 FM(IP4_31_28)   IP4_31_28       FM(IP5_31_28)   IP5_31_28       FM(IP6_31_28)   IP6_31_28       FM(IP7_31_28)   IP7_31_28 \
 407 \
 408 FM(IP8_3_0)     IP8_3_0         FM(IP9_3_0)     IP9_3_0         FM(IP10_3_0)    IP10_3_0        FM(IP11_3_0)    IP11_3_0 \
 409 FM(IP8_7_4)     IP8_7_4         FM(IP9_7_4)     IP9_7_4         FM(IP10_7_4)    IP10_7_4        FM(IP11_7_4)    IP11_7_4 \
 410 FM(IP8_11_8)    IP8_11_8        FM(IP9_11_8)    IP9_11_8        FM(IP10_11_8)   IP10_11_8       FM(IP11_11_8)   IP11_11_8 \
 411 FM(IP8_15_12)   IP8_15_12       FM(IP9_15_12)   IP9_15_12       FM(IP10_15_12)  IP10_15_12      FM(IP11_15_12)  IP11_15_12 \
 412 FM(IP8_19_16)   IP8_19_16       FM(IP9_19_16)   IP9_19_16       FM(IP10_19_16)  IP10_19_16      FM(IP11_19_16)  IP11_19_16 \
 413 FM(IP8_23_20)   IP8_23_20       FM(IP9_23_20)   IP9_23_20       FM(IP10_23_20)  IP10_23_20      FM(IP11_23_20)  IP11_23_20 \
 414 FM(IP8_27_24)   IP8_27_24       FM(IP9_27_24)   IP9_27_24       FM(IP10_27_24)  IP10_27_24      FM(IP11_27_24)  IP11_27_24 \
 415 FM(IP8_31_28)   IP8_31_28       FM(IP9_31_28)   IP9_31_28       FM(IP10_31_28)  IP10_31_28      FM(IP11_31_28)  IP11_31_28 \
 416 \
 417 FM(IP12_3_0)    IP12_3_0        FM(IP13_3_0)    IP13_3_0        FM(IP14_3_0)    IP14_3_0        FM(IP15_3_0)    IP15_3_0 \
 418 FM(IP12_7_4)    IP12_7_4        FM(IP13_7_4)    IP13_7_4        FM(IP14_7_4)    IP14_7_4        FM(IP15_7_4)    IP15_7_4 \
 419 FM(IP12_11_8)   IP12_11_8       FM(IP13_11_8)   IP13_11_8       FM(IP14_11_8)   IP14_11_8       FM(IP15_11_8)   IP15_11_8 \
 420 FM(IP12_15_12)  IP12_15_12      FM(IP13_15_12)  IP13_15_12      FM(IP14_15_12)  IP14_15_12      FM(IP15_15_12)  IP15_15_12 \
 421 FM(IP12_19_16)  IP12_19_16      FM(IP13_19_16)  IP13_19_16      FM(IP14_19_16)  IP14_19_16      FM(IP15_19_16)  IP15_19_16 \
 422 FM(IP12_23_20)  IP12_23_20      FM(IP13_23_20)  IP13_23_20      FM(IP14_23_20)  IP14_23_20      FM(IP15_23_20)  IP15_23_20 \
 423 FM(IP12_27_24)  IP12_27_24      FM(IP13_27_24)  IP13_27_24      FM(IP14_27_24)  IP14_27_24      FM(IP15_27_24)  IP15_27_24 \
 424 FM(IP12_31_28)  IP12_31_28      FM(IP13_31_28)  IP13_31_28      FM(IP14_31_28)  IP14_31_28      FM(IP15_31_28)  IP15_31_28 \
 425 \
 426 FM(IP16_3_0)    IP16_3_0        FM(IP17_3_0)    IP17_3_0 \
 427 FM(IP16_7_4)    IP16_7_4        FM(IP17_7_4)    IP17_7_4 \
 428 FM(IP16_11_8)   IP16_11_8 \
 429 FM(IP16_15_12)  IP16_15_12 \
 430 FM(IP16_19_16)  IP16_19_16 \
 431 FM(IP16_23_20)  IP16_23_20 \
 432 FM(IP16_27_24)  IP16_27_24 \
 433 FM(IP16_31_28)  IP16_31_28
 434
 435 /* MOD_SEL0 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 436 #define MOD_SEL0_30_29          FM(SEL_MSIOF3_0)        FM(SEL_MSIOF3_1)        FM(SEL_MSIOF3_2)        FM(SEL_MSIOF3_3)
 437 #define MOD_SEL0_28_27          FM(SEL_MSIOF2_0)        FM(SEL_MSIOF2_1)        FM(SEL_MSIOF2_2)        FM(SEL_MSIOF2_3)
 438 #define MOD_SEL0_26_25_24       FM(SEL_MSIOF1_0)        FM(SEL_MSIOF1_1)        FM(SEL_MSIOF1_2)        FM(SEL_MSIOF1_3)        FM(SEL_MSIOF1_4)        FM(SEL_MSIOF1_5)        FM(SEL_MSIOF1_6)        F_(0, 0)
 439 #define MOD_SEL0_23             FM(SEL_LBSC_0)          FM(SEL_LBSC_1)
 440 #define MOD_SEL0_22             FM(SEL_IEBUS_0)         FM(SEL_IEBUS_1)
 441 #define MOD_SEL0_21_20          FM(SEL_I2C6_0)          FM(SEL_I2C6_1)          FM(SEL_I2C6_2)          F_(0, 0)
 442 #define MOD_SEL0_19             FM(SEL_I2C2_0)          FM(SEL_I2C2_1)
 443 #define MOD_SEL0_18             FM(SEL_I2C1_0)          FM(SEL_I2C1_1)
 444 #define MOD_SEL0_17             FM(SEL_HSCIF4_0)        FM(SEL_HSCIF4_1)
 445 #define MOD_SEL0_16_15          FM(SEL_HSCIF3_0)        FM(SEL_HSCIF3_1)        FM(SEL_HSCIF3_2)        FM(SEL_HSCIF3_3)
 446 #define MOD_SEL0_14             FM(SEL_HSCIF2_0)        FM(SEL_HSCIF2_1)
 447 #define MOD_SEL0_13             FM(SEL_HSCIF1_0)        FM(SEL_HSCIF1_1)
 448 #define MOD_SEL0_12             FM(SEL_FSO_0)           FM(SEL_FSO_1)
 449 #define MOD_SEL0_11             FM(SEL_FM_0)            FM(SEL_FM_1)
 450 #define MOD_SEL0_10             FM(SEL_ETHERAVB_0)      FM(SEL_ETHERAVB_1)
 451 #define MOD_SEL0_9              FM(SEL_DRIF3_0)         FM(SEL_DRIF3_1)
 452 #define MOD_SEL0_8              FM(SEL_DRIF2_0)         FM(SEL_DRIF2_1)
 453 #define MOD_SEL0_7_6            FM(SEL_DRIF1_0)         FM(SEL_DRIF1_1)         FM(SEL_DRIF1_2)         F_(0, 0)
 454 #define MOD_SEL0_5_4            FM(SEL_DRIF0_0)         FM(SEL_DRIF0_1)         FM(SEL_DRIF0_2)         F_(0, 0)
 455 #define MOD_SEL0_3              FM(SEL_CANFD0_0)        FM(SEL_CANFD0_1)
 456 #define MOD_SEL0_2_1            FM(SEL_ADG_0)           FM(SEL_ADG_1)           FM(SEL_ADG_2)           FM(SEL_ADG_3)
 457
 458 /* MOD_SEL1 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 459 #define MOD_SEL1_31_30          FM(SEL_TSIF1_0)         FM(SEL_TSIF1_1)         FM(SEL_TSIF1_2)         FM(SEL_TSIF1_3)
 460 #define MOD_SEL1_29_28_27       FM(SEL_TSIF0_0)         FM(SEL_TSIF0_1)         FM(SEL_TSIF0_2)         FM(SEL_TSIF0_3)         FM(SEL_TSIF0_4)         F_(0, 0)                F_(0, 0)                F_(0, 0)
 461 #define MOD_SEL1_26             FM(SEL_TIMER_TMU_0)     FM(SEL_TIMER_TMU_1)
 462 #define MOD_SEL1_25_24          FM(SEL_SSP1_1_0)        FM(SEL_SSP1_1_1)        FM(SEL_SSP1_1_2)        FM(SEL_SSP1_1_3)
 463 #define MOD_SEL1_23_22_21       FM(SEL_SSP1_0_0)        FM(SEL_SSP1_0_1)        FM(SEL_SSP1_0_2)        FM(SEL_SSP1_0_3)        FM(SEL_SSP1_0_4)        F_(0, 0)                F_(0, 0)                F_(0, 0)
 464 #define MOD_SEL1_20             FM(SEL_SSI_0)           FM(SEL_SSI_1)
 465 #define MOD_SEL1_19             FM(SEL_SPEED_PULSE_0)   FM(SEL_SPEED_PULSE_1)
 466 #define MOD_SEL1_18_17          FM(SEL_SIMCARD_0)       FM(SEL_SIMCARD_1)       FM(SEL_SIMCARD_2)       FM(SEL_SIMCARD_3)
 467 #define MOD_SEL1_16             FM(SEL_SDHI2_0)         FM(SEL_SDHI2_1)
 468 #define MOD_SEL1_15_14          FM(SEL_SCIF4_0)         FM(SEL_SCIF4_1)         FM(SEL_SCIF4_2)         F_(0, 0)
 469 #define MOD_SEL1_13             FM(SEL_SCIF3_0)         FM(SEL_SCIF3_1)
 470 #define MOD_SEL1_12             FM(SEL_SCIF2_0)         FM(SEL_SCIF2_1)
 471 #define MOD_SEL1_11             FM(SEL_SCIF1_0)         FM(SEL_SCIF1_1)
 472 #define MOD_SEL1_10             FM(SEL_SATA_0)          FM(SEL_SATA_1)
 473 #define MOD_SEL1_9              FM(SEL_REMOCON_0)       FM(SEL_REMOCON_1)
 474 #define MOD_SEL1_6              FM(SEL_RCAN0_0)         FM(SEL_RCAN0_1)
 475 #define MOD_SEL1_5              FM(SEL_PWM6_0)          FM(SEL_PWM6_1)
 476 #define MOD_SEL1_4              FM(SEL_PWM5_0)          FM(SEL_PWM5_1)
 477 #define MOD_SEL1_3              FM(SEL_PWM4_0)          FM(SEL_PWM4_1)
 478 #define MOD_SEL1_2              FM(SEL_PWM3_0)          FM(SEL_PWM3_1)
 479 #define MOD_SEL1_1              FM(SEL_PWM2_0)          FM(SEL_PWM2_1)
 480 #define MOD_SEL1_0              FM(SEL_PWM1_0)          FM(SEL_PWM1_1)
 481
 482 /* MOD_SEL2 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */
 483 #define MOD_SEL2_31             FM(I2C_SEL_5_0)         FM(I2C_SEL_5_1)
 484 #define MOD_SEL2_30             FM(I2C_SEL_3_0)         FM(I2C_SEL_3_1)
 485 #define MOD_SEL2_29             FM(I2C_SEL_0_0)         FM(I2C_SEL_0_1)
 486 #define MOD_SEL2_0              FM(SEL_VIN4_0)          FM(SEL_VIN4_1)
 487
 488 #define PINMUX_MOD_SELS\
 489 \
 490                         MOD_SEL1_31_30          MOD_SEL2_31 \
 491 MOD_SEL0_30_29                                  MOD_SEL2_30 \
 492                         MOD_SEL1_29_28_27       MOD_SEL2_29 \
 493 MOD_SEL0_28_27 \
 494 \
 495 MOD_SEL0_26_25_24       MOD_SEL1_26 \
 496                         MOD_SEL1_25_24 \
 497 \
 498 MOD_SEL0_23             MOD_SEL1_23_22_21 \
 499 MOD_SEL0_22 \
 500 MOD_SEL0_21_20 \
 501                         MOD_SEL1_20 \
 502 MOD_SEL0_19             MOD_SEL1_19 \
 503 MOD_SEL0_18             MOD_SEL1_18_17 \
 504 MOD_SEL0_17 \
 505 MOD_SEL0_16_15          MOD_SEL1_16 \
 506                         MOD_SEL1_15_14 \
 507 MOD_SEL0_14 \
 508 MOD_SEL0_13             MOD_SEL1_13 \
 509 MOD_SEL0_12             MOD_SEL1_12 \
 510 MOD_SEL0_11             MOD_SEL1_11 \
 511 MOD_SEL0_10             MOD_SEL1_10 \
 512 MOD_SEL0_9              MOD_SEL1_9 \
 513 MOD_SEL0_8 \
 514 MOD_SEL0_7_6 \
 515                         MOD_SEL1_6 \
 516 MOD_SEL0_5_4            MOD_SEL1_5 \
 517                         MOD_SEL1_4 \
 518 MOD_SEL0_3              MOD_SEL1_3 \
 519 MOD_SEL0_2_1            MOD_SEL1_2 \
 520                         MOD_SEL1_1 \
 521                         MOD_SEL1_0              MOD_SEL2_0
 522
 523 /*
 524  * These pins are not able to be muxed but have other properties
 525  * that can be set, such as drive-strength or pull-up/pull-down enable.
 526  */
 527 #define PINMUX_STATIC \
 528         FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
 529         FM(QSPI0_IO2) FM(QSPI0_IO3) \
 530         FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
 531         FM(QSPI1_IO2) FM(QSPI1_IO3) \
 532         FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
 533         FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
 534         FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
 535         FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
 536         FM(CLKOUT) FM(PRESETOUT) \
 537         FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
 538         FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
 539
 540 enum {
 541         PINMUX_RESERVED = 0,
 542
 543         PINMUX_DATA_BEGIN,
 544         GP_ALL(DATA),
 545         PINMUX_DATA_END,
 546
 547 #define F_(x, y)
 548 #define FM(x)   FN_##x,
 549         PINMUX_FUNCTION_BEGIN,
 550         GP_ALL(FN),
 551         PINMUX_GPSR
 552         PINMUX_IPSR
 553         PINMUX_MOD_SELS
 554         PINMUX_FUNCTION_END,
 555 #undef F_
 556 #undef FM
 557
 558 #define F_(x, y)
 559 #define FM(x)   x##_MARK,
 560         PINMUX_MARK_BEGIN,
 561         PINMUX_GPSR
 562         PINMUX_IPSR
 563         PINMUX_MOD_SELS
 564         PINMUX_STATIC
 565         PINMUX_MARK_END,
 566 #undef F_
 567 #undef FM
 568 };
 569
 570 static const u16 pinmux_data[] = {
 571         PINMUX_DATA_GP_ALL(),
 572
 573         PINMUX_SINGLE(AVS1),
 574         PINMUX_SINGLE(AVS2),
 575         PINMUX_SINGLE(HDMI0_CEC),
 576         PINMUX_SINGLE(HDMI1_CEC),
 577         PINMUX_SINGLE(I2C_SEL_0_1),
 578         PINMUX_SINGLE(I2C_SEL_3_1),
 579         PINMUX_SINGLE(I2C_SEL_5_1),
 580         PINMUX_SINGLE(MSIOF0_RXD),
 581         PINMUX_SINGLE(MSIOF0_SCK),
 582         PINMUX_SINGLE(MSIOF0_TXD),
 583         PINMUX_SINGLE(SD2_CMD),
 584         PINMUX_SINGLE(SD3_CLK),
 585         PINMUX_SINGLE(SD3_CMD),
 586         PINMUX_SINGLE(SD3_DAT0),
 587         PINMUX_SINGLE(SD3_DAT1),
 588         PINMUX_SINGLE(SD3_DAT2),
 589         PINMUX_SINGLE(SD3_DAT3),
 590         PINMUX_SINGLE(SD3_DS),
 591         PINMUX_SINGLE(SSI_SCK5),
 592         PINMUX_SINGLE(SSI_SDATA5),
 593         PINMUX_SINGLE(SSI_WS5),
 594
 595         /* IPSR0 */
 596         PINMUX_IPSR_GPSR(IP0_3_0,       AVB_MDC),
 597         PINMUX_IPSR_MSEL(IP0_3_0,       MSIOF2_SS2_C,           SEL_MSIOF2_2),
 598
 599         PINMUX_IPSR_GPSR(IP0_7_4,       AVB_MAGIC),
 600         PINMUX_IPSR_MSEL(IP0_7_4,       MSIOF2_SS1_C,           SEL_MSIOF2_2),
 601         PINMUX_IPSR_MSEL(IP0_7_4,       SCK4_A,                 SEL_SCIF4_0),
 602
 603         PINMUX_IPSR_GPSR(IP0_11_8,      AVB_PHY_INT),
 604         PINMUX_IPSR_MSEL(IP0_11_8,      MSIOF2_SYNC_C,          SEL_MSIOF2_2),
 605         PINMUX_IPSR_MSEL(IP0_11_8,      RX4_A,                  SEL_SCIF4_0),
 606
 607         PINMUX_IPSR_GPSR(IP0_15_12,     AVB_LINK),
 608         PINMUX_IPSR_MSEL(IP0_15_12,     MSIOF2_SCK_C,           SEL_MSIOF2_2),
 609         PINMUX_IPSR_MSEL(IP0_15_12,     TX4_A,                  SEL_SCIF4_0),
 610
 611         PINMUX_IPSR_MSEL(IP0_19_16,     AVB_AVTP_MATCH_A,       SEL_ETHERAVB_0),
 612         PINMUX_IPSR_MSEL(IP0_19_16,     MSIOF2_RXD_C,           SEL_MSIOF2_2),
 613         PINMUX_IPSR_MSEL(IP0_19_16,     CTS4_N_A,               SEL_SCIF4_0),
 614
 615         PINMUX_IPSR_MSEL(IP0_23_20,     AVB_AVTP_CAPTURE_A,     SEL_ETHERAVB_0),
 616         PINMUX_IPSR_MSEL(IP0_23_20,     MSIOF2_TXD_C,           SEL_MSIOF2_2),
 617         PINMUX_IPSR_MSEL(IP0_23_20,     RTS4_N_TANS_A,          SEL_SCIF4_0),
 618
 619         PINMUX_IPSR_GPSR(IP0_27_24,     IRQ0),
 620         PINMUX_IPSR_GPSR(IP0_27_24,     QPOLB),
 621         PINMUX_IPSR_GPSR(IP0_27_24,     DU_CDE),
 622         PINMUX_IPSR_MSEL(IP0_27_24,     VI4_DATA0_B,            SEL_VIN4_1),
 623         PINMUX_IPSR_MSEL(IP0_27_24,     CAN0_TX_B,              SEL_RCAN0_1),
 624         PINMUX_IPSR_MSEL(IP0_27_24,     CANFD0_TX_B,            SEL_CANFD0_1),
 625
 626         PINMUX_IPSR_GPSR(IP0_31_28,     IRQ1),
 627         PINMUX_IPSR_GPSR(IP0_31_28,     QPOLA),
 628         PINMUX_IPSR_GPSR(IP0_31_28,     DU_DISP),
 629         PINMUX_IPSR_MSEL(IP0_31_28,     VI4_DATA1_B,            SEL_VIN4_1),
 630         PINMUX_IPSR_MSEL(IP0_31_28,     CAN0_RX_B,              SEL_RCAN0_1),
 631         PINMUX_IPSR_MSEL(IP0_31_28,     CANFD0_RX_B,            SEL_CANFD0_1),
 632
 633         /* IPSR1 */
 634         PINMUX_IPSR_GPSR(IP1_3_0,       IRQ2),
 635         PINMUX_IPSR_GPSR(IP1_3_0,       QCPV_QDE),
 636         PINMUX_IPSR_GPSR(IP1_3_0,       DU_EXODDF_DU_ODDF_DISP_CDE),
 637         PINMUX_IPSR_MSEL(IP1_3_0,       VI4_DATA2_B,            SEL_VIN4_1),
 638         PINMUX_IPSR_MSEL(IP1_3_0,       PWM3_B,                 SEL_PWM3_1),
 639
 640         PINMUX_IPSR_GPSR(IP1_7_4,       IRQ3),
 641         PINMUX_IPSR_GPSR(IP1_7_4,       QSTVB_QVE),
 642         PINMUX_IPSR_GPSR(IP1_7_4,       A25),
 643         PINMUX_IPSR_GPSR(IP1_7_4,       DU_DOTCLKOUT1),
 644         PINMUX_IPSR_MSEL(IP1_7_4,       VI4_DATA3_B,            SEL_VIN4_1),
 645         PINMUX_IPSR_MSEL(IP1_7_4,       PWM4_B,                 SEL_PWM4_1),
 646
 647         PINMUX_IPSR_GPSR(IP1_11_8,      IRQ4),
 648         PINMUX_IPSR_GPSR(IP1_11_8,      QSTH_QHS),
 649         PINMUX_IPSR_GPSR(IP1_11_8,      A24),
 650         PINMUX_IPSR_GPSR(IP1_11_8,      DU_EXHSYNC_DU_HSYNC),
 651         PINMUX_IPSR_MSEL(IP1_11_8,      VI4_DATA4_B,            SEL_VIN4_1),
 652         PINMUX_IPSR_MSEL(IP1_11_8,      PWM5_B,                 SEL_PWM5_1),
 653
 654         PINMUX_IPSR_GPSR(IP1_15_12,     IRQ5),
 655         PINMUX_IPSR_GPSR(IP1_15_12,     QSTB_QHE),
 656         PINMUX_IPSR_GPSR(IP1_15_12,     A23),
 657         PINMUX_IPSR_GPSR(IP1_15_12,     DU_EXVSYNC_DU_VSYNC),
 658         PINMUX_IPSR_MSEL(IP1_15_12,     VI4_DATA5_B,            SEL_VIN4_1),
 659         PINMUX_IPSR_MSEL(IP1_15_12,     PWM6_B,                 SEL_PWM6_1),
 660
 661         PINMUX_IPSR_GPSR(IP1_19_16,     PWM0),
 662         PINMUX_IPSR_GPSR(IP1_19_16,     AVB_AVTP_PPS),
 663         PINMUX_IPSR_GPSR(IP1_19_16,     A22),
 664         PINMUX_IPSR_MSEL(IP1_19_16,     VI4_DATA6_B,            SEL_VIN4_1),
 665         PINMUX_IPSR_MSEL(IP1_19_16,     IECLK_B,                SEL_IEBUS_1),
 666
 667         PINMUX_IPSR_MSEL(IP1_23_20,     PWM1_A,                 SEL_PWM1_0),
 668         PINMUX_IPSR_GPSR(IP1_23_20,     A21),
 669         PINMUX_IPSR_MSEL(IP1_23_20,     HRX3_D,                 SEL_HSCIF3_3),
 670         PINMUX_IPSR_MSEL(IP1_23_20,     VI4_DATA7_B,            SEL_VIN4_1),
 671         PINMUX_IPSR_MSEL(IP1_23_20,     IERX_B,                 SEL_IEBUS_1),
 672
 673         PINMUX_IPSR_MSEL(IP1_27_24,     PWM2_A,                 SEL_PWM2_0),
 674         PINMUX_IPSR_GPSR(IP1_27_24,     A20),
 675         PINMUX_IPSR_MSEL(IP1_27_24,     HTX3_D,                 SEL_HSCIF3_3),
 676         PINMUX_IPSR_MSEL(IP1_27_24,     IETX_B,                 SEL_IEBUS_1),
 677
 678         PINMUX_IPSR_GPSR(IP1_31_28,     A0),
 679         PINMUX_IPSR_GPSR(IP1_31_28,     LCDOUT16),
 680         PINMUX_IPSR_MSEL(IP1_31_28,     MSIOF3_SYNC_B,          SEL_MSIOF3_1),
 681         PINMUX_IPSR_GPSR(IP1_31_28,     VI4_DATA8),
 682         PINMUX_IPSR_GPSR(IP1_31_28,     DU_DB0),
 683         PINMUX_IPSR_MSEL(IP1_31_28,     PWM3_A,                 SEL_PWM3_0),
 684
 685         /* IPSR2 */
 686         PINMUX_IPSR_GPSR(IP2_3_0,       A1),
 687         PINMUX_IPSR_GPSR(IP2_3_0,       LCDOUT17),
 688         PINMUX_IPSR_MSEL(IP2_3_0,       MSIOF3_TXD_B,           SEL_MSIOF3_1),
 689         PINMUX_IPSR_GPSR(IP2_3_0,       VI4_DATA9),
 690         PINMUX_IPSR_GPSR(IP2_3_0,       DU_DB1),
 691         PINMUX_IPSR_MSEL(IP2_3_0,       PWM4_A,                 SEL_PWM4_0),
 692
 693         PINMUX_IPSR_GPSR(IP2_7_4,       A2),
 694         PINMUX_IPSR_GPSR(IP2_7_4,       LCDOUT18),
 695         PINMUX_IPSR_MSEL(IP2_7_4,       MSIOF3_SCK_B,           SEL_MSIOF3_1),
 696         PINMUX_IPSR_GPSR(IP2_7_4,       VI4_DATA10),
 697         PINMUX_IPSR_GPSR(IP2_7_4,       DU_DB2),
 698         PINMUX_IPSR_MSEL(IP2_7_4,       PWM5_A,                 SEL_PWM5_0),
 699
 700         PINMUX_IPSR_GPSR(IP2_11_8,      A3),
 701         PINMUX_IPSR_GPSR(IP2_11_8,      LCDOUT19),
 702         PINMUX_IPSR_MSEL(IP2_11_8,      MSIOF3_RXD_B,           SEL_MSIOF3_1),
 703         PINMUX_IPSR_GPSR(IP2_11_8,      VI4_DATA11),
 704         PINMUX_IPSR_GPSR(IP2_11_8,      DU_DB3),
 705         PINMUX_IPSR_MSEL(IP2_11_8,      PWM6_A,                 SEL_PWM6_0),
 706
 707         PINMUX_IPSR_GPSR(IP2_15_12,     A4),
 708         PINMUX_IPSR_GPSR(IP2_15_12,     LCDOUT20),
 709         PINMUX_IPSR_MSEL(IP2_15_12,     MSIOF3_SS1_B,           SEL_MSIOF3_1),
 710         PINMUX_IPSR_GPSR(IP2_15_12,     VI4_DATA12),
 711         PINMUX_IPSR_GPSR(IP2_15_12,     VI5_DATA12),
 712         PINMUX_IPSR_GPSR(IP2_15_12,     DU_DB4),
 713
 714         PINMUX_IPSR_GPSR(IP2_19_16,     A5),
 715         PINMUX_IPSR_GPSR(IP2_19_16,     LCDOUT21),
 716         PINMUX_IPSR_MSEL(IP2_19_16,     MSIOF3_SS2_B,           SEL_MSIOF3_1),
 717         PINMUX_IPSR_MSEL(IP2_19_16,     SCK4_B,                 SEL_SCIF4_1),
 718         PINMUX_IPSR_GPSR(IP2_19_16,     VI4_DATA13),
 719         PINMUX_IPSR_GPSR(IP2_19_16,     VI5_DATA13),
 720         PINMUX_IPSR_GPSR(IP2_19_16,     DU_DB5),
 721
 722         PINMUX_IPSR_GPSR(IP2_23_20,     A6),
 723         PINMUX_IPSR_GPSR(IP2_23_20,     LCDOUT22),
 724         PINMUX_IPSR_MSEL(IP2_23_20,     MSIOF2_SS1_A,           SEL_MSIOF2_0),
 725         PINMUX_IPSR_MSEL(IP2_23_20,     RX4_B,                  SEL_SCIF4_1),
 726         PINMUX_IPSR_GPSR(IP2_23_20,     VI4_DATA14),
 727         PINMUX_IPSR_GPSR(IP2_23_20,     VI5_DATA14),
 728         PINMUX_IPSR_GPSR(IP2_23_20,     DU_DB6),
 729
 730         PINMUX_IPSR_GPSR(IP2_27_24,     A7),
 731         PINMUX_IPSR_GPSR(IP2_27_24,     LCDOUT23),
 732         PINMUX_IPSR_MSEL(IP2_27_24,     MSIOF2_SS2_A,           SEL_MSIOF2_0),
 733         PINMUX_IPSR_MSEL(IP2_27_24,     TX4_B,                  SEL_SCIF4_1),
 734         PINMUX_IPSR_GPSR(IP2_27_24,     VI4_DATA15),
 735         PINMUX_IPSR_GPSR(IP2_27_24,     VI5_DATA15),
 736         PINMUX_IPSR_GPSR(IP2_27_24,     DU_DB7),
 737
 738         PINMUX_IPSR_GPSR(IP2_31_28,     A8),
 739         PINMUX_IPSR_MSEL(IP2_31_28,     RX3_B,                  SEL_SCIF3_1),
 740         PINMUX_IPSR_MSEL(IP2_31_28,     MSIOF2_SYNC_A,          SEL_MSIOF2_0),
 741         PINMUX_IPSR_MSEL(IP2_31_28,     HRX4_B,                 SEL_HSCIF4_1),
 742         PINMUX_IPSR_MSEL(IP2_31_28,     SDA6_A,                 SEL_I2C6_0),
 743         PINMUX_IPSR_MSEL(IP2_31_28,     AVB_AVTP_MATCH_B,       SEL_ETHERAVB_1),
 744         PINMUX_IPSR_MSEL(IP2_31_28,     PWM1_B,                 SEL_PWM1_1),
 745
 746         /* IPSR3 */
 747         PINMUX_IPSR_GPSR(IP3_3_0,       A9),
 748         PINMUX_IPSR_MSEL(IP3_3_0,       MSIOF2_SCK_A,           SEL_MSIOF2_0),
 749         PINMUX_IPSR_MSEL(IP3_3_0,       CTS4_N_B,               SEL_SCIF4_1),
 750         PINMUX_IPSR_GPSR(IP3_3_0,       VI5_VSYNC_N),
 751
 752         PINMUX_IPSR_GPSR(IP3_7_4,       A10),
 753         PINMUX_IPSR_MSEL(IP3_7_4,       MSIOF2_RXD_A,           SEL_MSIOF2_0),
 754         PINMUX_IPSR_MSEL(IP3_7_4,       RTS4_N_TANS_B,          SEL_SCIF4_1),
 755         PINMUX_IPSR_GPSR(IP3_7_4,       VI5_HSYNC_N),
 756
 757         PINMUX_IPSR_GPSR(IP3_11_8,      A11),
 758         PINMUX_IPSR_MSEL(IP3_11_8,      TX3_B,                  SEL_SCIF3_1),
 759         PINMUX_IPSR_MSEL(IP3_11_8,      MSIOF2_TXD_A,           SEL_MSIOF2_0),
 760         PINMUX_IPSR_MSEL(IP3_11_8,      HTX4_B,                 SEL_HSCIF4_1),
 761         PINMUX_IPSR_GPSR(IP3_11_8,      HSCK4),
 762         PINMUX_IPSR_GPSR(IP3_11_8,      VI5_FIELD),
 763         PINMUX_IPSR_MSEL(IP3_11_8,      SCL6_A,                 SEL_I2C6_0),
 764         PINMUX_IPSR_MSEL(IP3_11_8,      AVB_AVTP_CAPTURE_B,     SEL_ETHERAVB_1),
 765         PINMUX_IPSR_MSEL(IP3_11_8,      PWM2_B,                 SEL_PWM2_1),
 766
 767         PINMUX_IPSR_GPSR(IP3_15_12,     A12),
 768         PINMUX_IPSR_GPSR(IP3_15_12,     LCDOUT12),
 769         PINMUX_IPSR_MSEL(IP3_15_12,     MSIOF3_SCK_C,           SEL_MSIOF3_2),
 770         PINMUX_IPSR_MSEL(IP3_15_12,     HRX4_A,                 SEL_HSCIF4_0),
 771         PINMUX_IPSR_GPSR(IP3_15_12,     VI5_DATA8),
 772         PINMUX_IPSR_GPSR(IP3_15_12,     DU_DG4),
 773
 774         PINMUX_IPSR_GPSR(IP3_19_16,     A13),
 775         PINMUX_IPSR_GPSR(IP3_19_16,     LCDOUT13),
 776         PINMUX_IPSR_MSEL(IP3_19_16,     MSIOF3_SYNC_C,          SEL_MSIOF3_2),
 777         PINMUX_IPSR_MSEL(IP3_19_16,     HTX4_A,                 SEL_HSCIF4_0),
 778         PINMUX_IPSR_GPSR(IP3_19_16,     VI5_DATA9),
 779         PINMUX_IPSR_GPSR(IP3_19_16,     DU_DG5),
 780
 781         PINMUX_IPSR_GPSR(IP3_23_20,     A14),
 782         PINMUX_IPSR_GPSR(IP3_23_20,     LCDOUT14),
 783         PINMUX_IPSR_MSEL(IP3_23_20,     MSIOF3_RXD_C,           SEL_MSIOF3_2),
 784         PINMUX_IPSR_GPSR(IP3_23_20,     HCTS4_N),
 785         PINMUX_IPSR_GPSR(IP3_23_20,     VI5_DATA10),
 786         PINMUX_IPSR_GPSR(IP3_23_20,     DU_DG6),
 787
 788         PINMUX_IPSR_GPSR(IP3_27_24,     A15),
 789         PINMUX_IPSR_GPSR(IP3_27_24,     LCDOUT15),
 790         PINMUX_IPSR_MSEL(IP3_27_24,     MSIOF3_TXD_C,           SEL_MSIOF3_2),
 791         PINMUX_IPSR_GPSR(IP3_27_24,     HRTS4_N),
 792         PINMUX_IPSR_GPSR(IP3_27_24,     VI5_DATA11),
 793         PINMUX_IPSR_GPSR(IP3_27_24,     DU_DG7),
 794
 795         PINMUX_IPSR_GPSR(IP3_31_28,     A16),
 796         PINMUX_IPSR_GPSR(IP3_31_28,     LCDOUT8),
 797         PINMUX_IPSR_GPSR(IP3_31_28,     VI4_FIELD),
 798         PINMUX_IPSR_GPSR(IP3_31_28,     DU_DG0),
 799
 800         /* IPSR4 */
 801         PINMUX_IPSR_GPSR(IP4_3_0,       A17),
 802         PINMUX_IPSR_GPSR(IP4_3_0,       LCDOUT9),
 803         PINMUX_IPSR_GPSR(IP4_3_0,       VI4_VSYNC_N),
 804         PINMUX_IPSR_GPSR(IP4_3_0,       DU_DG1),
 805
 806         PINMUX_IPSR_GPSR(IP4_7_4,       A18),
 807         PINMUX_IPSR_GPSR(IP4_7_4,       LCDOUT10),
 808         PINMUX_IPSR_GPSR(IP4_7_4,       VI4_HSYNC_N),
 809         PINMUX_IPSR_GPSR(IP4_7_4,       DU_DG2),
 810
 811         PINMUX_IPSR_GPSR(IP4_11_8,      A19),
 812         PINMUX_IPSR_GPSR(IP4_11_8,      LCDOUT11),
 813         PINMUX_IPSR_GPSR(IP4_11_8,      VI4_CLKENB),
 814         PINMUX_IPSR_GPSR(IP4_11_8,      DU_DG3),
 815
 816         PINMUX_IPSR_GPSR(IP4_15_12,     CS0_N),
 817         PINMUX_IPSR_GPSR(IP4_15_12,     VI5_CLKENB),
 818
 819         PINMUX_IPSR_GPSR(IP4_19_16,     CS1_N_A26),
 820         PINMUX_IPSR_GPSR(IP4_19_16,     VI5_CLK),
 821         PINMUX_IPSR_MSEL(IP4_19_16,     EX_WAIT0_B,             SEL_LBSC_1),
 822
 823         PINMUX_IPSR_GPSR(IP4_23_20,     BS_N),
 824         PINMUX_IPSR_GPSR(IP4_23_20,     QSTVA_QVS),
 825         PINMUX_IPSR_MSEL(IP4_23_20,     MSIOF3_SCK_D,           SEL_MSIOF3_3),
 826         PINMUX_IPSR_GPSR(IP4_23_20,     SCK3),
 827         PINMUX_IPSR_GPSR(IP4_23_20,     HSCK3),
 828         PINMUX_IPSR_GPSR(IP4_23_20,     CAN1_TX),
 829         PINMUX_IPSR_GPSR(IP4_23_20,     CANFD1_TX),
 830         PINMUX_IPSR_MSEL(IP4_23_20,     IETX_A,                 SEL_IEBUS_0),
 831
 832         PINMUX_IPSR_GPSR(IP4_27_24,     RD_N),
 833         PINMUX_IPSR_MSEL(IP4_27_24,     MSIOF3_SYNC_D,          SEL_MSIOF3_3),
 834         PINMUX_IPSR_MSEL(IP4_27_24,     RX3_A,                  SEL_SCIF3_0),
 835         PINMUX_IPSR_MSEL(IP4_27_24,     HRX3_A,                 SEL_HSCIF3_0),
 836         PINMUX_IPSR_MSEL(IP4_27_24,     CAN0_TX_A,              SEL_RCAN0_0),
 837         PINMUX_IPSR_MSEL(IP4_27_24,     CANFD0_TX_A,            SEL_CANFD0_0),
 838
 839         PINMUX_IPSR_GPSR(IP4_31_28,     RD_WR_N),
 840         PINMUX_IPSR_MSEL(IP4_31_28,     MSIOF3_RXD_D,           SEL_MSIOF3_3),
 841         PINMUX_IPSR_MSEL(IP4_31_28,     TX3_A,                  SEL_SCIF3_0),
 842         PINMUX_IPSR_MSEL(IP4_31_28,     HTX3_A,                 SEL_HSCIF3_0),
 843         PINMUX_IPSR_MSEL(IP4_31_28,     CAN0_RX_A,              SEL_RCAN0_0),
 844         PINMUX_IPSR_MSEL(IP4_31_28,     CANFD0_RX_A,            SEL_CANFD0_0),
 845
 846         /* IPSR5 */
 847         PINMUX_IPSR_GPSR(IP5_3_0,       WE0_N),
 848         PINMUX_IPSR_MSEL(IP5_3_0,       MSIOF3_TXD_D,           SEL_MSIOF3_3),
 849         PINMUX_IPSR_GPSR(IP5_3_0,       CTS3_N),
 850         PINMUX_IPSR_GPSR(IP5_3_0,       HCTS3_N),
 851         PINMUX_IPSR_MSEL(IP5_3_0,       SCL6_B,                 SEL_I2C6_1),
 852         PINMUX_IPSR_GPSR(IP5_3_0,       CAN_CLK),
 853         PINMUX_IPSR_MSEL(IP5_3_0,       IECLK_A,                SEL_IEBUS_0),
 854
 855         PINMUX_IPSR_GPSR(IP5_7_4,       WE1_N),
 856         PINMUX_IPSR_MSEL(IP5_7_4,       MSIOF3_SS1_D,           SEL_MSIOF3_3),
 857         PINMUX_IPSR_GPSR(IP5_7_4,       RTS3_N_TANS),
 858         PINMUX_IPSR_GPSR(IP5_7_4,       HRTS3_N),
 859         PINMUX_IPSR_MSEL(IP5_7_4,       SDA6_B,                 SEL_I2C6_1),
 860         PINMUX_IPSR_GPSR(IP5_7_4,       CAN1_RX),
 861         PINMUX_IPSR_GPSR(IP5_7_4,       CANFD1_RX),
 862         PINMUX_IPSR_MSEL(IP5_7_4,       IERX_A,                 SEL_IEBUS_0),
 863
 864         PINMUX_IPSR_MSEL(IP5_11_8,      EX_WAIT0_A,             SEL_LBSC_0),
 865         PINMUX_IPSR_GPSR(IP5_11_8,      QCLK),
 866         PINMUX_IPSR_GPSR(IP5_11_8,      VI4_CLK),
 867         PINMUX_IPSR_GPSR(IP5_11_8,      DU_DOTCLKOUT0),
 868
 869         PINMUX_IPSR_GPSR(IP5_15_12,     D0),
 870         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF2_SS1_B,           SEL_MSIOF2_1),
 871         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF3_SCK_A,           SEL_MSIOF3_0),
 872         PINMUX_IPSR_GPSR(IP5_15_12,     VI4_DATA16),
 873         PINMUX_IPSR_GPSR(IP5_15_12,     VI5_DATA0),
 874
 875         PINMUX_IPSR_GPSR(IP5_19_16,     D1),
 876         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF2_SS2_B,           SEL_MSIOF2_1),
 877         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF3_SYNC_A,          SEL_MSIOF3_0),
 878         PINMUX_IPSR_GPSR(IP5_19_16,     VI4_DATA17),
 879         PINMUX_IPSR_GPSR(IP5_19_16,     VI5_DATA1),
 880
 881         PINMUX_IPSR_GPSR(IP5_23_20,     D2),
 882         PINMUX_IPSR_MSEL(IP5_23_20,     MSIOF3_RXD_A,           SEL_MSIOF3_0),
 883         PINMUX_IPSR_GPSR(IP5_23_20,     VI4_DATA18),
 884         PINMUX_IPSR_GPSR(IP5_23_20,     VI5_DATA2),
 885
 886         PINMUX_IPSR_GPSR(IP5_27_24,     D3),
 887         PINMUX_IPSR_MSEL(IP5_27_24,     MSIOF3_TXD_A,           SEL_MSIOF3_0),
 888         PINMUX_IPSR_GPSR(IP5_27_24,     VI4_DATA19),
 889         PINMUX_IPSR_GPSR(IP5_27_24,     VI5_DATA3),
 890
 891         PINMUX_IPSR_GPSR(IP5_31_28,     D4),
 892         PINMUX_IPSR_MSEL(IP5_31_28,     MSIOF2_SCK_B,           SEL_MSIOF2_1),
 893         PINMUX_IPSR_GPSR(IP5_31_28,     VI4_DATA20),
 894         PINMUX_IPSR_GPSR(IP5_31_28,     VI5_DATA4),
 895
 896         /* IPSR6 */
 897         PINMUX_IPSR_GPSR(IP6_3_0,       D5),
 898         PINMUX_IPSR_MSEL(IP6_3_0,       MSIOF2_SYNC_B,          SEL_MSIOF2_1),
 899         PINMUX_IPSR_GPSR(IP6_3_0,       VI4_DATA21),
 900         PINMUX_IPSR_GPSR(IP6_3_0,       VI5_DATA5),
 901
 902         PINMUX_IPSR_GPSR(IP6_7_4,       D6),
 903         PINMUX_IPSR_MSEL(IP6_7_4,       MSIOF2_RXD_B,           SEL_MSIOF2_1),
 904         PINMUX_IPSR_GPSR(IP6_7_4,       VI4_DATA22),
 905         PINMUX_IPSR_GPSR(IP6_7_4,       VI5_DATA6),
 906
 907         PINMUX_IPSR_GPSR(IP6_11_8,      D7),
 908         PINMUX_IPSR_MSEL(IP6_11_8,      MSIOF2_TXD_B,           SEL_MSIOF2_1),
 909         PINMUX_IPSR_GPSR(IP6_11_8,      VI4_DATA23),
 910         PINMUX_IPSR_GPSR(IP6_11_8,      VI5_DATA7),
 911
 912         PINMUX_IPSR_GPSR(IP6_15_12,     D8),
 913         PINMUX_IPSR_GPSR(IP6_15_12,     LCDOUT0),
 914         PINMUX_IPSR_MSEL(IP6_15_12,     MSIOF2_SCK_D,           SEL_MSIOF2_3),
 915         PINMUX_IPSR_MSEL(IP6_15_12,     SCK4_C,                 SEL_SCIF4_2),
 916         PINMUX_IPSR_MSEL(IP6_15_12,     VI4_DATA0_A,            SEL_VIN4_0),
 917         PINMUX_IPSR_GPSR(IP6_15_12,     DU_DR0),
 918
 919         PINMUX_IPSR_GPSR(IP6_19_16,     D9),
 920         PINMUX_IPSR_GPSR(IP6_19_16,     LCDOUT1),
 921         PINMUX_IPSR_MSEL(IP6_19_16,     MSIOF2_SYNC_D,          SEL_MSIOF2_3),
 922         PINMUX_IPSR_MSEL(IP6_19_16,     VI4_DATA1_A,            SEL_VIN4_0),
 923         PINMUX_IPSR_GPSR(IP6_19_16,     DU_DR1),
 924
 925         PINMUX_IPSR_GPSR(IP6_23_20,     D10),
 926         PINMUX_IPSR_GPSR(IP6_23_20,     LCDOUT2),
 927         PINMUX_IPSR_MSEL(IP6_23_20,     MSIOF2_RXD_D,           SEL_MSIOF2_3),
 928         PINMUX_IPSR_MSEL(IP6_23_20,     HRX3_B,                 SEL_HSCIF3_1),
 929         PINMUX_IPSR_MSEL(IP6_23_20,     VI4_DATA2_A,            SEL_VIN4_0),
 930         PINMUX_IPSR_MSEL(IP6_23_20,     CTS4_N_C,               SEL_SCIF4_2),
 931         PINMUX_IPSR_GPSR(IP6_23_20,     DU_DR2),
 932
 933         PINMUX_IPSR_GPSR(IP6_27_24,     D11),
 934         PINMUX_IPSR_GPSR(IP6_27_24,     LCDOUT3),
 935         PINMUX_IPSR_MSEL(IP6_27_24,     MSIOF2_TXD_D,           SEL_MSIOF2_3),
 936         PINMUX_IPSR_MSEL(IP6_27_24,     HTX3_B,                 SEL_HSCIF3_1),
 937         PINMUX_IPSR_MSEL(IP6_27_24,     VI4_DATA3_A,            SEL_VIN4_0),
 938         PINMUX_IPSR_MSEL(IP6_27_24,     RTS4_N_TANS_C,          SEL_SCIF4_2),
 939         PINMUX_IPSR_GPSR(IP6_27_24,     DU_DR3),
 940
 941         PINMUX_IPSR_GPSR(IP6_31_28,     D12),
 942         PINMUX_IPSR_GPSR(IP6_31_28,     LCDOUT4),
 943         PINMUX_IPSR_MSEL(IP6_31_28,     MSIOF2_SS1_D,           SEL_MSIOF2_3),
 944         PINMUX_IPSR_MSEL(IP6_31_28,     RX4_C,                  SEL_SCIF4_2),
 945         PINMUX_IPSR_MSEL(IP6_31_28,     VI4_DATA4_A,            SEL_VIN4_0),
 946         PINMUX_IPSR_GPSR(IP6_31_28,     DU_DR4),
 947
 948         /* IPSR7 */
 949         PINMUX_IPSR_GPSR(IP7_3_0,       D13),
 950         PINMUX_IPSR_GPSR(IP7_3_0,       LCDOUT5),
 951         PINMUX_IPSR_MSEL(IP7_3_0,       MSIOF2_SS2_D,           SEL_MSIOF2_3),
 952         PINMUX_IPSR_MSEL(IP7_3_0,       TX4_C,                  SEL_SCIF4_2),
 953         PINMUX_IPSR_MSEL(IP7_3_0,       VI4_DATA5_A,            SEL_VIN4_0),
 954         PINMUX_IPSR_GPSR(IP7_3_0,       DU_DR5),
 955
 956         PINMUX_IPSR_GPSR(IP7_7_4,       D14),
 957         PINMUX_IPSR_GPSR(IP7_7_4,       LCDOUT6),
 958         PINMUX_IPSR_MSEL(IP7_7_4,       MSIOF3_SS1_A,           SEL_MSIOF3_0),
 959         PINMUX_IPSR_MSEL(IP7_7_4,       HRX3_C,                 SEL_HSCIF3_2),
 960         PINMUX_IPSR_MSEL(IP7_7_4,       VI4_DATA6_A,            SEL_VIN4_0),
 961         PINMUX_IPSR_GPSR(IP7_7_4,       DU_DR6),
 962         PINMUX_IPSR_MSEL(IP7_7_4,       SCL6_C,                 SEL_I2C6_2),
 963
 964         PINMUX_IPSR_GPSR(IP7_11_8,      D15),
 965         PINMUX_IPSR_GPSR(IP7_11_8,      LCDOUT7),
 966         PINMUX_IPSR_MSEL(IP7_11_8,      MSIOF3_SS2_A,           SEL_MSIOF3_0),
 967         PINMUX_IPSR_MSEL(IP7_11_8,      HTX3_C,                 SEL_HSCIF3_2),
 968         PINMUX_IPSR_MSEL(IP7_11_8,      VI4_DATA7_A,            SEL_VIN4_0),
 969         PINMUX_IPSR_GPSR(IP7_11_8,      DU_DR7),
 970         PINMUX_IPSR_MSEL(IP7_11_8,      SDA6_C,                 SEL_I2C6_2),
 971
 972         PINMUX_IPSR_GPSR(IP7_15_12,     FSCLKST),
 973
 974         PINMUX_IPSR_GPSR(IP7_19_16,     SD0_CLK),
 975         PINMUX_IPSR_MSEL(IP7_19_16,     MSIOF1_SCK_E,           SEL_MSIOF1_4),
 976         PINMUX_IPSR_MSEL(IP7_19_16,     STP_OPWM_0_B,           SEL_SSP1_0_1),
 977
 978         PINMUX_IPSR_GPSR(IP7_23_20,     SD0_CMD),
 979         PINMUX_IPSR_MSEL(IP7_23_20,     MSIOF1_SYNC_E,          SEL_MSIOF1_4),
 980         PINMUX_IPSR_MSEL(IP7_23_20,     STP_IVCXO27_0_B,        SEL_SSP1_0_1),
 981
 982         PINMUX_IPSR_GPSR(IP7_27_24,     SD0_DAT0),
 983         PINMUX_IPSR_MSEL(IP7_27_24,     MSIOF1_RXD_E,           SEL_MSIOF1_4),
 984         PINMUX_IPSR_MSEL(IP7_27_24,     TS_SCK0_B,              SEL_TSIF0_1),
 985         PINMUX_IPSR_MSEL(IP7_27_24,     STP_ISCLK_0_B,          SEL_SSP1_0_1),
 986
 987         PINMUX_IPSR_GPSR(IP7_31_28,     SD0_DAT1),
 988         PINMUX_IPSR_MSEL(IP7_31_28,     MSIOF1_TXD_E,           SEL_MSIOF1_4),
 989         PINMUX_IPSR_MSEL(IP7_31_28,     TS_SPSYNC0_B,           SEL_TSIF0_1),
 990         PINMUX_IPSR_MSEL(IP7_31_28,     STP_ISSYNC_0_B,         SEL_SSP1_0_1),
 991
 992         /* IPSR8 */
 993         PINMUX_IPSR_GPSR(IP8_3_0,       SD0_DAT2),
 994         PINMUX_IPSR_MSEL(IP8_3_0,       MSIOF1_SS1_E,           SEL_MSIOF1_4),
 995         PINMUX_IPSR_MSEL(IP8_3_0,       TS_SDAT0_B,             SEL_TSIF0_1),
 996         PINMUX_IPSR_MSEL(IP8_3_0,       STP_ISD_0_B,            SEL_SSP1_0_1),
 997
 998         PINMUX_IPSR_GPSR(IP8_7_4,       SD0_DAT3),
 999         PINMUX_IPSR_MSEL(IP8_7_4,       MSIOF1_SS2_E,           SEL_MSIOF1_4),
1000         PINMUX_IPSR_MSEL(IP8_7_4,       TS_SDEN0_B,             SEL_TSIF0_1),
1001         PINMUX_IPSR_MSEL(IP8_7_4,       STP_ISEN_0_B,           SEL_SSP1_0_1),
1002
1003         PINMUX_IPSR_GPSR(IP8_11_8,      SD1_CLK),
1004         PINMUX_IPSR_MSEL(IP8_11_8,      MSIOF1_SCK_G,           SEL_MSIOF1_6),
1005         PINMUX_IPSR_MSEL(IP8_11_8,      SIM0_CLK_A,             SEL_SIMCARD_0),
1006
1007         PINMUX_IPSR_GPSR(IP8_15_12,     SD1_CMD),
1008         PINMUX_IPSR_MSEL(IP8_15_12,     MSIOF1_SYNC_G,          SEL_MSIOF1_6),
1009         PINMUX_IPSR_MSEL(IP8_15_12,     SIM0_D_A,               SEL_SIMCARD_0),
1010         PINMUX_IPSR_MSEL(IP8_15_12,     STP_IVCXO27_1_B,        SEL_SSP1_1_1),
1011
1012         PINMUX_IPSR_GPSR(IP8_19_16,     SD1_DAT0),
1013         PINMUX_IPSR_GPSR(IP8_19_16,     SD2_DAT4),
1014         PINMUX_IPSR_MSEL(IP8_19_16,     MSIOF1_RXD_G,           SEL_MSIOF1_6),
1015         PINMUX_IPSR_MSEL(IP8_19_16,     TS_SCK1_B,              SEL_TSIF1_1),
1016         PINMUX_IPSR_MSEL(IP8_19_16,     STP_ISCLK_1_B,          SEL_SSP1_1_1),
1017
1018         PINMUX_IPSR_GPSR(IP8_23_20,     SD1_DAT1),
1019         PINMUX_IPSR_GPSR(IP8_23_20,     SD2_DAT5),
1020         PINMUX_IPSR_MSEL(IP8_23_20,     MSIOF1_TXD_G,           SEL_MSIOF1_6),
1021         PINMUX_IPSR_MSEL(IP8_23_20,     TS_SPSYNC1_B,           SEL_TSIF1_1),
1022         PINMUX_IPSR_MSEL(IP8_23_20,     STP_ISSYNC_1_B,         SEL_SSP1_1_1),
1023
1024         PINMUX_IPSR_GPSR(IP8_27_24,     SD1_DAT2),
1025         PINMUX_IPSR_GPSR(IP8_27_24,     SD2_DAT6),
1026         PINMUX_IPSR_MSEL(IP8_27_24,     MSIOF1_SS1_G,           SEL_MSIOF1_6),
1027         PINMUX_IPSR_MSEL(IP8_27_24,     TS_SDAT1_B,             SEL_TSIF1_1),
1028         PINMUX_IPSR_MSEL(IP8_27_24,     STP_ISD_1_B,            SEL_SSP1_1_1),
1029
1030         PINMUX_IPSR_GPSR(IP8_31_28,     SD1_DAT3),
1031         PINMUX_IPSR_GPSR(IP8_31_28,     SD2_DAT7),
1032         PINMUX_IPSR_MSEL(IP8_31_28,     MSIOF1_SS2_G,           SEL_MSIOF1_6),
1033         PINMUX_IPSR_MSEL(IP8_31_28,     TS_SDEN1_B,             SEL_TSIF1_1),
1034         PINMUX_IPSR_MSEL(IP8_31_28,     STP_ISEN_1_B,           SEL_SSP1_1_1),
1035
1036         /* IPSR9 */
1037         PINMUX_IPSR_GPSR(IP9_3_0,       SD2_CLK),
1038
1039         PINMUX_IPSR_GPSR(IP9_7_4,       SD2_DAT0),
1040
1041         PINMUX_IPSR_GPSR(IP9_11_8,      SD2_DAT1),
1042
1043         PINMUX_IPSR_GPSR(IP9_15_12,     SD2_DAT2),
1044
1045         PINMUX_IPSR_GPSR(IP9_19_16,     SD2_DAT3),
1046
1047         PINMUX_IPSR_GPSR(IP9_23_20,     SD2_DS),
1048         PINMUX_IPSR_MSEL(IP9_23_20,     SATA_DEVSLP_B,          SEL_SATA_1),
1049
1050         PINMUX_IPSR_GPSR(IP9_27_24,     SD3_DAT4),
1051         PINMUX_IPSR_MSEL(IP9_27_24,     SD2_CD_A,               SEL_SDHI2_0),
1052
1053         PINMUX_IPSR_GPSR(IP9_31_28,     SD3_DAT5),
1054         PINMUX_IPSR_MSEL(IP9_31_28,     SD2_WP_A,               SEL_SDHI2_0),
1055
1056         /* IPSR10 */
1057         PINMUX_IPSR_GPSR(IP10_3_0,      SD3_DAT6),
1058         PINMUX_IPSR_GPSR(IP10_3_0,      SD3_CD),
1059
1060         PINMUX_IPSR_GPSR(IP10_7_4,      SD3_DAT7),
1061         PINMUX_IPSR_GPSR(IP10_7_4,      SD3_WP),
1062
1063         PINMUX_IPSR_GPSR(IP10_11_8,     SD0_CD),
1064         PINMUX_IPSR_MSEL(IP10_11_8,     SCL2_B,                 SEL_I2C2_1),
1065         PINMUX_IPSR_MSEL(IP10_11_8,     SIM0_RST_A,             SEL_SIMCARD_0),
1066
1067         PINMUX_IPSR_GPSR(IP10_15_12,    SD0_WP),
1068         PINMUX_IPSR_MSEL(IP10_15_12,    SDA2_B,                 SEL_I2C2_1),
1069
1070         PINMUX_IPSR_GPSR(IP10_19_16,    SD1_CD),
1071         PINMUX_IPSR_MSEL(IP10_19_16,    SIM0_CLK_B,             SEL_SIMCARD_1),
1072
1073         PINMUX_IPSR_GPSR(IP10_23_20,    SD1_WP),
1074         PINMUX_IPSR_MSEL(IP10_23_20,    SIM0_D_B,               SEL_SIMCARD_1),
1075
1076         PINMUX_IPSR_GPSR(IP10_27_24,    SCK0),
1077         PINMUX_IPSR_MSEL(IP10_27_24,    HSCK1_B,                SEL_HSCIF1_1),
1078         PINMUX_IPSR_MSEL(IP10_27_24,    MSIOF1_SS2_B,           SEL_MSIOF1_1),
1079         PINMUX_IPSR_MSEL(IP10_27_24,    AUDIO_CLKC_B,           SEL_ADG_1),
1080         PINMUX_IPSR_MSEL(IP10_27_24,    SDA2_A,                 SEL_I2C2_0),
1081         PINMUX_IPSR_MSEL(IP10_27_24,    SIM0_RST_B,             SEL_SIMCARD_1),
1082         PINMUX_IPSR_MSEL(IP10_27_24,    STP_OPWM_0_C,           SEL_SSP1_0_2),
1083         PINMUX_IPSR_MSEL(IP10_27_24,    RIF0_CLK_B,             SEL_DRIF0_1),
1084         PINMUX_IPSR_GPSR(IP10_27_24,    ADICHS2),
1085
1086         PINMUX_IPSR_GPSR(IP10_31_28,    RX0),
1087         PINMUX_IPSR_MSEL(IP10_31_28,    HRX1_B,                 SEL_HSCIF1_1),
1088         PINMUX_IPSR_MSEL(IP10_31_28,    TS_SCK0_C,              SEL_TSIF0_2),
1089         PINMUX_IPSR_MSEL(IP10_31_28,    STP_ISCLK_0_C,          SEL_SSP1_0_2),
1090         PINMUX_IPSR_MSEL(IP10_31_28,    RIF0_D0_B,              SEL_DRIF0_1),
1091
1092         /* IPSR11 */
1093         PINMUX_IPSR_GPSR(IP11_3_0,      TX0),
1094         PINMUX_IPSR_MSEL(IP11_3_0,      HTX1_B,                 SEL_HSCIF1_1),
1095         PINMUX_IPSR_MSEL(IP11_3_0,      TS_SPSYNC0_C,           SEL_TSIF0_2),
1096         PINMUX_IPSR_MSEL(IP11_3_0,      STP_ISSYNC_0_C,         SEL_SSP1_0_2),
1097         PINMUX_IPSR_MSEL(IP11_3_0,      RIF0_D1_B,              SEL_DRIF0_1),
1098
1099         PINMUX_IPSR_GPSR(IP11_7_4,      CTS0_N),
1100         PINMUX_IPSR_MSEL(IP11_7_4,      HCTS1_N_B,              SEL_HSCIF1_1),
1101         PINMUX_IPSR_MSEL(IP11_7_4,      MSIOF1_SYNC_B,          SEL_MSIOF1_1),
1102         PINMUX_IPSR_MSEL(IP11_7_4,      TS_SPSYNC1_C,           SEL_TSIF1_2),
1103         PINMUX_IPSR_MSEL(IP11_7_4,      STP_ISSYNC_1_C,         SEL_SSP1_1_2),
1104         PINMUX_IPSR_MSEL(IP11_7_4,      RIF1_SYNC_B,            SEL_DRIF1_1),
1105         PINMUX_IPSR_MSEL(IP11_7_4,      AUDIO_CLKOUT_C,         SEL_ADG_2),
1106         PINMUX_IPSR_GPSR(IP11_7_4,      ADICS_SAMP),
1107
1108         PINMUX_IPSR_GPSR(IP11_11_8,     RTS0_N_TANS),
1109         PINMUX_IPSR_MSEL(IP11_11_8,     HRTS1_N_B,              SEL_HSCIF1_1),
1110         PINMUX_IPSR_MSEL(IP11_11_8,     MSIOF1_SS1_B,           SEL_MSIOF1_1),
1111         PINMUX_IPSR_MSEL(IP11_11_8,     AUDIO_CLKA_B,           SEL_ADG_1),
1112         PINMUX_IPSR_MSEL(IP11_11_8,     SCL2_A,                 SEL_I2C2_0),
1113         PINMUX_IPSR_MSEL(IP11_11_8,     STP_IVCXO27_1_C,        SEL_SSP1_1_2),
1114         PINMUX_IPSR_MSEL(IP11_11_8,     RIF0_SYNC_B,            SEL_DRIF0_1),
1115         PINMUX_IPSR_GPSR(IP11_11_8,     ADICHS1),
1116
1117         PINMUX_IPSR_MSEL(IP11_15_12,    RX1_A,                  SEL_SCIF1_0),
1118         PINMUX_IPSR_MSEL(IP11_15_12,    HRX1_A,                 SEL_HSCIF1_0),
1119         PINMUX_IPSR_MSEL(IP11_15_12,    TS_SDAT0_C,             SEL_TSIF0_2),
1120         PINMUX_IPSR_MSEL(IP11_15_12,    STP_ISD_0_C,            SEL_SSP1_0_2),
1121         PINMUX_IPSR_MSEL(IP11_15_12,    RIF1_CLK_C,             SEL_DRIF1_2),
1122
1123         PINMUX_IPSR_MSEL(IP11_19_16,    TX1_A,                  SEL_SCIF1_0),
1124         PINMUX_IPSR_MSEL(IP11_19_16,    HTX1_A,                 SEL_HSCIF1_0),
1125         PINMUX_IPSR_MSEL(IP11_19_16,    TS_SDEN0_C,             SEL_TSIF0_2),
1126         PINMUX_IPSR_MSEL(IP11_19_16,    STP_ISEN_0_C,           SEL_SSP1_0_2),
1127         PINMUX_IPSR_MSEL(IP11_19_16,    RIF1_D0_C,              SEL_DRIF1_2),
1128
1129         PINMUX_IPSR_GPSR(IP11_23_20,    CTS1_N),
1130         PINMUX_IPSR_MSEL(IP11_23_20,    HCTS1_N_A,              SEL_HSCIF1_0),
1131         PINMUX_IPSR_MSEL(IP11_23_20,    MSIOF1_RXD_B,           SEL_MSIOF1_1),
1132         PINMUX_IPSR_MSEL(IP11_23_20,    TS_SDEN1_C,             SEL_TSIF1_2),
1133         PINMUX_IPSR_MSEL(IP11_23_20,    STP_ISEN_1_C,           SEL_SSP1_1_2),
1134         PINMUX_IPSR_MSEL(IP11_23_20,    RIF1_D0_B,              SEL_DRIF1_1),
1135         PINMUX_IPSR_GPSR(IP11_23_20,    ADIDATA),
1136
1137         PINMUX_IPSR_GPSR(IP11_27_24,    RTS1_N_TANS),
1138         PINMUX_IPSR_MSEL(IP11_27_24,    HRTS1_N_A,              SEL_HSCIF1_0),
1139         PINMUX_IPSR_MSEL(IP11_27_24,    MSIOF1_TXD_B,           SEL_MSIOF1_1),
1140         PINMUX_IPSR_MSEL(IP11_27_24,    TS_SDAT1_C,             SEL_TSIF1_2),
1141         PINMUX_IPSR_MSEL(IP11_27_24,    STP_ISD_1_C,            SEL_SSP1_1_2),
1142         PINMUX_IPSR_MSEL(IP11_27_24,    RIF1_D1_B,              SEL_DRIF1_1),
1143         PINMUX_IPSR_GPSR(IP11_27_24,    ADICHS0),
1144
1145         PINMUX_IPSR_GPSR(IP11_31_28,    SCK2),
1146         PINMUX_IPSR_MSEL(IP11_31_28,    SCIF_CLK_B,             SEL_SCIF1_1),
1147         PINMUX_IPSR_MSEL(IP11_31_28,    MSIOF1_SCK_B,           SEL_MSIOF1_1),
1148         PINMUX_IPSR_MSEL(IP11_31_28,    TS_SCK1_C,              SEL_TSIF1_2),
1149         PINMUX_IPSR_MSEL(IP11_31_28,    STP_ISCLK_1_C,          SEL_SSP1_1_2),
1150         PINMUX_IPSR_MSEL(IP11_31_28,    RIF1_CLK_B,             SEL_DRIF1_1),
1151         PINMUX_IPSR_GPSR(IP11_31_28,    ADICLK),
1152
1153         /* IPSR12 */
1154         PINMUX_IPSR_MSEL(IP12_3_0,      TX2_A,                  SEL_SCIF2_0),
1155         PINMUX_IPSR_MSEL(IP12_3_0,      SD2_CD_B,               SEL_SDHI2_1),
1156         PINMUX_IPSR_MSEL(IP12_3_0,      SCL1_A,                 SEL_I2C1_0),
1157         PINMUX_IPSR_MSEL(IP12_3_0,      FMCLK_A,                SEL_FM_0),
1158         PINMUX_IPSR_MSEL(IP12_3_0,      RIF1_D1_C,              SEL_DRIF1_2),
1159         PINMUX_IPSR_MSEL(IP12_3_0,      FSO_CFE_0_B,            SEL_FSO_1),
1160
1161         PINMUX_IPSR_MSEL(IP12_7_4,      RX2_A,                  SEL_SCIF2_0),
1162         PINMUX_IPSR_MSEL(IP12_7_4,      SD2_WP_B,               SEL_SDHI2_1),
1163         PINMUX_IPSR_MSEL(IP12_7_4,      SDA1_A,                 SEL_I2C1_0),
1164         PINMUX_IPSR_MSEL(IP12_7_4,      FMIN_A,                 SEL_FM_0),
1165         PINMUX_IPSR_MSEL(IP12_7_4,      RIF1_SYNC_C,            SEL_DRIF1_2),
1166         PINMUX_IPSR_MSEL(IP12_7_4,      FSO_CFE_1_B,            SEL_FSO_1),
1167
1168         PINMUX_IPSR_GPSR(IP12_11_8,     HSCK0),
1169         PINMUX_IPSR_MSEL(IP12_11_8,     MSIOF1_SCK_D,           SEL_MSIOF1_3),
1170         PINMUX_IPSR_MSEL(IP12_11_8,     AUDIO_CLKB_A,           SEL_ADG_0),
1171         PINMUX_IPSR_MSEL(IP12_11_8,     SSI_SDATA1_B,           SEL_SSI_1),
1172         PINMUX_IPSR_MSEL(IP12_11_8,     TS_SCK0_D,              SEL_TSIF0_3),
1173         PINMUX_IPSR_MSEL(IP12_11_8,     STP_ISCLK_0_D,          SEL_SSP1_0_3),
1174         PINMUX_IPSR_MSEL(IP12_11_8,     RIF0_CLK_C,             SEL_DRIF0_2),
1175
1176         PINMUX_IPSR_GPSR(IP12_15_12,    HRX0),
1177         PINMUX_IPSR_MSEL(IP12_15_12,    MSIOF1_RXD_D,           SEL_MSIOF1_3),
1178         PINMUX_IPSR_MSEL(IP12_15_12,    SSI_SDATA2_B,           SEL_SSI_1),
1179         PINMUX_IPSR_MSEL(IP12_15_12,    TS_SDEN0_D,             SEL_TSIF0_3),
1180         PINMUX_IPSR_MSEL(IP12_15_12,    STP_ISEN_0_D,           SEL_SSP1_0_3),
1181         PINMUX_IPSR_MSEL(IP12_15_12,    RIF0_D0_C,              SEL_DRIF0_2),
1182
1183         PINMUX_IPSR_GPSR(IP12_19_16,    HTX0),
1184         PINMUX_IPSR_MSEL(IP12_19_16,    MSIOF1_TXD_D,           SEL_MSIOF1_3),
1185         PINMUX_IPSR_MSEL(IP12_19_16,    SSI_SDATA9_B,           SEL_SSI_1),
1186         PINMUX_IPSR_MSEL(IP12_19_16,    TS_SDAT0_D,             SEL_TSIF0_3),
1187         PINMUX_IPSR_MSEL(IP12_19_16,    STP_ISD_0_D,            SEL_SSP1_0_3),
1188         PINMUX_IPSR_MSEL(IP12_19_16,    RIF0_D1_C,              SEL_DRIF0_2),
1189
1190         PINMUX_IPSR_GPSR(IP12_23_20,    HCTS0_N),
1191         PINMUX_IPSR_MSEL(IP12_23_20,    RX2_B,                  SEL_SCIF2_1),
1192         PINMUX_IPSR_MSEL(IP12_23_20,    MSIOF1_SYNC_D,          SEL_MSIOF1_3),
1193         PINMUX_IPSR_MSEL(IP12_23_20,    SSI_SCK9_A,             SEL_SSI_0),
1194         PINMUX_IPSR_MSEL(IP12_23_20,    TS_SPSYNC0_D,           SEL_TSIF0_3),
1195         PINMUX_IPSR_MSEL(IP12_23_20,    STP_ISSYNC_0_D,         SEL_SSP1_0_3),
1196         PINMUX_IPSR_MSEL(IP12_23_20,    RIF0_SYNC_C,            SEL_DRIF0_2),
1197         PINMUX_IPSR_MSEL(IP12_23_20,    AUDIO_CLKOUT1_A,        SEL_ADG_0),
1198
1199         PINMUX_IPSR_GPSR(IP12_27_24,    HRTS0_N),
1200         PINMUX_IPSR_MSEL(IP12_27_24,    TX2_B,                  SEL_SCIF2_1),
1201         PINMUX_IPSR_MSEL(IP12_27_24,    MSIOF1_SS1_D,           SEL_MSIOF1_3),
1202         PINMUX_IPSR_MSEL(IP12_27_24,    SSI_WS9_A,              SEL_SSI_0),
1203         PINMUX_IPSR_MSEL(IP12_27_24,    STP_IVCXO27_0_D,        SEL_SSP1_0_3),
1204         PINMUX_IPSR_MSEL(IP12_27_24,    BPFCLK_A,               SEL_FM_0),
1205         PINMUX_IPSR_MSEL(IP12_27_24,    AUDIO_CLKOUT2_A,        SEL_ADG_0),
1206
1207         PINMUX_IPSR_GPSR(IP12_31_28,    MSIOF0_SYNC),
1208         PINMUX_IPSR_MSEL(IP12_31_28,    AUDIO_CLKOUT_A,         SEL_ADG_0),
1209
1210         /* IPSR13 */
1211         PINMUX_IPSR_GPSR(IP13_3_0,      MSIOF0_SS1),
1212         PINMUX_IPSR_GPSR(IP13_3_0,      RX5),
1213         PINMUX_IPSR_MSEL(IP13_3_0,      AUDIO_CLKA_C,           SEL_ADG_2),
1214         PINMUX_IPSR_MSEL(IP13_3_0,      SSI_SCK2_A,             SEL_SSI_0),
1215         PINMUX_IPSR_MSEL(IP13_3_0,      STP_IVCXO27_0_C,        SEL_SSP1_0_2),
1216         PINMUX_IPSR_MSEL(IP13_3_0,      AUDIO_CLKOUT3_A,        SEL_ADG_0),
1217         PINMUX_IPSR_MSEL(IP13_3_0,      TCLK1_B,                SEL_TIMER_TMU_1),
1218
1219         PINMUX_IPSR_GPSR(IP13_7_4,      MSIOF0_SS2),
1220         PINMUX_IPSR_GPSR(IP13_7_4,      TX5),
1221         PINMUX_IPSR_MSEL(IP13_7_4,      MSIOF1_SS2_D,           SEL_MSIOF1_3),
1222         PINMUX_IPSR_MSEL(IP13_7_4,      AUDIO_CLKC_A,           SEL_ADG_0),
1223         PINMUX_IPSR_MSEL(IP13_7_4,      SSI_WS2_A,              SEL_SSI_0),
1224         PINMUX_IPSR_MSEL(IP13_7_4,      STP_OPWM_0_D,           SEL_SSP1_0_3),
1225         PINMUX_IPSR_MSEL(IP13_7_4,      AUDIO_CLKOUT_D,         SEL_ADG_3),
1226         PINMUX_IPSR_MSEL(IP13_7_4,      SPEEDIN_B,              SEL_SPEED_PULSE_1),
1227
1228         PINMUX_IPSR_GPSR(IP13_11_8,     MLB_CLK),
1229         PINMUX_IPSR_MSEL(IP13_11_8,     MSIOF1_SCK_F,           SEL_MSIOF1_5),
1230         PINMUX_IPSR_MSEL(IP13_11_8,     SCL1_B,                 SEL_I2C1_1),
1231
1232         PINMUX_IPSR_GPSR(IP13_15_12,    MLB_SIG),
1233         PINMUX_IPSR_MSEL(IP13_15_12,    RX1_B,                  SEL_SCIF1_1),
1234         PINMUX_IPSR_MSEL(IP13_15_12,    MSIOF1_SYNC_F,          SEL_MSIOF1_5),
1235         PINMUX_IPSR_MSEL(IP13_15_12,    SDA1_B,                 SEL_I2C1_1),
1236
1237         PINMUX_IPSR_GPSR(IP13_19_16,    MLB_DAT),
1238         PINMUX_IPSR_MSEL(IP13_19_16,    TX1_B,                  SEL_SCIF1_1),
1239         PINMUX_IPSR_MSEL(IP13_19_16,    MSIOF1_RXD_F,           SEL_MSIOF1_5),
1240
1241         PINMUX_IPSR_GPSR(IP13_23_20,    SSI_SCK01239),
1242         PINMUX_IPSR_MSEL(IP13_23_20,    MSIOF1_TXD_F,           SEL_MSIOF1_5),
1243
1244         PINMUX_IPSR_GPSR(IP13_27_24,    SSI_WS01239),
1245         PINMUX_IPSR_MSEL(IP13_27_24,    MSIOF1_SS1_F,           SEL_MSIOF1_5),
1246
1247         PINMUX_IPSR_GPSR(IP13_31_28,    SSI_SDATA0),
1248         PINMUX_IPSR_MSEL(IP13_31_28,    MSIOF1_SS2_F,           SEL_MSIOF1_5),
1249
1250         /* IPSR14 */
1251         PINMUX_IPSR_MSEL(IP14_3_0,      SSI_SDATA1_A,           SEL_SSI_0),
1252
1253         PINMUX_IPSR_MSEL(IP14_7_4,      SSI_SDATA2_A,           SEL_SSI_0),
1254         PINMUX_IPSR_MSEL(IP14_7_4,      SSI_SCK1_B,             SEL_SSI_1),
1255
1256         PINMUX_IPSR_GPSR(IP14_11_8,     SSI_SCK349),
1257         PINMUX_IPSR_MSEL(IP14_11_8,     MSIOF1_SS1_A,           SEL_MSIOF1_0),
1258         PINMUX_IPSR_MSEL(IP14_11_8,     STP_OPWM_0_A,           SEL_SSP1_0_0),
1259
1260         PINMUX_IPSR_GPSR(IP14_15_12,    SSI_WS349),
1261         PINMUX_IPSR_MSEL(IP14_15_12,    HCTS2_N_A,              SEL_HSCIF2_0),
1262         PINMUX_IPSR_MSEL(IP14_15_12,    MSIOF1_SS2_A,           SEL_MSIOF1_0),
1263         PINMUX_IPSR_MSEL(IP14_15_12,    STP_IVCXO27_0_A,        SEL_SSP1_0_0),
1264
1265         PINMUX_IPSR_GPSR(IP14_19_16,    SSI_SDATA3),
1266         PINMUX_IPSR_MSEL(IP14_19_16,    HRTS2_N_A,              SEL_HSCIF2_0),
1267         PINMUX_IPSR_MSEL(IP14_19_16,    MSIOF1_TXD_A,           SEL_MSIOF1_0),
1268         PINMUX_IPSR_MSEL(IP14_19_16,    TS_SCK0_A,              SEL_TSIF0_0),
1269         PINMUX_IPSR_MSEL(IP14_19_16,    STP_ISCLK_0_A,          SEL_SSP1_0_0),
1270         PINMUX_IPSR_MSEL(IP14_19_16,    RIF0_D1_A,              SEL_DRIF0_0),
1271         PINMUX_IPSR_MSEL(IP14_19_16,    RIF2_D0_A,              SEL_DRIF2_0),
1272
1273         PINMUX_IPSR_GPSR(IP14_23_20,    SSI_SCK4),
1274         PINMUX_IPSR_MSEL(IP14_23_20,    HRX2_A,                 SEL_HSCIF2_0),
1275         PINMUX_IPSR_MSEL(IP14_23_20,    MSIOF1_SCK_A,           SEL_MSIOF1_0),
1276         PINMUX_IPSR_MSEL(IP14_23_20,    TS_SDAT0_A,             SEL_TSIF0_0),
1277         PINMUX_IPSR_MSEL(IP14_23_20,    STP_ISD_0_A,            SEL_SSP1_0_0),
1278         PINMUX_IPSR_MSEL(IP14_23_20,    RIF0_CLK_A,             SEL_DRIF0_0),
1279         PINMUX_IPSR_MSEL(IP14_23_20,    RIF2_CLK_A,             SEL_DRIF2_0),
1280
1281         PINMUX_IPSR_GPSR(IP14_27_24,    SSI_WS4),
1282         PINMUX_IPSR_MSEL(IP14_27_24,    HTX2_A,                 SEL_HSCIF2_0),
1283         PINMUX_IPSR_MSEL(IP14_27_24,    MSIOF1_SYNC_A,          SEL_MSIOF1_0),
1284         PINMUX_IPSR_MSEL(IP14_27_24,    TS_SDEN0_A,             SEL_TSIF0_0),
1285         PINMUX_IPSR_MSEL(IP14_27_24,    STP_ISEN_0_A,           SEL_SSP1_0_0),
1286         PINMUX_IPSR_MSEL(IP14_27_24,    RIF0_SYNC_A,            SEL_DRIF0_0),
1287         PINMUX_IPSR_MSEL(IP14_27_24,    RIF2_SYNC_A,            SEL_DRIF2_0),
1288
1289         PINMUX_IPSR_GPSR(IP14_31_28,    SSI_SDATA4),
1290         PINMUX_IPSR_MSEL(IP14_31_28,    HSCK2_A,                SEL_HSCIF2_0),
1291         PINMUX_IPSR_MSEL(IP14_31_28,    MSIOF1_RXD_A,           SEL_MSIOF1_0),
1292         PINMUX_IPSR_MSEL(IP14_31_28,    TS_SPSYNC0_A,           SEL_TSIF0_0),
1293         PINMUX_IPSR_MSEL(IP14_31_28,    STP_ISSYNC_0_A,         SEL_SSP1_0_0),
1294         PINMUX_IPSR_MSEL(IP14_31_28,    RIF0_D0_A,              SEL_DRIF0_0),
1295         PINMUX_IPSR_MSEL(IP14_31_28,    RIF2_D1_A,              SEL_DRIF2_0),
1296
1297         /* IPSR15 */
1298         PINMUX_IPSR_GPSR(IP15_3_0,      SSI_SCK6),
1299         PINMUX_IPSR_GPSR(IP15_3_0,      USB2_PWEN),
1300         PINMUX_IPSR_MSEL(IP15_3_0,      SIM0_RST_D,             SEL_SIMCARD_3),
1301
1302         PINMUX_IPSR_GPSR(IP15_7_4,      SSI_WS6),
1303         PINMUX_IPSR_GPSR(IP15_7_4,      USB2_OVC),
1304         PINMUX_IPSR_MSEL(IP15_7_4,      SIM0_D_D,               SEL_SIMCARD_3),
1305
1306         PINMUX_IPSR_GPSR(IP15_11_8,     SSI_SDATA6),
1307         PINMUX_IPSR_MSEL(IP15_11_8,     SIM0_CLK_D,             SEL_SIMCARD_3),
1308         PINMUX_IPSR_MSEL(IP15_11_8,     SATA_DEVSLP_A,          SEL_SATA_0),
1309
1310         PINMUX_IPSR_GPSR(IP15_15_12,    SSI_SCK78),
1311         PINMUX_IPSR_MSEL(IP15_15_12,    HRX2_B,                 SEL_HSCIF2_1),
1312         PINMUX_IPSR_MSEL(IP15_15_12,    MSIOF1_SCK_C,           SEL_MSIOF1_2),
1313         PINMUX_IPSR_MSEL(IP15_15_12,    TS_SCK1_A,              SEL_TSIF1_0),
1314         PINMUX_IPSR_MSEL(IP15_15_12,    STP_ISCLK_1_A,          SEL_SSP1_1_0),
1315         PINMUX_IPSR_MSEL(IP15_15_12,    RIF1_CLK_A,             SEL_DRIF1_0),
1316         PINMUX_IPSR_MSEL(IP15_15_12,    RIF3_CLK_A,             SEL_DRIF3_0),
1317
1318         PINMUX_IPSR_GPSR(IP15_19_16,    SSI_WS78),
1319         PINMUX_IPSR_MSEL(IP15_19_16,    HTX2_B,                 SEL_HSCIF2_1),
1320         PINMUX_IPSR_MSEL(IP15_19_16,    MSIOF1_SYNC_C,          SEL_MSIOF1_2),
1321         PINMUX_IPSR_MSEL(IP15_19_16,    TS_SDAT1_A,             SEL_TSIF1_0),
1322         PINMUX_IPSR_MSEL(IP15_19_16,    STP_ISD_1_A,            SEL_SSP1_1_0),
1323         PINMUX_IPSR_MSEL(IP15_19_16,    RIF1_SYNC_A,            SEL_DRIF1_0),
1324         PINMUX_IPSR_MSEL(IP15_19_16,    RIF3_SYNC_A,            SEL_DRIF3_0),
1325
1326         PINMUX_IPSR_GPSR(IP15_23_20,    SSI_SDATA7),
1327         PINMUX_IPSR_MSEL(IP15_23_20,    HCTS2_N_B,              SEL_HSCIF2_1),
1328         PINMUX_IPSR_MSEL(IP15_23_20,    MSIOF1_RXD_C,           SEL_MSIOF1_2),
1329         PINMUX_IPSR_MSEL(IP15_23_20,    TS_SDEN1_A,             SEL_TSIF1_0),
1330         PINMUX_IPSR_MSEL(IP15_23_20,    STP_ISEN_1_A,           SEL_SSP1_1_0),
1331         PINMUX_IPSR_MSEL(IP15_23_20,    RIF1_D0_A,              SEL_DRIF1_0),
1332         PINMUX_IPSR_MSEL(IP15_23_20,    RIF3_D0_A,              SEL_DRIF3_0),
1333         PINMUX_IPSR_MSEL(IP15_23_20,    TCLK2_A,                SEL_TIMER_TMU_0),
1334
1335         PINMUX_IPSR_GPSR(IP15_27_24,    SSI_SDATA8),
1336         PINMUX_IPSR_MSEL(IP15_27_24,    HRTS2_N_B,              SEL_HSCIF2_1),
1337         PINMUX_IPSR_MSEL(IP15_27_24,    MSIOF1_TXD_C,           SEL_MSIOF1_2),
1338         PINMUX_IPSR_MSEL(IP15_27_24,    TS_SPSYNC1_A,           SEL_TSIF1_0),
1339         PINMUX_IPSR_MSEL(IP15_27_24,    STP_ISSYNC_1_A,         SEL_SSP1_1_0),
1340         PINMUX_IPSR_MSEL(IP15_27_24,    RIF1_D1_A,              SEL_DRIF1_0),
1341         PINMUX_IPSR_MSEL(IP15_27_24,    RIF3_D1_A,              SEL_DRIF3_0),
1342
1343         PINMUX_IPSR_MSEL(IP15_31_28,    SSI_SDATA9_A,           SEL_SSI_0),
1344         PINMUX_IPSR_MSEL(IP15_31_28,    HSCK2_B,                SEL_HSCIF2_1),
1345         PINMUX_IPSR_MSEL(IP15_31_28,    MSIOF1_SS1_C,           SEL_MSIOF1_2),
1346         PINMUX_IPSR_MSEL(IP15_31_28,    HSCK1_A,                SEL_HSCIF1_0),
1347         PINMUX_IPSR_MSEL(IP15_31_28,    SSI_WS1_B,              SEL_SSI_1),
1348         PINMUX_IPSR_GPSR(IP15_31_28,    SCK1),
1349         PINMUX_IPSR_MSEL(IP15_31_28,    STP_IVCXO27_1_A,        SEL_SSP1_1_0),
1350         PINMUX_IPSR_GPSR(IP15_31_28,    SCK5),
1351
1352         /* IPSR16 */
1353         PINMUX_IPSR_MSEL(IP16_3_0,      AUDIO_CLKA_A,           SEL_ADG_0),
1354         PINMUX_IPSR_GPSR(IP16_3_0,      CC5_OSCOUT),
1355
1356         PINMUX_IPSR_MSEL(IP16_7_4,      AUDIO_CLKB_B,           SEL_ADG_1),
1357         PINMUX_IPSR_MSEL(IP16_7_4,      SCIF_CLK_A,             SEL_SCIF1_0),
1358         PINMUX_IPSR_MSEL(IP16_7_4,      STP_IVCXO27_1_D,        SEL_SSP1_1_3),
1359         PINMUX_IPSR_MSEL(IP16_7_4,      REMOCON_A,              SEL_REMOCON_0),
1360         PINMUX_IPSR_MSEL(IP16_7_4,      TCLK1_A,                SEL_TIMER_TMU_0),
1361
1362         PINMUX_IPSR_GPSR(IP16_11_8,     USB0_PWEN),
1363         PINMUX_IPSR_MSEL(IP16_11_8,     SIM0_RST_C,             SEL_SIMCARD_2),
1364         PINMUX_IPSR_MSEL(IP16_11_8,     TS_SCK1_D,              SEL_TSIF1_3),
1365         PINMUX_IPSR_MSEL(IP16_11_8,     STP_ISCLK_1_D,          SEL_SSP1_1_3),
1366         PINMUX_IPSR_MSEL(IP16_11_8,     BPFCLK_B,               SEL_FM_1),
1367         PINMUX_IPSR_MSEL(IP16_11_8,     RIF3_CLK_B,             SEL_DRIF3_1),
1368
1369         PINMUX_IPSR_GPSR(IP16_15_12,    USB0_OVC),
1370         PINMUX_IPSR_MSEL(IP16_11_8,     SIM0_D_C,               SEL_SIMCARD_2),
1371         PINMUX_IPSR_MSEL(IP16_11_8,     TS_SDAT1_D,             SEL_TSIF1_3),
1372         PINMUX_IPSR_MSEL(IP16_11_8,     STP_ISD_1_D,            SEL_SSP1_1_3),
1373         PINMUX_IPSR_MSEL(IP16_11_8,     RIF3_SYNC_B,            SEL_DRIF3_1),
1374
1375         PINMUX_IPSR_GPSR(IP16_19_16,    USB1_PWEN),
1376         PINMUX_IPSR_MSEL(IP16_19_16,    SIM0_CLK_C,             SEL_SIMCARD_2),
1377         PINMUX_IPSR_MSEL(IP16_19_16,    SSI_SCK1_A,             SEL_SSI_0),
1378         PINMUX_IPSR_MSEL(IP16_19_16,    TS_SCK0_E,              SEL_TSIF0_4),
1379         PINMUX_IPSR_MSEL(IP16_19_16,    STP_ISCLK_0_E,          SEL_SSP1_0_4),
1380         PINMUX_IPSR_MSEL(IP16_19_16,    FMCLK_B,                SEL_FM_1),
1381         PINMUX_IPSR_MSEL(IP16_19_16,    RIF2_CLK_B,             SEL_DRIF2_1),
1382         PINMUX_IPSR_MSEL(IP16_19_16,    SPEEDIN_A,              SEL_SPEED_PULSE_0),
1383
1384         PINMUX_IPSR_GPSR(IP16_23_20,    USB1_OVC),
1385         PINMUX_IPSR_MSEL(IP16_23_20,    MSIOF1_SS2_C,           SEL_MSIOF1_2),
1386         PINMUX_IPSR_MSEL(IP16_23_20,    SSI_WS1_A,              SEL_SSI_0),
1387         PINMUX_IPSR_MSEL(IP16_23_20,    TS_SDAT0_E,             SEL_TSIF0_4),
1388         PINMUX_IPSR_MSEL(IP16_23_20,    STP_ISD_0_E,            SEL_SSP1_0_4),
1389         PINMUX_IPSR_MSEL(IP16_23_20,    FMIN_B,                 SEL_FM_1),
1390         PINMUX_IPSR_MSEL(IP16_23_20,    RIF2_SYNC_B,            SEL_DRIF2_1),
1391         PINMUX_IPSR_MSEL(IP16_23_20,    REMOCON_B,              SEL_REMOCON_1),
1392
1393         PINMUX_IPSR_GPSR(IP16_27_24,    USB30_PWEN),
1394         PINMUX_IPSR_MSEL(IP16_27_24,    AUDIO_CLKOUT_B,         SEL_ADG_1),
1395         PINMUX_IPSR_MSEL(IP16_27_24,    SSI_SCK2_B,             SEL_SSI_1),
1396         PINMUX_IPSR_MSEL(IP16_27_24,    TS_SDEN1_D,             SEL_TSIF1_3),
1397         PINMUX_IPSR_MSEL(IP16_27_24,    STP_ISEN_1_D,           SEL_SSP1_1_3),
1398         PINMUX_IPSR_MSEL(IP16_27_24,    STP_OPWM_0_E,           SEL_SSP1_0_4),
1399         PINMUX_IPSR_MSEL(IP16_27_24,    RIF3_D0_B,              SEL_DRIF3_1),
1400         PINMUX_IPSR_MSEL(IP16_27_24,    TCLK2_B,                SEL_TIMER_TMU_1),
1401         PINMUX_IPSR_GPSR(IP16_27_24,    TPU0TO0),
1402
1403         PINMUX_IPSR_GPSR(IP16_31_28,    USB30_OVC),
1404         PINMUX_IPSR_MSEL(IP16_31_28,    AUDIO_CLKOUT1_B,        SEL_ADG_1),
1405         PINMUX_IPSR_MSEL(IP16_31_28,    SSI_WS2_B,              SEL_SSI_1),
1406         PINMUX_IPSR_MSEL(IP16_31_28,    TS_SPSYNC1_D,           SEL_TSIF1_3),
1407         PINMUX_IPSR_MSEL(IP16_31_28,    STP_ISSYNC_1_D,         SEL_SSP1_1_3),
1408         PINMUX_IPSR_MSEL(IP16_31_28,    STP_IVCXO27_0_E,        SEL_SSP1_0_4),
1409         PINMUX_IPSR_MSEL(IP16_31_28,    RIF3_D1_B,              SEL_DRIF3_1),
1410         PINMUX_IPSR_MSEL(IP16_31_28,    FSO_TOE_B,              SEL_FSO_1),
1411         PINMUX_IPSR_GPSR(IP16_31_28,    TPU0TO1),
1412
1413         /* IPSR17 */
1414         PINMUX_IPSR_GPSR(IP17_3_0,      USB31_PWEN),
1415         PINMUX_IPSR_MSEL(IP17_3_0,      AUDIO_CLKOUT2_B,        SEL_ADG_1),
1416         PINMUX_IPSR_MSEL(IP17_3_0,      SSI_SCK9_B,             SEL_SSI_1),
1417         PINMUX_IPSR_MSEL(IP17_3_0,      TS_SDEN0_E,             SEL_TSIF0_4),
1418         PINMUX_IPSR_MSEL(IP17_3_0,      STP_ISEN_0_E,           SEL_SSP1_0_4),
1419         PINMUX_IPSR_MSEL(IP17_3_0,      RIF2_D0_B,              SEL_DRIF2_1),
1420         PINMUX_IPSR_GPSR(IP17_3_0,      TPU0TO2),
1421
1422         PINMUX_IPSR_GPSR(IP17_7_4,      USB31_OVC),
1423         PINMUX_IPSR_MSEL(IP17_7_4,      AUDIO_CLKOUT3_B,        SEL_ADG_1),
1424         PINMUX_IPSR_MSEL(IP17_7_4,      SSI_WS9_B,              SEL_SSI_1),
1425         PINMUX_IPSR_MSEL(IP17_7_4,      TS_SPSYNC0_E,           SEL_TSIF0_4),
1426         PINMUX_IPSR_MSEL(IP17_7_4,      STP_ISSYNC_0_E,         SEL_SSP1_0_4),
1427         PINMUX_IPSR_MSEL(IP17_7_4,      RIF2_D1_B,              SEL_DRIF2_1),
1428         PINMUX_IPSR_GPSR(IP17_7_4,      TPU0TO3),
1429
1430 /*
1431  * Static pins can not be muxed between different functions but
1432  * still need mark entries in the pinmux list. Add each static
1433  * pin to the list without an associated function. The sh-pfc
1434  * core will do the right thing and skip trying to mux the pin
1435  * while still applying configuration to it.
1436  */
1437 #define FM(x)   PINMUX_DATA(x##_MARK, 0),
1438         PINMUX_STATIC
1439 #undef FM
1440 };
1441
1442 /*
1443  * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1444  * Physical layout rows: A - AW, cols: 1 - 39.
1445  */
1446 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1447 #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1448 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1449 #define PIN_NONE U16_MAX
1450
1451 static const struct sh_pfc_pin pinmux_pins[] = {
1452         PINMUX_GPIO_GP_ALL(),
1453
1454         /*
1455          * Pins not associated with a GPIO port.
1456          *
1457          * The pin positions are different between different r8a7795
1458          * packages, all that is needed for the pfc driver is a unique
1459          * number for each pin. To this end use the pin layout from
1460          * R-Car H3SiP to calculate a unique number for each pin.
1461          */
1462         SH_PFC_PIN_NAMED_CFG('A',  8, AVB_TX_CTL, CFG_FLAGS),
1463         SH_PFC_PIN_NAMED_CFG('A',  9, AVB_MDIO, CFG_FLAGS),
1464         SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1465         SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1466         SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1467         SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1468         SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1469         SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1470         SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1471         SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1472         SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1473         SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1474         SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1475         SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1476         SH_PFC_PIN_NAMED_CFG('C',  1, PRESETOUT#, CFG_FLAGS),
1477         SH_PFC_PIN_NAMED_CFG('F',  1, CLKOUT, CFG_FLAGS),
1478         SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1479         SH_PFC_PIN_NAMED_CFG('V',  3, QSPI1_SPCLK, CFG_FLAGS),
1480         SH_PFC_PIN_NAMED_CFG('V',  5, QSPI1_SSL, CFG_FLAGS),
1481         SH_PFC_PIN_NAMED_CFG('V',  6, RPC_WP#, CFG_FLAGS),
1482         SH_PFC_PIN_NAMED_CFG('V',  7, RPC_RESET#, CFG_FLAGS),
1483         SH_PFC_PIN_NAMED_CFG('W',  3, QSPI0_SPCLK, CFG_FLAGS),
1484         SH_PFC_PIN_NAMED_CFG('Y',  3, QSPI0_SSL, CFG_FLAGS),
1485         SH_PFC_PIN_NAMED_CFG('Y',  6, QSPI0_IO2, CFG_FLAGS),
1486         SH_PFC_PIN_NAMED_CFG('Y',  7, RPC_INT#, CFG_FLAGS),
1487         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  4, QSPI0_MISO_IO1, CFG_FLAGS),
1488         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  6, QSPI0_IO3, CFG_FLAGS),
1489         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  3, QSPI1_IO3, CFG_FLAGS),
1490         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  5, QSPI0_MOSI_IO0, CFG_FLAGS),
1491         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  7, QSPI1_MOSI_IO0, CFG_FLAGS),
1492         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
1493         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1494         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  4, QSPI1_IO2, CFG_FLAGS),
1495         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  5, QSPI1_MISO_IO1, CFG_FLAGS),
1496         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  7, DU_DOTCLKIN0, CFG_FLAGS),
1497         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  8, DU_DOTCLKIN1, CFG_FLAGS),
1498         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  7, DU_DOTCLKIN2, CFG_FLAGS),
1499         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  8, DU_DOTCLKIN3, CFG_FLAGS),
1500         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1501         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1502         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1503         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1504         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1505         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1506 };
1507
1508 /* - AUDIO CLOCK ------------------------------------------------------------ */
1509 static const unsigned int audio_clk_a_a_pins[] = {
1510         /* CLK A */
1511         RCAR_GP_PIN(6, 22),
1512 };
1513 static const unsigned int audio_clk_a_a_mux[] = {
1514         AUDIO_CLKA_A_MARK,
1515 };
1516 static const unsigned int audio_clk_a_b_pins[] = {
1517         /* CLK A */
1518         RCAR_GP_PIN(5, 4),
1519 };
1520 static const unsigned int audio_clk_a_b_mux[] = {
1521         AUDIO_CLKA_B_MARK,
1522 };
1523 static const unsigned int audio_clk_a_c_pins[] = {
1524         /* CLK A */
1525         RCAR_GP_PIN(5, 19),
1526 };
1527 static const unsigned int audio_clk_a_c_mux[] = {
1528         AUDIO_CLKA_C_MARK,
1529 };
1530 static const unsigned int audio_clk_b_a_pins[] = {
1531         /* CLK B */
1532         RCAR_GP_PIN(5, 12),
1533 };
1534 static const unsigned int audio_clk_b_a_mux[] = {
1535         AUDIO_CLKB_A_MARK,
1536 };
1537 static const unsigned int audio_clk_b_b_pins[] = {
1538         /* CLK B */
1539         RCAR_GP_PIN(6, 23),
1540 };
1541 static const unsigned int audio_clk_b_b_mux[] = {
1542         AUDIO_CLKB_B_MARK,
1543 };
1544 static const unsigned int audio_clk_c_a_pins[] = {
1545         /* CLK C */
1546         RCAR_GP_PIN(5, 21),
1547 };
1548 static const unsigned int audio_clk_c_a_mux[] = {
1549         AUDIO_CLKC_A_MARK,
1550 };
1551 static const unsigned int audio_clk_c_b_pins[] = {
1552         /* CLK C */
1553         RCAR_GP_PIN(5, 0),
1554 };
1555 static const unsigned int audio_clk_c_b_mux[] = {
1556         AUDIO_CLKC_B_MARK,
1557 };
1558 static const unsigned int audio_clkout_a_pins[] = {
1559         /* CLKOUT */
1560         RCAR_GP_PIN(5, 18),
1561 };
1562 static const unsigned int audio_clkout_a_mux[] = {
1563         AUDIO_CLKOUT_A_MARK,
1564 };
1565 static const unsigned int audio_clkout_b_pins[] = {
1566         /* CLKOUT */
1567         RCAR_GP_PIN(6, 28),
1568 };
1569 static const unsigned int audio_clkout_b_mux[] = {
1570         AUDIO_CLKOUT_B_MARK,
1571 };
1572 static const unsigned int audio_clkout_c_pins[] = {
1573         /* CLKOUT */
1574         RCAR_GP_PIN(5, 3),
1575 };
1576 static const unsigned int audio_clkout_c_mux[] = {
1577         AUDIO_CLKOUT_C_MARK,
1578 };
1579 static const unsigned int audio_clkout_d_pins[] = {
1580         /* CLKOUT */
1581         RCAR_GP_PIN(5, 21),
1582 };
1583 static const unsigned int audio_clkout_d_mux[] = {
1584         AUDIO_CLKOUT_D_MARK,
1585 };
1586 static const unsigned int audio_clkout1_a_pins[] = {
1587         /* CLKOUT1 */
1588         RCAR_GP_PIN(5, 15),
1589 };
1590 static const unsigned int audio_clkout1_a_mux[] = {
1591         AUDIO_CLKOUT1_A_MARK,
1592 };
1593 static const unsigned int audio_clkout1_b_pins[] = {
1594         /* CLKOUT1 */
1595         RCAR_GP_PIN(6, 29),
1596 };
1597 static const unsigned int audio_clkout1_b_mux[] = {
1598         AUDIO_CLKOUT1_B_MARK,
1599 };
1600 static const unsigned int audio_clkout2_a_pins[] = {
1601         /* CLKOUT2 */
1602         RCAR_GP_PIN(5, 16),
1603 };
1604 static const unsigned int audio_clkout2_a_mux[] = {
1605         AUDIO_CLKOUT2_A_MARK,
1606 };
1607 static const unsigned int audio_clkout2_b_pins[] = {
1608         /* CLKOUT2 */
1609         RCAR_GP_PIN(6, 30),
1610 };
1611 static const unsigned int audio_clkout2_b_mux[] = {
1612         AUDIO_CLKOUT2_B_MARK,
1613 };
1614
1615 static const unsigned int audio_clkout3_a_pins[] = {
1616         /* CLKOUT3 */
1617         RCAR_GP_PIN(5, 19),
1618 };
1619 static const unsigned int audio_clkout3_a_mux[] = {
1620         AUDIO_CLKOUT3_A_MARK,
1621 };
1622 static const unsigned int audio_clkout3_b_pins[] = {
1623         /* CLKOUT3 */
1624         RCAR_GP_PIN(6, 31),
1625 };
1626 static const unsigned int audio_clkout3_b_mux[] = {
1627         AUDIO_CLKOUT3_B_MARK,
1628 };
1629
1630 /* - EtherAVB --------------------------------------------------------------- */
1631 static const unsigned int avb_link_pins[] = {
1632         /* AVB_LINK */
1633         RCAR_GP_PIN(2, 12),
1634 };
1635 static const unsigned int avb_link_mux[] = {
1636         AVB_LINK_MARK,
1637 };
1638 static const unsigned int avb_magic_pins[] = {
1639         /* AVB_MAGIC_ */
1640         RCAR_GP_PIN(2, 10),
1641 };
1642 static const unsigned int avb_magic_mux[] = {
1643         AVB_MAGIC_MARK,
1644 };
1645 static const unsigned int avb_phy_int_pins[] = {
1646         /* AVB_PHY_INT */
1647         RCAR_GP_PIN(2, 11),
1648 };
1649 static const unsigned int avb_phy_int_mux[] = {
1650         AVB_PHY_INT_MARK,
1651 };
1652 static const unsigned int avb_mdio_pins[] = {
1653         /* AVB_MDC, AVB_MDIO */
1654         RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1655 };
1656 static const unsigned int avb_mdio_mux[] = {
1657         AVB_MDC_MARK, AVB_MDIO_MARK,
1658 };
1659 static const unsigned int avb_mii_pins[] = {
1660         /*
1661          * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1662          * AVB_TD1, AVB_TD2, AVB_TD3,
1663          * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1664          * AVB_RD1, AVB_RD2, AVB_RD3,
1665          * AVB_TXCREFCLK
1666          */
1667         PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1668         PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1669         PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1670         PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1671         PIN_NUMBER('A', 12),
1672
1673 };
1674 static const unsigned int avb_mii_mux[] = {
1675         AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1676         AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1677         AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1678         AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1679         AVB_TXCREFCLK_MARK,
1680 };
1681 static const unsigned int avb_avtp_pps_pins[] = {
1682         /* AVB_AVTP_PPS */
1683         RCAR_GP_PIN(2, 6),
1684 };
1685 static const unsigned int avb_avtp_pps_mux[] = {
1686         AVB_AVTP_PPS_MARK,
1687 };
1688 static const unsigned int avb_avtp_match_a_pins[] = {
1689         /* AVB_AVTP_MATCH_A */
1690         RCAR_GP_PIN(2, 13),
1691 };
1692 static const unsigned int avb_avtp_match_a_mux[] = {
1693         AVB_AVTP_MATCH_A_MARK,
1694 };
1695 static const unsigned int avb_avtp_capture_a_pins[] = {
1696         /* AVB_AVTP_CAPTURE_A */
1697         RCAR_GP_PIN(2, 14),
1698 };
1699 static const unsigned int avb_avtp_capture_a_mux[] = {
1700         AVB_AVTP_CAPTURE_A_MARK,
1701 };
1702 static const unsigned int avb_avtp_match_b_pins[] = {
1703         /*  AVB_AVTP_MATCH_B */
1704         RCAR_GP_PIN(1, 8),
1705 };
1706 static const unsigned int avb_avtp_match_b_mux[] = {
1707         AVB_AVTP_MATCH_B_MARK,
1708 };
1709 static const unsigned int avb_avtp_capture_b_pins[] = {
1710         /* AVB_AVTP_CAPTURE_B */
1711         RCAR_GP_PIN(1, 11),
1712 };
1713 static const unsigned int avb_avtp_capture_b_mux[] = {
1714         AVB_AVTP_CAPTURE_B_MARK,
1715 };
1716
1717 /* - CAN ------------------------------------------------------------------ */
1718 static const unsigned int can0_data_a_pins[] = {
1719         /* TX, RX */
1720         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1721 };
1722 static const unsigned int can0_data_a_mux[] = {
1723         CAN0_TX_A_MARK,         CAN0_RX_A_MARK,
1724 };
1725 static const unsigned int can0_data_b_pins[] = {
1726         /* TX, RX */
1727         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1728 };
1729 static const unsigned int can0_data_b_mux[] = {
1730         CAN0_TX_B_MARK,         CAN0_RX_B_MARK,
1731 };
1732 static const unsigned int can1_data_pins[] = {
1733         /* TX, RX */
1734         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1735 };
1736 static const unsigned int can1_data_mux[] = {
1737         CAN1_TX_MARK,           CAN1_RX_MARK,
1738 };
1739
1740 /* - CAN Clock -------------------------------------------------------------- */
1741 static const unsigned int can_clk_pins[] = {
1742         /* CLK */
1743         RCAR_GP_PIN(1, 25),
1744 };
1745 static const unsigned int can_clk_mux[] = {
1746         CAN_CLK_MARK,
1747 };
1748
1749 /* - CAN FD --------------------------------------------------------------- */
1750 static const unsigned int canfd0_data_a_pins[] = {
1751         /* TX, RX */
1752         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1753 };
1754 static const unsigned int canfd0_data_a_mux[] = {
1755         CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
1756 };
1757 static const unsigned int canfd0_data_b_pins[] = {
1758         /* TX, RX */
1759         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1760 };
1761 static const unsigned int canfd0_data_b_mux[] = {
1762         CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
1763 };
1764 static const unsigned int canfd1_data_pins[] = {
1765         /* TX, RX */
1766         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1767 };
1768 static const unsigned int canfd1_data_mux[] = {
1769         CANFD1_TX_MARK,         CANFD1_RX_MARK,
1770 };
1771
1772 /* - DRIF0 --------------------------------------------------------------- */
1773 static const unsigned int drif0_ctrl_a_pins[] = {
1774         /* CLK, SYNC */
1775         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1776 };
1777 static const unsigned int drif0_ctrl_a_mux[] = {
1778         RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1779 };
1780 static const unsigned int drif0_data0_a_pins[] = {
1781         /* D0 */
1782         RCAR_GP_PIN(6, 10),
1783 };
1784 static const unsigned int drif0_data0_a_mux[] = {
1785         RIF0_D0_A_MARK,
1786 };
1787 static const unsigned int drif0_data1_a_pins[] = {
1788         /* D1 */
1789         RCAR_GP_PIN(6, 7),
1790 };
1791 static const unsigned int drif0_data1_a_mux[] = {
1792         RIF0_D1_A_MARK,
1793 };
1794 static const unsigned int drif0_ctrl_b_pins[] = {
1795         /* CLK, SYNC */
1796         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1797 };
1798 static const unsigned int drif0_ctrl_b_mux[] = {
1799         RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1800 };
1801 static const unsigned int drif0_data0_b_pins[] = {
1802         /* D0 */
1803         RCAR_GP_PIN(5, 1),
1804 };
1805 static const unsigned int drif0_data0_b_mux[] = {
1806         RIF0_D0_B_MARK,
1807 };
1808 static const unsigned int drif0_data1_b_pins[] = {
1809         /* D1 */
1810         RCAR_GP_PIN(5, 2),
1811 };
1812 static const unsigned int drif0_data1_b_mux[] = {
1813         RIF0_D1_B_MARK,
1814 };
1815 static const unsigned int drif0_ctrl_c_pins[] = {
1816         /* CLK, SYNC */
1817         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1818 };
1819 static const unsigned int drif0_ctrl_c_mux[] = {
1820         RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1821 };
1822 static const unsigned int drif0_data0_c_pins[] = {
1823         /* D0 */
1824         RCAR_GP_PIN(5, 13),
1825 };
1826 static const unsigned int drif0_data0_c_mux[] = {
1827         RIF0_D0_C_MARK,
1828 };
1829 static const unsigned int drif0_data1_c_pins[] = {
1830         /* D1 */
1831         RCAR_GP_PIN(5, 14),
1832 };
1833 static const unsigned int drif0_data1_c_mux[] = {
1834         RIF0_D1_C_MARK,
1835 };
1836 /* - DRIF1 --------------------------------------------------------------- */
1837 static const unsigned int drif1_ctrl_a_pins[] = {
1838         /* CLK, SYNC */
1839         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1840 };
1841 static const unsigned int drif1_ctrl_a_mux[] = {
1842         RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1843 };
1844 static const unsigned int drif1_data0_a_pins[] = {
1845         /* D0 */
1846         RCAR_GP_PIN(6, 19),
1847 };
1848 static const unsigned int drif1_data0_a_mux[] = {
1849         RIF1_D0_A_MARK,
1850 };
1851 static const unsigned int drif1_data1_a_pins[] = {
1852         /* D1 */
1853         RCAR_GP_PIN(6, 20),
1854 };
1855 static const unsigned int drif1_data1_a_mux[] = {
1856         RIF1_D1_A_MARK,
1857 };
1858 static const unsigned int drif1_ctrl_b_pins[] = {
1859         /* CLK, SYNC */
1860         RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1861 };
1862 static const unsigned int drif1_ctrl_b_mux[] = {
1863         RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1864 };
1865 static const unsigned int drif1_data0_b_pins[] = {
1866         /* D0 */
1867         RCAR_GP_PIN(5, 7),
1868 };
1869 static const unsigned int drif1_data0_b_mux[] = {
1870         RIF1_D0_B_MARK,
1871 };
1872 static const unsigned int drif1_data1_b_pins[] = {
1873         /* D1 */
1874         RCAR_GP_PIN(5, 8),
1875 };
1876 static const unsigned int drif1_data1_b_mux[] = {
1877         RIF1_D1_B_MARK,
1878 };
1879 static const unsigned int drif1_ctrl_c_pins[] = {
1880         /* CLK, SYNC */
1881         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1882 };
1883 static const unsigned int drif1_ctrl_c_mux[] = {
1884         RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1885 };
1886 static const unsigned int drif1_data0_c_pins[] = {
1887         /* D0 */
1888         RCAR_GP_PIN(5, 6),
1889 };
1890 static const unsigned int drif1_data0_c_mux[] = {
1891         RIF1_D0_C_MARK,
1892 };
1893 static const unsigned int drif1_data1_c_pins[] = {
1894         /* D1 */
1895         RCAR_GP_PIN(5, 10),
1896 };
1897 static const unsigned int drif1_data1_c_mux[] = {
1898         RIF1_D1_C_MARK,
1899 };
1900 /* - DRIF2 --------------------------------------------------------------- */
1901 static const unsigned int drif2_ctrl_a_pins[] = {
1902         /* CLK, SYNC */
1903         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1904 };
1905 static const unsigned int drif2_ctrl_a_mux[] = {
1906         RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1907 };
1908 static const unsigned int drif2_data0_a_pins[] = {
1909         /* D0 */
1910         RCAR_GP_PIN(6, 7),
1911 };
1912 static const unsigned int drif2_data0_a_mux[] = {
1913         RIF2_D0_A_MARK,
1914 };
1915 static const unsigned int drif2_data1_a_pins[] = {
1916         /* D1 */
1917         RCAR_GP_PIN(6, 10),
1918 };
1919 static const unsigned int drif2_data1_a_mux[] = {
1920         RIF2_D1_A_MARK,
1921 };
1922 static const unsigned int drif2_ctrl_b_pins[] = {
1923         /* CLK, SYNC */
1924         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1925 };
1926 static const unsigned int drif2_ctrl_b_mux[] = {
1927         RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1928 };
1929 static const unsigned int drif2_data0_b_pins[] = {
1930         /* D0 */
1931         RCAR_GP_PIN(6, 30),
1932 };
1933 static const unsigned int drif2_data0_b_mux[] = {
1934         RIF2_D0_B_MARK,
1935 };
1936 static const unsigned int drif2_data1_b_pins[] = {
1937         /* D1 */
1938         RCAR_GP_PIN(6, 31),
1939 };
1940 static const unsigned int drif2_data1_b_mux[] = {
1941         RIF2_D1_B_MARK,
1942 };
1943 /* - DRIF3 --------------------------------------------------------------- */
1944 static const unsigned int drif3_ctrl_a_pins[] = {
1945         /* CLK, SYNC */
1946         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1947 };
1948 static const unsigned int drif3_ctrl_a_mux[] = {
1949         RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
1950 };
1951 static const unsigned int drif3_data0_a_pins[] = {
1952         /* D0 */
1953         RCAR_GP_PIN(6, 19),
1954 };
1955 static const unsigned int drif3_data0_a_mux[] = {
1956         RIF3_D0_A_MARK,
1957 };
1958 static const unsigned int drif3_data1_a_pins[] = {
1959         /* D1 */
1960         RCAR_GP_PIN(6, 20),
1961 };
1962 static const unsigned int drif3_data1_a_mux[] = {
1963         RIF3_D1_A_MARK,
1964 };
1965 static const unsigned int drif3_ctrl_b_pins[] = {
1966         /* CLK, SYNC */
1967         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
1968 };
1969 static const unsigned int drif3_ctrl_b_mux[] = {
1970         RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
1971 };
1972 static const unsigned int drif3_data0_b_pins[] = {
1973         /* D0 */
1974         RCAR_GP_PIN(6, 28),
1975 };
1976 static const unsigned int drif3_data0_b_mux[] = {
1977         RIF3_D0_B_MARK,
1978 };
1979 static const unsigned int drif3_data1_b_pins[] = {
1980         /* D1 */
1981         RCAR_GP_PIN(6, 29),
1982 };
1983 static const unsigned int drif3_data1_b_mux[] = {
1984         RIF3_D1_B_MARK,
1985 };
1986
1987 /* - DU --------------------------------------------------------------------- */
1988 static const unsigned int du_rgb666_pins[] = {
1989         /* R[7:2], G[7:2], B[7:2] */
1990         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1991         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1992         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1993         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1994         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
1995         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
1996 };
1997 static const unsigned int du_rgb666_mux[] = {
1998         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1999         DU_DR3_MARK, DU_DR2_MARK,
2000         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2001         DU_DG3_MARK, DU_DG2_MARK,
2002         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2003         DU_DB3_MARK, DU_DB2_MARK,
2004 };
2005 static const unsigned int du_rgb888_pins[] = {
2006         /* R[7:0], G[7:0], B[7:0] */
2007         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2008         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2009         RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),
2010         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2011         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2012         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2013         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2014         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2015         RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
2016 };
2017 static const unsigned int du_rgb888_mux[] = {
2018         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2019         DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2020         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2021         DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2022         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2023         DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2024 };
2025 static const unsigned int du_clk_out_0_pins[] = {
2026         /* CLKOUT */
2027         RCAR_GP_PIN(1, 27),
2028 };
2029 static const unsigned int du_clk_out_0_mux[] = {
2030         DU_DOTCLKOUT0_MARK
2031 };
2032 static const unsigned int du_clk_out_1_pins[] = {
2033         /* CLKOUT */
2034         RCAR_GP_PIN(2, 3),
2035 };
2036 static const unsigned int du_clk_out_1_mux[] = {
2037         DU_DOTCLKOUT1_MARK
2038 };
2039 static const unsigned int du_sync_pins[] = {
2040         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2041         RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2042 };
2043 static const unsigned int du_sync_mux[] = {
2044         DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2045 };
2046 static const unsigned int du_oddf_pins[] = {
2047         /* EXDISP/EXODDF/EXCDE */
2048         RCAR_GP_PIN(2, 2),
2049 };
2050 static const unsigned int du_oddf_mux[] = {
2051         DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2052 };
2053 static const unsigned int du_cde_pins[] = {
2054         /* CDE */
2055         RCAR_GP_PIN(2, 0),
2056 };
2057 static const unsigned int du_cde_mux[] = {
2058         DU_CDE_MARK,
2059 };
2060 static const unsigned int du_disp_pins[] = {
2061         /* DISP */
2062         RCAR_GP_PIN(2, 1),
2063 };
2064 static const unsigned int du_disp_mux[] = {
2065         DU_DISP_MARK,
2066 };
2067 /* - HDMI ------------------------------------------------------------------- */
2068 static const unsigned int hdmi0_cec_pins[] = {
2069         /* HDMI0_CEC */
2070         RCAR_GP_PIN(7, 2),
2071 };
2072 static const unsigned int hdmi0_cec_mux[] = {
2073         HDMI0_CEC_MARK,
2074 };
2075 static const unsigned int hdmi1_cec_pins[] = {
2076         /* HDMI1_CEC */
2077         RCAR_GP_PIN(7, 3),
2078 };
2079 static const unsigned int hdmi1_cec_mux[] = {
2080         HDMI1_CEC_MARK,
2081 };
2082
2083 /* - HSCIF0 ----------------------------------------------------------------- */
2084 static const unsigned int hscif0_data_pins[] = {
2085         /* RX, TX */
2086         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2087 };
2088 static const unsigned int hscif0_data_mux[] = {
2089         HRX0_MARK, HTX0_MARK,
2090 };
2091 static const unsigned int hscif0_clk_pins[] = {
2092         /* SCK */
2093         RCAR_GP_PIN(5, 12),
2094 };
2095 static const unsigned int hscif0_clk_mux[] = {
2096         HSCK0_MARK,
2097 };
2098 static const unsigned int hscif0_ctrl_pins[] = {
2099         /* RTS, CTS */
2100         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2101 };
2102 static const unsigned int hscif0_ctrl_mux[] = {
2103         HRTS0_N_MARK, HCTS0_N_MARK,
2104 };
2105 /* - HSCIF1 ----------------------------------------------------------------- */
2106 static const unsigned int hscif1_data_a_pins[] = {
2107         /* RX, TX */
2108         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2109 };
2110 static const unsigned int hscif1_data_a_mux[] = {
2111         HRX1_A_MARK, HTX1_A_MARK,
2112 };
2113 static const unsigned int hscif1_clk_a_pins[] = {
2114         /* SCK */
2115         RCAR_GP_PIN(6, 21),
2116 };
2117 static const unsigned int hscif1_clk_a_mux[] = {
2118         HSCK1_A_MARK,
2119 };
2120 static const unsigned int hscif1_ctrl_a_pins[] = {
2121         /* RTS, CTS */
2122         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2123 };
2124 static const unsigned int hscif1_ctrl_a_mux[] = {
2125         HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2126 };
2127
2128 static const unsigned int hscif1_data_b_pins[] = {
2129         /* RX, TX */
2130         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2131 };
2132 static const unsigned int hscif1_data_b_mux[] = {
2133         HRX1_B_MARK, HTX1_B_MARK,
2134 };
2135 static const unsigned int hscif1_clk_b_pins[] = {
2136         /* SCK */
2137         RCAR_GP_PIN(5, 0),
2138 };
2139 static const unsigned int hscif1_clk_b_mux[] = {
2140         HSCK1_B_MARK,
2141 };
2142 static const unsigned int hscif1_ctrl_b_pins[] = {
2143         /* RTS, CTS */
2144         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2145 };
2146 static const unsigned int hscif1_ctrl_b_mux[] = {
2147         HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2148 };
2149 /* - HSCIF2 ----------------------------------------------------------------- */
2150 static const unsigned int hscif2_data_a_pins[] = {
2151         /* RX, TX */
2152         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2153 };
2154 static const unsigned int hscif2_data_a_mux[] = {
2155         HRX2_A_MARK, HTX2_A_MARK,
2156 };
2157 static const unsigned int hscif2_clk_a_pins[] = {
2158         /* SCK */
2159         RCAR_GP_PIN(6, 10),
2160 };
2161 static const unsigned int hscif2_clk_a_mux[] = {
2162         HSCK2_A_MARK,
2163 };
2164 static const unsigned int hscif2_ctrl_a_pins[] = {
2165         /* RTS, CTS */
2166         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2167 };
2168 static const unsigned int hscif2_ctrl_a_mux[] = {
2169         HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2170 };
2171
2172 static const unsigned int hscif2_data_b_pins[] = {
2173         /* RX, TX */
2174         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2175 };
2176 static const unsigned int hscif2_data_b_mux[] = {
2177         HRX2_B_MARK, HTX2_B_MARK,
2178 };
2179 static const unsigned int hscif2_clk_b_pins[] = {
2180         /* SCK */
2181         RCAR_GP_PIN(6, 21),
2182 };
2183 static const unsigned int hscif2_clk_b_mux[] = {
2184         HSCK2_B_MARK,
2185 };
2186 static const unsigned int hscif2_ctrl_b_pins[] = {
2187         /* RTS, CTS */
2188         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2189 };
2190 static const unsigned int hscif2_ctrl_b_mux[] = {
2191         HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2192 };
2193 /* - HSCIF3 ----------------------------------------------------------------- */
2194 static const unsigned int hscif3_data_a_pins[] = {
2195         /* RX, TX */
2196         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2197 };
2198 static const unsigned int hscif3_data_a_mux[] = {
2199         HRX3_A_MARK, HTX3_A_MARK,
2200 };
2201 static const unsigned int hscif3_clk_pins[] = {
2202         /* SCK */
2203         RCAR_GP_PIN(1, 22),
2204 };
2205 static const unsigned int hscif3_clk_mux[] = {
2206         HSCK3_MARK,
2207 };
2208 static const unsigned int hscif3_ctrl_pins[] = {
2209         /* RTS, CTS */
2210         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2211 };
2212 static const unsigned int hscif3_ctrl_mux[] = {
2213         HRTS3_N_MARK, HCTS3_N_MARK,
2214 };
2215
2216 static const unsigned int hscif3_data_b_pins[] = {
2217         /* RX, TX */
2218         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2219 };
2220 static const unsigned int hscif3_data_b_mux[] = {
2221         HRX3_B_MARK, HTX3_B_MARK,
2222 };
2223 static const unsigned int hscif3_data_c_pins[] = {
2224         /* RX, TX */
2225         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2226 };
2227 static const unsigned int hscif3_data_c_mux[] = {
2228         HRX3_C_MARK, HTX3_C_MARK,
2229 };
2230 static const unsigned int hscif3_data_d_pins[] = {
2231         /* RX, TX */
2232         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2233 };
2234 static const unsigned int hscif3_data_d_mux[] = {
2235         HRX3_D_MARK, HTX3_D_MARK,
2236 };
2237 /* - HSCIF4 ----------------------------------------------------------------- */
2238 static const unsigned int hscif4_data_a_pins[] = {
2239         /* RX, TX */
2240         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2241 };
2242 static const unsigned int hscif4_data_a_mux[] = {
2243         HRX4_A_MARK, HTX4_A_MARK,
2244 };
2245 static const unsigned int hscif4_clk_pins[] = {
2246         /* SCK */
2247         RCAR_GP_PIN(1, 11),
2248 };
2249 static const unsigned int hscif4_clk_mux[] = {
2250         HSCK4_MARK,
2251 };
2252 static const unsigned int hscif4_ctrl_pins[] = {
2253         /* RTS, CTS */
2254         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2255 };
2256 static const unsigned int hscif4_ctrl_mux[] = {
2257         HRTS4_N_MARK, HCTS4_N_MARK,
2258 };
2259
2260 static const unsigned int hscif4_data_b_pins[] = {
2261         /* RX, TX */
2262         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2263 };
2264 static const unsigned int hscif4_data_b_mux[] = {
2265         HRX4_B_MARK, HTX4_B_MARK,
2266 };
2267
2268 /* - I2C -------------------------------------------------------------------- */
2269 static const unsigned int i2c1_a_pins[] = {
2270         /* SDA, SCL */
2271         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2272 };
2273 static const unsigned int i2c1_a_mux[] = {
2274         SDA1_A_MARK, SCL1_A_MARK,
2275 };
2276 static const unsigned int i2c1_b_pins[] = {
2277         /* SDA, SCL */
2278         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2279 };
2280 static const unsigned int i2c1_b_mux[] = {
2281         SDA1_B_MARK, SCL1_B_MARK,
2282 };
2283 static const unsigned int i2c2_a_pins[] = {
2284         /* SDA, SCL */
2285         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2286 };
2287 static const unsigned int i2c2_a_mux[] = {
2288         SDA2_A_MARK, SCL2_A_MARK,
2289 };
2290 static const unsigned int i2c2_b_pins[] = {
2291         /* SDA, SCL */
2292         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2293 };
2294 static const unsigned int i2c2_b_mux[] = {
2295         SDA2_B_MARK, SCL2_B_MARK,
2296 };
2297 static const unsigned int i2c6_a_pins[] = {
2298         /* SDA, SCL */
2299         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2300 };
2301 static const unsigned int i2c6_a_mux[] = {
2302         SDA6_A_MARK, SCL6_A_MARK,
2303 };
2304 static const unsigned int i2c6_b_pins[] = {
2305         /* SDA, SCL */
2306         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2307 };
2308 static const unsigned int i2c6_b_mux[] = {
2309         SDA6_B_MARK, SCL6_B_MARK,
2310 };
2311 static const unsigned int i2c6_c_pins[] = {
2312         /* SDA, SCL */
2313         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2314 };
2315 static const unsigned int i2c6_c_mux[] = {
2316         SDA6_C_MARK, SCL6_C_MARK,
2317 };
2318
2319 /* - INTC-EX ---------------------------------------------------------------- */
2320 static const unsigned int intc_ex_irq0_pins[] = {
2321         /* IRQ0 */
2322         RCAR_GP_PIN(2, 0),
2323 };
2324 static const unsigned int intc_ex_irq0_mux[] = {
2325         IRQ0_MARK,
2326 };
2327 static const unsigned int intc_ex_irq1_pins[] = {
2328         /* IRQ1 */
2329         RCAR_GP_PIN(2, 1),
2330 };
2331 static const unsigned int intc_ex_irq1_mux[] = {
2332         IRQ1_MARK,
2333 };
2334 static const unsigned int intc_ex_irq2_pins[] = {
2335         /* IRQ2 */
2336         RCAR_GP_PIN(2, 2),
2337 };
2338 static const unsigned int intc_ex_irq2_mux[] = {
2339         IRQ2_MARK,
2340 };
2341 static const unsigned int intc_ex_irq3_pins[] = {
2342         /* IRQ3 */
2343         RCAR_GP_PIN(2, 3),
2344 };
2345 static const unsigned int intc_ex_irq3_mux[] = {
2346         IRQ3_MARK,
2347 };
2348 static const unsigned int intc_ex_irq4_pins[] = {
2349         /* IRQ4 */
2350         RCAR_GP_PIN(2, 4),
2351 };
2352 static const unsigned int intc_ex_irq4_mux[] = {
2353         IRQ4_MARK,
2354 };
2355 static const unsigned int intc_ex_irq5_pins[] = {
2356         /* IRQ5 */
2357         RCAR_GP_PIN(2, 5),
2358 };
2359 static const unsigned int intc_ex_irq5_mux[] = {
2360         IRQ5_MARK,
2361 };
2362
2363 /* - MSIOF0 ----------------------------------------------------------------- */
2364 static const unsigned int msiof0_clk_pins[] = {
2365         /* SCK */
2366         RCAR_GP_PIN(5, 17),
2367 };
2368 static const unsigned int msiof0_clk_mux[] = {
2369         MSIOF0_SCK_MARK,
2370 };
2371 static const unsigned int msiof0_sync_pins[] = {
2372         /* SYNC */
2373         RCAR_GP_PIN(5, 18),
2374 };
2375 static const unsigned int msiof0_sync_mux[] = {
2376         MSIOF0_SYNC_MARK,
2377 };
2378 static const unsigned int msiof0_ss1_pins[] = {
2379         /* SS1 */
2380         RCAR_GP_PIN(5, 19),
2381 };
2382 static const unsigned int msiof0_ss1_mux[] = {
2383         MSIOF0_SS1_MARK,
2384 };
2385 static const unsigned int msiof0_ss2_pins[] = {
2386         /* SS2 */
2387         RCAR_GP_PIN(5, 21),
2388 };
2389 static const unsigned int msiof0_ss2_mux[] = {
2390         MSIOF0_SS2_MARK,
2391 };
2392 static const unsigned int msiof0_txd_pins[] = {
2393         /* TXD */
2394         RCAR_GP_PIN(5, 20),
2395 };
2396 static const unsigned int msiof0_txd_mux[] = {
2397         MSIOF0_TXD_MARK,
2398 };
2399 static const unsigned int msiof0_rxd_pins[] = {
2400         /* RXD */
2401         RCAR_GP_PIN(5, 22),
2402 };
2403 static const unsigned int msiof0_rxd_mux[] = {
2404         MSIOF0_RXD_MARK,
2405 };
2406 /* - MSIOF1 ----------------------------------------------------------------- */
2407 static const unsigned int msiof1_clk_a_pins[] = {
2408         /* SCK */
2409         RCAR_GP_PIN(6, 8),
2410 };
2411 static const unsigned int msiof1_clk_a_mux[] = {
2412         MSIOF1_SCK_A_MARK,
2413 };
2414 static const unsigned int msiof1_sync_a_pins[] = {
2415         /* SYNC */
2416         RCAR_GP_PIN(6, 9),
2417 };
2418 static const unsigned int msiof1_sync_a_mux[] = {
2419         MSIOF1_SYNC_A_MARK,
2420 };
2421 static const unsigned int msiof1_ss1_a_pins[] = {
2422         /* SS1 */
2423         RCAR_GP_PIN(6, 5),
2424 };
2425 static const unsigned int msiof1_ss1_a_mux[] = {
2426         MSIOF1_SS1_A_MARK,
2427 };
2428 static const unsigned int msiof1_ss2_a_pins[] = {
2429         /* SS2 */
2430         RCAR_GP_PIN(6, 6),
2431 };
2432 static const unsigned int msiof1_ss2_a_mux[] = {
2433         MSIOF1_SS2_A_MARK,
2434 };
2435 static const unsigned int msiof1_txd_a_pins[] = {
2436         /* TXD */
2437         RCAR_GP_PIN(6, 7),
2438 };
2439 static const unsigned int msiof1_txd_a_mux[] = {
2440         MSIOF1_TXD_A_MARK,
2441 };
2442 static const unsigned int msiof1_rxd_a_pins[] = {
2443         /* RXD */
2444         RCAR_GP_PIN(6, 10),
2445 };
2446 static const unsigned int msiof1_rxd_a_mux[] = {
2447         MSIOF1_RXD_A_MARK,
2448 };
2449 static const unsigned int msiof1_clk_b_pins[] = {
2450         /* SCK */
2451         RCAR_GP_PIN(5, 9),
2452 };
2453 static const unsigned int msiof1_clk_b_mux[] = {
2454         MSIOF1_SCK_B_MARK,
2455 };
2456 static const unsigned int msiof1_sync_b_pins[] = {
2457         /* SYNC */
2458         RCAR_GP_PIN(5, 3),
2459 };
2460 static const unsigned int msiof1_sync_b_mux[] = {
2461         MSIOF1_SYNC_B_MARK,
2462 };
2463 static const unsigned int msiof1_ss1_b_pins[] = {
2464         /* SS1 */
2465         RCAR_GP_PIN(5, 4),
2466 };
2467 static const unsigned int msiof1_ss1_b_mux[] = {
2468         MSIOF1_SS1_B_MARK,
2469 };
2470 static const unsigned int msiof1_ss2_b_pins[] = {
2471         /* SS2 */
2472         RCAR_GP_PIN(5, 0),
2473 };
2474 static const unsigned int msiof1_ss2_b_mux[] = {
2475         MSIOF1_SS2_B_MARK,
2476 };
2477 static const unsigned int msiof1_txd_b_pins[] = {
2478         /* TXD */
2479         RCAR_GP_PIN(5, 8),
2480 };
2481 static const unsigned int msiof1_txd_b_mux[] = {
2482         MSIOF1_TXD_B_MARK,
2483 };
2484 static const unsigned int msiof1_rxd_b_pins[] = {
2485         /* RXD */
2486         RCAR_GP_PIN(5, 7),
2487 };
2488 static const unsigned int msiof1_rxd_b_mux[] = {
2489         MSIOF1_RXD_B_MARK,
2490 };
2491 static const unsigned int msiof1_clk_c_pins[] = {
2492         /* SCK */
2493         RCAR_GP_PIN(6, 17),
2494 };
2495 static const unsigned int msiof1_clk_c_mux[] = {
2496         MSIOF1_SCK_C_MARK,
2497 };
2498 static const unsigned int msiof1_sync_c_pins[] = {
2499         /* SYNC */
2500         RCAR_GP_PIN(6, 18),
2501 };
2502 static const unsigned int msiof1_sync_c_mux[] = {
2503         MSIOF1_SYNC_C_MARK,
2504 };
2505 static const unsigned int msiof1_ss1_c_pins[] = {
2506         /* SS1 */
2507         RCAR_GP_PIN(6, 21),
2508 };
2509 static const unsigned int msiof1_ss1_c_mux[] = {
2510         MSIOF1_SS1_C_MARK,
2511 };
2512 static const unsigned int msiof1_ss2_c_pins[] = {
2513         /* SS2 */
2514         RCAR_GP_PIN(6, 27),
2515 };
2516 static const unsigned int msiof1_ss2_c_mux[] = {
2517         MSIOF1_SS2_C_MARK,
2518 };
2519 static const unsigned int msiof1_txd_c_pins[] = {
2520         /* TXD */
2521         RCAR_GP_PIN(6, 20),
2522 };
2523 static const unsigned int msiof1_txd_c_mux[] = {
2524         MSIOF1_TXD_C_MARK,
2525 };
2526 static const unsigned int msiof1_rxd_c_pins[] = {
2527         /* RXD */
2528         RCAR_GP_PIN(6, 19),
2529 };
2530 static const unsigned int msiof1_rxd_c_mux[] = {
2531         MSIOF1_RXD_C_MARK,
2532 };
2533 static const unsigned int msiof1_clk_d_pins[] = {
2534         /* SCK */
2535         RCAR_GP_PIN(5, 12),
2536 };
2537 static const unsigned int msiof1_clk_d_mux[] = {
2538         MSIOF1_SCK_D_MARK,
2539 };
2540 static const unsigned int msiof1_sync_d_pins[] = {
2541         /* SYNC */
2542         RCAR_GP_PIN(5, 15),
2543 };
2544 static const unsigned int msiof1_sync_d_mux[] = {
2545         MSIOF1_SYNC_D_MARK,
2546 };
2547 static const unsigned int msiof1_ss1_d_pins[] = {
2548         /* SS1 */
2549         RCAR_GP_PIN(5, 16),
2550 };
2551 static const unsigned int msiof1_ss1_d_mux[] = {
2552         MSIOF1_SS1_D_MARK,
2553 };
2554 static const unsigned int msiof1_ss2_d_pins[] = {
2555         /* SS2 */
2556         RCAR_GP_PIN(5, 21),
2557 };
2558 static const unsigned int msiof1_ss2_d_mux[] = {
2559         MSIOF1_SS2_D_MARK,
2560 };
2561 static const unsigned int msiof1_txd_d_pins[] = {
2562         /* TXD */
2563         RCAR_GP_PIN(5, 14),
2564 };
2565 static const unsigned int msiof1_txd_d_mux[] = {
2566         MSIOF1_TXD_D_MARK,
2567 };
2568 static const unsigned int msiof1_rxd_d_pins[] = {
2569         /* RXD */
2570         RCAR_GP_PIN(5, 13),
2571 };
2572 static const unsigned int msiof1_rxd_d_mux[] = {
2573         MSIOF1_RXD_D_MARK,
2574 };
2575 static const unsigned int msiof1_clk_e_pins[] = {
2576         /* SCK */
2577         RCAR_GP_PIN(3, 0),
2578 };
2579 static const unsigned int msiof1_clk_e_mux[] = {
2580         MSIOF1_SCK_E_MARK,
2581 };
2582 static const unsigned int msiof1_sync_e_pins[] = {
2583         /* SYNC */
2584         RCAR_GP_PIN(3, 1),
2585 };
2586 static const unsigned int msiof1_sync_e_mux[] = {
2587         MSIOF1_SYNC_E_MARK,
2588 };
2589 static const unsigned int msiof1_ss1_e_pins[] = {
2590         /* SS1 */
2591         RCAR_GP_PIN(3, 4),
2592 };
2593 static const unsigned int msiof1_ss1_e_mux[] = {
2594         MSIOF1_SS1_E_MARK,
2595 };
2596 static const unsigned int msiof1_ss2_e_pins[] = {
2597         /* SS2 */
2598         RCAR_GP_PIN(3, 5),
2599 };
2600 static const unsigned int msiof1_ss2_e_mux[] = {
2601         MSIOF1_SS2_E_MARK,
2602 };
2603 static const unsigned int msiof1_txd_e_pins[] = {
2604         /* TXD */
2605         RCAR_GP_PIN(3, 3),
2606 };
2607 static const unsigned int msiof1_txd_e_mux[] = {
2608         MSIOF1_TXD_E_MARK,
2609 };
2610 static const unsigned int msiof1_rxd_e_pins[] = {
2611         /* RXD */
2612         RCAR_GP_PIN(3, 2),
2613 };
2614 static const unsigned int msiof1_rxd_e_mux[] = {
2615         MSIOF1_RXD_E_MARK,
2616 };
2617 static const unsigned int msiof1_clk_f_pins[] = {
2618         /* SCK */
2619         RCAR_GP_PIN(5, 23),
2620 };
2621 static const unsigned int msiof1_clk_f_mux[] = {
2622         MSIOF1_SCK_F_MARK,
2623 };
2624 static const unsigned int msiof1_sync_f_pins[] = {
2625         /* SYNC */
2626         RCAR_GP_PIN(5, 24),
2627 };
2628 static const unsigned int msiof1_sync_f_mux[] = {
2629         MSIOF1_SYNC_F_MARK,
2630 };
2631 static const unsigned int msiof1_ss1_f_pins[] = {
2632         /* SS1 */
2633         RCAR_GP_PIN(6, 1),
2634 };
2635 static const unsigned int msiof1_ss1_f_mux[] = {
2636         MSIOF1_SS1_F_MARK,
2637 };
2638 static const unsigned int msiof1_ss2_f_pins[] = {
2639         /* SS2 */
2640         RCAR_GP_PIN(6, 2),
2641 };
2642 static const unsigned int msiof1_ss2_f_mux[] = {
2643         MSIOF1_SS2_F_MARK,
2644 };
2645 static const unsigned int msiof1_txd_f_pins[] = {
2646         /* TXD */
2647         RCAR_GP_PIN(6, 0),
2648 };
2649 static const unsigned int msiof1_txd_f_mux[] = {
2650         MSIOF1_TXD_F_MARK,
2651 };
2652 static const unsigned int msiof1_rxd_f_pins[] = {
2653         /* RXD */
2654         RCAR_GP_PIN(5, 25),
2655 };
2656 static const unsigned int msiof1_rxd_f_mux[] = {
2657         MSIOF1_RXD_F_MARK,
2658 };
2659 static const unsigned int msiof1_clk_g_pins[] = {
2660         /* SCK */
2661         RCAR_GP_PIN(3, 6),
2662 };
2663 static const unsigned int msiof1_clk_g_mux[] = {
2664         MSIOF1_SCK_G_MARK,
2665 };
2666 static const unsigned int msiof1_sync_g_pins[] = {
2667         /* SYNC */
2668         RCAR_GP_PIN(3, 7),
2669 };
2670 static const unsigned int msiof1_sync_g_mux[] = {
2671         MSIOF1_SYNC_G_MARK,
2672 };
2673 static const unsigned int msiof1_ss1_g_pins[] = {
2674         /* SS1 */
2675         RCAR_GP_PIN(3, 10),
2676 };
2677 static const unsigned int msiof1_ss1_g_mux[] = {
2678         MSIOF1_SS1_G_MARK,
2679 };
2680 static const unsigned int msiof1_ss2_g_pins[] = {
2681         /* SS2 */
2682         RCAR_GP_PIN(3, 11),
2683 };
2684 static const unsigned int msiof1_ss2_g_mux[] = {
2685         MSIOF1_SS2_G_MARK,
2686 };
2687 static const unsigned int msiof1_txd_g_pins[] = {
2688         /* TXD */
2689         RCAR_GP_PIN(3, 9),
2690 };
2691 static const unsigned int msiof1_txd_g_mux[] = {
2692         MSIOF1_TXD_G_MARK,
2693 };
2694 static const unsigned int msiof1_rxd_g_pins[] = {
2695         /* RXD */
2696         RCAR_GP_PIN(3, 8),
2697 };
2698 static const unsigned int msiof1_rxd_g_mux[] = {
2699         MSIOF1_RXD_G_MARK,
2700 };
2701 /* - MSIOF2 ----------------------------------------------------------------- */
2702 static const unsigned int msiof2_clk_a_pins[] = {
2703         /* SCK */
2704         RCAR_GP_PIN(1, 9),
2705 };
2706 static const unsigned int msiof2_clk_a_mux[] = {
2707         MSIOF2_SCK_A_MARK,
2708 };
2709 static const unsigned int msiof2_sync_a_pins[] = {
2710         /* SYNC */
2711         RCAR_GP_PIN(1, 8),
2712 };
2713 static const unsigned int msiof2_sync_a_mux[] = {
2714         MSIOF2_SYNC_A_MARK,
2715 };
2716 static const unsigned int msiof2_ss1_a_pins[] = {
2717         /* SS1 */
2718         RCAR_GP_PIN(1, 6),
2719 };
2720 static const unsigned int msiof2_ss1_a_mux[] = {
2721         MSIOF2_SS1_A_MARK,
2722 };
2723 static const unsigned int msiof2_ss2_a_pins[] = {
2724         /* SS2 */
2725         RCAR_GP_PIN(1, 7),
2726 };
2727 static const unsigned int msiof2_ss2_a_mux[] = {
2728         MSIOF2_SS2_A_MARK,
2729 };
2730 static const unsigned int msiof2_txd_a_pins[] = {
2731         /* TXD */
2732         RCAR_GP_PIN(1, 11),
2733 };
2734 static const unsigned int msiof2_txd_a_mux[] = {
2735         MSIOF2_TXD_A_MARK,
2736 };
2737 static const unsigned int msiof2_rxd_a_pins[] = {
2738         /* RXD */
2739         RCAR_GP_PIN(1, 10),
2740 };
2741 static const unsigned int msiof2_rxd_a_mux[] = {
2742         MSIOF2_RXD_A_MARK,
2743 };
2744 static const unsigned int msiof2_clk_b_pins[] = {
2745         /* SCK */
2746         RCAR_GP_PIN(0, 4),
2747 };
2748 static const unsigned int msiof2_clk_b_mux[] = {
2749         MSIOF2_SCK_B_MARK,
2750 };
2751 static const unsigned int msiof2_sync_b_pins[] = {
2752         /* SYNC */
2753         RCAR_GP_PIN(0, 5),
2754 };
2755 static const unsigned int msiof2_sync_b_mux[] = {
2756         MSIOF2_SYNC_B_MARK,
2757 };
2758 static const unsigned int msiof2_ss1_b_pins[] = {
2759         /* SS1 */
2760         RCAR_GP_PIN(0, 0),
2761 };
2762 static const unsigned int msiof2_ss1_b_mux[] = {
2763         MSIOF2_SS1_B_MARK,
2764 };
2765 static const unsigned int msiof2_ss2_b_pins[] = {
2766         /* SS2 */
2767         RCAR_GP_PIN(0, 1),
2768 };
2769 static const unsigned int msiof2_ss2_b_mux[] = {
2770         MSIOF2_SS2_B_MARK,
2771 };
2772 static const unsigned int msiof2_txd_b_pins[] = {
2773         /* TXD */
2774         RCAR_GP_PIN(0, 7),
2775 };
2776 static const unsigned int msiof2_txd_b_mux[] = {
2777         MSIOF2_TXD_B_MARK,
2778 };
2779 static const unsigned int msiof2_rxd_b_pins[] = {
2780         /* RXD */
2781         RCAR_GP_PIN(0, 6),
2782 };
2783 static const unsigned int msiof2_rxd_b_mux[] = {
2784         MSIOF2_RXD_B_MARK,
2785 };
2786 static const unsigned int msiof2_clk_c_pins[] = {
2787         /* SCK */
2788         RCAR_GP_PIN(2, 12),
2789 };
2790 static const unsigned int msiof2_clk_c_mux[] = {
2791         MSIOF2_SCK_C_MARK,
2792 };
2793 static const unsigned int msiof2_sync_c_pins[] = {
2794         /* SYNC */
2795         RCAR_GP_PIN(2, 11),
2796 };
2797 static const unsigned int msiof2_sync_c_mux[] = {
2798         MSIOF2_SYNC_C_MARK,
2799 };
2800 static const unsigned int msiof2_ss1_c_pins[] = {
2801         /* SS1 */
2802         RCAR_GP_PIN(2, 10),
2803 };
2804 static const unsigned int msiof2_ss1_c_mux[] = {
2805         MSIOF2_SS1_C_MARK,
2806 };
2807 static const unsigned int msiof2_ss2_c_pins[] = {
2808         /* SS2 */
2809         RCAR_GP_PIN(2, 9),
2810 };
2811 static const unsigned int msiof2_ss2_c_mux[] = {
2812         MSIOF2_SS2_C_MARK,
2813 };
2814 static const unsigned int msiof2_txd_c_pins[] = {
2815         /* TXD */
2816         RCAR_GP_PIN(2, 14),
2817 };
2818 static const unsigned int msiof2_txd_c_mux[] = {
2819         MSIOF2_TXD_C_MARK,
2820 };
2821 static const unsigned int msiof2_rxd_c_pins[] = {
2822         /* RXD */
2823         RCAR_GP_PIN(2, 13),
2824 };
2825 static const unsigned int msiof2_rxd_c_mux[] = {
2826         MSIOF2_RXD_C_MARK,
2827 };
2828 static const unsigned int msiof2_clk_d_pins[] = {
2829         /* SCK */
2830         RCAR_GP_PIN(0, 8),
2831 };
2832 static const unsigned int msiof2_clk_d_mux[] = {
2833         MSIOF2_SCK_D_MARK,
2834 };
2835 static const unsigned int msiof2_sync_d_pins[] = {
2836         /* SYNC */
2837         RCAR_GP_PIN(0, 9),
2838 };
2839 static const unsigned int msiof2_sync_d_mux[] = {
2840         MSIOF2_SYNC_D_MARK,
2841 };
2842 static const unsigned int msiof2_ss1_d_pins[] = {
2843         /* SS1 */
2844         RCAR_GP_PIN(0, 12),
2845 };
2846 static const unsigned int msiof2_ss1_d_mux[] = {
2847         MSIOF2_SS1_D_MARK,
2848 };
2849 static const unsigned int msiof2_ss2_d_pins[] = {
2850         /* SS2 */
2851         RCAR_GP_PIN(0, 13),
2852 };
2853 static const unsigned int msiof2_ss2_d_mux[] = {
2854         MSIOF2_SS2_D_MARK,
2855 };
2856 static const unsigned int msiof2_txd_d_pins[] = {
2857         /* TXD */
2858         RCAR_GP_PIN(0, 11),
2859 };
2860 static const unsigned int msiof2_txd_d_mux[] = {
2861         MSIOF2_TXD_D_MARK,
2862 };
2863 static const unsigned int msiof2_rxd_d_pins[] = {
2864         /* RXD */
2865         RCAR_GP_PIN(0, 10),
2866 };
2867 static const unsigned int msiof2_rxd_d_mux[] = {
2868         MSIOF2_RXD_D_MARK,
2869 };
2870 /* - MSIOF3 ----------------------------------------------------------------- */
2871 static const unsigned int msiof3_clk_a_pins[] = {
2872         /* SCK */
2873         RCAR_GP_PIN(0, 0),
2874 };
2875 static const unsigned int msiof3_clk_a_mux[] = {
2876         MSIOF3_SCK_A_MARK,
2877 };
2878 static const unsigned int msiof3_sync_a_pins[] = {
2879         /* SYNC */
2880         RCAR_GP_PIN(0, 1),
2881 };
2882 static const unsigned int msiof3_sync_a_mux[] = {
2883         MSIOF3_SYNC_A_MARK,
2884 };
2885 static const unsigned int msiof3_ss1_a_pins[] = {
2886         /* SS1 */
2887         RCAR_GP_PIN(0, 14),
2888 };
2889 static const unsigned int msiof3_ss1_a_mux[] = {
2890         MSIOF3_SS1_A_MARK,
2891 };
2892 static const unsigned int msiof3_ss2_a_pins[] = {
2893         /* SS2 */
2894         RCAR_GP_PIN(0, 15),
2895 };
2896 static const unsigned int msiof3_ss2_a_mux[] = {
2897         MSIOF3_SS2_A_MARK,
2898 };
2899 static const unsigned int msiof3_txd_a_pins[] = {
2900         /* TXD */
2901         RCAR_GP_PIN(0, 3),
2902 };
2903 static const unsigned int msiof3_txd_a_mux[] = {
2904         MSIOF3_TXD_A_MARK,
2905 };
2906 static const unsigned int msiof3_rxd_a_pins[] = {
2907         /* RXD */
2908         RCAR_GP_PIN(0, 2),
2909 };
2910 static const unsigned int msiof3_rxd_a_mux[] = {
2911         MSIOF3_RXD_A_MARK,
2912 };
2913 static const unsigned int msiof3_clk_b_pins[] = {
2914         /* SCK */
2915         RCAR_GP_PIN(1, 2),
2916 };
2917 static const unsigned int msiof3_clk_b_mux[] = {
2918         MSIOF3_SCK_B_MARK,
2919 };
2920 static const unsigned int msiof3_sync_b_pins[] = {
2921         /* SYNC */
2922         RCAR_GP_PIN(1, 0),
2923 };
2924 static const unsigned int msiof3_sync_b_mux[] = {
2925         MSIOF3_SYNC_B_MARK,
2926 };
2927 static const unsigned int msiof3_ss1_b_pins[] = {
2928         /* SS1 */
2929         RCAR_GP_PIN(1, 4),
2930 };
2931 static const unsigned int msiof3_ss1_b_mux[] = {
2932         MSIOF3_SS1_B_MARK,
2933 };
2934 static const unsigned int msiof3_ss2_b_pins[] = {
2935         /* SS2 */
2936         RCAR_GP_PIN(1, 5),
2937 };
2938 static const unsigned int msiof3_ss2_b_mux[] = {
2939         MSIOF3_SS2_B_MARK,
2940 };
2941 static const unsigned int msiof3_txd_b_pins[] = {
2942         /* TXD */
2943         RCAR_GP_PIN(1, 1),
2944 };
2945 static const unsigned int msiof3_txd_b_mux[] = {
2946         MSIOF3_TXD_B_MARK,
2947 };
2948 static const unsigned int msiof3_rxd_b_pins[] = {
2949         /* RXD */
2950         RCAR_GP_PIN(1, 3),
2951 };
2952 static const unsigned int msiof3_rxd_b_mux[] = {
2953         MSIOF3_RXD_B_MARK,
2954 };
2955 static const unsigned int msiof3_clk_c_pins[] = {
2956         /* SCK */
2957         RCAR_GP_PIN(1, 12),
2958 };
2959 static const unsigned int msiof3_clk_c_mux[] = {
2960         MSIOF3_SCK_C_MARK,
2961 };
2962 static const unsigned int msiof3_sync_c_pins[] = {
2963         /* SYNC */
2964         RCAR_GP_PIN(1, 13),
2965 };
2966 static const unsigned int msiof3_sync_c_mux[] = {
2967         MSIOF3_SYNC_C_MARK,
2968 };
2969 static const unsigned int msiof3_txd_c_pins[] = {
2970         /* TXD */
2971         RCAR_GP_PIN(1, 15),
2972 };
2973 static const unsigned int msiof3_txd_c_mux[] = {
2974         MSIOF3_TXD_C_MARK,
2975 };
2976 static const unsigned int msiof3_rxd_c_pins[] = {
2977         /* RXD */
2978         RCAR_GP_PIN(1, 14),
2979 };
2980 static const unsigned int msiof3_rxd_c_mux[] = {
2981         MSIOF3_RXD_C_MARK,
2982 };
2983 static const unsigned int msiof3_clk_d_pins[] = {
2984         /* SCK */
2985         RCAR_GP_PIN(1, 22),
2986 };
2987 static const unsigned int msiof3_clk_d_mux[] = {
2988         MSIOF3_SCK_D_MARK,
2989 };
2990 static const unsigned int msiof3_sync_d_pins[] = {
2991         /* SYNC */
2992         RCAR_GP_PIN(1, 23),
2993 };
2994 static const unsigned int msiof3_sync_d_mux[] = {
2995         MSIOF3_SYNC_D_MARK,
2996 };
2997 static const unsigned int msiof3_ss1_d_pins[] = {
2998         /* SS1 */
2999         RCAR_GP_PIN(1, 26),
3000 };
3001 static const unsigned int msiof3_ss1_d_mux[] = {
3002         MSIOF3_SS1_D_MARK,
3003 };
3004 static const unsigned int msiof3_txd_d_pins[] = {
3005         /* TXD */
3006         RCAR_GP_PIN(1, 25),
3007 };
3008 static const unsigned int msiof3_txd_d_mux[] = {
3009         MSIOF3_TXD_D_MARK,
3010 };
3011 static const unsigned int msiof3_rxd_d_pins[] = {
3012         /* RXD */
3013         RCAR_GP_PIN(1, 24),
3014 };
3015 static const unsigned int msiof3_rxd_d_mux[] = {
3016         MSIOF3_RXD_D_MARK,
3017 };
3018
3019 /* - PWM0 --------------------------------------------------------------------*/
3020 static const unsigned int pwm0_pins[] = {
3021         /* PWM */
3022         RCAR_GP_PIN(2, 6),
3023 };
3024 static const unsigned int pwm0_mux[] = {
3025         PWM0_MARK,
3026 };
3027 /* - PWM1 --------------------------------------------------------------------*/
3028 static const unsigned int pwm1_a_pins[] = {
3029         /* PWM */
3030         RCAR_GP_PIN(2, 7),
3031 };
3032 static const unsigned int pwm1_a_mux[] = {
3033         PWM1_A_MARK,
3034 };
3035 static const unsigned int pwm1_b_pins[] = {
3036         /* PWM */
3037         RCAR_GP_PIN(1, 8),
3038 };
3039 static const unsigned int pwm1_b_mux[] = {
3040         PWM1_B_MARK,
3041 };
3042 /* - PWM2 --------------------------------------------------------------------*/
3043 static const unsigned int pwm2_a_pins[] = {
3044         /* PWM */
3045         RCAR_GP_PIN(2, 8),
3046 };
3047 static const unsigned int pwm2_a_mux[] = {
3048         PWM2_A_MARK,
3049 };
3050 static const unsigned int pwm2_b_pins[] = {
3051         /* PWM */
3052         RCAR_GP_PIN(1, 11),
3053 };
3054 static const unsigned int pwm2_b_mux[] = {
3055         PWM2_B_MARK,
3056 };
3057 /* - PWM3 --------------------------------------------------------------------*/
3058 static const unsigned int pwm3_a_pins[] = {
3059         /* PWM */
3060         RCAR_GP_PIN(1, 0),
3061 };
3062 static const unsigned int pwm3_a_mux[] = {
3063         PWM3_A_MARK,
3064 };
3065 static const unsigned int pwm3_b_pins[] = {
3066         /* PWM */
3067         RCAR_GP_PIN(2, 2),
3068 };
3069 static const unsigned int pwm3_b_mux[] = {
3070         PWM3_B_MARK,
3071 };
3072 /* - PWM4 --------------------------------------------------------------------*/
3073 static const unsigned int pwm4_a_pins[] = {
3074         /* PWM */
3075         RCAR_GP_PIN(1, 1),
3076 };
3077 static const unsigned int pwm4_a_mux[] = {
3078         PWM4_A_MARK,
3079 };
3080 static const unsigned int pwm4_b_pins[] = {
3081         /* PWM */
3082         RCAR_GP_PIN(2, 3),
3083 };
3084 static const unsigned int pwm4_b_mux[] = {
3085         PWM4_B_MARK,
3086 };
3087 /* - PWM5 --------------------------------------------------------------------*/
3088 static const unsigned int pwm5_a_pins[] = {
3089         /* PWM */
3090         RCAR_GP_PIN(1, 2),
3091 };
3092 static const unsigned int pwm5_a_mux[] = {
3093         PWM5_A_MARK,
3094 };
3095 static const unsigned int pwm5_b_pins[] = {
3096         /* PWM */
3097         RCAR_GP_PIN(2, 4),
3098 };
3099 static const unsigned int pwm5_b_mux[] = {
3100         PWM5_B_MARK,
3101 };
3102 /* - PWM6 --------------------------------------------------------------------*/
3103 static const unsigned int pwm6_a_pins[] = {
3104         /* PWM */
3105         RCAR_GP_PIN(1, 3),
3106 };
3107 static const unsigned int pwm6_a_mux[] = {
3108         PWM6_A_MARK,
3109 };
3110 static const unsigned int pwm6_b_pins[] = {
3111         /* PWM */
3112         RCAR_GP_PIN(2, 5),
3113 };
3114 static const unsigned int pwm6_b_mux[] = {
3115         PWM6_B_MARK,
3116 };
3117
3118 /* - QSPI0 ------------------------------------------------------------------ */
3119 static const unsigned int qspi0_ctrl_pins[] = {
3120         /* QSPI0_SPCLK, QSPI0_SSL */
3121         PIN_NUMBER('W', 3), PIN_NUMBER('Y', 3),
3122 };
3123 static const unsigned int qspi0_ctrl_mux[] = {
3124         QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3125 };
3126 static const unsigned int qspi0_data2_pins[] = {
3127         /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3128         PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4),
3129 };
3130 static const unsigned int qspi0_data2_mux[] = {
3131         QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3132 };
3133 static const unsigned int qspi0_data4_pins[] = {
3134         /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */
3135         PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4),
3136         PIN_NUMBER('Y', 6), PIN_A_NUMBER('B', 6),
3137 };
3138 static const unsigned int qspi0_data4_mux[] = {
3139         QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3140         QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3141 };
3142 /* - QSPI1 ------------------------------------------------------------------ */
3143 static const unsigned int qspi1_ctrl_pins[] = {
3144         /* QSPI1_SPCLK, QSPI1_SSL */
3145         PIN_NUMBER('V', 3), PIN_NUMBER('V', 5),
3146 };
3147 static const unsigned int qspi1_ctrl_mux[] = {
3148         QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3149 };
3150 static const unsigned int qspi1_data2_pins[] = {
3151         /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3152         PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5),
3153 };
3154 static const unsigned int qspi1_data2_mux[] = {
3155         QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3156 };
3157 static const unsigned int qspi1_data4_pins[] = {
3158         /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */
3159         PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5),
3160         PIN_A_NUMBER('E', 4), PIN_A_NUMBER('C', 3),
3161 };
3162 static const unsigned int qspi1_data4_mux[] = {
3163         QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3164         QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3165 };
3166
3167 /* - SATA --------------------------------------------------------------------*/
3168 static const unsigned int sata0_devslp_a_pins[] = {
3169         /* DEVSLP */
3170         RCAR_GP_PIN(6, 16),
3171 };
3172 static const unsigned int sata0_devslp_a_mux[] = {
3173         SATA_DEVSLP_A_MARK,
3174 };
3175 static const unsigned int sata0_devslp_b_pins[] = {
3176         /* DEVSLP */
3177         RCAR_GP_PIN(4, 6),
3178 };
3179 static const unsigned int sata0_devslp_b_mux[] = {
3180         SATA_DEVSLP_B_MARK,
3181 };
3182
3183 /* - SCIF0 ------------------------------------------------------------------ */
3184 static const unsigned int scif0_data_pins[] = {
3185         /* RX, TX */
3186         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3187 };
3188 static const unsigned int scif0_data_mux[] = {
3189         RX0_MARK, TX0_MARK,
3190 };
3191 static const unsigned int scif0_clk_pins[] = {
3192         /* SCK */
3193         RCAR_GP_PIN(5, 0),
3194 };
3195 static const unsigned int scif0_clk_mux[] = {
3196         SCK0_MARK,
3197 };
3198 static const unsigned int scif0_ctrl_pins[] = {
3199         /* RTS, CTS */
3200         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3201 };
3202 static const unsigned int scif0_ctrl_mux[] = {
3203         RTS0_N_TANS_MARK, CTS0_N_MARK,
3204 };
3205 /* - SCIF1 ------------------------------------------------------------------ */
3206 static const unsigned int scif1_data_a_pins[] = {
3207         /* RX, TX */
3208         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3209 };
3210 static const unsigned int scif1_data_a_mux[] = {
3211         RX1_A_MARK, TX1_A_MARK,
3212 };
3213 static const unsigned int scif1_clk_pins[] = {
3214         /* SCK */
3215         RCAR_GP_PIN(6, 21),
3216 };
3217 static const unsigned int scif1_clk_mux[] = {
3218         SCK1_MARK,
3219 };
3220 static const unsigned int scif1_ctrl_pins[] = {
3221         /* RTS, CTS */
3222         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3223 };
3224 static const unsigned int scif1_ctrl_mux[] = {
3225         RTS1_N_TANS_MARK, CTS1_N_MARK,
3226 };
3227
3228 static const unsigned int scif1_data_b_pins[] = {
3229         /* RX, TX */
3230         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3231 };
3232 static const unsigned int scif1_data_b_mux[] = {
3233         RX1_B_MARK, TX1_B_MARK,
3234 };
3235 /* - SCIF2 ------------------------------------------------------------------ */
3236 static const unsigned int scif2_data_a_pins[] = {
3237         /* RX, TX */
3238         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3239 };
3240 static const unsigned int scif2_data_a_mux[] = {
3241         RX2_A_MARK, TX2_A_MARK,
3242 };
3243 static const unsigned int scif2_clk_pins[] = {
3244         /* SCK */
3245         RCAR_GP_PIN(5, 9),
3246 };
3247 static const unsigned int scif2_clk_mux[] = {
3248         SCK2_MARK,
3249 };
3250 static const unsigned int scif2_data_b_pins[] = {
3251         /* RX, TX */
3252         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3253 };
3254 static const unsigned int scif2_data_b_mux[] = {
3255         RX2_B_MARK, TX2_B_MARK,
3256 };
3257 /* - SCIF3 ------------------------------------------------------------------ */
3258 static const unsigned int scif3_data_a_pins[] = {
3259         /* RX, TX */
3260         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3261 };
3262 static const unsigned int scif3_data_a_mux[] = {
3263         RX3_A_MARK, TX3_A_MARK,
3264 };
3265 static const unsigned int scif3_clk_pins[] = {
3266         /* SCK */
3267         RCAR_GP_PIN(1, 22),
3268 };
3269 static const unsigned int scif3_clk_mux[] = {
3270         SCK3_MARK,
3271 };
3272 static const unsigned int scif3_ctrl_pins[] = {
3273         /* RTS, CTS */
3274         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3275 };
3276 static const unsigned int scif3_ctrl_mux[] = {
3277         RTS3_N_TANS_MARK, CTS3_N_MARK,
3278 };
3279 static const unsigned int scif3_data_b_pins[] = {
3280         /* RX, TX */
3281         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3282 };
3283 static const unsigned int scif3_data_b_mux[] = {
3284         RX3_B_MARK, TX3_B_MARK,
3285 };
3286 /* - SCIF4 ------------------------------------------------------------------ */
3287 static const unsigned int scif4_data_a_pins[] = {
3288         /* RX, TX */
3289         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3290 };
3291 static const unsigned int scif4_data_a_mux[] = {
3292         RX4_A_MARK, TX4_A_MARK,
3293 };
3294 static const unsigned int scif4_clk_a_pins[] = {
3295         /* SCK */
3296         RCAR_GP_PIN(2, 10),
3297 };
3298 static const unsigned int scif4_clk_a_mux[] = {
3299         SCK4_A_MARK,
3300 };
3301 static const unsigned int scif4_ctrl_a_pins[] = {
3302         /* RTS, CTS */
3303         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3304 };
3305 static const unsigned int scif4_ctrl_a_mux[] = {
3306         RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
3307 };
3308 static const unsigned int scif4_data_b_pins[] = {
3309         /* RX, TX */
3310         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3311 };
3312 static const unsigned int scif4_data_b_mux[] = {
3313         RX4_B_MARK, TX4_B_MARK,
3314 };
3315 static const unsigned int scif4_clk_b_pins[] = {
3316         /* SCK */
3317         RCAR_GP_PIN(1, 5),
3318 };
3319 static const unsigned int scif4_clk_b_mux[] = {
3320         SCK4_B_MARK,
3321 };
3322 static const unsigned int scif4_ctrl_b_pins[] = {
3323         /* RTS, CTS */
3324         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3325 };
3326 static const unsigned int scif4_ctrl_b_mux[] = {
3327         RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
3328 };
3329 static const unsigned int scif4_data_c_pins[] = {
3330         /* RX, TX */
3331         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3332 };
3333 static const unsigned int scif4_data_c_mux[] = {
3334         RX4_C_MARK, TX4_C_MARK,
3335 };
3336 static const unsigned int scif4_clk_c_pins[] = {
3337         /* SCK */
3338         RCAR_GP_PIN(0, 8),
3339 };
3340 static const unsigned int scif4_clk_c_mux[] = {
3341         SCK4_C_MARK,
3342 };
3343 static const unsigned int scif4_ctrl_c_pins[] = {
3344         /* RTS, CTS */
3345         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3346 };
3347 static const unsigned int scif4_ctrl_c_mux[] = {
3348         RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
3349 };
3350 /* - SCIF5 ------------------------------------------------------------------ */
3351 static const unsigned int scif5_data_pins[] = {
3352         /* RX, TX */
3353         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3354 };
3355 static const unsigned int scif5_data_mux[] = {
3356         RX5_MARK, TX5_MARK,
3357 };
3358 static const unsigned int scif5_clk_pins[] = {
3359         /* SCK */
3360         RCAR_GP_PIN(6, 21),
3361 };
3362 static const unsigned int scif5_clk_mux[] = {
3363         SCK5_MARK,
3364 };
3365
3366 /* - SCIF Clock ------------------------------------------------------------- */
3367 static const unsigned int scif_clk_a_pins[] = {
3368         /* SCIF_CLK */
3369         RCAR_GP_PIN(6, 23),
3370 };
3371 static const unsigned int scif_clk_a_mux[] = {
3372         SCIF_CLK_A_MARK,
3373 };
3374 static const unsigned int scif_clk_b_pins[] = {
3375         /* SCIF_CLK */
3376         RCAR_GP_PIN(5, 9),
3377 };
3378 static const unsigned int scif_clk_b_mux[] = {
3379         SCIF_CLK_B_MARK,
3380 };
3381
3382 /* - SDHI0 ------------------------------------------------------------------ */
3383 static const unsigned int sdhi0_data1_pins[] = {
3384         /* D0 */
3385         RCAR_GP_PIN(3, 2),
3386 };
3387 static const unsigned int sdhi0_data1_mux[] = {
3388         SD0_DAT0_MARK,
3389 };
3390 static const unsigned int sdhi0_data4_pins[] = {
3391         /* D[0:3] */
3392         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3393         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3394 };
3395 static const unsigned int sdhi0_data4_mux[] = {
3396         SD0_DAT0_MARK, SD0_DAT1_MARK,
3397         SD0_DAT2_MARK, SD0_DAT3_MARK,
3398 };
3399 static const unsigned int sdhi0_ctrl_pins[] = {
3400         /* CLK, CMD */
3401         RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3402 };
3403 static const unsigned int sdhi0_ctrl_mux[] = {
3404         SD0_CLK_MARK, SD0_CMD_MARK,
3405 };
3406 static const unsigned int sdhi0_cd_pins[] = {
3407         /* CD */
3408         RCAR_GP_PIN(3, 12),
3409 };
3410 static const unsigned int sdhi0_cd_mux[] = {
3411         SD0_CD_MARK,
3412 };
3413 static const unsigned int sdhi0_wp_pins[] = {
3414         /* WP */
3415         RCAR_GP_PIN(3, 13),
3416 };
3417 static const unsigned int sdhi0_wp_mux[] = {
3418         SD0_WP_MARK,
3419 };
3420 /* - SDHI1 ------------------------------------------------------------------ */
3421 static const unsigned int sdhi1_data1_pins[] = {
3422         /* D0 */
3423         RCAR_GP_PIN(3, 8),
3424 };
3425 static const unsigned int sdhi1_data1_mux[] = {
3426         SD1_DAT0_MARK,
3427 };
3428 static const unsigned int sdhi1_data4_pins[] = {
3429         /* D[0:3] */
3430         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3431         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3432 };
3433 static const unsigned int sdhi1_data4_mux[] = {
3434         SD1_DAT0_MARK, SD1_DAT1_MARK,
3435         SD1_DAT2_MARK, SD1_DAT3_MARK,
3436 };
3437 static const unsigned int sdhi1_ctrl_pins[] = {
3438         /* CLK, CMD */
3439         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3440 };
3441 static const unsigned int sdhi1_ctrl_mux[] = {
3442         SD1_CLK_MARK, SD1_CMD_MARK,
3443 };
3444 static const unsigned int sdhi1_cd_pins[] = {
3445         /* CD */
3446         RCAR_GP_PIN(3, 14),
3447 };
3448 static const unsigned int sdhi1_cd_mux[] = {
3449         SD1_CD_MARK,
3450 };
3451 static const unsigned int sdhi1_wp_pins[] = {
3452         /* WP */
3453         RCAR_GP_PIN(3, 15),
3454 };
3455 static const unsigned int sdhi1_wp_mux[] = {
3456         SD1_WP_MARK,
3457 };
3458 /* - SDHI2 ------------------------------------------------------------------ */
3459 static const unsigned int sdhi2_data1_pins[] = {
3460         /* D0 */
3461         RCAR_GP_PIN(4, 2),
3462 };
3463 static const unsigned int sdhi2_data1_mux[] = {
3464         SD2_DAT0_MARK,
3465 };
3466 static const unsigned int sdhi2_data4_pins[] = {
3467         /* D[0:3] */
3468         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3469         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3470 };
3471 static const unsigned int sdhi2_data4_mux[] = {
3472         SD2_DAT0_MARK, SD2_DAT1_MARK,
3473         SD2_DAT2_MARK, SD2_DAT3_MARK,
3474 };
3475 static const unsigned int sdhi2_data8_pins[] = {
3476         /* D[0:7] */
3477         RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
3478         RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
3479         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3480         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3481 };
3482 static const unsigned int sdhi2_data8_mux[] = {
3483         SD2_DAT0_MARK, SD2_DAT1_MARK,
3484         SD2_DAT2_MARK, SD2_DAT3_MARK,
3485         SD2_DAT4_MARK, SD2_DAT5_MARK,
3486         SD2_DAT6_MARK, SD2_DAT7_MARK,
3487 };
3488 static const unsigned int sdhi2_ctrl_pins[] = {
3489         /* CLK, CMD */
3490         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3491 };
3492 static const unsigned int sdhi2_ctrl_mux[] = {
3493         SD2_CLK_MARK, SD2_CMD_MARK,
3494 };
3495 static const unsigned int sdhi2_cd_a_pins[] = {
3496         /* CD */
3497         RCAR_GP_PIN(4, 13),
3498 };
3499 static const unsigned int sdhi2_cd_a_mux[] = {
3500         SD2_CD_A_MARK,
3501 };
3502 static const unsigned int sdhi2_cd_b_pins[] = {
3503         /* CD */
3504         RCAR_GP_PIN(5, 10),
3505 };
3506 static const unsigned int sdhi2_cd_b_mux[] = {
3507         SD2_CD_B_MARK,
3508 };
3509 static const unsigned int sdhi2_wp_a_pins[] = {
3510         /* WP */
3511         RCAR_GP_PIN(4, 14),
3512 };
3513 static const unsigned int sdhi2_wp_a_mux[] = {
3514         SD2_WP_A_MARK,
3515 };
3516 static const unsigned int sdhi2_wp_b_pins[] = {
3517         /* WP */
3518         RCAR_GP_PIN(5, 11),
3519 };
3520 static const unsigned int sdhi2_wp_b_mux[] = {
3521         SD2_WP_B_MARK,
3522 };
3523 static const unsigned int sdhi2_ds_pins[] = {
3524         /* DS */
3525         RCAR_GP_PIN(4, 6),
3526 };
3527 static const unsigned int sdhi2_ds_mux[] = {
3528         SD2_DS_MARK,
3529 };
3530 /* - SDHI3 ------------------------------------------------------------------ */
3531 static const unsigned int sdhi3_data1_pins[] = {
3532         /* D0 */
3533         RCAR_GP_PIN(4, 9),
3534 };
3535 static const unsigned int sdhi3_data1_mux[] = {
3536         SD3_DAT0_MARK,
3537 };
3538 static const unsigned int sdhi3_data4_pins[] = {
3539         /* D[0:3] */
3540         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3541         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3542 };
3543 static const unsigned int sdhi3_data4_mux[] = {
3544         SD3_DAT0_MARK, SD3_DAT1_MARK,
3545         SD3_DAT2_MARK, SD3_DAT3_MARK,
3546 };
3547 static const unsigned int sdhi3_data8_pins[] = {
3548         /* D[0:7] */
3549         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3550         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3551         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3552         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3553 };
3554 static const unsigned int sdhi3_data8_mux[] = {
3555         SD3_DAT0_MARK, SD3_DAT1_MARK,
3556         SD3_DAT2_MARK, SD3_DAT3_MARK,
3557         SD3_DAT4_MARK, SD3_DAT5_MARK,
3558         SD3_DAT6_MARK, SD3_DAT7_MARK,
3559 };
3560 static const unsigned int sdhi3_ctrl_pins[] = {
3561         /* CLK, CMD */
3562         RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3563 };
3564 static const unsigned int sdhi3_ctrl_mux[] = {
3565         SD3_CLK_MARK, SD3_CMD_MARK,
3566 };
3567 static const unsigned int sdhi3_cd_pins[] = {
3568         /* CD */
3569         RCAR_GP_PIN(4, 15),
3570 };
3571 static const unsigned int sdhi3_cd_mux[] = {
3572         SD3_CD_MARK,
3573 };
3574 static const unsigned int sdhi3_wp_pins[] = {
3575         /* WP */
3576         RCAR_GP_PIN(4, 16),
3577 };
3578 static const unsigned int sdhi3_wp_mux[] = {
3579         SD3_WP_MARK,
3580 };
3581 static const unsigned int sdhi3_ds_pins[] = {
3582         /* DS */
3583         RCAR_GP_PIN(4, 17),
3584 };
3585 static const unsigned int sdhi3_ds_mux[] = {
3586         SD3_DS_MARK,
3587 };
3588
3589 /* - SSI -------------------------------------------------------------------- */
3590 static const unsigned int ssi0_data_pins[] = {
3591         /* SDATA */
3592         RCAR_GP_PIN(6, 2),
3593 };
3594 static const unsigned int ssi0_data_mux[] = {
3595         SSI_SDATA0_MARK,
3596 };
3597 static const unsigned int ssi01239_ctrl_pins[] = {
3598         /* SCK, WS */
3599         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3600 };
3601 static const unsigned int ssi01239_ctrl_mux[] = {
3602         SSI_SCK01239_MARK, SSI_WS01239_MARK,
3603 };
3604 static const unsigned int ssi1_data_a_pins[] = {
3605         /* SDATA */
3606         RCAR_GP_PIN(6, 3),
3607 };
3608 static const unsigned int ssi1_data_a_mux[] = {
3609         SSI_SDATA1_A_MARK,
3610 };
3611 static const unsigned int ssi1_data_b_pins[] = {
3612         /* SDATA */
3613         RCAR_GP_PIN(5, 12),
3614 };
3615 static const unsigned int ssi1_data_b_mux[] = {
3616         SSI_SDATA1_B_MARK,
3617 };
3618 static const unsigned int ssi1_ctrl_a_pins[] = {
3619         /* SCK, WS */
3620         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3621 };
3622 static const unsigned int ssi1_ctrl_a_mux[] = {
3623         SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3624 };
3625 static const unsigned int ssi1_ctrl_b_pins[] = {
3626         /* SCK, WS */
3627         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3628 };
3629 static const unsigned int ssi1_ctrl_b_mux[] = {
3630         SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3631 };
3632 static const unsigned int ssi2_data_a_pins[] = {
3633         /* SDATA */
3634         RCAR_GP_PIN(6, 4),
3635 };
3636 static const unsigned int ssi2_data_a_mux[] = {
3637         SSI_SDATA2_A_MARK,
3638 };
3639 static const unsigned int ssi2_data_b_pins[] = {
3640         /* SDATA */
3641         RCAR_GP_PIN(5, 13),
3642 };
3643 static const unsigned int ssi2_data_b_mux[] = {
3644         SSI_SDATA2_B_MARK,
3645 };
3646 static const unsigned int ssi2_ctrl_a_pins[] = {
3647         /* SCK, WS */
3648         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3649 };
3650 static const unsigned int ssi2_ctrl_a_mux[] = {
3651         SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3652 };
3653 static const unsigned int ssi2_ctrl_b_pins[] = {
3654         /* SCK, WS */
3655         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3656 };
3657 static const unsigned int ssi2_ctrl_b_mux[] = {
3658         SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3659 };
3660 static const unsigned int ssi3_data_pins[] = {
3661         /* SDATA */
3662         RCAR_GP_PIN(6, 7),
3663 };
3664 static const unsigned int ssi3_data_mux[] = {
3665         SSI_SDATA3_MARK,
3666 };
3667 static const unsigned int ssi349_ctrl_pins[] = {
3668         /* SCK, WS */
3669         RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3670 };
3671 static const unsigned int ssi349_ctrl_mux[] = {
3672         SSI_SCK349_MARK, SSI_WS349_MARK,
3673 };
3674 static const unsigned int ssi4_data_pins[] = {
3675         /* SDATA */
3676         RCAR_GP_PIN(6, 10),
3677 };
3678 static const unsigned int ssi4_data_mux[] = {
3679         SSI_SDATA4_MARK,
3680 };
3681 static const unsigned int ssi4_ctrl_pins[] = {
3682         /* SCK, WS */
3683         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3684 };
3685 static const unsigned int ssi4_ctrl_mux[] = {
3686         SSI_SCK4_MARK, SSI_WS4_MARK,
3687 };
3688 static const unsigned int ssi5_data_pins[] = {
3689         /* SDATA */
3690         RCAR_GP_PIN(6, 13),
3691 };
3692 static const unsigned int ssi5_data_mux[] = {
3693         SSI_SDATA5_MARK,
3694 };
3695 static const unsigned int ssi5_ctrl_pins[] = {
3696         /* SCK, WS */
3697         RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3698 };
3699 static const unsigned int ssi5_ctrl_mux[] = {
3700         SSI_SCK5_MARK, SSI_WS5_MARK,
3701 };
3702 static const unsigned int ssi6_data_pins[] = {
3703         /* SDATA */
3704         RCAR_GP_PIN(6, 16),
3705 };
3706 static const unsigned int ssi6_data_mux[] = {
3707         SSI_SDATA6_MARK,
3708 };
3709 static const unsigned int ssi6_ctrl_pins[] = {
3710         /* SCK, WS */
3711         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3712 };
3713 static const unsigned int ssi6_ctrl_mux[] = {
3714         SSI_SCK6_MARK, SSI_WS6_MARK,
3715 };
3716 static const unsigned int ssi7_data_pins[] = {
3717         /* SDATA */
3718         RCAR_GP_PIN(6, 19),
3719 };
3720 static const unsigned int ssi7_data_mux[] = {
3721         SSI_SDATA7_MARK,
3722 };
3723 static const unsigned int ssi78_ctrl_pins[] = {
3724         /* SCK, WS */
3725         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3726 };
3727 static const unsigned int ssi78_ctrl_mux[] = {
3728         SSI_SCK78_MARK, SSI_WS78_MARK,
3729 };
3730 static const unsigned int ssi8_data_pins[] = {
3731         /* SDATA */
3732         RCAR_GP_PIN(6, 20),
3733 };
3734 static const unsigned int ssi8_data_mux[] = {
3735         SSI_SDATA8_MARK,
3736 };
3737 static const unsigned int ssi9_data_a_pins[] = {
3738         /* SDATA */
3739         RCAR_GP_PIN(6, 21),
3740 };
3741 static const unsigned int ssi9_data_a_mux[] = {
3742         SSI_SDATA9_A_MARK,
3743 };
3744 static const unsigned int ssi9_data_b_pins[] = {
3745         /* SDATA */
3746         RCAR_GP_PIN(5, 14),
3747 };
3748 static const unsigned int ssi9_data_b_mux[] = {
3749         SSI_SDATA9_B_MARK,
3750 };
3751 static const unsigned int ssi9_ctrl_a_pins[] = {
3752         /* SCK, WS */
3753         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3754 };
3755 static const unsigned int ssi9_ctrl_a_mux[] = {
3756         SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3757 };
3758 static const unsigned int ssi9_ctrl_b_pins[] = {
3759         /* SCK, WS */
3760         RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3761 };
3762 static const unsigned int ssi9_ctrl_b_mux[] = {
3763         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3764 };
3765
3766 /* - TMU -------------------------------------------------------------------- */
3767 static const unsigned int tmu_tclk1_a_pins[] = {
3768         /* TCLK */
3769         RCAR_GP_PIN(6, 23),
3770 };
3771 static const unsigned int tmu_tclk1_a_mux[] = {
3772         TCLK1_A_MARK,
3773 };
3774 static const unsigned int tmu_tclk1_b_pins[] = {
3775         /* TCLK */
3776         RCAR_GP_PIN(5, 19),
3777 };
3778 static const unsigned int tmu_tclk1_b_mux[] = {
3779         TCLK1_B_MARK,
3780 };
3781 static const unsigned int tmu_tclk2_a_pins[] = {
3782         /* TCLK */
3783         RCAR_GP_PIN(6, 19),
3784 };
3785 static const unsigned int tmu_tclk2_a_mux[] = {
3786         TCLK2_A_MARK,
3787 };
3788 static const unsigned int tmu_tclk2_b_pins[] = {
3789         /* TCLK */
3790         RCAR_GP_PIN(6, 28),
3791 };
3792 static const unsigned int tmu_tclk2_b_mux[] = {
3793         TCLK2_B_MARK,
3794 };
3795
3796 /* - USB0 ------------------------------------------------------------------- */
3797 static const unsigned int usb0_pins[] = {
3798         /* PWEN, OVC */
3799         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3800 };
3801 static const unsigned int usb0_mux[] = {
3802         USB0_PWEN_MARK, USB0_OVC_MARK,
3803 };
3804 /* - USB1 ------------------------------------------------------------------- */
3805 static const unsigned int usb1_pins[] = {
3806         /* PWEN, OVC */
3807         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3808 };
3809 static const unsigned int usb1_mux[] = {
3810         USB1_PWEN_MARK, USB1_OVC_MARK,
3811 };
3812 /* - USB2 ------------------------------------------------------------------- */
3813 static const unsigned int usb2_pins[] = {
3814         /* PWEN, OVC */
3815         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3816 };
3817 static const unsigned int usb2_mux[] = {
3818         USB2_PWEN_MARK, USB2_OVC_MARK,
3819 };
3820
3821 /* - USB30 ------------------------------------------------------------------ */
3822 static const unsigned int usb30_pins[] = {
3823         /* PWEN, OVC */
3824         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3825 };
3826 static const unsigned int usb30_mux[] = {
3827         USB30_PWEN_MARK, USB30_OVC_MARK,
3828 };
3829 /* - USB31 ------------------------------------------------------------------ */
3830 static const unsigned int usb31_pins[] = {
3831         /* PWEN, OVC */
3832         RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3833 };
3834 static const unsigned int usb31_mux[] = {
3835         USB31_PWEN_MARK, USB31_OVC_MARK,
3836 };
3837
3838 static const struct sh_pfc_pin_group pinmux_groups[] = {
3839         SH_PFC_PIN_GROUP(audio_clk_a_a),
3840         SH_PFC_PIN_GROUP(audio_clk_a_b),
3841         SH_PFC_PIN_GROUP(audio_clk_a_c),
3842         SH_PFC_PIN_GROUP(audio_clk_b_a),
3843         SH_PFC_PIN_GROUP(audio_clk_b_b),
3844         SH_PFC_PIN_GROUP(audio_clk_c_a),
3845         SH_PFC_PIN_GROUP(audio_clk_c_b),
3846         SH_PFC_PIN_GROUP(audio_clkout_a),
3847         SH_PFC_PIN_GROUP(audio_clkout_b),
3848         SH_PFC_PIN_GROUP(audio_clkout_c),
3849         SH_PFC_PIN_GROUP(audio_clkout_d),
3850         SH_PFC_PIN_GROUP(audio_clkout1_a),
3851         SH_PFC_PIN_GROUP(audio_clkout1_b),
3852         SH_PFC_PIN_GROUP(audio_clkout2_a),
3853         SH_PFC_PIN_GROUP(audio_clkout2_b),
3854         SH_PFC_PIN_GROUP(audio_clkout3_a),
3855         SH_PFC_PIN_GROUP(audio_clkout3_b),
3856         SH_PFC_PIN_GROUP(avb_link),
3857         SH_PFC_PIN_GROUP(avb_magic),
3858         SH_PFC_PIN_GROUP(avb_phy_int),
3859         SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio),      /* Deprecated */
3860         SH_PFC_PIN_GROUP(avb_mdio),
3861         SH_PFC_PIN_GROUP(avb_mii),
3862         SH_PFC_PIN_GROUP(avb_avtp_pps),
3863         SH_PFC_PIN_GROUP(avb_avtp_match_a),
3864         SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3865         SH_PFC_PIN_GROUP(avb_avtp_match_b),
3866         SH_PFC_PIN_GROUP(avb_avtp_capture_b),
3867         SH_PFC_PIN_GROUP(can0_data_a),
3868         SH_PFC_PIN_GROUP(can0_data_b),
3869         SH_PFC_PIN_GROUP(can1_data),
3870         SH_PFC_PIN_GROUP(can_clk),
3871         SH_PFC_PIN_GROUP(canfd0_data_a),
3872         SH_PFC_PIN_GROUP(canfd0_data_b),
3873         SH_PFC_PIN_GROUP(canfd1_data),
3874         SH_PFC_PIN_GROUP(drif0_ctrl_a),
3875         SH_PFC_PIN_GROUP(drif0_data0_a),
3876         SH_PFC_PIN_GROUP(drif0_data1_a),
3877         SH_PFC_PIN_GROUP(drif0_ctrl_b),
3878         SH_PFC_PIN_GROUP(drif0_data0_b),
3879         SH_PFC_PIN_GROUP(drif0_data1_b),
3880         SH_PFC_PIN_GROUP(drif0_ctrl_c),
3881         SH_PFC_PIN_GROUP(drif0_data0_c),
3882         SH_PFC_PIN_GROUP(drif0_data1_c),
3883         SH_PFC_PIN_GROUP(drif1_ctrl_a),
3884         SH_PFC_PIN_GROUP(drif1_data0_a),
3885         SH_PFC_PIN_GROUP(drif1_data1_a),
3886         SH_PFC_PIN_GROUP(drif1_ctrl_b),
3887         SH_PFC_PIN_GROUP(drif1_data0_b),
3888         SH_PFC_PIN_GROUP(drif1_data1_b),
3889         SH_PFC_PIN_GROUP(drif1_ctrl_c),
3890         SH_PFC_PIN_GROUP(drif1_data0_c),
3891         SH_PFC_PIN_GROUP(drif1_data1_c),
3892         SH_PFC_PIN_GROUP(drif2_ctrl_a),
3893         SH_PFC_PIN_GROUP(drif2_data0_a),
3894         SH_PFC_PIN_GROUP(drif2_data1_a),
3895         SH_PFC_PIN_GROUP(drif2_ctrl_b),
3896         SH_PFC_PIN_GROUP(drif2_data0_b),
3897         SH_PFC_PIN_GROUP(drif2_data1_b),
3898         SH_PFC_PIN_GROUP(drif3_ctrl_a),
3899         SH_PFC_PIN_GROUP(drif3_data0_a),
3900         SH_PFC_PIN_GROUP(drif3_data1_a),
3901         SH_PFC_PIN_GROUP(drif3_ctrl_b),
3902         SH_PFC_PIN_GROUP(drif3_data0_b),
3903         SH_PFC_PIN_GROUP(drif3_data1_b),
3904         SH_PFC_PIN_GROUP(du_rgb666),
3905         SH_PFC_PIN_GROUP(du_rgb888),
3906         SH_PFC_PIN_GROUP(du_clk_out_0),
3907         SH_PFC_PIN_GROUP(du_clk_out_1),
3908         SH_PFC_PIN_GROUP(du_sync),
3909         SH_PFC_PIN_GROUP(du_oddf),
3910         SH_PFC_PIN_GROUP(du_cde),
3911         SH_PFC_PIN_GROUP(du_disp),
3912         SH_PFC_PIN_GROUP(hdmi0_cec),
3913         SH_PFC_PIN_GROUP(hdmi1_cec),
3914         SH_PFC_PIN_GROUP(hscif0_data),
3915         SH_PFC_PIN_GROUP(hscif0_clk),
3916         SH_PFC_PIN_GROUP(hscif0_ctrl),
3917         SH_PFC_PIN_GROUP(hscif1_data_a),
3918         SH_PFC_PIN_GROUP(hscif1_clk_a),
3919         SH_PFC_PIN_GROUP(hscif1_ctrl_a),
3920         SH_PFC_PIN_GROUP(hscif1_data_b),
3921         SH_PFC_PIN_GROUP(hscif1_clk_b),
3922         SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3923         SH_PFC_PIN_GROUP(hscif2_data_a),
3924         SH_PFC_PIN_GROUP(hscif2_clk_a),
3925         SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3926         SH_PFC_PIN_GROUP(hscif2_data_b),
3927         SH_PFC_PIN_GROUP(hscif2_clk_b),
3928         SH_PFC_PIN_GROUP(hscif2_ctrl_b),
3929         SH_PFC_PIN_GROUP(hscif3_data_a),
3930         SH_PFC_PIN_GROUP(hscif3_clk),
3931         SH_PFC_PIN_GROUP(hscif3_ctrl),
3932         SH_PFC_PIN_GROUP(hscif3_data_b),
3933         SH_PFC_PIN_GROUP(hscif3_data_c),
3934         SH_PFC_PIN_GROUP(hscif3_data_d),
3935         SH_PFC_PIN_GROUP(hscif4_data_a),
3936         SH_PFC_PIN_GROUP(hscif4_clk),
3937         SH_PFC_PIN_GROUP(hscif4_ctrl),
3938         SH_PFC_PIN_GROUP(hscif4_data_b),
3939         SH_PFC_PIN_GROUP(i2c1_a),
3940         SH_PFC_PIN_GROUP(i2c1_b),
3941         SH_PFC_PIN_GROUP(i2c2_a),
3942         SH_PFC_PIN_GROUP(i2c2_b),
3943         SH_PFC_PIN_GROUP(i2c6_a),
3944         SH_PFC_PIN_GROUP(i2c6_b),
3945         SH_PFC_PIN_GROUP(i2c6_c),
3946         SH_PFC_PIN_GROUP(intc_ex_irq0),
3947         SH_PFC_PIN_GROUP(intc_ex_irq1),
3948         SH_PFC_PIN_GROUP(intc_ex_irq2),
3949         SH_PFC_PIN_GROUP(intc_ex_irq3),
3950         SH_PFC_PIN_GROUP(intc_ex_irq4),
3951         SH_PFC_PIN_GROUP(intc_ex_irq5),
3952         SH_PFC_PIN_GROUP(msiof0_clk),
3953         SH_PFC_PIN_GROUP(msiof0_sync),
3954         SH_PFC_PIN_GROUP(msiof0_ss1),
3955         SH_PFC_PIN_GROUP(msiof0_ss2),
3956         SH_PFC_PIN_GROUP(msiof0_txd),
3957         SH_PFC_PIN_GROUP(msiof0_rxd),
3958         SH_PFC_PIN_GROUP(msiof1_clk_a),
3959         SH_PFC_PIN_GROUP(msiof1_sync_a),
3960         SH_PFC_PIN_GROUP(msiof1_ss1_a),
3961         SH_PFC_PIN_GROUP(msiof1_ss2_a),
3962         SH_PFC_PIN_GROUP(msiof1_txd_a),
3963         SH_PFC_PIN_GROUP(msiof1_rxd_a),
3964         SH_PFC_PIN_GROUP(msiof1_clk_b),
3965         SH_PFC_PIN_GROUP(msiof1_sync_b),
3966         SH_PFC_PIN_GROUP(msiof1_ss1_b),
3967         SH_PFC_PIN_GROUP(msiof1_ss2_b),
3968         SH_PFC_PIN_GROUP(msiof1_txd_b),
3969         SH_PFC_PIN_GROUP(msiof1_rxd_b),
3970         SH_PFC_PIN_GROUP(msiof1_clk_c),
3971         SH_PFC_PIN_GROUP(msiof1_sync_c),
3972         SH_PFC_PIN_GROUP(msiof1_ss1_c),
3973         SH_PFC_PIN_GROUP(msiof1_ss2_c),
3974         SH_PFC_PIN_GROUP(msiof1_txd_c),
3975         SH_PFC_PIN_GROUP(msiof1_rxd_c),
3976         SH_PFC_PIN_GROUP(msiof1_clk_d),
3977         SH_PFC_PIN_GROUP(msiof1_sync_d),
3978         SH_PFC_PIN_GROUP(msiof1_ss1_d),
3979         SH_PFC_PIN_GROUP(msiof1_ss2_d),
3980         SH_PFC_PIN_GROUP(msiof1_txd_d),
3981         SH_PFC_PIN_GROUP(msiof1_rxd_d),
3982         SH_PFC_PIN_GROUP(msiof1_clk_e),
3983         SH_PFC_PIN_GROUP(msiof1_sync_e),
3984         SH_PFC_PIN_GROUP(msiof1_ss1_e),
3985         SH_PFC_PIN_GROUP(msiof1_ss2_e),
3986         SH_PFC_PIN_GROUP(msiof1_txd_e),
3987         SH_PFC_PIN_GROUP(msiof1_rxd_e),
3988         SH_PFC_PIN_GROUP(msiof1_clk_f),
3989         SH_PFC_PIN_GROUP(msiof1_sync_f),
3990         SH_PFC_PIN_GROUP(msiof1_ss1_f),
3991         SH_PFC_PIN_GROUP(msiof1_ss2_f),
3992         SH_PFC_PIN_GROUP(msiof1_txd_f),
3993         SH_PFC_PIN_GROUP(msiof1_rxd_f),
3994         SH_PFC_PIN_GROUP(msiof1_clk_g),
3995         SH_PFC_PIN_GROUP(msiof1_sync_g),
3996         SH_PFC_PIN_GROUP(msiof1_ss1_g),
3997         SH_PFC_PIN_GROUP(msiof1_ss2_g),
3998         SH_PFC_PIN_GROUP(msiof1_txd_g),
3999         SH_PFC_PIN_GROUP(msiof1_rxd_g),
4000         SH_PFC_PIN_GROUP(msiof2_clk_a),
4001         SH_PFC_PIN_GROUP(msiof2_sync_a),
4002         SH_PFC_PIN_GROUP(msiof2_ss1_a),
4003         SH_PFC_PIN_GROUP(msiof2_ss2_a),
4004         SH_PFC_PIN_GROUP(msiof2_txd_a),
4005         SH_PFC_PIN_GROUP(msiof2_rxd_a),
4006         SH_PFC_PIN_GROUP(msiof2_clk_b),
4007         SH_PFC_PIN_GROUP(msiof2_sync_b),
4008         SH_PFC_PIN_GROUP(msiof2_ss1_b),
4009         SH_PFC_PIN_GROUP(msiof2_ss2_b),
4010         SH_PFC_PIN_GROUP(msiof2_txd_b),
4011         SH_PFC_PIN_GROUP(msiof2_rxd_b),
4012         SH_PFC_PIN_GROUP(msiof2_clk_c),
4013         SH_PFC_PIN_GROUP(msiof2_sync_c),
4014         SH_PFC_PIN_GROUP(msiof2_ss1_c),
4015         SH_PFC_PIN_GROUP(msiof2_ss2_c),
4016         SH_PFC_PIN_GROUP(msiof2_txd_c),
4017         SH_PFC_PIN_GROUP(msiof2_rxd_c),
4018         SH_PFC_PIN_GROUP(msiof2_clk_d),
4019         SH_PFC_PIN_GROUP(msiof2_sync_d),
4020         SH_PFC_PIN_GROUP(msiof2_ss1_d),
4021         SH_PFC_PIN_GROUP(msiof2_ss2_d),
4022         SH_PFC_PIN_GROUP(msiof2_txd_d),
4023         SH_PFC_PIN_GROUP(msiof2_rxd_d),
4024         SH_PFC_PIN_GROUP(msiof3_clk_a),
4025         SH_PFC_PIN_GROUP(msiof3_sync_a),
4026         SH_PFC_PIN_GROUP(msiof3_ss1_a),
4027         SH_PFC_PIN_GROUP(msiof3_ss2_a),
4028         SH_PFC_PIN_GROUP(msiof3_txd_a),
4029         SH_PFC_PIN_GROUP(msiof3_rxd_a),
4030         SH_PFC_PIN_GROUP(msiof3_clk_b),
4031         SH_PFC_PIN_GROUP(msiof3_sync_b),
4032         SH_PFC_PIN_GROUP(msiof3_ss1_b),
4033         SH_PFC_PIN_GROUP(msiof3_ss2_b),
4034         SH_PFC_PIN_GROUP(msiof3_txd_b),
4035         SH_PFC_PIN_GROUP(msiof3_rxd_b),
4036         SH_PFC_PIN_GROUP(msiof3_clk_c),
4037         SH_PFC_PIN_GROUP(msiof3_sync_c),
4038         SH_PFC_PIN_GROUP(msiof3_txd_c),
4039         SH_PFC_PIN_GROUP(msiof3_rxd_c),
4040         SH_PFC_PIN_GROUP(msiof3_clk_d),
4041         SH_PFC_PIN_GROUP(msiof3_sync_d),
4042         SH_PFC_PIN_GROUP(msiof3_ss1_d),
4043         SH_PFC_PIN_GROUP(msiof3_txd_d),
4044         SH_PFC_PIN_GROUP(msiof3_rxd_d),
4045         SH_PFC_PIN_GROUP(pwm0),
4046         SH_PFC_PIN_GROUP(pwm1_a),
4047         SH_PFC_PIN_GROUP(pwm1_b),
4048         SH_PFC_PIN_GROUP(pwm2_a),
4049         SH_PFC_PIN_GROUP(pwm2_b),
4050         SH_PFC_PIN_GROUP(pwm3_a),
4051         SH_PFC_PIN_GROUP(pwm3_b),
4052         SH_PFC_PIN_GROUP(pwm4_a),
4053         SH_PFC_PIN_GROUP(pwm4_b),
4054         SH_PFC_PIN_GROUP(pwm5_a),
4055         SH_PFC_PIN_GROUP(pwm5_b),
4056         SH_PFC_PIN_GROUP(pwm6_a),
4057         SH_PFC_PIN_GROUP(pwm6_b),
4058         SH_PFC_PIN_GROUP(qspi0_ctrl),
4059         SH_PFC_PIN_GROUP(qspi0_data2),
4060         SH_PFC_PIN_GROUP(qspi0_data4),
4061         SH_PFC_PIN_GROUP(qspi1_ctrl),
4062         SH_PFC_PIN_GROUP(qspi1_data2),
4063         SH_PFC_PIN_GROUP(qspi1_data4),
4064         SH_PFC_PIN_GROUP(sata0_devslp_a),
4065         SH_PFC_PIN_GROUP(sata0_devslp_b),
4066         SH_PFC_PIN_GROUP(scif0_data),
4067         SH_PFC_PIN_GROUP(scif0_clk),
4068         SH_PFC_PIN_GROUP(scif0_ctrl),
4069         SH_PFC_PIN_GROUP(scif1_data_a),
4070         SH_PFC_PIN_GROUP(scif1_clk),
4071         SH_PFC_PIN_GROUP(scif1_ctrl),
4072         SH_PFC_PIN_GROUP(scif1_data_b),
4073         SH_PFC_PIN_GROUP(scif2_data_a),
4074         SH_PFC_PIN_GROUP(scif2_clk),
4075         SH_PFC_PIN_GROUP(scif2_data_b),
4076         SH_PFC_PIN_GROUP(scif3_data_a),
4077         SH_PFC_PIN_GROUP(scif3_clk),
4078         SH_PFC_PIN_GROUP(scif3_ctrl),
4079         SH_PFC_PIN_GROUP(scif3_data_b),
4080         SH_PFC_PIN_GROUP(scif4_data_a),
4081         SH_PFC_PIN_GROUP(scif4_clk_a),
4082         SH_PFC_PIN_GROUP(scif4_ctrl_a),
4083         SH_PFC_PIN_GROUP(scif4_data_b),
4084         SH_PFC_PIN_GROUP(scif4_clk_b),
4085         SH_PFC_PIN_GROUP(scif4_ctrl_b),
4086         SH_PFC_PIN_GROUP(scif4_data_c),
4087         SH_PFC_PIN_GROUP(scif4_clk_c),
4088         SH_PFC_PIN_GROUP(scif4_ctrl_c),
4089         SH_PFC_PIN_GROUP(scif5_data),
4090         SH_PFC_PIN_GROUP(scif5_clk),
4091         SH_PFC_PIN_GROUP(scif_clk_a),
4092         SH_PFC_PIN_GROUP(scif_clk_b),
4093         SH_PFC_PIN_GROUP(sdhi0_data1),
4094         SH_PFC_PIN_GROUP(sdhi0_data4),
4095         SH_PFC_PIN_GROUP(sdhi0_ctrl),
4096         SH_PFC_PIN_GROUP(sdhi0_cd),
4097         SH_PFC_PIN_GROUP(sdhi0_wp),
4098         SH_PFC_PIN_GROUP(sdhi1_data1),
4099         SH_PFC_PIN_GROUP(sdhi1_data4),
4100         SH_PFC_PIN_GROUP(sdhi1_ctrl),
4101         SH_PFC_PIN_GROUP(sdhi1_cd),
4102         SH_PFC_PIN_GROUP(sdhi1_wp),
4103         SH_PFC_PIN_GROUP(sdhi2_data1),
4104         SH_PFC_PIN_GROUP(sdhi2_data4),
4105         SH_PFC_PIN_GROUP(sdhi2_data8),
4106         SH_PFC_PIN_GROUP(sdhi2_ctrl),
4107         SH_PFC_PIN_GROUP(sdhi2_cd_a),
4108         SH_PFC_PIN_GROUP(sdhi2_wp_a),
4109         SH_PFC_PIN_GROUP(sdhi2_cd_b),
4110         SH_PFC_PIN_GROUP(sdhi2_wp_b),
4111         SH_PFC_PIN_GROUP(sdhi2_ds),
4112         SH_PFC_PIN_GROUP(sdhi3_data1),
4113         SH_PFC_PIN_GROUP(sdhi3_data4),
4114         SH_PFC_PIN_GROUP(sdhi3_data8),
4115         SH_PFC_PIN_GROUP(sdhi3_ctrl),
4116         SH_PFC_PIN_GROUP(sdhi3_cd),
4117         SH_PFC_PIN_GROUP(sdhi3_wp),
4118         SH_PFC_PIN_GROUP(sdhi3_ds),
4119         SH_PFC_PIN_GROUP(ssi0_data),
4120         SH_PFC_PIN_GROUP(ssi01239_ctrl),
4121         SH_PFC_PIN_GROUP(ssi1_data_a),
4122         SH_PFC_PIN_GROUP(ssi1_data_b),
4123         SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4124         SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4125         SH_PFC_PIN_GROUP(ssi2_data_a),
4126         SH_PFC_PIN_GROUP(ssi2_data_b),
4127         SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4128         SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4129         SH_PFC_PIN_GROUP(ssi3_data),
4130         SH_PFC_PIN_GROUP(ssi349_ctrl),
4131         SH_PFC_PIN_GROUP(ssi4_data),
4132         SH_PFC_PIN_GROUP(ssi4_ctrl),
4133         SH_PFC_PIN_GROUP(ssi5_data),
4134         SH_PFC_PIN_GROUP(ssi5_ctrl),
4135         SH_PFC_PIN_GROUP(ssi6_data),
4136         SH_PFC_PIN_GROUP(ssi6_ctrl),
4137         SH_PFC_PIN_GROUP(ssi7_data),
4138         SH_PFC_PIN_GROUP(ssi78_ctrl),
4139         SH_PFC_PIN_GROUP(ssi8_data),
4140         SH_PFC_PIN_GROUP(ssi9_data_a),
4141         SH_PFC_PIN_GROUP(ssi9_data_b),
4142         SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4143         SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4144         SH_PFC_PIN_GROUP(tmu_tclk1_a),
4145         SH_PFC_PIN_GROUP(tmu_tclk1_b),
4146         SH_PFC_PIN_GROUP(tmu_tclk2_a),
4147         SH_PFC_PIN_GROUP(tmu_tclk2_b),
4148         SH_PFC_PIN_GROUP(usb0),
4149         SH_PFC_PIN_GROUP(usb1),
4150         SH_PFC_PIN_GROUP(usb2),
4151         SH_PFC_PIN_GROUP(usb30),
4152         SH_PFC_PIN_GROUP(usb31),
4153 };
4154
4155 static const char * const audio_clk_groups[] = {
4156         "audio_clk_a_a",
4157         "audio_clk_a_b",
4158         "audio_clk_a_c",
4159         "audio_clk_b_a",
4160         "audio_clk_b_b",
4161         "audio_clk_c_a",
4162         "audio_clk_c_b",
4163         "audio_clkout_a",
4164         "audio_clkout_b",
4165         "audio_clkout_c",
4166         "audio_clkout_d",
4167         "audio_clkout1_a",
4168         "audio_clkout1_b",
4169         "audio_clkout2_a",
4170         "audio_clkout2_b",
4171         "audio_clkout3_a",
4172         "audio_clkout3_b",
4173 };
4174
4175 static const char * const avb_groups[] = {
4176         "avb_link",
4177         "avb_magic",
4178         "avb_phy_int",
4179         "avb_mdc",      /* Deprecated, please use "avb_mdio" instead */
4180         "avb_mdio",
4181         "avb_mii",
4182         "avb_avtp_pps",
4183         "avb_avtp_match_a",
4184         "avb_avtp_capture_a",
4185         "avb_avtp_match_b",
4186         "avb_avtp_capture_b",
4187 };
4188
4189 static const char * const can0_groups[] = {
4190         "can0_data_a",
4191         "can0_data_b",
4192 };
4193
4194 static const char * const can1_groups[] = {
4195         "can1_data",
4196 };
4197
4198 static const char * const can_clk_groups[] = {
4199         "can_clk",
4200 };
4201
4202 static const char * const canfd0_groups[] = {
4203         "canfd0_data_a",
4204         "canfd0_data_b",
4205 };
4206
4207 static const char * const canfd1_groups[] = {
4208         "canfd1_data",
4209 };
4210
4211 static const char * const drif0_groups[] = {
4212         "drif0_ctrl_a",
4213         "drif0_data0_a",
4214         "drif0_data1_a",
4215         "drif0_ctrl_b",
4216         "drif0_data0_b",
4217         "drif0_data1_b",
4218         "drif0_ctrl_c",
4219         "drif0_data0_c",
4220         "drif0_data1_c",
4221 };
4222
4223 static const char * const drif1_groups[] = {
4224         "drif1_ctrl_a",
4225         "drif1_data0_a",
4226         "drif1_data1_a",
4227         "drif1_ctrl_b",
4228         "drif1_data0_b",
4229         "drif1_data1_b",
4230         "drif1_ctrl_c",
4231         "drif1_data0_c",
4232         "drif1_data1_c",
4233 };
4234
4235 static const char * const drif2_groups[] = {
4236         "drif2_ctrl_a",
4237         "drif2_data0_a",
4238         "drif2_data1_a",
4239         "drif2_ctrl_b",
4240         "drif2_data0_b",
4241         "drif2_data1_b",
4242 };
4243
4244 static const char * const drif3_groups[] = {
4245         "drif3_ctrl_a",
4246         "drif3_data0_a",
4247         "drif3_data1_a",
4248         "drif3_ctrl_b",
4249         "drif3_data0_b",
4250         "drif3_data1_b",
4251 };
4252
4253 static const char * const du_groups[] = {
4254         "du_rgb666",
4255         "du_rgb888",
4256         "du_clk_out_0",
4257         "du_clk_out_1",
4258         "du_sync",
4259         "du_oddf",
4260         "du_cde",
4261         "du_disp",
4262 };
4263
4264 static const char * const hdmi0_groups[] = {
4265         "hdmi0_cec",
4266 };
4267
4268 static const char * const hdmi1_groups[] = {
4269         "hdmi1_cec",
4270 };
4271
4272 static const char * const hscif0_groups[] = {
4273         "hscif0_data",
4274         "hscif0_clk",
4275         "hscif0_ctrl",
4276 };
4277
4278 static const char * const hscif1_groups[] = {
4279         "hscif1_data_a",
4280         "hscif1_clk_a",
4281         "hscif1_ctrl_a",
4282         "hscif1_data_b",
4283         "hscif1_clk_b",
4284         "hscif1_ctrl_b",
4285 };
4286
4287 static const char * const hscif2_groups[] = {
4288         "hscif2_data_a",
4289         "hscif2_clk_a",
4290         "hscif2_ctrl_a",
4291         "hscif2_data_b",
4292         "hscif2_clk_b",
4293         "hscif2_ctrl_b",
4294 };
4295
4296 static const char * const hscif3_groups[] = {
4297         "hscif3_data_a",
4298         "hscif3_clk",
4299         "hscif3_ctrl",
4300         "hscif3_data_b",
4301         "hscif3_data_c",
4302         "hscif3_data_d",
4303 };
4304
4305 static const char * const hscif4_groups[] = {
4306         "hscif4_data_a",
4307         "hscif4_clk",
4308         "hscif4_ctrl",
4309         "hscif4_data_b",
4310 };
4311
4312 static const char * const i2c1_groups[] = {
4313         "i2c1_a",
4314         "i2c1_b",
4315 };
4316
4317 static const char * const i2c2_groups[] = {
4318         "i2c2_a",
4319         "i2c2_b",
4320 };
4321
4322 static const char * const i2c6_groups[] = {
4323         "i2c6_a",
4324         "i2c6_b",
4325         "i2c6_c",
4326 };
4327
4328 static const char * const intc_ex_groups[] = {
4329         "intc_ex_irq0",
4330         "intc_ex_irq1",
4331         "intc_ex_irq2",
4332         "intc_ex_irq3",
4333         "intc_ex_irq4",
4334         "intc_ex_irq5",
4335 };
4336
4337 static const char * const msiof0_groups[] = {
4338         "msiof0_clk",
4339         "msiof0_sync",
4340         "msiof0_ss1",
4341         "msiof0_ss2",
4342         "msiof0_txd",
4343         "msiof0_rxd",
4344 };
4345
4346 static const char * const msiof1_groups[] = {
4347         "msiof1_clk_a",
4348         "msiof1_sync_a",
4349         "msiof1_ss1_a",
4350         "msiof1_ss2_a",
4351         "msiof1_txd_a",
4352         "msiof1_rxd_a",
4353         "msiof1_clk_b",
4354         "msiof1_sync_b",
4355         "msiof1_ss1_b",
4356         "msiof1_ss2_b",
4357         "msiof1_txd_b",
4358         "msiof1_rxd_b",
4359         "msiof1_clk_c",
4360         "msiof1_sync_c",
4361         "msiof1_ss1_c",
4362         "msiof1_ss2_c",
4363         "msiof1_txd_c",
4364         "msiof1_rxd_c",
4365         "msiof1_clk_d",
4366         "msiof1_sync_d",
4367         "msiof1_ss1_d",
4368         "msiof1_ss2_d",
4369         "msiof1_txd_d",
4370         "msiof1_rxd_d",
4371         "msiof1_clk_e",
4372         "msiof1_sync_e",
4373         "msiof1_ss1_e",
4374         "msiof1_ss2_e",
4375         "msiof1_txd_e",
4376         "msiof1_rxd_e",
4377         "msiof1_clk_f",
4378         "msiof1_sync_f",
4379         "msiof1_ss1_f",
4380         "msiof1_ss2_f",
4381         "msiof1_txd_f",
4382         "msiof1_rxd_f",
4383         "msiof1_clk_g",
4384         "msiof1_sync_g",
4385         "msiof1_ss1_g",
4386         "msiof1_ss2_g",
4387         "msiof1_txd_g",
4388         "msiof1_rxd_g",
4389 };
4390
4391 static const char * const msiof2_groups[] = {
4392         "msiof2_clk_a",
4393         "msiof2_sync_a",
4394         "msiof2_ss1_a",
4395         "msiof2_ss2_a",
4396         "msiof2_txd_a",
4397         "msiof2_rxd_a",
4398         "msiof2_clk_b",
4399         "msiof2_sync_b",
4400         "msiof2_ss1_b",
4401         "msiof2_ss2_b",
4402         "msiof2_txd_b",
4403         "msiof2_rxd_b",
4404         "msiof2_clk_c",
4405         "msiof2_sync_c",
4406         "msiof2_ss1_c",
4407         "msiof2_ss2_c",
4408         "msiof2_txd_c",
4409         "msiof2_rxd_c",
4410         "msiof2_clk_d",
4411         "msiof2_sync_d",
4412         "msiof2_ss1_d",
4413         "msiof2_ss2_d",
4414         "msiof2_txd_d",
4415         "msiof2_rxd_d",
4416 };
4417
4418 static const char * const msiof3_groups[] = {
4419         "msiof3_clk_a",
4420         "msiof3_sync_a",
4421         "msiof3_ss1_a",
4422         "msiof3_ss2_a",
4423         "msiof3_txd_a",
4424         "msiof3_rxd_a",
4425         "msiof3_clk_b",
4426         "msiof3_sync_b",
4427         "msiof3_ss1_b",
4428         "msiof3_ss2_b",
4429         "msiof3_txd_b",
4430         "msiof3_rxd_b",
4431         "msiof3_clk_c",
4432         "msiof3_sync_c",
4433         "msiof3_txd_c",
4434         "msiof3_rxd_c",
4435         "msiof3_clk_d",
4436         "msiof3_sync_d",
4437         "msiof3_ss1_d",
4438         "msiof3_txd_d",
4439         "msiof3_rxd_d",
4440 };
4441
4442 static const char * const pwm0_groups[] = {
4443         "pwm0",
4444 };
4445
4446 static const char * const pwm1_groups[] = {
4447         "pwm1_a",
4448         "pwm1_b",
4449 };
4450
4451 static const char * const pwm2_groups[] = {
4452         "pwm2_a",
4453         "pwm2_b",
4454 };
4455
4456 static const char * const pwm3_groups[] = {
4457         "pwm3_a",
4458         "pwm3_b",
4459 };
4460
4461 static const char * const pwm4_groups[] = {
4462         "pwm4_a",
4463         "pwm4_b",
4464 };
4465
4466 static const char * const pwm5_groups[] = {
4467         "pwm5_a",
4468         "pwm5_b",
4469 };
4470
4471 static const char * const pwm6_groups[] = {
4472         "pwm6_a",
4473         "pwm6_b",
4474 };
4475
4476 static const char * const qspi0_groups[] = {
4477         "qspi0_ctrl",
4478         "qspi0_data2",
4479         "qspi0_data4",
4480 };
4481
4482 static const char * const qspi1_groups[] = {
4483         "qspi1_ctrl",
4484         "qspi1_data2",
4485         "qspi1_data4",
4486 };
4487
4488 static const char * const sata0_groups[] = {
4489         "sata0_devslp_a",
4490         "sata0_devslp_b",
4491 };
4492
4493 static const char * const scif0_groups[] = {
4494         "scif0_data",
4495         "scif0_clk",
4496         "scif0_ctrl",
4497 };
4498
4499 static const char * const scif1_groups[] = {
4500         "scif1_data_a",
4501         "scif1_clk",
4502         "scif1_ctrl",
4503         "scif1_data_b",
4504 };
4505
4506 static const char * const scif2_groups[] = {
4507         "scif2_data_a",
4508         "scif2_clk",
4509         "scif2_data_b",
4510 };
4511
4512 static const char * const scif3_groups[] = {
4513         "scif3_data_a",
4514         "scif3_clk",
4515         "scif3_ctrl",
4516         "scif3_data_b",
4517 };
4518
4519 static const char * const scif4_groups[] = {
4520         "scif4_data_a",
4521         "scif4_clk_a",
4522         "scif4_ctrl_a",
4523         "scif4_data_b",
4524         "scif4_clk_b",
4525         "scif4_ctrl_b",
4526         "scif4_data_c",
4527         "scif4_clk_c",
4528         "scif4_ctrl_c",
4529 };
4530
4531 static const char * const scif5_groups[] = {
4532         "scif5_data",
4533         "scif5_clk",
4534 };
4535
4536 static const char * const scif_clk_groups[] = {
4537         "scif_clk_a",
4538         "scif_clk_b",
4539 };
4540
4541 static const char * const sdhi0_groups[] = {
4542         "sdhi0_data1",
4543         "sdhi0_data4",
4544         "sdhi0_ctrl",
4545         "sdhi0_cd",
4546         "sdhi0_wp",
4547 };
4548
4549 static const char * const sdhi1_groups[] = {
4550         "sdhi1_data1",
4551         "sdhi1_data4",
4552         "sdhi1_ctrl",
4553         "sdhi1_cd",
4554         "sdhi1_wp",
4555 };
4556
4557 static const char * const sdhi2_groups[] = {
4558         "sdhi2_data1",
4559         "sdhi2_data4",
4560         "sdhi2_data8",
4561         "sdhi2_ctrl",
4562         "sdhi2_cd_a",
4563         "sdhi2_wp_a",
4564         "sdhi2_cd_b",
4565         "sdhi2_wp_b",
4566         "sdhi2_ds",
4567 };
4568
4569 static const char * const sdhi3_groups[] = {
4570         "sdhi3_data1",
4571         "sdhi3_data4",
4572         "sdhi3_data8",
4573         "sdhi3_ctrl",
4574         "sdhi3_cd",
4575         "sdhi3_wp",
4576         "sdhi3_ds",
4577 };
4578
4579 static const char * const ssi_groups[] = {
4580         "ssi0_data",
4581         "ssi01239_ctrl",
4582         "ssi1_data_a",
4583         "ssi1_data_b",
4584         "ssi1_ctrl_a",
4585         "ssi1_ctrl_b",
4586         "ssi2_data_a",
4587         "ssi2_data_b",
4588         "ssi2_ctrl_a",
4589         "ssi2_ctrl_b",
4590         "ssi3_data",
4591         "ssi349_ctrl",
4592         "ssi4_data",
4593         "ssi4_ctrl",
4594         "ssi5_data",
4595         "ssi5_ctrl",
4596         "ssi6_data",
4597         "ssi6_ctrl",
4598         "ssi7_data",
4599         "ssi78_ctrl",
4600         "ssi8_data",
4601         "ssi9_data_a",
4602         "ssi9_data_b",
4603         "ssi9_ctrl_a",
4604         "ssi9_ctrl_b",
4605 };
4606
4607 static const char * const tmu_groups[] = {
4608         "tmu_tclk1_a",
4609         "tmu_tclk1_b",
4610         "tmu_tclk2_a",
4611         "tmu_tclk2_b",
4612 };
4613
4614 static const char * const usb0_groups[] = {
4615         "usb0",
4616 };
4617
4618 static const char * const usb1_groups[] = {
4619         "usb1",
4620 };
4621
4622 static const char * const usb2_groups[] = {
4623         "usb2",
4624 };
4625
4626 static const char * const usb30_groups[] = {
4627         "usb30",
4628 };
4629
4630 static const char * const usb31_groups[] = {
4631         "usb31",
4632 };
4633
4634 static const struct sh_pfc_function pinmux_functions[] = {
4635         SH_PFC_FUNCTION(audio_clk),
4636         SH_PFC_FUNCTION(avb),
4637         SH_PFC_FUNCTION(can0),
4638         SH_PFC_FUNCTION(can1),
4639         SH_PFC_FUNCTION(can_clk),
4640         SH_PFC_FUNCTION(canfd0),
4641         SH_PFC_FUNCTION(canfd1),
4642         SH_PFC_FUNCTION(drif0),
4643         SH_PFC_FUNCTION(drif1),
4644         SH_PFC_FUNCTION(drif2),
4645         SH_PFC_FUNCTION(drif3),
4646         SH_PFC_FUNCTION(du),
4647         SH_PFC_FUNCTION(hdmi0),
4648         SH_PFC_FUNCTION(hdmi1),
4649         SH_PFC_FUNCTION(hscif0),
4650         SH_PFC_FUNCTION(hscif1),
4651         SH_PFC_FUNCTION(hscif2),
4652         SH_PFC_FUNCTION(hscif3),
4653         SH_PFC_FUNCTION(hscif4),
4654         SH_PFC_FUNCTION(i2c1),
4655         SH_PFC_FUNCTION(i2c2),
4656         SH_PFC_FUNCTION(i2c6),
4657         SH_PFC_FUNCTION(intc_ex),
4658         SH_PFC_FUNCTION(msiof0),
4659         SH_PFC_FUNCTION(msiof1),
4660         SH_PFC_FUNCTION(msiof2),
4661         SH_PFC_FUNCTION(msiof3),
4662         SH_PFC_FUNCTION(pwm0),
4663         SH_PFC_FUNCTION(pwm1),
4664         SH_PFC_FUNCTION(pwm2),
4665         SH_PFC_FUNCTION(pwm3),
4666         SH_PFC_FUNCTION(pwm4),
4667         SH_PFC_FUNCTION(pwm5),
4668         SH_PFC_FUNCTION(pwm6),
4669         SH_PFC_FUNCTION(qspi0),
4670         SH_PFC_FUNCTION(qspi1),
4671         SH_PFC_FUNCTION(sata0),
4672         SH_PFC_FUNCTION(scif0),
4673         SH_PFC_FUNCTION(scif1),
4674         SH_PFC_FUNCTION(scif2),
4675         SH_PFC_FUNCTION(scif3),
4676         SH_PFC_FUNCTION(scif4),
4677         SH_PFC_FUNCTION(scif5),
4678         SH_PFC_FUNCTION(scif_clk),
4679         SH_PFC_FUNCTION(sdhi0),
4680         SH_PFC_FUNCTION(sdhi1),
4681         SH_PFC_FUNCTION(sdhi2),
4682         SH_PFC_FUNCTION(sdhi3),
4683         SH_PFC_FUNCTION(ssi),
4684         SH_PFC_FUNCTION(tmu),
4685         SH_PFC_FUNCTION(usb0),
4686         SH_PFC_FUNCTION(usb1),
4687         SH_PFC_FUNCTION(usb2),
4688         SH_PFC_FUNCTION(usb30),
4689         SH_PFC_FUNCTION(usb31),
4690 };
4691
4692 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4693 #define F_(x, y)        FN_##y
4694 #define FM(x)           FN_##x
4695         { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
4696                 0, 0,
4697                 0, 0,
4698                 0, 0,
4699                 0, 0,
4700                 0, 0,
4701                 0, 0,
4702                 0, 0,
4703                 0, 0,
4704                 0, 0,
4705                 0, 0,
4706                 0, 0,
4707                 0, 0,
4708                 0, 0,
4709                 0, 0,
4710                 0, 0,
4711                 0, 0,
4712                 GP_0_15_FN,     GPSR0_15,
4713                 GP_0_14_FN,     GPSR0_14,
4714                 GP_0_13_FN,     GPSR0_13,
4715                 GP_0_12_FN,     GPSR0_12,
4716                 GP_0_11_FN,     GPSR0_11,
4717                 GP_0_10_FN,     GPSR0_10,
4718                 GP_0_9_FN,      GPSR0_9,
4719                 GP_0_8_FN,      GPSR0_8,
4720                 GP_0_7_FN,      GPSR0_7,
4721                 GP_0_6_FN,      GPSR0_6,
4722                 GP_0_5_FN,      GPSR0_5,
4723                 GP_0_4_FN,      GPSR0_4,
4724                 GP_0_3_FN,      GPSR0_3,
4725                 GP_0_2_FN,      GPSR0_2,
4726                 GP_0_1_FN,      GPSR0_1,
4727                 GP_0_0_FN,      GPSR0_0, }
4728         },
4729         { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
4730                 0, 0,
4731                 0, 0,
4732                 0, 0,
4733                 0, 0,
4734                 GP_1_27_FN,     GPSR1_27,
4735                 GP_1_26_FN,     GPSR1_26,
4736                 GP_1_25_FN,     GPSR1_25,
4737                 GP_1_24_FN,     GPSR1_24,
4738                 GP_1_23_FN,     GPSR1_23,
4739                 GP_1_22_FN,     GPSR1_22,
4740                 GP_1_21_FN,     GPSR1_21,
4741                 GP_1_20_FN,     GPSR1_20,
4742                 GP_1_19_FN,     GPSR1_19,
4743                 GP_1_18_FN,     GPSR1_18,
4744                 GP_1_17_FN,     GPSR1_17,
4745                 GP_1_16_FN,     GPSR1_16,
4746                 GP_1_15_FN,     GPSR1_15,
4747                 GP_1_14_FN,     GPSR1_14,
4748                 GP_1_13_FN,     GPSR1_13,
4749                 GP_1_12_FN,     GPSR1_12,
4750                 GP_1_11_FN,     GPSR1_11,
4751                 GP_1_10_FN,     GPSR1_10,
4752                 GP_1_9_FN,      GPSR1_9,
4753                 GP_1_8_FN,      GPSR1_8,
4754                 GP_1_7_FN,      GPSR1_7,
4755                 GP_1_6_FN,      GPSR1_6,
4756                 GP_1_5_FN,      GPSR1_5,
4757                 GP_1_4_FN,      GPSR1_4,
4758                 GP_1_3_FN,      GPSR1_3,
4759                 GP_1_2_FN,      GPSR1_2,
4760                 GP_1_1_FN,      GPSR1_1,
4761                 GP_1_0_FN,      GPSR1_0, }
4762         },
4763         { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
4764                 0, 0,
4765                 0, 0,
4766                 0, 0,
4767                 0, 0,
4768                 0, 0,
4769                 0, 0,
4770                 0, 0,
4771                 0, 0,
4772                 0, 0,
4773                 0, 0,
4774                 0, 0,
4775                 0, 0,
4776                 0, 0,
4777                 0, 0,
4778                 0, 0,
4779                 0, 0,
4780                 0, 0,
4781                 GP_2_14_FN,     GPSR2_14,
4782                 GP_2_13_FN,     GPSR2_13,
4783                 GP_2_12_FN,     GPSR2_12,
4784                 GP_2_11_FN,     GPSR2_11,
4785                 GP_2_10_FN,     GPSR2_10,
4786                 GP_2_9_FN,      GPSR2_9,
4787                 GP_2_8_FN,      GPSR2_8,
4788                 GP_2_7_FN,      GPSR2_7,
4789                 GP_2_6_FN,      GPSR2_6,
4790                 GP_2_5_FN,      GPSR2_5,
4791                 GP_2_4_FN,      GPSR2_4,
4792                 GP_2_3_FN,      GPSR2_3,
4793                 GP_2_2_FN,      GPSR2_2,
4794                 GP_2_1_FN,      GPSR2_1,
4795                 GP_2_0_FN,      GPSR2_0, }
4796         },
4797         { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
4798                 0, 0,
4799                 0, 0,
4800                 0, 0,
4801                 0, 0,
4802                 0, 0,
4803                 0, 0,
4804                 0, 0,
4805                 0, 0,
4806                 0, 0,
4807                 0, 0,
4808                 0, 0,
4809                 0, 0,
4810                 0, 0,
4811                 0, 0,
4812                 0, 0,
4813                 0, 0,
4814                 GP_3_15_FN,     GPSR3_15,
4815                 GP_3_14_FN,     GPSR3_14,
4816                 GP_3_13_FN,     GPSR3_13,
4817                 GP_3_12_FN,     GPSR3_12,
4818                 GP_3_11_FN,     GPSR3_11,
4819                 GP_3_10_FN,     GPSR3_10,
4820                 GP_3_9_FN,      GPSR3_9,
4821                 GP_3_8_FN,      GPSR3_8,
4822                 GP_3_7_FN,      GPSR3_7,
4823                 GP_3_6_FN,      GPSR3_6,
4824                 GP_3_5_FN,      GPSR3_5,
4825                 GP_3_4_FN,      GPSR3_4,
4826                 GP_3_3_FN,      GPSR3_3,
4827                 GP_3_2_FN,      GPSR3_2,
4828                 GP_3_1_FN,      GPSR3_1,
4829                 GP_3_0_FN,      GPSR3_0, }
4830         },
4831         { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
4832                 0, 0,
4833                 0, 0,
4834                 0, 0,
4835                 0, 0,
4836                 0, 0,
4837                 0, 0,
4838                 0, 0,
4839                 0, 0,
4840                 0, 0,
4841                 0, 0,
4842                 0, 0,
4843                 0, 0,
4844                 0, 0,
4845                 0, 0,
4846                 GP_4_17_FN,     GPSR4_17,
4847                 GP_4_16_FN,     GPSR4_16,
4848                 GP_4_15_FN,     GPSR4_15,
4849                 GP_4_14_FN,     GPSR4_14,
4850                 GP_4_13_FN,     GPSR4_13,
4851                 GP_4_12_FN,     GPSR4_12,
4852                 GP_4_11_FN,     GPSR4_11,
4853                 GP_4_10_FN,     GPSR4_10,
4854                 GP_4_9_FN,      GPSR4_9,
4855                 GP_4_8_FN,      GPSR4_8,
4856                 GP_4_7_FN,      GPSR4_7,
4857                 GP_4_6_FN,      GPSR4_6,
4858                 GP_4_5_FN,      GPSR4_5,
4859                 GP_4_4_FN,      GPSR4_4,
4860                 GP_4_3_FN,      GPSR4_3,
4861                 GP_4_2_FN,      GPSR4_2,
4862                 GP_4_1_FN,      GPSR4_1,
4863                 GP_4_0_FN,      GPSR4_0, }
4864         },
4865         { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
4866                 0, 0,
4867                 0, 0,
4868                 0, 0,
4869                 0, 0,
4870                 0, 0,
4871                 0, 0,
4872                 GP_5_25_FN,     GPSR5_25,
4873                 GP_5_24_FN,     GPSR5_24,
4874                 GP_5_23_FN,     GPSR5_23,
4875                 GP_5_22_FN,     GPSR5_22,
4876                 GP_5_21_FN,     GPSR5_21,
4877                 GP_5_20_FN,     GPSR5_20,
4878                 GP_5_19_FN,     GPSR5_19,
4879                 GP_5_18_FN,     GPSR5_18,
4880                 GP_5_17_FN,     GPSR5_17,
4881                 GP_5_16_FN,     GPSR5_16,
4882                 GP_5_15_FN,     GPSR5_15,
4883                 GP_5_14_FN,     GPSR5_14,
4884                 GP_5_13_FN,     GPSR5_13,
4885                 GP_5_12_FN,     GPSR5_12,
4886                 GP_5_11_FN,     GPSR5_11,
4887                 GP_5_10_FN,     GPSR5_10,
4888                 GP_5_9_FN,      GPSR5_9,
4889                 GP_5_8_FN,      GPSR5_8,
4890                 GP_5_7_FN,      GPSR5_7,
4891                 GP_5_6_FN,      GPSR5_6,
4892                 GP_5_5_FN,      GPSR5_5,
4893                 GP_5_4_FN,      GPSR5_4,
4894                 GP_5_3_FN,      GPSR5_3,
4895                 GP_5_2_FN,      GPSR5_2,
4896                 GP_5_1_FN,      GPSR5_1,
4897                 GP_5_0_FN,      GPSR5_0, }
4898         },
4899         { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
4900                 GP_6_31_FN,     GPSR6_31,
4901                 GP_6_30_FN,     GPSR6_30,
4902                 GP_6_29_FN,     GPSR6_29,
4903                 GP_6_28_FN,     GPSR6_28,
4904                 GP_6_27_FN,     GPSR6_27,
4905                 GP_6_26_FN,     GPSR6_26,
4906                 GP_6_25_FN,     GPSR6_25,
4907                 GP_6_24_FN,     GPSR6_24,
4908                 GP_6_23_FN,     GPSR6_23,
4909                 GP_6_22_FN,     GPSR6_22,
4910                 GP_6_21_FN,     GPSR6_21,
4911                 GP_6_20_FN,     GPSR6_20,
4912                 GP_6_19_FN,     GPSR6_19,
4913                 GP_6_18_FN,     GPSR6_18,
4914                 GP_6_17_FN,     GPSR6_17,
4915                 GP_6_16_FN,     GPSR6_16,
4916                 GP_6_15_FN,     GPSR6_15,
4917                 GP_6_14_FN,     GPSR6_14,
4918                 GP_6_13_FN,     GPSR6_13,
4919                 GP_6_12_FN,     GPSR6_12,
4920                 GP_6_11_FN,     GPSR6_11,
4921                 GP_6_10_FN,     GPSR6_10,
4922                 GP_6_9_FN,      GPSR6_9,
4923                 GP_6_8_FN,      GPSR6_8,
4924                 GP_6_7_FN,      GPSR6_7,
4925                 GP_6_6_FN,      GPSR6_6,
4926                 GP_6_5_FN,      GPSR6_5,
4927                 GP_6_4_FN,      GPSR6_4,
4928                 GP_6_3_FN,      GPSR6_3,
4929                 GP_6_2_FN,      GPSR6_2,
4930                 GP_6_1_FN,      GPSR6_1,
4931                 GP_6_0_FN,      GPSR6_0, }
4932         },
4933         { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
4934                 0, 0,
4935                 0, 0,
4936                 0, 0,
4937                 0, 0,
4938                 0, 0,
4939                 0, 0,
4940                 0, 0,
4941                 0, 0,
4942                 0, 0,
4943                 0, 0,
4944                 0, 0,
4945                 0, 0,
4946                 0, 0,
4947                 0, 0,
4948                 0, 0,
4949                 0, 0,
4950                 0, 0,
4951                 0, 0,
4952                 0, 0,
4953                 0, 0,
4954                 0, 0,
4955                 0, 0,
4956                 0, 0,
4957                 0, 0,
4958                 0, 0,
4959                 0, 0,
4960                 0, 0,
4961                 0, 0,
4962                 GP_7_3_FN, GPSR7_3,
4963                 GP_7_2_FN, GPSR7_2,
4964                 GP_7_1_FN, GPSR7_1,
4965                 GP_7_0_FN, GPSR7_0, }
4966         },
4967 #undef F_
4968 #undef FM
4969
4970 #define F_(x, y)        x,
4971 #define FM(x)           FN_##x,
4972         { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
4973                 IP0_31_28
4974                 IP0_27_24
4975                 IP0_23_20
4976                 IP0_19_16
4977                 IP0_15_12
4978                 IP0_11_8
4979                 IP0_7_4
4980                 IP0_3_0 }
4981         },
4982         { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
4983                 IP1_31_28
4984                 IP1_27_24
4985                 IP1_23_20
4986                 IP1_19_16
4987                 IP1_15_12
4988                 IP1_11_8
4989                 IP1_7_4
4990                 IP1_3_0 }
4991         },
4992         { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
4993                 IP2_31_28
4994                 IP2_27_24
4995                 IP2_23_20
4996                 IP2_19_16
4997                 IP2_15_12
4998                 IP2_11_8
4999                 IP2_7_4
5000                 IP2_3_0 }
5001         },
5002         { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
5003                 IP3_31_28
5004                 IP3_27_24
5005                 IP3_23_20
5006                 IP3_19_16
5007                 IP3_15_12
5008                 IP3_11_8
5009                 IP3_7_4
5010                 IP3_3_0 }
5011         },
5012         { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
5013                 IP4_31_28
5014                 IP4_27_24
5015                 IP4_23_20
5016                 IP4_19_16
5017                 IP4_15_12
5018                 IP4_11_8
5019                 IP4_7_4
5020                 IP4_3_0 }
5021         },
5022         { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
5023                 IP5_31_28
5024                 IP5_27_24
5025                 IP5_23_20
5026                 IP5_19_16
5027                 IP5_15_12
5028                 IP5_11_8
5029                 IP5_7_4
5030                 IP5_3_0 }
5031         },
5032         { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
5033                 IP6_31_28
5034                 IP6_27_24
5035                 IP6_23_20
5036                 IP6_19_16
5037                 IP6_15_12
5038                 IP6_11_8
5039                 IP6_7_4
5040                 IP6_3_0 }
5041         },
5042         { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
5043                 IP7_31_28
5044                 IP7_27_24
5045                 IP7_23_20
5046                 IP7_19_16
5047                 IP7_15_12
5048                 IP7_11_8
5049                 IP7_7_4
5050                 IP7_3_0 }
5051         },
5052         { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
5053                 IP8_31_28
5054                 IP8_27_24
5055                 IP8_23_20
5056                 IP8_19_16
5057                 IP8_15_12
5058                 IP8_11_8
5059                 IP8_7_4
5060                 IP8_3_0 }
5061         },
5062         { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
5063                 IP9_31_28
5064                 IP9_27_24
5065                 IP9_23_20
5066                 IP9_19_16
5067                 IP9_15_12
5068                 IP9_11_8
5069                 IP9_7_4
5070                 IP9_3_0 }
5071         },
5072         { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
5073                 IP10_31_28
5074                 IP10_27_24
5075                 IP10_23_20
5076                 IP10_19_16
5077                 IP10_15_12
5078                 IP10_11_8
5079                 IP10_7_4
5080                 IP10_3_0 }
5081         },
5082         { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
5083                 IP11_31_28
5084                 IP11_27_24
5085                 IP11_23_20
5086                 IP11_19_16
5087                 IP11_15_12
5088                 IP11_11_8
5089                 IP11_7_4
5090                 IP11_3_0 }
5091         },
5092         { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
5093                 IP12_31_28
5094                 IP12_27_24
5095                 IP12_23_20
5096                 IP12_19_16
5097                 IP12_15_12
5098                 IP12_11_8
5099                 IP12_7_4
5100                 IP12_3_0 }
5101         },
5102         { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
5103                 IP13_31_28
5104                 IP13_27_24
5105                 IP13_23_20
5106                 IP13_19_16
5107                 IP13_15_12
5108                 IP13_11_8
5109                 IP13_7_4
5110                 IP13_3_0 }
5111         },
5112         { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5113                 IP14_31_28
5114                 IP14_27_24
5115                 IP14_23_20
5116                 IP14_19_16
5117                 IP14_15_12
5118                 IP14_11_8
5119                 IP14_7_4
5120                 IP14_3_0 }
5121         },
5122         { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5123                 IP15_31_28
5124                 IP15_27_24
5125                 IP15_23_20
5126                 IP15_19_16
5127                 IP15_15_12
5128                 IP15_11_8
5129                 IP15_7_4
5130                 IP15_3_0 }
5131         },
5132         { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
5133                 IP16_31_28
5134                 IP16_27_24
5135                 IP16_23_20
5136                 IP16_19_16
5137                 IP16_15_12
5138                 IP16_11_8
5139                 IP16_7_4
5140                 IP16_3_0 }
5141         },
5142         { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
5143                 /* IP17_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5144                 /* IP17_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5145                 /* IP17_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5146                 /* IP17_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5147                 /* IP17_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5148                 /* IP17_11_8  */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5149                 IP17_7_4
5150                 IP17_3_0 }
5151         },
5152 #undef F_
5153 #undef FM
5154
5155 #define F_(x, y)        x,
5156 #define FM(x)           FN_##x,
5157         { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5158                              1, 2, 2, 3, 1, 1, 2, 1, 1, 1,
5159                              2, 1, 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1) {
5160                 0, 0, /* RESERVED 31 */
5161                 MOD_SEL0_30_29
5162                 MOD_SEL0_28_27
5163                 MOD_SEL0_26_25_24
5164                 MOD_SEL0_23
5165                 MOD_SEL0_22
5166                 MOD_SEL0_21_20
5167                 MOD_SEL0_19
5168                 MOD_SEL0_18
5169                 MOD_SEL0_17
5170                 MOD_SEL0_16_15
5171                 MOD_SEL0_14
5172                 MOD_SEL0_13
5173                 MOD_SEL0_12
5174                 MOD_SEL0_11
5175                 MOD_SEL0_10
5176                 MOD_SEL0_9
5177                 MOD_SEL0_8
5178                 MOD_SEL0_7_6
5179                 MOD_SEL0_5_4
5180                 MOD_SEL0_3
5181                 MOD_SEL0_2_1
5182                 0, 0, /* RESERVED 0 */ }
5183         },
5184         { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5185                              2, 3, 1, 2, 3, 1, 1, 2, 1,
5186                              2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
5187                 MOD_SEL1_31_30
5188                 MOD_SEL1_29_28_27
5189                 MOD_SEL1_26
5190                 MOD_SEL1_25_24
5191                 MOD_SEL1_23_22_21
5192                 MOD_SEL1_20
5193                 MOD_SEL1_19
5194                 MOD_SEL1_18_17
5195                 MOD_SEL1_16
5196                 MOD_SEL1_15_14
5197                 MOD_SEL1_13
5198                 MOD_SEL1_12
5199                 MOD_SEL1_11
5200                 MOD_SEL1_10
5201                 MOD_SEL1_9
5202                 0, 0, 0, 0, /* RESERVED 8, 7 */
5203                 MOD_SEL1_6
5204                 MOD_SEL1_5
5205                 MOD_SEL1_4
5206                 MOD_SEL1_3
5207                 MOD_SEL1_2
5208                 MOD_SEL1_1
5209                 MOD_SEL1_0 }
5210         },
5211         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5212                              1, 1, 1, 1, 4, 4, 4,
5213                              4, 4, 4, 1, 2, 1) {
5214                 MOD_SEL2_31
5215                 MOD_SEL2_30
5216                 MOD_SEL2_29
5217                 /* RESERVED 28 */
5218                 0, 0,
5219                 /* RESERVED 27, 26, 25, 24 */
5220                 0, 0, 0, 0, 0, 0, 0, 0,
5221                 0, 0, 0, 0, 0, 0, 0, 0,
5222                 /* RESERVED 23, 22, 21, 20 */
5223                 0, 0, 0, 0, 0, 0, 0, 0,
5224                 0, 0, 0, 0, 0, 0, 0, 0,
5225                 /* RESERVED 19, 18, 17, 16 */
5226                 0, 0, 0, 0, 0, 0, 0, 0,
5227                 0, 0, 0, 0, 0, 0, 0, 0,
5228                 /* RESERVED 15, 14, 13, 12 */
5229                 0, 0, 0, 0, 0, 0, 0, 0,
5230                 0, 0, 0, 0, 0, 0, 0, 0,
5231                 /* RESERVED 11, 10, 9, 8 */
5232                 0, 0, 0, 0, 0, 0, 0, 0,
5233                 0, 0, 0, 0, 0, 0, 0, 0,
5234                 /* RESERVED 7, 6, 5, 4 */
5235                 0, 0, 0, 0, 0, 0, 0, 0,
5236                 0, 0, 0, 0, 0, 0, 0, 0,
5237                 /* RESERVED 3 */
5238                 0, 0,
5239                 /* RESERVED 2, 1 */
5240                 0, 0, 0, 0,
5241                 MOD_SEL2_0 }
5242         },
5243         { },
5244 };
5245
5246 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5247         { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5248                 { PIN_NUMBER('W', 3),   28, 2 },        /* QSPI0_SPCLK */
5249                 { PIN_A_NUMBER('C', 5), 24, 2 },        /* QSPI0_MOSI_IO0 */
5250                 { PIN_A_NUMBER('B', 4), 20, 2 },        /* QSPI0_MISO_IO1 */
5251                 { PIN_NUMBER('Y', 6),   16, 2 },        /* QSPI0_IO2 */
5252                 { PIN_A_NUMBER('B', 6), 12, 2 },        /* QSPI0_IO3 */
5253                 { PIN_NUMBER('Y', 3),    8, 2 },        /* QSPI0_SSL */
5254                 { PIN_NUMBER('V', 3),    4, 2 },        /* QSPI1_SPCLK */
5255                 { PIN_A_NUMBER('C', 7),  0, 2 },        /* QSPI1_MOSI_IO0 */
5256         } },
5257         { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5258                 { PIN_A_NUMBER('E', 5), 28, 2 },        /* QSPI1_MISO_IO1 */
5259                 { PIN_A_NUMBER('E', 4), 24, 2 },        /* QSPI1_IO2 */
5260                 { PIN_A_NUMBER('C', 3), 20, 2 },        /* QSPI1_IO3 */
5261                 { PIN_NUMBER('V', 5),   16, 2 },        /* QSPI1_SSL */
5262                 { PIN_NUMBER('Y', 7),   12, 2 },        /* RPC_INT# */
5263                 { PIN_NUMBER('V', 6),    8, 2 },        /* RPC_WP# */
5264                 { PIN_NUMBER('V', 7),    4, 2 },        /* RPC_RESET# */
5265                 { PIN_NUMBER('A', 16),   0, 3 },        /* AVB_RX_CTL */
5266         } },
5267         { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5268                 { PIN_NUMBER('B', 19),  28, 3 },        /* AVB_RXC */
5269                 { PIN_NUMBER('A', 13),  24, 3 },        /* AVB_RD0 */
5270                 { PIN_NUMBER('B', 13),  20, 3 },        /* AVB_RD1 */
5271                 { PIN_NUMBER('A', 14),  16, 3 },        /* AVB_RD2 */
5272                 { PIN_NUMBER('B', 14),  12, 3 },        /* AVB_RD3 */
5273                 { PIN_NUMBER('A', 8),    8, 3 },        /* AVB_TX_CTL */
5274                 { PIN_NUMBER('A', 19),   4, 3 },        /* AVB_TXC */
5275                 { PIN_NUMBER('A', 18),   0, 3 },        /* AVB_TD0 */
5276         } },
5277         { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5278                 { PIN_NUMBER('B', 18),  28, 3 },        /* AVB_TD1 */
5279                 { PIN_NUMBER('A', 17),  24, 3 },        /* AVB_TD2 */
5280                 { PIN_NUMBER('B', 17),  20, 3 },        /* AVB_TD3 */
5281                 { PIN_NUMBER('A', 12),  16, 3 },        /* AVB_TXCREFCLK */
5282                 { PIN_NUMBER('A', 9),   12, 3 },        /* AVB_MDIO */
5283                 { RCAR_GP_PIN(2,  9),    8, 3 },        /* AVB_MDC */
5284                 { RCAR_GP_PIN(2, 10),    4, 3 },        /* AVB_MAGIC */
5285                 { RCAR_GP_PIN(2, 11),    0, 3 },        /* AVB_PHY_INT */
5286         } },
5287         { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5288                 { RCAR_GP_PIN(2, 12), 28, 3 },  /* AVB_LINK */
5289                 { RCAR_GP_PIN(2, 13), 24, 3 },  /* AVB_AVTP_MATCH */
5290                 { RCAR_GP_PIN(2, 14), 20, 3 },  /* AVB_AVTP_CAPTURE */
5291                 { RCAR_GP_PIN(2,  0), 16, 3 },  /* IRQ0 */
5292                 { RCAR_GP_PIN(2,  1), 12, 3 },  /* IRQ1 */
5293                 { RCAR_GP_PIN(2,  2),  8, 3 },  /* IRQ2 */
5294                 { RCAR_GP_PIN(2,  3),  4, 3 },  /* IRQ3 */
5295                 { RCAR_GP_PIN(2,  4),  0, 3 },  /* IRQ4 */
5296         } },
5297         { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5298                 { RCAR_GP_PIN(2,  5), 28, 3 },  /* IRQ5 */
5299                 { RCAR_GP_PIN(2,  6), 24, 3 },  /* PWM0 */
5300                 { RCAR_GP_PIN(2,  7), 20, 3 },  /* PWM1 */
5301                 { RCAR_GP_PIN(2,  8), 16, 3 },  /* PWM2 */
5302                 { RCAR_GP_PIN(1,  0), 12, 3 },  /* A0 */
5303                 { RCAR_GP_PIN(1,  1),  8, 3 },  /* A1 */
5304                 { RCAR_GP_PIN(1,  2),  4, 3 },  /* A2 */
5305                 { RCAR_GP_PIN(1,  3),  0, 3 },  /* A3 */
5306         } },
5307         { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5308                 { RCAR_GP_PIN(1,  4), 28, 3 },  /* A4 */
5309                 { RCAR_GP_PIN(1,  5), 24, 3 },  /* A5 */
5310                 { RCAR_GP_PIN(1,  6), 20, 3 },  /* A6 */
5311                 { RCAR_GP_PIN(1,  7), 16, 3 },  /* A7 */
5312                 { RCAR_GP_PIN(1,  8), 12, 3 },  /* A8 */
5313                 { RCAR_GP_PIN(1,  9),  8, 3 },  /* A9 */
5314                 { RCAR_GP_PIN(1, 10),  4, 3 },  /* A10 */
5315                 { RCAR_GP_PIN(1, 11),  0, 3 },  /* A11 */
5316         } },
5317         { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5318                 { RCAR_GP_PIN(1, 12), 28, 3 },  /* A12 */
5319                 { RCAR_GP_PIN(1, 13), 24, 3 },  /* A13 */
5320                 { RCAR_GP_PIN(1, 14), 20, 3 },  /* A14 */
5321                 { RCAR_GP_PIN(1, 15), 16, 3 },  /* A15 */
5322                 { RCAR_GP_PIN(1, 16), 12, 3 },  /* A16 */
5323                 { RCAR_GP_PIN(1, 17),  8, 3 },  /* A17 */
5324                 { RCAR_GP_PIN(1, 18),  4, 3 },  /* A18 */
5325                 { RCAR_GP_PIN(1, 19),  0, 3 },  /* A19 */
5326         } },
5327         { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5328                 { PIN_NUMBER('F', 1), 28, 3 },  /* CLKOUT */
5329                 { RCAR_GP_PIN(1, 20), 24, 3 },  /* CS0 */
5330                 { RCAR_GP_PIN(1, 21), 20, 3 },  /* CS1_A26 */
5331                 { RCAR_GP_PIN(1, 22), 16, 3 },  /* BS */
5332                 { RCAR_GP_PIN(1, 23), 12, 3 },  /* RD */
5333                 { RCAR_GP_PIN(1, 24),  8, 3 },  /* RD_WR */
5334                 { RCAR_GP_PIN(1, 25),  4, 3 },  /* WE0 */
5335                 { RCAR_GP_PIN(1, 26),  0, 3 },  /* WE1 */
5336         } },
5337         { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5338                 { RCAR_GP_PIN(1, 27), 28, 3 },  /* EX_WAIT0 */
5339                 { PIN_NUMBER('C', 1), 24, 3 },  /* PRESETOUT# */
5340                 { RCAR_GP_PIN(0,  0), 20, 3 },  /* D0 */
5341                 { RCAR_GP_PIN(0,  1), 16, 3 },  /* D1 */
5342                 { RCAR_GP_PIN(0,  2), 12, 3 },  /* D2 */
5343                 { RCAR_GP_PIN(0,  3),  8, 3 },  /* D3 */
5344                 { RCAR_GP_PIN(0,  4),  4, 3 },  /* D4 */
5345                 { RCAR_GP_PIN(0,  5),  0, 3 },  /* D5 */
5346         } },
5347         { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5348                 { RCAR_GP_PIN(0,  6), 28, 3 },  /* D6 */
5349                 { RCAR_GP_PIN(0,  7), 24, 3 },  /* D7 */
5350                 { RCAR_GP_PIN(0,  8), 20, 3 },  /* D8 */
5351                 { RCAR_GP_PIN(0,  9), 16, 3 },  /* D9 */
5352                 { RCAR_GP_PIN(0, 10), 12, 3 },  /* D10 */
5353                 { RCAR_GP_PIN(0, 11),  8, 3 },  /* D11 */
5354                 { RCAR_GP_PIN(0, 12),  4, 3 },  /* D12 */
5355                 { RCAR_GP_PIN(0, 13),  0, 3 },  /* D13 */
5356         } },
5357         { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5358                 { RCAR_GP_PIN(0, 14),   28, 3 },        /* D14 */
5359                 { RCAR_GP_PIN(0, 15),   24, 3 },        /* D15 */
5360                 { RCAR_GP_PIN(7,  0),   20, 3 },        /* AVS1 */
5361                 { RCAR_GP_PIN(7,  1),   16, 3 },        /* AVS2 */
5362                 { RCAR_GP_PIN(7,  2),   12, 3 },        /* HDMI0_CEC */
5363                 { RCAR_GP_PIN(7,  3),    8, 3 },        /* HDMI1_CEC */
5364                 { PIN_A_NUMBER('P', 7),  4, 2 },        /* DU_DOTCLKIN0 */
5365                 { PIN_A_NUMBER('P', 8),  0, 2 },        /* DU_DOTCLKIN1 */
5366         } },
5367         { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5368                 { PIN_A_NUMBER('R', 7),  28, 2 },       /* DU_DOTCLKIN2 */
5369                 { PIN_A_NUMBER('R', 8),  24, 2 },       /* DU_DOTCLKIN3 */
5370                 { PIN_A_NUMBER('D', 38), 20, 2 },       /* FSCLKST# */
5371                 { PIN_A_NUMBER('R', 30),  4, 2 },       /* TMS */
5372         } },
5373         { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5374                 { PIN_A_NUMBER('T', 28), 28, 2 },       /* TDO */
5375                 { PIN_A_NUMBER('T', 30), 24, 2 },       /* ASEBRK */
5376                 { RCAR_GP_PIN(3,  0),    20, 3 },       /* SD0_CLK */
5377                 { RCAR_GP_PIN(3,  1),    16, 3 },       /* SD0_CMD */
5378                 { RCAR_GP_PIN(3,  2),    12, 3 },       /* SD0_DAT0 */
5379                 { RCAR_GP_PIN(3,  3),     8, 3 },       /* SD0_DAT1 */
5380                 { RCAR_GP_PIN(3,  4),     4, 3 },       /* SD0_DAT2 */
5381                 { RCAR_GP_PIN(3,  5),     0, 3 },       /* SD0_DAT3 */
5382         } },
5383         { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5384                 { RCAR_GP_PIN(3,  6), 28, 3 },  /* SD1_CLK */
5385                 { RCAR_GP_PIN(3,  7), 24, 3 },  /* SD1_CMD */
5386                 { RCAR_GP_PIN(3,  8), 20, 3 },  /* SD1_DAT0 */
5387                 { RCAR_GP_PIN(3,  9), 16, 3 },  /* SD1_DAT1 */
5388                 { RCAR_GP_PIN(3, 10), 12, 3 },  /* SD1_DAT2 */
5389                 { RCAR_GP_PIN(3, 11),  8, 3 },  /* SD1_DAT3 */
5390                 { RCAR_GP_PIN(4,  0),  4, 3 },  /* SD2_CLK */
5391                 { RCAR_GP_PIN(4,  1),  0, 3 },  /* SD2_CMD */
5392         } },
5393         { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5394                 { RCAR_GP_PIN(4,  2), 28, 3 },  /* SD2_DAT0 */
5395                 { RCAR_GP_PIN(4,  3), 24, 3 },  /* SD2_DAT1 */
5396                 { RCAR_GP_PIN(4,  4), 20, 3 },  /* SD2_DAT2 */
5397                 { RCAR_GP_PIN(4,  5), 16, 3 },  /* SD2_DAT3 */
5398                 { RCAR_GP_PIN(4,  6), 12, 3 },  /* SD2_DS */
5399                 { RCAR_GP_PIN(4,  7),  8, 3 },  /* SD3_CLK */
5400                 { RCAR_GP_PIN(4,  8),  4, 3 },  /* SD3_CMD */
5401                 { RCAR_GP_PIN(4,  9),  0, 3 },  /* SD3_DAT0 */
5402         } },
5403         { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5404                 { RCAR_GP_PIN(4, 10), 28, 3 },  /* SD3_DAT1 */
5405                 { RCAR_GP_PIN(4, 11), 24, 3 },  /* SD3_DAT2 */
5406                 { RCAR_GP_PIN(4, 12), 20, 3 },  /* SD3_DAT3 */
5407                 { RCAR_GP_PIN(4, 13), 16, 3 },  /* SD3_DAT4 */
5408                 { RCAR_GP_PIN(4, 14), 12, 3 },  /* SD3_DAT5 */
5409                 { RCAR_GP_PIN(4, 15),  8, 3 },  /* SD3_DAT6 */
5410                 { RCAR_GP_PIN(4, 16),  4, 3 },  /* SD3_DAT7 */
5411                 { RCAR_GP_PIN(4, 17),  0, 3 },  /* SD3_DS */
5412         } },
5413         { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5414                 { RCAR_GP_PIN(3, 12), 28, 3 },  /* SD0_CD */
5415                 { RCAR_GP_PIN(3, 13), 24, 3 },  /* SD0_WP */
5416                 { RCAR_GP_PIN(3, 14), 20, 3 },  /* SD1_CD */
5417                 { RCAR_GP_PIN(3, 15), 16, 3 },  /* SD1_WP */
5418                 { RCAR_GP_PIN(5,  0), 12, 3 },  /* SCK0 */
5419                 { RCAR_GP_PIN(5,  1),  8, 3 },  /* RX0 */
5420                 { RCAR_GP_PIN(5,  2),  4, 3 },  /* TX0 */
5421                 { RCAR_GP_PIN(5,  3),  0, 3 },  /* CTS0 */
5422         } },
5423         { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5424                 { RCAR_GP_PIN(5,  4), 28, 3 },  /* RTS0_TANS */
5425                 { RCAR_GP_PIN(5,  5), 24, 3 },  /* RX1 */
5426                 { RCAR_GP_PIN(5,  6), 20, 3 },  /* TX1 */
5427                 { RCAR_GP_PIN(5,  7), 16, 3 },  /* CTS1 */
5428                 { RCAR_GP_PIN(5,  8), 12, 3 },  /* RTS1_TANS */
5429                 { RCAR_GP_PIN(5,  9),  8, 3 },  /* SCK2 */
5430                 { RCAR_GP_PIN(5, 10),  4, 3 },  /* TX2 */
5431                 { RCAR_GP_PIN(5, 11),  0, 3 },  /* RX2 */
5432         } },
5433         { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5434                 { RCAR_GP_PIN(5, 12), 28, 3 },  /* HSCK0 */
5435                 { RCAR_GP_PIN(5, 13), 24, 3 },  /* HRX0 */
5436                 { RCAR_GP_PIN(5, 14), 20, 3 },  /* HTX0 */
5437                 { RCAR_GP_PIN(5, 15), 16, 3 },  /* HCTS0 */
5438                 { RCAR_GP_PIN(5, 16), 12, 3 },  /* HRTS0 */
5439                 { RCAR_GP_PIN(5, 17),  8, 3 },  /* MSIOF0_SCK */
5440                 { RCAR_GP_PIN(5, 18),  4, 3 },  /* MSIOF0_SYNC */
5441                 { RCAR_GP_PIN(5, 19),  0, 3 },  /* MSIOF0_SS1 */
5442         } },
5443         { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5444                 { RCAR_GP_PIN(5, 20), 28, 3 },  /* MSIOF0_TXD */
5445                 { RCAR_GP_PIN(5, 21), 24, 3 },  /* MSIOF0_SS2 */
5446                 { RCAR_GP_PIN(5, 22), 20, 3 },  /* MSIOF0_RXD */
5447                 { RCAR_GP_PIN(5, 23), 16, 3 },  /* MLB_CLK */
5448                 { RCAR_GP_PIN(5, 24), 12, 3 },  /* MLB_SIG */
5449                 { RCAR_GP_PIN(5, 25),  8, 3 },  /* MLB_DAT */
5450                 { PIN_NUMBER('H', 37),  4, 3 }, /* MLB_REF */
5451                 { RCAR_GP_PIN(6,  0),  0, 3 },  /* SSI_SCK01239 */
5452         } },
5453         { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5454                 { RCAR_GP_PIN(6,  1), 28, 3 },  /* SSI_WS01239 */
5455                 { RCAR_GP_PIN(6,  2), 24, 3 },  /* SSI_SDATA0 */
5456                 { RCAR_GP_PIN(6,  3), 20, 3 },  /* SSI_SDATA1 */
5457                 { RCAR_GP_PIN(6,  4), 16, 3 },  /* SSI_SDATA2 */
5458                 { RCAR_GP_PIN(6,  5), 12, 3 },  /* SSI_SCK349 */
5459                 { RCAR_GP_PIN(6,  6),  8, 3 },  /* SSI_WS349 */
5460                 { RCAR_GP_PIN(6,  7),  4, 3 },  /* SSI_SDATA3 */
5461                 { RCAR_GP_PIN(6,  8),  0, 3 },  /* SSI_SCK4 */
5462         } },
5463         { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5464                 { RCAR_GP_PIN(6,  9), 28, 3 },  /* SSI_WS4 */
5465                 { RCAR_GP_PIN(6, 10), 24, 3 },  /* SSI_SDATA4 */
5466                 { RCAR_GP_PIN(6, 11), 20, 3 },  /* SSI_SCK5 */
5467                 { RCAR_GP_PIN(6, 12), 16, 3 },  /* SSI_WS5 */
5468                 { RCAR_GP_PIN(6, 13), 12, 3 },  /* SSI_SDATA5 */
5469                 { RCAR_GP_PIN(6, 14),  8, 3 },  /* SSI_SCK6 */
5470                 { RCAR_GP_PIN(6, 15),  4, 3 },  /* SSI_WS6 */
5471                 { RCAR_GP_PIN(6, 16),  0, 3 },  /* SSI_SDATA6 */
5472         } },
5473         { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5474                 { RCAR_GP_PIN(6, 17), 28, 3 },  /* SSI_SCK78 */
5475                 { RCAR_GP_PIN(6, 18), 24, 3 },  /* SSI_WS78 */
5476                 { RCAR_GP_PIN(6, 19), 20, 3 },  /* SSI_SDATA7 */
5477                 { RCAR_GP_PIN(6, 20), 16, 3 },  /* SSI_SDATA8 */
5478                 { RCAR_GP_PIN(6, 21), 12, 3 },  /* SSI_SDATA9 */
5479                 { RCAR_GP_PIN(6, 22),  8, 3 },  /* AUDIO_CLKA */
5480                 { RCAR_GP_PIN(6, 23),  4, 3 },  /* AUDIO_CLKB */
5481                 { RCAR_GP_PIN(6, 24),  0, 3 },  /* USB0_PWEN */
5482         } },
5483         { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5484                 { RCAR_GP_PIN(6, 25), 28, 3 },  /* USB0_OVC */
5485                 { RCAR_GP_PIN(6, 26), 24, 3 },  /* USB1_PWEN */
5486                 { RCAR_GP_PIN(6, 27), 20, 3 },  /* USB1_OVC */
5487                 { RCAR_GP_PIN(6, 28), 16, 3 },  /* USB30_PWEN */
5488                 { RCAR_GP_PIN(6, 29), 12, 3 },  /* USB30_OVC */
5489                 { RCAR_GP_PIN(6, 30),  8, 3 },  /* USB31_PWEN */
5490                 { RCAR_GP_PIN(6, 31),  4, 3 },  /* USB31_OVC */
5491         } },
5492         { },
5493 };
5494
5495 enum ioctrl_regs {
5496         POCCTRL,
5497 };
5498
5499 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5500         [POCCTRL] = { 0xe6060380, },
5501         { /* sentinel */ },
5502 };
5503
5504 static int r8a7795es1_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
5505                                      u32 *pocctrl)
5506 {
5507         int bit = -EINVAL;
5508
5509         *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5510
5511         if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5512                 bit = pin & 0x1f;
5513
5514         if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5515                 bit = (pin & 0x1f) + 12;
5516
5517         return bit;
5518 }
5519
5520 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5521         { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5522                 [ 0] = PIN_NUMBER('W', 3),      /* QSPI0_SPCLK */
5523                 [ 1] = PIN_A_NUMBER('C', 5),    /* QSPI0_MOSI_IO0 */
5524                 [ 2] = PIN_A_NUMBER('B', 4),    /* QSPI0_MISO_IO1 */
5525                 [ 3] = PIN_NUMBER('Y', 6),      /* QSPI0_IO2 */
5526                 [ 4] = PIN_A_NUMBER('B', 6),    /* QSPI0_IO3 */
5527                 [ 5] = PIN_NUMBER('Y', 3),      /* QSPI0_SSL */
5528                 [ 6] = PIN_NUMBER('V', 3),      /* QSPI1_SPCLK */
5529                 [ 7] = PIN_A_NUMBER('C', 7),    /* QSPI1_MOSI_IO0 */
5530                 [ 8] = PIN_A_NUMBER('E', 5),    /* QSPI1_MISO_IO1 */
5531                 [ 9] = PIN_A_NUMBER('E', 4),    /* QSPI1_IO2 */
5532                 [10] = PIN_A_NUMBER('C', 3),    /* QSPI1_IO3 */
5533                 [11] = PIN_NUMBER('V', 5),      /* QSPI1_SSL */
5534                 [12] = PIN_NUMBER('Y', 7),      /* RPC_INT# */
5535                 [13] = PIN_NUMBER('V', 6),      /* RPC_WP# */
5536                 [14] = PIN_NUMBER('V', 7),      /* RPC_RESET# */
5537                 [15] = PIN_NUMBER('A', 16),     /* AVB_RX_CTL */
5538                 [16] = PIN_NUMBER('B', 19),     /* AVB_RXC */
5539                 [17] = PIN_NUMBER('A', 13),     /* AVB_RD0 */
5540                 [18] = PIN_NUMBER('B', 13),     /* AVB_RD1 */
5541                 [19] = PIN_NUMBER('A', 14),     /* AVB_RD2 */
5542                 [20] = PIN_NUMBER('B', 14),     /* AVB_RD3 */
5543                 [21] = PIN_NUMBER('A', 8),      /* AVB_TX_CTL */
5544                 [22] = PIN_NUMBER('A', 19),     /* AVB_TXC */
5545                 [23] = PIN_NUMBER('A', 18),     /* AVB_TD0 */
5546                 [24] = PIN_NUMBER('B', 18),     /* AVB_TD1 */
5547                 [25] = PIN_NUMBER('A', 17),     /* AVB_TD2 */
5548                 [26] = PIN_NUMBER('B', 17),     /* AVB_TD3 */
5549                 [27] = PIN_NUMBER('A', 12),     /* AVB_TXCREFCLK */
5550                 [28] = PIN_NUMBER('A', 9),      /* AVB_MDIO */
5551                 [29] = RCAR_GP_PIN(2,  9),      /* AVB_MDC */
5552                 [30] = RCAR_GP_PIN(2, 10),      /* AVB_MAGIC */
5553                 [31] = RCAR_GP_PIN(2, 11),      /* AVB_PHY_INT */
5554         } },
5555         { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5556                 [ 0] = RCAR_GP_PIN(2, 12),      /* AVB_LINK */
5557                 [ 1] = RCAR_GP_PIN(2, 13),      /* AVB_AVTP_MATCH_A */
5558                 [ 2] = RCAR_GP_PIN(2, 14),      /* AVB_AVTP_CAPTURE_A */
5559                 [ 3] = RCAR_GP_PIN(2,  0),      /* IRQ0 */
5560                 [ 4] = RCAR_GP_PIN(2,  1),      /* IRQ1 */
5561                 [ 5] = RCAR_GP_PIN(2,  2),      /* IRQ2 */
5562                 [ 6] = RCAR_GP_PIN(2,  3),      /* IRQ3 */
5563                 [ 7] = RCAR_GP_PIN(2,  4),      /* IRQ4 */
5564                 [ 8] = RCAR_GP_PIN(2,  5),      /* IRQ5 */
5565                 [ 9] = RCAR_GP_PIN(2,  6),      /* PWM0 */
5566                 [10] = RCAR_GP_PIN(2,  7),      /* PWM1_A */
5567                 [11] = RCAR_GP_PIN(2,  8),      /* PWM2_A */
5568                 [12] = RCAR_GP_PIN(1,  0),      /* A0 */
5569                 [13] = RCAR_GP_PIN(1,  1),      /* A1 */
5570                 [14] = RCAR_GP_PIN(1,  2),      /* A2 */
5571                 [15] = RCAR_GP_PIN(1,  3),      /* A3 */
5572                 [16] = RCAR_GP_PIN(1,  4),      /* A4 */
5573                 [17] = RCAR_GP_PIN(1,  5),      /* A5 */
5574                 [18] = RCAR_GP_PIN(1,  6),      /* A6 */
5575                 [19] = RCAR_GP_PIN(1,  7),      /* A7 */
5576                 [20] = RCAR_GP_PIN(1,  8),      /* A8 */
5577                 [21] = RCAR_GP_PIN(1,  9),      /* A9 */
5578                 [22] = RCAR_GP_PIN(1, 10),      /* A10 */
5579                 [23] = RCAR_GP_PIN(1, 11),      /* A11 */
5580                 [24] = RCAR_GP_PIN(1, 12),      /* A12 */
5581                 [25] = RCAR_GP_PIN(1, 13),      /* A13 */
5582                 [26] = RCAR_GP_PIN(1, 14),      /* A14 */
5583                 [27] = RCAR_GP_PIN(1, 15),      /* A15 */
5584                 [28] = RCAR_GP_PIN(1, 16),      /* A16 */
5585                 [29] = RCAR_GP_PIN(1, 17),      /* A17 */
5586                 [30] = RCAR_GP_PIN(1, 18),      /* A18 */
5587                 [31] = RCAR_GP_PIN(1, 19),      /* A19 */
5588         } },
5589         { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5590                 [ 0] = PIN_NUMBER('F', 1),      /* CLKOUT */
5591                 [ 1] = RCAR_GP_PIN(1, 20),      /* CS0_N */
5592                 [ 2] = RCAR_GP_PIN(1, 21),      /* CS1_N_A26 */
5593                 [ 3] = RCAR_GP_PIN(1, 22),      /* BS_N */
5594                 [ 4] = RCAR_GP_PIN(1, 23),      /* RD_N */
5595                 [ 5] = RCAR_GP_PIN(1, 24),      /* RD_WR_N */
5596                 [ 6] = RCAR_GP_PIN(1, 25),      /* WE0_N */
5597                 [ 7] = RCAR_GP_PIN(1, 26),      /* WE1_N */
5598                 [ 8] = RCAR_GP_PIN(1, 27),      /* EX_WAIT0_A */
5599                 [ 9] = PIN_NUMBER('C', 1),      /* PRESETOUT# */
5600                 [10] = RCAR_GP_PIN(0,  0),      /* D0 */
5601                 [11] = RCAR_GP_PIN(0,  1),      /* D1 */
5602                 [12] = RCAR_GP_PIN(0,  2),      /* D2 */
5603                 [13] = RCAR_GP_PIN(0,  3),      /* D3 */
5604                 [14] = RCAR_GP_PIN(0,  4),      /* D4 */
5605                 [15] = RCAR_GP_PIN(0,  5),      /* D5 */
5606                 [16] = RCAR_GP_PIN(0,  6),      /* D6 */
5607                 [17] = RCAR_GP_PIN(0,  7),      /* D7 */
5608                 [18] = RCAR_GP_PIN(0,  8),      /* D8 */
5609                 [19] = RCAR_GP_PIN(0,  9),      /* D9 */
5610                 [20] = RCAR_GP_PIN(0, 10),      /* D10 */
5611                 [21] = RCAR_GP_PIN(0, 11),      /* D11 */
5612                 [22] = RCAR_GP_PIN(0, 12),      /* D12 */
5613                 [23] = RCAR_GP_PIN(0, 13),      /* D13 */
5614                 [24] = RCAR_GP_PIN(0, 14),      /* D14 */
5615                 [25] = RCAR_GP_PIN(0, 15),      /* D15 */
5616                 [26] = RCAR_GP_PIN(7,  0),      /* AVS1 */
5617                 [27] = RCAR_GP_PIN(7,  1),      /* AVS2 */
5618                 [28] = RCAR_GP_PIN(7,  2),      /* HDMI0_CEC */
5619                 [29] = RCAR_GP_PIN(7,  3),      /* HDMI1_CEC */
5620                 [30] = PIN_A_NUMBER('P', 7),    /* DU_DOTCLKIN0 */
5621                 [31] = PIN_A_NUMBER('P', 8),    /* DU_DOTCLKIN1 */
5622         } },
5623         { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5624                 [ 0] = PIN_A_NUMBER('R', 7),    /* DU_DOTCLKIN2 */
5625                 [ 1] = PIN_A_NUMBER('R', 8),    /* DU_DOTCLKIN3 */
5626                 [ 2] = PIN_A_NUMBER('D', 38),   /* FSCLKST# */
5627                 [ 3] = PIN_A_NUMBER('D', 39),   /* EXTALR*/
5628                 [ 4] = PIN_A_NUMBER('R', 26),   /* TRST# */
5629                 [ 5] = PIN_A_NUMBER('T', 27),   /* TCK */
5630                 [ 6] = PIN_A_NUMBER('R', 30),   /* TMS */
5631                 [ 7] = PIN_A_NUMBER('R', 29),   /* TDI */
5632                 [ 8] = PIN_NONE,
5633                 [ 9] = PIN_A_NUMBER('T', 30),   /* ASEBRK */
5634                 [10] = RCAR_GP_PIN(3,  0),      /* SD0_CLK */
5635                 [11] = RCAR_GP_PIN(3,  1),      /* SD0_CMD */
5636                 [12] = RCAR_GP_PIN(3,  2),      /* SD0_DAT0 */
5637                 [13] = RCAR_GP_PIN(3,  3),      /* SD0_DAT1 */
5638                 [14] = RCAR_GP_PIN(3,  4),      /* SD0_DAT2 */
5639                 [15] = RCAR_GP_PIN(3,  5),      /* SD0_DAT3 */
5640                 [16] = RCAR_GP_PIN(3,  6),      /* SD1_CLK */
5641                 [17] = RCAR_GP_PIN(3,  7),      /* SD1_CMD */
5642                 [18] = RCAR_GP_PIN(3,  8),      /* SD1_DAT0 */
5643                 [19] = RCAR_GP_PIN(3,  9),      /* SD1_DAT1 */
5644                 [20] = RCAR_GP_PIN(3, 10),      /* SD1_DAT2 */
5645                 [21] = RCAR_GP_PIN(3, 11),      /* SD1_DAT3 */
5646                 [22] = RCAR_GP_PIN(4,  0),      /* SD2_CLK */
5647                 [23] = RCAR_GP_PIN(4,  1),      /* SD2_CMD */
5648                 [24] = RCAR_GP_PIN(4,  2),      /* SD2_DAT0 */
5649                 [25] = RCAR_GP_PIN(4,  3),      /* SD2_DAT1 */
5650                 [26] = RCAR_GP_PIN(4,  4),      /* SD2_DAT2 */
5651                 [27] = RCAR_GP_PIN(4,  5),      /* SD2_DAT3 */
5652                 [28] = RCAR_GP_PIN(4,  6),      /* SD2_DS */
5653                 [29] = RCAR_GP_PIN(4,  7),      /* SD3_CLK */
5654                 [30] = RCAR_GP_PIN(4,  8),      /* SD3_CMD */
5655                 [31] = RCAR_GP_PIN(4,  9),      /* SD3_DAT0 */
5656         } },
5657         { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5658                 [ 0] = RCAR_GP_PIN(4, 10),      /* SD3_DAT1 */
5659                 [ 1] = RCAR_GP_PIN(4, 11),      /* SD3_DAT2 */
5660                 [ 2] = RCAR_GP_PIN(4, 12),      /* SD3_DAT3 */
5661                 [ 3] = RCAR_GP_PIN(4, 13),      /* SD3_DAT4 */
5662                 [ 4] = RCAR_GP_PIN(4, 14),      /* SD3_DAT5 */
5663                 [ 5] = RCAR_GP_PIN(4, 15),      /* SD3_DAT6 */
5664                 [ 6] = RCAR_GP_PIN(4, 16),      /* SD3_DAT7 */
5665                 [ 7] = RCAR_GP_PIN(4, 17),      /* SD3_DS */
5666                 [ 8] = RCAR_GP_PIN(3, 12),      /* SD0_CD */
5667                 [ 9] = RCAR_GP_PIN(3, 13),      /* SD0_WP */
5668                 [10] = RCAR_GP_PIN(3, 14),      /* SD1_CD */
5669                 [11] = RCAR_GP_PIN(3, 15),      /* SD1_WP */
5670                 [12] = RCAR_GP_PIN(5,  0),      /* SCK0 */
5671                 [13] = RCAR_GP_PIN(5,  1),      /* RX0 */
5672                 [14] = RCAR_GP_PIN(5,  2),      /* TX0 */
5673                 [15] = RCAR_GP_PIN(5,  3),      /* CTS0_N */
5674                 [16] = RCAR_GP_PIN(5,  4),      /* RTS0_N_TANS */
5675                 [17] = RCAR_GP_PIN(5,  5),      /* RX1_A */
5676                 [18] = RCAR_GP_PIN(5,  6),      /* TX1_A */
5677                 [19] = RCAR_GP_PIN(5,  7),      /* CTS1_N */
5678                 [20] = RCAR_GP_PIN(5,  8),      /* RTS1_N_TANS */
5679                 [21] = RCAR_GP_PIN(5,  9),      /* SCK2 */
5680                 [22] = RCAR_GP_PIN(5, 10),      /* TX2_A */
5681                 [23] = RCAR_GP_PIN(5, 11),      /* RX2_A */
5682                 [24] = RCAR_GP_PIN(5, 12),      /* HSCK0 */
5683                 [25] = RCAR_GP_PIN(5, 13),      /* HRX0 */
5684                 [26] = RCAR_GP_PIN(5, 14),      /* HTX0 */
5685                 [27] = RCAR_GP_PIN(5, 15),      /* HCTS0_N */
5686                 [28] = RCAR_GP_PIN(5, 16),      /* HRTS0_N */
5687                 [29] = RCAR_GP_PIN(5, 17),      /* MSIOF0_SCK */
5688                 [30] = RCAR_GP_PIN(5, 18),      /* MSIOF0_SYNC */
5689                 [31] = RCAR_GP_PIN(5, 19),      /* MSIOF0_SS1 */
5690         } },
5691         { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
5692                 [ 0] = RCAR_GP_PIN(5, 20),      /* MSIOF0_TXD */
5693                 [ 1] = RCAR_GP_PIN(5, 21),      /* MSIOF0_SS2 */
5694                 [ 2] = RCAR_GP_PIN(5, 22),      /* MSIOF0_RXD */
5695                 [ 3] = RCAR_GP_PIN(5, 23),      /* MLB_CLK */
5696                 [ 4] = RCAR_GP_PIN(5, 24),      /* MLB_SIG */
5697                 [ 5] = RCAR_GP_PIN(5, 25),      /* MLB_DAT */
5698                 [ 6] = PIN_NUMBER('H', 37),     /* MLB_REF */
5699                 [ 7] = RCAR_GP_PIN(6,  0),      /* SSI_SCK01239 */
5700                 [ 8] = RCAR_GP_PIN(6,  1),      /* SSI_WS01239 */
5701                 [ 9] = RCAR_GP_PIN(6,  2),      /* SSI_SDATA0 */
5702                 [10] = RCAR_GP_PIN(6,  3),      /* SSI_SDATA1_A */
5703                 [11] = RCAR_GP_PIN(6,  4),      /* SSI_SDATA2_A */
5704                 [12] = RCAR_GP_PIN(6,  5),      /* SSI_SCK349 */
5705                 [13] = RCAR_GP_PIN(6,  6),      /* SSI_WS349 */
5706                 [14] = RCAR_GP_PIN(6,  7),      /* SSI_SDATA3 */
5707                 [15] = RCAR_GP_PIN(6,  8),      /* SSI_SCK4 */
5708                 [16] = RCAR_GP_PIN(6,  9),      /* SSI_WS4 */
5709                 [17] = RCAR_GP_PIN(6, 10),      /* SSI_SDATA4 */
5710                 [18] = RCAR_GP_PIN(6, 11),      /* SSI_SCK5 */
5711                 [19] = RCAR_GP_PIN(6, 12),      /* SSI_WS5 */
5712                 [20] = RCAR_GP_PIN(6, 13),      /* SSI_SDATA5 */
5713                 [21] = RCAR_GP_PIN(6, 14),      /* SSI_SCK6 */
5714                 [22] = RCAR_GP_PIN(6, 15),      /* SSI_WS6 */
5715                 [23] = RCAR_GP_PIN(6, 16),      /* SSI_SDATA6 */
5716                 [24] = RCAR_GP_PIN(6, 17),      /* SSI_SCK78 */
5717                 [25] = RCAR_GP_PIN(6, 18),      /* SSI_WS78 */
5718                 [26] = RCAR_GP_PIN(6, 19),      /* SSI_SDATA7 */
5719                 [27] = RCAR_GP_PIN(6, 20),      /* SSI_SDATA8 */
5720                 [28] = RCAR_GP_PIN(6, 21),      /* SSI_SDATA9_A */
5721                 [29] = RCAR_GP_PIN(6, 22),      /* AUDIO_CLKA_A */
5722                 [30] = RCAR_GP_PIN(6, 23),      /* AUDIO_CLKB_B */
5723                 [31] = RCAR_GP_PIN(6, 24),      /* USB0_PWEN */
5724         } },
5725         { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
5726                 [ 0] = RCAR_GP_PIN(6, 25),      /* USB0_OVC */
5727                 [ 1] = RCAR_GP_PIN(6, 26),      /* USB1_PWEN */
5728                 [ 2] = RCAR_GP_PIN(6, 27),      /* USB1_OVC */
5729                 [ 3] = RCAR_GP_PIN(6, 28),      /* USB30_PWEN */
5730                 [ 4] = RCAR_GP_PIN(6, 29),      /* USB30_OVC */
5731                 [ 5] = RCAR_GP_PIN(6, 30),      /* USB31_PWEN */
5732                 [ 6] = RCAR_GP_PIN(6, 31),      /* USB31_OVC */
5733                 [ 7] = PIN_NONE,
5734                 [ 8] = PIN_NONE,
5735                 [ 9] = PIN_NONE,
5736                 [10] = PIN_NONE,
5737                 [11] = PIN_NONE,
5738                 [12] = PIN_NONE,
5739                 [13] = PIN_NONE,
5740                 [14] = PIN_NONE,
5741                 [15] = PIN_NONE,
5742                 [16] = PIN_NONE,
5743                 [17] = PIN_NONE,
5744                 [18] = PIN_NONE,
5745                 [19] = PIN_NONE,
5746                 [20] = PIN_NONE,
5747                 [21] = PIN_NONE,
5748                 [22] = PIN_NONE,
5749                 [23] = PIN_NONE,
5750                 [24] = PIN_NONE,
5751                 [25] = PIN_NONE,
5752                 [26] = PIN_NONE,
5753                 [27] = PIN_NONE,
5754                 [28] = PIN_NONE,
5755                 [29] = PIN_NONE,
5756                 [30] = PIN_NONE,
5757                 [31] = PIN_NONE,
5758         } },
5759         { /* sentinel */ },
5760 };
5761
5762 static unsigned int r8a7795es1_pinmux_get_bias(struct sh_pfc *pfc,
5763                                                unsigned int pin)
5764 {
5765         const struct pinmux_bias_reg *reg;
5766         unsigned int bit;
5767
5768         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5769         if (!reg)
5770                 return PIN_CONFIG_BIAS_DISABLE;
5771
5772         if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
5773                 return PIN_CONFIG_BIAS_DISABLE;
5774         else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
5775                 return PIN_CONFIG_BIAS_PULL_UP;
5776         else
5777                 return PIN_CONFIG_BIAS_PULL_DOWN;
5778 }
5779
5780 static void r8a7795es1_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5781                                        unsigned int bias)
5782 {
5783         const struct pinmux_bias_reg *reg;
5784         u32 enable, updown;
5785         unsigned int bit;
5786
5787         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5788         if (!reg)
5789                 return;
5790
5791         enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
5792         if (bias != PIN_CONFIG_BIAS_DISABLE)
5793                 enable |= BIT(bit);
5794
5795         updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
5796         if (bias == PIN_CONFIG_BIAS_PULL_UP)
5797                 updown |= BIT(bit);
5798
5799         sh_pfc_write(pfc, reg->pud, updown);
5800         sh_pfc_write(pfc, reg->puen, enable);
5801 }
5802
5803 static const struct sh_pfc_soc_operations r8a7795es1_pinmux_ops = {
5804         .pin_to_pocctrl = r8a7795es1_pin_to_pocctrl,
5805         .get_bias = r8a7795es1_pinmux_get_bias,
5806         .set_bias = r8a7795es1_pinmux_set_bias,
5807 };
5808
5809 const struct sh_pfc_soc_info r8a7795es1_pinmux_info = {
5810         .name = "r8a77950_pfc",
5811         .ops = &r8a7795es1_pinmux_ops,
5812         .unlock_reg = 0xe6060000, /* PMMR */
5813
5814         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5815
5816         .pins = pinmux_pins,
5817         .nr_pins = ARRAY_SIZE(pinmux_pins),
5818         .groups = pinmux_groups,
5819         .nr_groups = ARRAY_SIZE(pinmux_groups),
5820         .functions = pinmux_functions,
5821         .nr_functions = ARRAY_SIZE(pinmux_functions),
5822
5823         .cfg_regs = pinmux_config_regs,
5824         .drive_regs = pinmux_drive_regs,
5825         .bias_regs = pinmux_bias_regs,
5826         .ioctrl_regs = pinmux_ioctrl_regs,
5827
5828         .pinmux_data = pinmux_data,
5829         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5830 };