drivers/pinctrl/sh-pfc/pfc-r8a7795.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * R8A7795 ES2.0+ processor support - PFC hardware block.
   4  *
   5  * Copyright (C) 2015-2017 Renesas Electronics Corporation
   6  */
   7
   8 #include <linux/kernel.h>
   9 #include <linux/sys_soc.h>
  10
  11 #include "core.h"
  12 #include "sh_pfc.h"
  13
  14 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
  15                    SH_PFC_PIN_CFG_PULL_UP | \
  16                    SH_PFC_PIN_CFG_PULL_DOWN)
  17
  18 #define CPU_ALL_PORT(fn, sfx)                                           \
  19         PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),  \
  20         PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS),  \
  21         PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),  \
  22         PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  23         PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),       \
  24         PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),       \
  25         PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),       \
  26         PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),       \
  27         PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  28         PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),  \
  29         PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),  \
  30         PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
  31 /*
  32  * F_() : just information
  33  * FM() : macro for FN_xxx / xxx_MARK
  34  */
  35
  36 /* GPSR0 */
  37 #define GPSR0_15        F_(D15,                 IP7_11_8)
  38 #define GPSR0_14        F_(D14,                 IP7_7_4)
  39 #define GPSR0_13        F_(D13,                 IP7_3_0)
  40 #define GPSR0_12        F_(D12,                 IP6_31_28)
  41 #define GPSR0_11        F_(D11,                 IP6_27_24)
  42 #define GPSR0_10        F_(D10,                 IP6_23_20)
  43 #define GPSR0_9         F_(D9,                  IP6_19_16)
  44 #define GPSR0_8         F_(D8,                  IP6_15_12)
  45 #define GPSR0_7         F_(D7,                  IP6_11_8)
  46 #define GPSR0_6         F_(D6,                  IP6_7_4)
  47 #define GPSR0_5         F_(D5,                  IP6_3_0)
  48 #define GPSR0_4         F_(D4,                  IP5_31_28)
  49 #define GPSR0_3         F_(D3,                  IP5_27_24)
  50 #define GPSR0_2         F_(D2,                  IP5_23_20)
  51 #define GPSR0_1         F_(D1,                  IP5_19_16)
  52 #define GPSR0_0         F_(D0,                  IP5_15_12)
  53
  54 /* GPSR1 */
  55 #define GPSR1_28        FM(CLKOUT)
  56 #define GPSR1_27        F_(EX_WAIT0_A,          IP5_11_8)
  57 #define GPSR1_26        F_(WE1_N,               IP5_7_4)
  58 #define GPSR1_25        F_(WE0_N,               IP5_3_0)
  59 #define GPSR1_24        F_(RD_WR_N,             IP4_31_28)
  60 #define GPSR1_23        F_(RD_N,                IP4_27_24)
  61 #define GPSR1_22        F_(BS_N,                IP4_23_20)
  62 #define GPSR1_21        F_(CS1_N,               IP4_19_16)
  63 #define GPSR1_20        F_(CS0_N,               IP4_15_12)
  64 #define GPSR1_19        F_(A19,                 IP4_11_8)
  65 #define GPSR1_18        F_(A18,                 IP4_7_4)
  66 #define GPSR1_17        F_(A17,                 IP4_3_0)
  67 #define GPSR1_16        F_(A16,                 IP3_31_28)
  68 #define GPSR1_15        F_(A15,                 IP3_27_24)
  69 #define GPSR1_14        F_(A14,                 IP3_23_20)
  70 #define GPSR1_13        F_(A13,                 IP3_19_16)
  71 #define GPSR1_12        F_(A12,                 IP3_15_12)
  72 #define GPSR1_11        F_(A11,                 IP3_11_8)
  73 #define GPSR1_10        F_(A10,                 IP3_7_4)
  74 #define GPSR1_9         F_(A9,                  IP3_3_0)
  75 #define GPSR1_8         F_(A8,                  IP2_31_28)
  76 #define GPSR1_7         F_(A7,                  IP2_27_24)
  77 #define GPSR1_6         F_(A6,                  IP2_23_20)
  78 #define GPSR1_5         F_(A5,                  IP2_19_16)
  79 #define GPSR1_4         F_(A4,                  IP2_15_12)
  80 #define GPSR1_3         F_(A3,                  IP2_11_8)
  81 #define GPSR1_2         F_(A2,                  IP2_7_4)
  82 #define GPSR1_1         F_(A1,                  IP2_3_0)
  83 #define GPSR1_0         F_(A0,                  IP1_31_28)
  84
  85 /* GPSR2 */
  86 #define GPSR2_14        F_(AVB_AVTP_CAPTURE_A,  IP0_23_20)
  87 #define GPSR2_13        F_(AVB_AVTP_MATCH_A,    IP0_19_16)
  88 #define GPSR2_12        F_(AVB_LINK,            IP0_15_12)
  89 #define GPSR2_11        F_(AVB_PHY_INT,         IP0_11_8)
  90 #define GPSR2_10        F_(AVB_MAGIC,           IP0_7_4)
  91 #define GPSR2_9         F_(AVB_MDC,             IP0_3_0)
  92 #define GPSR2_8         F_(PWM2_A,              IP1_27_24)
  93 #define GPSR2_7         F_(PWM1_A,              IP1_23_20)
  94 #define GPSR2_6         F_(PWM0,                IP1_19_16)
  95 #define GPSR2_5         F_(IRQ5,                IP1_15_12)
  96 #define GPSR2_4         F_(IRQ4,                IP1_11_8)
  97 #define GPSR2_3         F_(IRQ3,                IP1_7_4)
  98 #define GPSR2_2         F_(IRQ2,                IP1_3_0)
  99 #define GPSR2_1         F_(IRQ1,                IP0_31_28)
 100 #define GPSR2_0         F_(IRQ0,                IP0_27_24)
 101
 102 /* GPSR3 */
 103 #define GPSR3_15        F_(SD1_WP,              IP11_23_20)
 104 #define GPSR3_14        F_(SD1_CD,              IP11_19_16)
 105 #define GPSR3_13        F_(SD0_WP,              IP11_15_12)
 106 #define GPSR3_12        F_(SD0_CD,              IP11_11_8)
 107 #define GPSR3_11        F_(SD1_DAT3,            IP8_31_28)
 108 #define GPSR3_10        F_(SD1_DAT2,            IP8_27_24)
 109 #define GPSR3_9         F_(SD1_DAT1,            IP8_23_20)
 110 #define GPSR3_8         F_(SD1_DAT0,            IP8_19_16)
 111 #define GPSR3_7         F_(SD1_CMD,             IP8_15_12)
 112 #define GPSR3_6         F_(SD1_CLK,             IP8_11_8)
 113 #define GPSR3_5         F_(SD0_DAT3,            IP8_7_4)
 114 #define GPSR3_4         F_(SD0_DAT2,            IP8_3_0)
 115 #define GPSR3_3         F_(SD0_DAT1,            IP7_31_28)
 116 #define GPSR3_2         F_(SD0_DAT0,            IP7_27_24)
 117 #define GPSR3_1         F_(SD0_CMD,             IP7_23_20)
 118 #define GPSR3_0         F_(SD0_CLK,             IP7_19_16)
 119
 120 /* GPSR4 */
 121 #define GPSR4_17        F_(SD3_DS,              IP11_7_4)
 122 #define GPSR4_16        F_(SD3_DAT7,            IP11_3_0)
 123 #define GPSR4_15        F_(SD3_DAT6,            IP10_31_28)
 124 #define GPSR4_14        F_(SD3_DAT5,            IP10_27_24)
 125 #define GPSR4_13        F_(SD3_DAT4,            IP10_23_20)
 126 #define GPSR4_12        F_(SD3_DAT3,            IP10_19_16)
 127 #define GPSR4_11        F_(SD3_DAT2,            IP10_15_12)
 128 #define GPSR4_10        F_(SD3_DAT1,            IP10_11_8)
 129 #define GPSR4_9         F_(SD3_DAT0,            IP10_7_4)
 130 #define GPSR4_8         F_(SD3_CMD,             IP10_3_0)
 131 #define GPSR4_7         F_(SD3_CLK,             IP9_31_28)
 132 #define GPSR4_6         F_(SD2_DS,              IP9_27_24)
 133 #define GPSR4_5         F_(SD2_DAT3,            IP9_23_20)
 134 #define GPSR4_4         F_(SD2_DAT2,            IP9_19_16)
 135 #define GPSR4_3         F_(SD2_DAT1,            IP9_15_12)
 136 #define GPSR4_2         F_(SD2_DAT0,            IP9_11_8)
 137 #define GPSR4_1         F_(SD2_CMD,             IP9_7_4)
 138 #define GPSR4_0         F_(SD2_CLK,             IP9_3_0)
 139
 140 /* GPSR5 */
 141 #define GPSR5_25        F_(MLB_DAT,             IP14_19_16)
 142 #define GPSR5_24        F_(MLB_SIG,             IP14_15_12)
 143 #define GPSR5_23        F_(MLB_CLK,             IP14_11_8)
 144 #define GPSR5_22        FM(MSIOF0_RXD)
 145 #define GPSR5_21        F_(MSIOF0_SS2,          IP14_7_4)
 146 #define GPSR5_20        FM(MSIOF0_TXD)
 147 #define GPSR5_19        F_(MSIOF0_SS1,          IP14_3_0)
 148 #define GPSR5_18        F_(MSIOF0_SYNC,         IP13_31_28)
 149 #define GPSR5_17        FM(MSIOF0_SCK)
 150 #define GPSR5_16        F_(HRTS0_N,             IP13_27_24)
 151 #define GPSR5_15        F_(HCTS0_N,             IP13_23_20)
 152 #define GPSR5_14        F_(HTX0,                IP13_19_16)
 153 #define GPSR5_13        F_(HRX0,                IP13_15_12)
 154 #define GPSR5_12        F_(HSCK0,               IP13_11_8)
 155 #define GPSR5_11        F_(RX2_A,               IP13_7_4)
 156 #define GPSR5_10        F_(TX2_A,               IP13_3_0)
 157 #define GPSR5_9         F_(SCK2,                IP12_31_28)
 158 #define GPSR5_8         F_(RTS1_N,              IP12_27_24)
 159 #define GPSR5_7         F_(CTS1_N,              IP12_23_20)
 160 #define GPSR5_6         F_(TX1_A,               IP12_19_16)
 161 #define GPSR5_5         F_(RX1_A,               IP12_15_12)
 162 #define GPSR5_4         F_(RTS0_N,              IP12_11_8)
 163 #define GPSR5_3         F_(CTS0_N,              IP12_7_4)
 164 #define GPSR5_2         F_(TX0,                 IP12_3_0)
 165 #define GPSR5_1         F_(RX0,                 IP11_31_28)
 166 #define GPSR5_0         F_(SCK0,                IP11_27_24)
 167
 168 /* GPSR6 */
 169 #define GPSR6_31        F_(USB2_CH3_OVC,        IP18_7_4)
 170 #define GPSR6_30        F_(USB2_CH3_PWEN,       IP18_3_0)
 171 #define GPSR6_29        F_(USB30_OVC,           IP17_31_28)
 172 #define GPSR6_28        F_(USB30_PWEN,          IP17_27_24)
 173 #define GPSR6_27        F_(USB1_OVC,            IP17_23_20)
 174 #define GPSR6_26        F_(USB1_PWEN,           IP17_19_16)
 175 #define GPSR6_25        F_(USB0_OVC,            IP17_15_12)
 176 #define GPSR6_24        F_(USB0_PWEN,           IP17_11_8)
 177 #define GPSR6_23        F_(AUDIO_CLKB_B,        IP17_7_4)
 178 #define GPSR6_22        F_(AUDIO_CLKA_A,        IP17_3_0)
 179 #define GPSR6_21        F_(SSI_SDATA9_A,        IP16_31_28)
 180 #define GPSR6_20        F_(SSI_SDATA8,          IP16_27_24)
 181 #define GPSR6_19        F_(SSI_SDATA7,          IP16_23_20)
 182 #define GPSR6_18        F_(SSI_WS78,            IP16_19_16)
 183 #define GPSR6_17        F_(SSI_SCK78,           IP16_15_12)
 184 #define GPSR6_16        F_(SSI_SDATA6,          IP16_11_8)
 185 #define GPSR6_15        F_(SSI_WS6,             IP16_7_4)
 186 #define GPSR6_14        F_(SSI_SCK6,            IP16_3_0)
 187 #define GPSR6_13        FM(SSI_SDATA5)
 188 #define GPSR6_12        FM(SSI_WS5)
 189 #define GPSR6_11        FM(SSI_SCK5)
 190 #define GPSR6_10        F_(SSI_SDATA4,          IP15_31_28)
 191 #define GPSR6_9         F_(SSI_WS4,             IP15_27_24)
 192 #define GPSR6_8         F_(SSI_SCK4,            IP15_23_20)
 193 #define GPSR6_7         F_(SSI_SDATA3,          IP15_19_16)
 194 #define GPSR6_6         F_(SSI_WS349,           IP15_15_12)
 195 #define GPSR6_5         F_(SSI_SCK349,          IP15_11_8)
 196 #define GPSR6_4         F_(SSI_SDATA2_A,        IP15_7_4)
 197 #define GPSR6_3         F_(SSI_SDATA1_A,        IP15_3_0)
 198 #define GPSR6_2         F_(SSI_SDATA0,          IP14_31_28)
 199 #define GPSR6_1         F_(SSI_WS01239,         IP14_27_24)
 200 #define GPSR6_0         F_(SSI_SCK01239,                IP14_23_20)
 201
 202 /* GPSR7 */
 203 #define GPSR7_3         FM(HDMI1_CEC)
 204 #define GPSR7_2         FM(HDMI0_CEC)
 205 #define GPSR7_1         FM(AVS2)
 206 #define GPSR7_0         FM(AVS1)
 207
 208
 209 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 210 #define IP0_3_0         FM(AVB_MDC)             F_(0, 0)        FM(MSIOF2_SS2_C)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 211 #define IP0_7_4         FM(AVB_MAGIC)           F_(0, 0)        FM(MSIOF2_SS1_C)        FM(SCK4_A)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 212 #define IP0_11_8        FM(AVB_PHY_INT)         F_(0, 0)        FM(MSIOF2_SYNC_C)       FM(RX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 213 #define IP0_15_12       FM(AVB_LINK)            F_(0, 0)        FM(MSIOF2_SCK_C)        FM(TX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 214 #define IP0_19_16       FM(AVB_AVTP_MATCH_A)    F_(0, 0)        FM(MSIOF2_RXD_C)        FM(CTS4_N_A)                    F_(0, 0)        FM(FSCLKST2_N_A) F_(0, 0)               F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 215 #define IP0_23_20       FM(AVB_AVTP_CAPTURE_A)  F_(0, 0)        FM(MSIOF2_TXD_C)        FM(RTS4_N_A)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 216 #define IP0_27_24       FM(IRQ0)                FM(QPOLB)       F_(0, 0)                FM(DU_CDE)                      FM(VI4_DATA0_B) FM(CAN0_TX_B)   FM(CANFD0_TX_B)         FM(MSIOF3_SS2_E) F_(0, 0)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 217 #define IP0_31_28       FM(IRQ1)                FM(QPOLA)       F_(0, 0)                FM(DU_DISP)                     FM(VI4_DATA1_B) FM(CAN0_RX_B)   FM(CANFD0_RX_B)         FM(MSIOF3_SS1_E) F_(0, 0)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 218 #define IP1_3_0         FM(IRQ2)                FM(QCPV_QDE)    F_(0, 0)                FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(VI4_DATA2_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_SYNC_E) F_(0, 0)              FM(PWM3_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 219 #define IP1_7_4         FM(IRQ3)                FM(QSTVB_QVE)   F_(0, 0)                FM(DU_DOTCLKOUT1)               FM(VI4_DATA3_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_SCK_E) F_(0, 0)               FM(PWM4_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 220 #define IP1_11_8        FM(IRQ4)                FM(QSTH_QHS)    F_(0, 0)                FM(DU_EXHSYNC_DU_HSYNC)         FM(VI4_DATA4_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_RXD_E) F_(0, 0)               FM(PWM5_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 221 #define IP1_15_12       FM(IRQ5)                FM(QSTB_QHE)    F_(0, 0)                FM(DU_EXVSYNC_DU_VSYNC)         FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0)               FM(MSIOF3_TXD_E) F_(0, 0)               FM(PWM6_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 222 #define IP1_19_16       FM(PWM0)                FM(AVB_AVTP_PPS)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA6_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IECLK_B)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 223 #define IP1_23_20       FM(PWM1_A)              F_(0, 0)        F_(0, 0)                FM(HRX3_D)                      FM(VI4_DATA7_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IERX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 224 #define IP1_27_24       FM(PWM2_A)              F_(0, 0)        F_(0, 0)                FM(HTX3_D)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IETX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 225 #define IP1_31_28       FM(A0)                  FM(LCDOUT16)    FM(MSIOF3_SYNC_B)       F_(0, 0)                        FM(VI4_DATA8)   F_(0, 0)        FM(DU_DB0)              F_(0, 0)        F_(0, 0)                FM(PWM3_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 226 #define IP2_3_0         FM(A1)                  FM(LCDOUT17)    FM(MSIOF3_TXD_B)        F_(0, 0)                        FM(VI4_DATA9)   F_(0, 0)        FM(DU_DB1)              F_(0, 0)        F_(0, 0)                FM(PWM4_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 227 #define IP2_7_4         FM(A2)                  FM(LCDOUT18)    FM(MSIOF3_SCK_B)        F_(0, 0)                        FM(VI4_DATA10)  F_(0, 0)        FM(DU_DB2)              F_(0, 0)        F_(0, 0)                FM(PWM5_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 228 #define IP2_11_8        FM(A3)                  FM(LCDOUT19)    FM(MSIOF3_RXD_B)        F_(0, 0)                        FM(VI4_DATA11)  F_(0, 0)        FM(DU_DB3)              F_(0, 0)        F_(0, 0)                FM(PWM6_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 229
 230 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 231 #define IP2_15_12       FM(A4)                  FM(LCDOUT20)    FM(MSIOF3_SS1_B)        F_(0, 0)                        FM(VI4_DATA12)  FM(VI5_DATA12)  FM(DU_DB4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 232 #define IP2_19_16       FM(A5)                  FM(LCDOUT21)    FM(MSIOF3_SS2_B)        FM(SCK4_B)                      FM(VI4_DATA13)  FM(VI5_DATA13)  FM(DU_DB5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 233 #define IP2_23_20       FM(A6)                  FM(LCDOUT22)    FM(MSIOF2_SS1_A)        FM(RX4_B)                       FM(VI4_DATA14)  FM(VI5_DATA14)  FM(DU_DB6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 234 #define IP2_27_24       FM(A7)                  FM(LCDOUT23)    FM(MSIOF2_SS2_A)        FM(TX4_B)                       FM(VI4_DATA15)  FM(VI5_DATA15)  FM(DU_DB7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 235 #define IP2_31_28       FM(A8)                  FM(RX3_B)       FM(MSIOF2_SYNC_A)       FM(HRX4_B)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                FM(SDA6_A)      FM(AVB_AVTP_MATCH_B)    FM(PWM1_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 236 #define IP3_3_0         FM(A9)                  F_(0, 0)        FM(MSIOF2_SCK_A)        FM(CTS4_N_B)                    F_(0, 0)        FM(VI5_VSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 237 #define IP3_7_4         FM(A10)                 F_(0, 0)        FM(MSIOF2_RXD_A)        FM(RTS4_N_B)                    F_(0, 0)        FM(VI5_HSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 238 #define IP3_11_8        FM(A11)                 FM(TX3_B)       FM(MSIOF2_TXD_A)        FM(HTX4_B)                      FM(HSCK4)       FM(VI5_FIELD)   F_(0, 0)                FM(SCL6_A)      FM(AVB_AVTP_CAPTURE_B)  FM(PWM2_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 239 #define IP3_15_12       FM(A12)                 FM(LCDOUT12)    FM(MSIOF3_SCK_C)        F_(0, 0)                        FM(HRX4_A)      FM(VI5_DATA8)   FM(DU_DG4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 240 #define IP3_19_16       FM(A13)                 FM(LCDOUT13)    FM(MSIOF3_SYNC_C)       F_(0, 0)                        FM(HTX4_A)      FM(VI5_DATA9)   FM(DU_DG5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 241 #define IP3_23_20       FM(A14)                 FM(LCDOUT14)    FM(MSIOF3_RXD_C)        F_(0, 0)                        FM(HCTS4_N)     FM(VI5_DATA10)  FM(DU_DG6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 242 #define IP3_27_24       FM(A15)                 FM(LCDOUT15)    FM(MSIOF3_TXD_C)        F_(0, 0)                        FM(HRTS4_N)     FM(VI5_DATA11)  FM(DU_DG7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 243 #define IP3_31_28       FM(A16)                 FM(LCDOUT8)     F_(0, 0)                F_(0, 0)                        FM(VI4_FIELD)   F_(0, 0)        FM(DU_DG0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 244 #define IP4_3_0         FM(A17)                 FM(LCDOUT9)     F_(0, 0)                F_(0, 0)                        FM(VI4_VSYNC_N) F_(0, 0)        FM(DU_DG1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 245 #define IP4_7_4         FM(A18)                 FM(LCDOUT10)    F_(0, 0)                F_(0, 0)                        FM(VI4_HSYNC_N) F_(0, 0)        FM(DU_DG2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 246 #define IP4_11_8        FM(A19)                 FM(LCDOUT11)    F_(0, 0)                F_(0, 0)                        FM(VI4_CLKENB)  F_(0, 0)        FM(DU_DG3)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 247 #define IP4_15_12       FM(CS0_N)               F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLKENB)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 248 #define IP4_19_16       FM(CS1_N)               F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLK)     F_(0, 0)                FM(EX_WAIT0_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 249 #define IP4_23_20       FM(BS_N)                FM(QSTVA_QVS)   FM(MSIOF3_SCK_D)        FM(SCK3)                        FM(HSCK3)       F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN1_TX)             FM(CANFD1_TX)   FM(IETX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 250 #define IP4_27_24       FM(RD_N)                F_(0, 0)        FM(MSIOF3_SYNC_D)       FM(RX3_A)                       FM(HRX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_TX_A)           FM(CANFD0_TX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 251 #define IP4_31_28       FM(RD_WR_N)             F_(0, 0)        FM(MSIOF3_RXD_D)        FM(TX3_A)                       FM(HTX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_RX_A)           FM(CANFD0_RX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 252 #define IP5_3_0         FM(WE0_N)               F_(0, 0)        FM(MSIOF3_TXD_D)        FM(CTS3_N)                      FM(HCTS3_N)     F_(0, 0)        F_(0, 0)                FM(SCL6_B)      FM(CAN_CLK)             F_(0, 0)        FM(IECLK_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 253 #define IP5_7_4         FM(WE1_N)               F_(0, 0)        FM(MSIOF3_SS1_D)        FM(RTS3_N)                      FM(HRTS3_N)     F_(0, 0)        F_(0, 0)                FM(SDA6_B)      FM(CAN1_RX)             FM(CANFD1_RX)   FM(IERX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 254 #define IP5_11_8        FM(EX_WAIT0_A)          FM(QCLK)        F_(0, 0)                F_(0, 0)                        FM(VI4_CLK)     F_(0, 0)        FM(DU_DOTCLKOUT0)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 255 #define IP5_15_12       FM(D0)                  FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)        F_(0, 0)                        FM(VI4_DATA16)  FM(VI5_DATA0)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 256 #define IP5_19_16       FM(D1)                  FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)       F_(0, 0)                        FM(VI4_DATA17)  FM(VI5_DATA1)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 257 #define IP5_23_20       FM(D2)                  F_(0, 0)        FM(MSIOF3_RXD_A)        F_(0, 0)                        FM(VI4_DATA18)  FM(VI5_DATA2)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 258 #define IP5_27_24       FM(D3)                  F_(0, 0)        FM(MSIOF3_TXD_A)        F_(0, 0)                        FM(VI4_DATA19)  FM(VI5_DATA3)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 259 #define IP5_31_28       FM(D4)                  FM(MSIOF2_SCK_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA20)  FM(VI5_DATA4)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 260 #define IP6_3_0         FM(D5)                  FM(MSIOF2_SYNC_B)F_(0, 0)               F_(0, 0)                        FM(VI4_DATA21)  FM(VI5_DATA5)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 261 #define IP6_7_4         FM(D6)                  FM(MSIOF2_RXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA22)  FM(VI5_DATA6)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 262 #define IP6_11_8        FM(D7)                  FM(MSIOF2_TXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA23)  FM(VI5_DATA7)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 263 #define IP6_15_12       FM(D8)                  FM(LCDOUT0)     FM(MSIOF2_SCK_D)        FM(SCK4_C)                      FM(VI4_DATA0_A) F_(0, 0)        FM(DU_DR0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 264 #define IP6_19_16       FM(D9)                  FM(LCDOUT1)     FM(MSIOF2_SYNC_D)       F_(0, 0)                        FM(VI4_DATA1_A) F_(0, 0)        FM(DU_DR1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 265 #define IP6_23_20       FM(D10)                 FM(LCDOUT2)     FM(MSIOF2_RXD_D)        FM(HRX3_B)                      FM(VI4_DATA2_A) FM(CTS4_N_C)    FM(DU_DR2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 266 #define IP6_27_24       FM(D11)                 FM(LCDOUT3)     FM(MSIOF2_TXD_D)        FM(HTX3_B)                      FM(VI4_DATA3_A) FM(RTS4_N_C)    FM(DU_DR3)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 267 #define IP6_31_28       FM(D12)                 FM(LCDOUT4)     FM(MSIOF2_SS1_D)        FM(RX4_C)                       FM(VI4_DATA4_A) F_(0, 0)        FM(DU_DR4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 268 #define IP7_3_0         FM(D13)                 FM(LCDOUT5)     FM(MSIOF2_SS2_D)        FM(TX4_C)                       FM(VI4_DATA5_A) F_(0, 0)        FM(DU_DR5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 269 #define IP7_7_4         FM(D14)                 FM(LCDOUT6)     FM(MSIOF3_SS1_A)        FM(HRX3_C)                      FM(VI4_DATA6_A) F_(0, 0)        FM(DU_DR6)              FM(SCL6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 270 #define IP7_11_8        FM(D15)                 FM(LCDOUT7)     FM(MSIOF3_SS2_A)        FM(HTX3_C)                      FM(VI4_DATA7_A) F_(0, 0)        FM(DU_DR7)              FM(SDA6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 271 #define IP7_19_16       FM(SD0_CLK)             F_(0, 0)        FM(MSIOF1_SCK_E)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 272
 273 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 274 #define IP7_23_20       FM(SD0_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_E)       F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 275 #define IP7_27_24       FM(SD0_DAT0)            F_(0, 0)        FM(MSIOF1_RXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_B)   FM(STP_ISCLK_0_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 276 #define IP7_31_28       FM(SD0_DAT1)            F_(0, 0)        FM(MSIOF1_TXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 277 #define IP8_3_0         FM(SD0_DAT2)            F_(0, 0)        FM(MSIOF1_SS1_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_B)  FM(STP_ISD_0_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 278 #define IP8_7_4         FM(SD0_DAT3)            F_(0, 0)        FM(MSIOF1_SS2_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_B)  FM(STP_ISEN_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 279 #define IP8_11_8        FM(SD1_CLK)             F_(0, 0)        FM(MSIOF1_SCK_G)        F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 280 #define IP8_15_12       FM(SD1_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_G)       FM(NFCE_N_B)                    F_(0, 0)        FM(SIM0_D_A)    FM(STP_IVCXO27_1_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 281 #define IP8_19_16       FM(SD1_DAT0)            FM(SD2_DAT4)    FM(MSIOF1_RXD_G)        FM(NFWP_N_B)                    F_(0, 0)        FM(TS_SCK1_B)   FM(STP_ISCLK_1_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 282 #define IP8_23_20       FM(SD1_DAT1)            FM(SD2_DAT5)    FM(MSIOF1_TXD_G)        FM(NFDATA14_B)                  F_(0, 0)        FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 283 #define IP8_27_24       FM(SD1_DAT2)            FM(SD2_DAT6)    FM(MSIOF1_SS1_G)        FM(NFDATA15_B)                  F_(0, 0)        FM(TS_SDAT1_B)  FM(STP_ISD_1_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 284 #define IP8_31_28       FM(SD1_DAT3)            FM(SD2_DAT7)    FM(MSIOF1_SS2_G)        FM(NFRB_N_B)                    F_(0, 0)        FM(TS_SDEN1_B)  FM(STP_ISEN_1_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 285 #define IP9_3_0         FM(SD2_CLK)             F_(0, 0)        FM(NFDATA8)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 286 #define IP9_7_4         FM(SD2_CMD)             F_(0, 0)        FM(NFDATA9)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 287 #define IP9_11_8        FM(SD2_DAT0)            F_(0, 0)        FM(NFDATA10)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 288 #define IP9_15_12       FM(SD2_DAT1)            F_(0, 0)        FM(NFDATA11)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 289 #define IP9_19_16       FM(SD2_DAT2)            F_(0, 0)        FM(NFDATA12)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 290 #define IP9_23_20       FM(SD2_DAT3)            F_(0, 0)        FM(NFDATA13)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 291 #define IP9_27_24       FM(SD2_DS)              F_(0, 0)        FM(NFALE)               F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(SATA_DEVSLP_B)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 292 #define IP9_31_28       FM(SD3_CLK)             F_(0, 0)        FM(NFWE_N)              F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 293 #define IP10_3_0        FM(SD3_CMD)             F_(0, 0)        FM(NFRE_N)              F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 294 #define IP10_7_4        FM(SD3_DAT0)            F_(0, 0)        FM(NFDATA0)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 295 #define IP10_11_8       FM(SD3_DAT1)            F_(0, 0)        FM(NFDATA1)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 296 #define IP10_15_12      FM(SD3_DAT2)            F_(0, 0)        FM(NFDATA2)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 297 #define IP10_19_16      FM(SD3_DAT3)            F_(0, 0)        FM(NFDATA3)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 298 #define IP10_23_20      FM(SD3_DAT4)            FM(SD2_CD_A)    FM(NFDATA4)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 299 #define IP10_27_24      FM(SD3_DAT5)            FM(SD2_WP_A)    FM(NFDATA5)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 300 #define IP10_31_28      FM(SD3_DAT6)            FM(SD3_CD)      FM(NFDATA6)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 301 #define IP11_3_0        FM(SD3_DAT7)            FM(SD3_WP)      FM(NFDATA7)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 302 #define IP11_7_4        FM(SD3_DS)              F_(0, 0)        FM(NFCLE)               F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 303 #define IP11_11_8       FM(SD0_CD)              F_(0, 0)        FM(NFDATA14_A)          F_(0, 0)                        FM(SCL2_B)      FM(SIM0_RST_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 304
 305 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 306 #define IP11_15_12      FM(SD0_WP)              F_(0, 0)        FM(NFDATA15_A)          F_(0, 0)                        FM(SDA2_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 307 #define IP11_19_16      FM(SD1_CD)              F_(0, 0)        FM(NFRB_N_A)            F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 308 #define IP11_23_20      FM(SD1_WP)              F_(0, 0)        FM(NFCE_N_A)            F_(0, 0)                        F_(0, 0)        FM(SIM0_D_B)    F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 309 #define IP11_27_24      FM(SCK0)                FM(HSCK1_B)     FM(MSIOF1_SS2_B)        FM(AUDIO_CLKC_B)                FM(SDA2_A)      FM(SIM0_RST_B)  FM(STP_OPWM_0_C)        FM(RIF0_CLK_B)  F_(0, 0)                FM(ADICHS2)     FM(SCK5_B)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 310 #define IP11_31_28      FM(RX0)                 FM(HRX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_C)   FM(STP_ISCLK_0_C)       FM(RIF0_D0_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 311 #define IP12_3_0        FM(TX0)                 FM(HTX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)      FM(RIF0_D1_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 312 #define IP12_7_4        FM(CTS0_N)              FM(HCTS1_N_B)   FM(MSIOF1_SYNC_B)       F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)      FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C)      FM(ADICS_SAMP)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 313 #define IP12_11_8       FM(RTS0_N)              FM(HRTS1_N_B)   FM(MSIOF1_SS1_B)        FM(AUDIO_CLKA_B)                FM(SCL2_A)      F_(0, 0)        FM(STP_IVCXO27_1_C)     FM(RIF0_SYNC_B) F_(0, 0)                FM(ADICHS1)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 314 #define IP12_15_12      FM(RX1_A)               FM(HRX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_C)  FM(STP_ISD_0_C)         FM(RIF1_CLK_C)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 315 #define IP12_19_16      FM(TX1_A)               FM(HTX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_C)  FM(STP_ISEN_0_C)        FM(RIF1_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 316 #define IP12_23_20      FM(CTS1_N)              FM(HCTS1_N_A)   FM(MSIOF1_RXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_C)  FM(STP_ISEN_1_C)        FM(RIF1_D0_B)   F_(0, 0)                FM(ADIDATA)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 317 #define IP12_27_24      FM(RTS1_N)              FM(HRTS1_N_A)   FM(MSIOF1_TXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_C)  FM(STP_ISD_1_C)         FM(RIF1_D1_B)   F_(0, 0)                FM(ADICHS0)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 318 #define IP12_31_28      FM(SCK2)                FM(SCIF_CLK_B)  FM(MSIOF1_SCK_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_C)   FM(STP_ISCLK_1_C)       FM(RIF1_CLK_B)  F_(0, 0)                FM(ADICLK)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 319 #define IP13_3_0        FM(TX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_CD_B)                    FM(SCL1_A)      F_(0, 0)        FM(FMCLK_A)             FM(RIF1_D1_C)   F_(0, 0)                FM(FSO_CFE_0_N) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 320 #define IP13_7_4        FM(RX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_WP_B)                    FM(SDA1_A)      F_(0, 0)        FM(FMIN_A)              FM(RIF1_SYNC_C) F_(0, 0)                FM(FSO_CFE_1_N) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 321 #define IP13_11_8       FM(HSCK0)               F_(0, 0)        FM(MSIOF1_SCK_D)        FM(AUDIO_CLKB_A)                FM(SSI_SDATA1_B)FM(TS_SCK0_D)   FM(STP_ISCLK_0_D)       FM(RIF0_CLK_C)  F_(0, 0)                F_(0, 0)        FM(RX5_B)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 322 #define IP13_15_12      FM(HRX0)                F_(0, 0)        FM(MSIOF1_RXD_D)        F_(0, 0)                        FM(SSI_SDATA2_B)FM(TS_SDEN0_D)  FM(STP_ISEN_0_D)        FM(RIF0_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 323 #define IP13_19_16      FM(HTX0)                F_(0, 0)        FM(MSIOF1_TXD_D)        F_(0, 0)                        FM(SSI_SDATA9_B)FM(TS_SDAT0_D)  FM(STP_ISD_0_D)         FM(RIF0_D1_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 324 #define IP13_23_20      FM(HCTS0_N)             FM(RX2_B)       FM(MSIOF1_SYNC_D)       F_(0, 0)                        FM(SSI_SCK9_A)  FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D)      FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 325 #define IP13_27_24      FM(HRTS0_N)             FM(TX2_B)       FM(MSIOF1_SS1_D)        F_(0, 0)                        FM(SSI_WS9_A)   F_(0, 0)        FM(STP_IVCXO27_0_D)     FM(BPFCLK_A)    FM(AUDIO_CLKOUT2_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 326 #define IP13_31_28      FM(MSIOF0_SYNC)         F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(AUDIO_CLKOUT_A)      F_(0, 0)        FM(TX5_B)       F_(0, 0)        F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
 327 #define IP14_3_0        FM(MSIOF0_SS1)          FM(RX5_A)       FM(NFWP_N_A)            FM(AUDIO_CLKA_C)                FM(SSI_SCK2_A)  F_(0, 0)        FM(STP_IVCXO27_0_C)     F_(0, 0)        FM(AUDIO_CLKOUT3_A)     F_(0, 0)        FM(TCLK1_B)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 328 #define IP14_7_4        FM(MSIOF0_SS2)          FM(TX5_A)       FM(MSIOF1_SS2_D)        FM(AUDIO_CLKC_A)                FM(SSI_WS2_A)   F_(0, 0)        FM(STP_OPWM_0_D)        F_(0, 0)        FM(AUDIO_CLKOUT_D)      F_(0, 0)        FM(SPEEDIN_B)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 329 #define IP14_11_8       FM(MLB_CLK)             F_(0, 0)        FM(MSIOF1_SCK_F)        F_(0, 0)                        FM(SCL1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 330 #define IP14_15_12      FM(MLB_SIG)             FM(RX1_B)       FM(MSIOF1_SYNC_F)       F_(0, 0)                        FM(SDA1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 331 #define IP14_19_16      FM(MLB_DAT)             FM(TX1_B)       FM(MSIOF1_RXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 332 #define IP14_23_20      FM(SSI_SCK01239)        F_(0, 0)        FM(MSIOF1_TXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 333 #define IP14_27_24      FM(SSI_WS01239)         F_(0, 0)        FM(MSIOF1_SS1_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 334
 335 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 336 #define IP14_31_28      FM(SSI_SDATA0)          F_(0, 0)        FM(MSIOF1_SS2_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 337 #define IP15_3_0        FM(SSI_SDATA1_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 338 #define IP15_7_4        FM(SSI_SDATA2_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        FM(SSI_SCK1_B)  F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 339 #define IP15_11_8       FM(SSI_SCK349)          F_(0, 0)        FM(MSIOF1_SS1_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 340 #define IP15_15_12      FM(SSI_WS349)           FM(HCTS2_N_A)   FM(MSIOF1_SS2_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_A)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 341 #define IP15_19_16      FM(SSI_SDATA3)          FM(HRTS2_N_A)   FM(MSIOF1_TXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_A)   FM(STP_ISCLK_0_A)       FM(RIF0_D1_A)   FM(RIF2_D0_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 342 #define IP15_23_20      FM(SSI_SCK4)            FM(HRX2_A)      FM(MSIOF1_SCK_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_A)  FM(STP_ISD_0_A)         FM(RIF0_CLK_A)  FM(RIF2_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 343 #define IP15_27_24      FM(SSI_WS4)             FM(HTX2_A)      FM(MSIOF1_SYNC_A)       F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_A)  FM(STP_ISEN_0_A)        FM(RIF0_SYNC_A) FM(RIF2_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 344 #define IP15_31_28      FM(SSI_SDATA4)          FM(HSCK2_A)     FM(MSIOF1_RXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)      FM(RIF0_D0_A)   FM(RIF2_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 345 #define IP16_3_0        FM(SSI_SCK6)            FM(USB2_PWEN)   F_(0, 0)                FM(SIM0_RST_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 346 #define IP16_7_4        FM(SSI_WS6)             FM(USB2_OVC)    F_(0, 0)                FM(SIM0_D_D)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 347 #define IP16_11_8       FM(SSI_SDATA6)          F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(SATA_DEVSLP_A)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 348 #define IP16_15_12      FM(SSI_SCK78)           FM(HRX2_B)      FM(MSIOF1_SCK_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_A)   FM(STP_ISCLK_1_A)       FM(RIF1_CLK_A)  FM(RIF3_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 349 #define IP16_19_16      FM(SSI_WS78)            FM(HTX2_B)      FM(MSIOF1_SYNC_C)       F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_A)  FM(STP_ISD_1_A)         FM(RIF1_SYNC_A) FM(RIF3_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 350 #define IP16_23_20      FM(SSI_SDATA7)          FM(HCTS2_N_B)   FM(MSIOF1_RXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_A)  FM(STP_ISEN_1_A)        FM(RIF1_D0_A)   FM(RIF3_D0_A)           F_(0, 0)        FM(TCLK2_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 351 #define IP16_27_24      FM(SSI_SDATA8)          FM(HRTS2_N_B)   FM(MSIOF1_TXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A)      FM(RIF1_D1_A)   FM(RIF3_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 352 #define IP16_31_28      FM(SSI_SDATA9_A)        FM(HSCK2_B)     FM(MSIOF1_SS1_C)        FM(HSCK1_A)                     FM(SSI_WS1_B)   FM(SCK1)        FM(STP_IVCXO27_1_A)     FM(SCK5_A)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 353 #define IP17_3_0        FM(AUDIO_CLKA_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        FM(CC5_OSCOUT)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 354 #define IP17_7_4        FM(AUDIO_CLKB_B)        FM(SCIF_CLK_A)  F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_1_D)     FM(REMOCON_A)   F_(0, 0)                F_(0, 0)        FM(TCLK1_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 355 #define IP17_11_8       FM(USB0_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_RST_C)                  F_(0, 0)        FM(TS_SCK1_D)   FM(STP_ISCLK_1_D)       FM(BPFCLK_B)    FM(RIF3_CLK_B)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
 356 #define IP17_15_12      FM(USB0_OVC)            F_(0, 0)        F_(0, 0)                FM(SIM0_D_C)                    F_(0, 0)        FM(TS_SDAT1_D)  FM(STP_ISD_1_D)         F_(0, 0)        FM(RIF3_SYNC_B)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
 357 #define IP17_19_16      FM(USB1_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_C)                  FM(SSI_SCK1_A)  FM(TS_SCK0_E)   FM(STP_ISCLK_0_E)       FM(FMCLK_B)     FM(RIF2_CLK_B)          F_(0, 0)        FM(SPEEDIN_A)   F_(0, 0)        F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
 358 #define IP17_23_20      FM(USB1_OVC)            F_(0, 0)        FM(MSIOF1_SS2_C)        F_(0, 0)                        FM(SSI_WS1_A)   FM(TS_SDAT0_E)  FM(STP_ISD_0_E)         FM(FMIN_B)      FM(RIF2_SYNC_B)         F_(0, 0)        FM(REMOCON_B)   F_(0, 0)        F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
 359 #define IP17_27_24      FM(USB30_PWEN)          F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT_B)              FM(SSI_SCK2_B)  FM(TS_SDEN1_D)  FM(STP_ISEN_1_D)        FM(STP_OPWM_0_E)FM(RIF3_D0_B)           F_(0, 0)        FM(TCLK2_B)     FM(TPU0TO0)     FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
 360 #define IP17_31_28      FM(USB30_OVC)           F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT1_B)             FM(SSI_WS2_B)   FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)      FM(STP_IVCXO27_0_E)FM(RIF3_D1_B)        F_(0, 0)        FM(FSO_TOE_N)   FM(TPU0TO1)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 361 #define IP18_3_0        FM(USB2_CH3_PWEN)       F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT2_B)             FM(SSI_SCK9_B)  FM(TS_SDEN0_E)  FM(STP_ISEN_0_E)        F_(0, 0)        FM(RIF2_D0_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO2)     FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
 362 #define IP18_7_4        FM(USB2_CH3_OVC)        F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT3_B)             FM(SSI_WS9_B)   FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)      F_(0, 0)        FM(RIF2_D1_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO3)     FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
 363
 364 #define PINMUX_GPSR     \
 365 \
 366                                                                                                 GPSR6_31 \
 367                                                                                                 GPSR6_30 \
 368                                                                                                 GPSR6_29 \
 369                 GPSR1_28                                                                        GPSR6_28 \
 370                 GPSR1_27                                                                        GPSR6_27 \
 371                 GPSR1_26                                                                        GPSR6_26 \
 372                 GPSR1_25                                                        GPSR5_25        GPSR6_25 \
 373                 GPSR1_24                                                        GPSR5_24        GPSR6_24 \
 374                 GPSR1_23                                                        GPSR5_23        GPSR6_23 \
 375                 GPSR1_22                                                        GPSR5_22        GPSR6_22 \
 376                 GPSR1_21                                                        GPSR5_21        GPSR6_21 \
 377                 GPSR1_20                                                        GPSR5_20        GPSR6_20 \
 378                 GPSR1_19                                                        GPSR5_19        GPSR6_19 \
 379                 GPSR1_18                                                        GPSR5_18        GPSR6_18 \
 380                 GPSR1_17                                        GPSR4_17        GPSR5_17        GPSR6_17 \
 381                 GPSR1_16                                        GPSR4_16        GPSR5_16        GPSR6_16 \
 382 GPSR0_15        GPSR1_15                        GPSR3_15        GPSR4_15        GPSR5_15        GPSR6_15 \
 383 GPSR0_14        GPSR1_14        GPSR2_14        GPSR3_14        GPSR4_14        GPSR5_14        GPSR6_14 \
 384 GPSR0_13        GPSR1_13        GPSR2_13        GPSR3_13        GPSR4_13        GPSR5_13        GPSR6_13 \
 385 GPSR0_12        GPSR1_12        GPSR2_12        GPSR3_12        GPSR4_12        GPSR5_12        GPSR6_12 \
 386 GPSR0_11        GPSR1_11        GPSR2_11        GPSR3_11        GPSR4_11        GPSR5_11        GPSR6_11 \
 387 GPSR0_10        GPSR1_10        GPSR2_10        GPSR3_10        GPSR4_10        GPSR5_10        GPSR6_10 \
 388 GPSR0_9         GPSR1_9         GPSR2_9         GPSR3_9         GPSR4_9         GPSR5_9         GPSR6_9 \
 389 GPSR0_8         GPSR1_8         GPSR2_8         GPSR3_8         GPSR4_8         GPSR5_8         GPSR6_8 \
 390 GPSR0_7         GPSR1_7         GPSR2_7         GPSR3_7         GPSR4_7         GPSR5_7         GPSR6_7 \
 391 GPSR0_6         GPSR1_6         GPSR2_6         GPSR3_6         GPSR4_6         GPSR5_6         GPSR6_6 \
 392 GPSR0_5         GPSR1_5         GPSR2_5         GPSR3_5         GPSR4_5         GPSR5_5         GPSR6_5 \
 393 GPSR0_4         GPSR1_4         GPSR2_4         GPSR3_4         GPSR4_4         GPSR5_4         GPSR6_4 \
 394 GPSR0_3         GPSR1_3         GPSR2_3         GPSR3_3         GPSR4_3         GPSR5_3         GPSR6_3         GPSR7_3 \
 395 GPSR0_2         GPSR1_2         GPSR2_2         GPSR3_2         GPSR4_2         GPSR5_2         GPSR6_2         GPSR7_2 \
 396 GPSR0_1         GPSR1_1         GPSR2_1         GPSR3_1         GPSR4_1         GPSR5_1         GPSR6_1         GPSR7_1 \
 397 GPSR0_0         GPSR1_0         GPSR2_0         GPSR3_0         GPSR4_0         GPSR5_0         GPSR6_0         GPSR7_0
 398
 399 #define PINMUX_IPSR                             \
 400 \
 401 FM(IP0_3_0)     IP0_3_0         FM(IP1_3_0)     IP1_3_0         FM(IP2_3_0)     IP2_3_0         FM(IP3_3_0)     IP3_3_0 \
 402 FM(IP0_7_4)     IP0_7_4         FM(IP1_7_4)     IP1_7_4         FM(IP2_7_4)     IP2_7_4         FM(IP3_7_4)     IP3_7_4 \
 403 FM(IP0_11_8)    IP0_11_8        FM(IP1_11_8)    IP1_11_8        FM(IP2_11_8)    IP2_11_8        FM(IP3_11_8)    IP3_11_8 \
 404 FM(IP0_15_12)   IP0_15_12       FM(IP1_15_12)   IP1_15_12       FM(IP2_15_12)   IP2_15_12       FM(IP3_15_12)   IP3_15_12 \
 405 FM(IP0_19_16)   IP0_19_16       FM(IP1_19_16)   IP1_19_16       FM(IP2_19_16)   IP2_19_16       FM(IP3_19_16)   IP3_19_16 \
 406 FM(IP0_23_20)   IP0_23_20       FM(IP1_23_20)   IP1_23_20       FM(IP2_23_20)   IP2_23_20       FM(IP3_23_20)   IP3_23_20 \
 407 FM(IP0_27_24)   IP0_27_24       FM(IP1_27_24)   IP1_27_24       FM(IP2_27_24)   IP2_27_24       FM(IP3_27_24)   IP3_27_24 \
 408 FM(IP0_31_28)   IP0_31_28       FM(IP1_31_28)   IP1_31_28       FM(IP2_31_28)   IP2_31_28       FM(IP3_31_28)   IP3_31_28 \
 409 \
 410 FM(IP4_3_0)     IP4_3_0         FM(IP5_3_0)     IP5_3_0         FM(IP6_3_0)     IP6_3_0         FM(IP7_3_0)     IP7_3_0 \
 411 FM(IP4_7_4)     IP4_7_4         FM(IP5_7_4)     IP5_7_4         FM(IP6_7_4)     IP6_7_4         FM(IP7_7_4)     IP7_7_4 \
 412 FM(IP4_11_8)    IP4_11_8        FM(IP5_11_8)    IP5_11_8        FM(IP6_11_8)    IP6_11_8        FM(IP7_11_8)    IP7_11_8 \
 413 FM(IP4_15_12)   IP4_15_12       FM(IP5_15_12)   IP5_15_12       FM(IP6_15_12)   IP6_15_12 \
 414 FM(IP4_19_16)   IP4_19_16       FM(IP5_19_16)   IP5_19_16       FM(IP6_19_16)   IP6_19_16       FM(IP7_19_16)   IP7_19_16 \
 415 FM(IP4_23_20)   IP4_23_20       FM(IP5_23_20)   IP5_23_20       FM(IP6_23_20)   IP6_23_20       FM(IP7_23_20)   IP7_23_20 \
 416 FM(IP4_27_24)   IP4_27_24       FM(IP5_27_24)   IP5_27_24       FM(IP6_27_24)   IP6_27_24       FM(IP7_27_24)   IP7_27_24 \
 417 FM(IP4_31_28)   IP4_31_28       FM(IP5_31_28)   IP5_31_28       FM(IP6_31_28)   IP6_31_28       FM(IP7_31_28)   IP7_31_28 \
 418 \
 419 FM(IP8_3_0)     IP8_3_0         FM(IP9_3_0)     IP9_3_0         FM(IP10_3_0)    IP10_3_0        FM(IP11_3_0)    IP11_3_0 \
 420 FM(IP8_7_4)     IP8_7_4         FM(IP9_7_4)     IP9_7_4         FM(IP10_7_4)    IP10_7_4        FM(IP11_7_4)    IP11_7_4 \
 421 FM(IP8_11_8)    IP8_11_8        FM(IP9_11_8)    IP9_11_8        FM(IP10_11_8)   IP10_11_8       FM(IP11_11_8)   IP11_11_8 \
 422 FM(IP8_15_12)   IP8_15_12       FM(IP9_15_12)   IP9_15_12       FM(IP10_15_12)  IP10_15_12      FM(IP11_15_12)  IP11_15_12 \
 423 FM(IP8_19_16)   IP8_19_16       FM(IP9_19_16)   IP9_19_16       FM(IP10_19_16)  IP10_19_16      FM(IP11_19_16)  IP11_19_16 \
 424 FM(IP8_23_20)   IP8_23_20       FM(IP9_23_20)   IP9_23_20       FM(IP10_23_20)  IP10_23_20      FM(IP11_23_20)  IP11_23_20 \
 425 FM(IP8_27_24)   IP8_27_24       FM(IP9_27_24)   IP9_27_24       FM(IP10_27_24)  IP10_27_24      FM(IP11_27_24)  IP11_27_24 \
 426 FM(IP8_31_28)   IP8_31_28       FM(IP9_31_28)   IP9_31_28       FM(IP10_31_28)  IP10_31_28      FM(IP11_31_28)  IP11_31_28 \
 427 \
 428 FM(IP12_3_0)    IP12_3_0        FM(IP13_3_0)    IP13_3_0        FM(IP14_3_0)    IP14_3_0        FM(IP15_3_0)    IP15_3_0 \
 429 FM(IP12_7_4)    IP12_7_4        FM(IP13_7_4)    IP13_7_4        FM(IP14_7_4)    IP14_7_4        FM(IP15_7_4)    IP15_7_4 \
 430 FM(IP12_11_8)   IP12_11_8       FM(IP13_11_8)   IP13_11_8       FM(IP14_11_8)   IP14_11_8       FM(IP15_11_8)   IP15_11_8 \
 431 FM(IP12_15_12)  IP12_15_12      FM(IP13_15_12)  IP13_15_12      FM(IP14_15_12)  IP14_15_12      FM(IP15_15_12)  IP15_15_12 \
 432 FM(IP12_19_16)  IP12_19_16      FM(IP13_19_16)  IP13_19_16      FM(IP14_19_16)  IP14_19_16      FM(IP15_19_16)  IP15_19_16 \
 433 FM(IP12_23_20)  IP12_23_20      FM(IP13_23_20)  IP13_23_20      FM(IP14_23_20)  IP14_23_20      FM(IP15_23_20)  IP15_23_20 \
 434 FM(IP12_27_24)  IP12_27_24      FM(IP13_27_24)  IP13_27_24      FM(IP14_27_24)  IP14_27_24      FM(IP15_27_24)  IP15_27_24 \
 435 FM(IP12_31_28)  IP12_31_28      FM(IP13_31_28)  IP13_31_28      FM(IP14_31_28)  IP14_31_28      FM(IP15_31_28)  IP15_31_28 \
 436 \
 437 FM(IP16_3_0)    IP16_3_0        FM(IP17_3_0)    IP17_3_0        FM(IP18_3_0)    IP18_3_0 \
 438 FM(IP16_7_4)    IP16_7_4        FM(IP17_7_4)    IP17_7_4        FM(IP18_7_4)    IP18_7_4 \
 439 FM(IP16_11_8)   IP16_11_8       FM(IP17_11_8)   IP17_11_8 \
 440 FM(IP16_15_12)  IP16_15_12      FM(IP17_15_12)  IP17_15_12 \
 441 FM(IP16_19_16)  IP16_19_16      FM(IP17_19_16)  IP17_19_16 \
 442 FM(IP16_23_20)  IP16_23_20      FM(IP17_23_20)  IP17_23_20 \
 443 FM(IP16_27_24)  IP16_27_24      FM(IP17_27_24)  IP17_27_24 \
 444 FM(IP16_31_28)  IP16_31_28      FM(IP17_31_28)  IP17_31_28
 445
 446 /* MOD_SEL0 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 447 #define MOD_SEL0_31_30_29       FM(SEL_MSIOF3_0)        FM(SEL_MSIOF3_1)        FM(SEL_MSIOF3_2)        FM(SEL_MSIOF3_3)        FM(SEL_MSIOF3_4)        F_(0, 0)                F_(0, 0)                F_(0, 0)
 448 #define MOD_SEL0_28_27          FM(SEL_MSIOF2_0)        FM(SEL_MSIOF2_1)        FM(SEL_MSIOF2_2)        FM(SEL_MSIOF2_3)
 449 #define MOD_SEL0_26_25_24       FM(SEL_MSIOF1_0)        FM(SEL_MSIOF1_1)        FM(SEL_MSIOF1_2)        FM(SEL_MSIOF1_3)        FM(SEL_MSIOF1_4)        FM(SEL_MSIOF1_5)        FM(SEL_MSIOF1_6)        F_(0, 0)
 450 #define MOD_SEL0_23             FM(SEL_LBSC_0)          FM(SEL_LBSC_1)
 451 #define MOD_SEL0_22             FM(SEL_IEBUS_0)         FM(SEL_IEBUS_1)
 452 #define MOD_SEL0_21             FM(SEL_I2C2_0)          FM(SEL_I2C2_1)
 453 #define MOD_SEL0_20             FM(SEL_I2C1_0)          FM(SEL_I2C1_1)
 454 #define MOD_SEL0_19             FM(SEL_HSCIF4_0)        FM(SEL_HSCIF4_1)
 455 #define MOD_SEL0_18_17          FM(SEL_HSCIF3_0)        FM(SEL_HSCIF3_1)        FM(SEL_HSCIF3_2)        FM(SEL_HSCIF3_3)
 456 #define MOD_SEL0_16             FM(SEL_HSCIF1_0)        FM(SEL_HSCIF1_1)
 457 #define MOD_SEL0_14_13          FM(SEL_HSCIF2_0)        FM(SEL_HSCIF2_1)        FM(SEL_HSCIF2_2)        F_(0, 0)
 458 #define MOD_SEL0_12             FM(SEL_ETHERAVB_0)      FM(SEL_ETHERAVB_1)
 459 #define MOD_SEL0_11             FM(SEL_DRIF3_0)         FM(SEL_DRIF3_1)
 460 #define MOD_SEL0_10             FM(SEL_DRIF2_0)         FM(SEL_DRIF2_1)
 461 #define MOD_SEL0_9_8            FM(SEL_DRIF1_0)         FM(SEL_DRIF1_1)         FM(SEL_DRIF1_2)         F_(0, 0)
 462 #define MOD_SEL0_7_6            FM(SEL_DRIF0_0)         FM(SEL_DRIF0_1)         FM(SEL_DRIF0_2)         F_(0, 0)
 463 #define MOD_SEL0_5              FM(SEL_CANFD0_0)        FM(SEL_CANFD0_1)
 464 #define MOD_SEL0_4_3            FM(SEL_ADG_A_0)         FM(SEL_ADG_A_1)         FM(SEL_ADG_A_2)         FM(SEL_ADG_A_3)
 465
 466 /* MOD_SEL1 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 467 #define MOD_SEL1_31_30          FM(SEL_TSIF1_0)         FM(SEL_TSIF1_1)         FM(SEL_TSIF1_2)         FM(SEL_TSIF1_3)
 468 #define MOD_SEL1_29_28_27       FM(SEL_TSIF0_0)         FM(SEL_TSIF0_1)         FM(SEL_TSIF0_2)         FM(SEL_TSIF0_3)         FM(SEL_TSIF0_4)         F_(0, 0)                F_(0, 0)                F_(0, 0)
 469 #define MOD_SEL1_26             FM(SEL_TIMER_TMU1_0)    FM(SEL_TIMER_TMU1_1)
 470 #define MOD_SEL1_25_24          FM(SEL_SSP1_1_0)        FM(SEL_SSP1_1_1)        FM(SEL_SSP1_1_2)        FM(SEL_SSP1_1_3)
 471 #define MOD_SEL1_23_22_21       FM(SEL_SSP1_0_0)        FM(SEL_SSP1_0_1)        FM(SEL_SSP1_0_2)        FM(SEL_SSP1_0_3)        FM(SEL_SSP1_0_4)        F_(0, 0)                F_(0, 0)                F_(0, 0)
 472 #define MOD_SEL1_20             FM(SEL_SSI1_0)          FM(SEL_SSI1_1)
 473 #define MOD_SEL1_19             FM(SEL_SPEED_PULSE_0)   FM(SEL_SPEED_PULSE_1)
 474 #define MOD_SEL1_18_17          FM(SEL_SIMCARD_0)       FM(SEL_SIMCARD_1)       FM(SEL_SIMCARD_2)       FM(SEL_SIMCARD_3)
 475 #define MOD_SEL1_16             FM(SEL_SDHI2_0)         FM(SEL_SDHI2_1)
 476 #define MOD_SEL1_15_14          FM(SEL_SCIF4_0)         FM(SEL_SCIF4_1)         FM(SEL_SCIF4_2)         F_(0, 0)
 477 #define MOD_SEL1_13             FM(SEL_SCIF3_0)         FM(SEL_SCIF3_1)
 478 #define MOD_SEL1_12             FM(SEL_SCIF2_0)         FM(SEL_SCIF2_1)
 479 #define MOD_SEL1_11             FM(SEL_SCIF1_0)         FM(SEL_SCIF1_1)
 480 #define MOD_SEL1_10             FM(SEL_SCIF_0)          FM(SEL_SCIF_1)
 481 #define MOD_SEL1_9              FM(SEL_REMOCON_0)       FM(SEL_REMOCON_1)
 482 #define MOD_SEL1_6              FM(SEL_RCAN0_0)         FM(SEL_RCAN0_1)
 483 #define MOD_SEL1_5              FM(SEL_PWM6_0)          FM(SEL_PWM6_1)
 484 #define MOD_SEL1_4              FM(SEL_PWM5_0)          FM(SEL_PWM5_1)
 485 #define MOD_SEL1_3              FM(SEL_PWM4_0)          FM(SEL_PWM4_1)
 486 #define MOD_SEL1_2              FM(SEL_PWM3_0)          FM(SEL_PWM3_1)
 487 #define MOD_SEL1_1              FM(SEL_PWM2_0)          FM(SEL_PWM2_1)
 488 #define MOD_SEL1_0              FM(SEL_PWM1_0)          FM(SEL_PWM1_1)
 489
 490 /* MOD_SEL2 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */
 491 #define MOD_SEL2_31             FM(I2C_SEL_5_0)         FM(I2C_SEL_5_1)
 492 #define MOD_SEL2_30             FM(I2C_SEL_3_0)         FM(I2C_SEL_3_1)
 493 #define MOD_SEL2_29             FM(I2C_SEL_0_0)         FM(I2C_SEL_0_1)
 494 #define MOD_SEL2_28_27          FM(SEL_FM_0)            FM(SEL_FM_1)            FM(SEL_FM_2)            FM(SEL_FM_3)
 495 #define MOD_SEL2_26             FM(SEL_SCIF5_0)         FM(SEL_SCIF5_1)
 496 #define MOD_SEL2_25_24_23       FM(SEL_I2C6_0)          FM(SEL_I2C6_1)          FM(SEL_I2C6_2)          F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)
 497 #define MOD_SEL2_21             FM(SEL_SSI2_0)          FM(SEL_SSI2_1)
 498 #define MOD_SEL2_20             FM(SEL_SSI9_0)          FM(SEL_SSI9_1)
 499 #define MOD_SEL2_19             FM(SEL_TIMER_TMU2_0)    FM(SEL_TIMER_TMU2_1)
 500 #define MOD_SEL2_18             FM(SEL_ADG_B_0)         FM(SEL_ADG_B_1)
 501 #define MOD_SEL2_17             FM(SEL_ADG_C_0)         FM(SEL_ADG_C_1)
 502 #define MOD_SEL2_0              FM(SEL_VIN4_0)          FM(SEL_VIN4_1)
 503
 504 #define PINMUX_MOD_SELS \
 505 \
 506 MOD_SEL0_31_30_29       MOD_SEL1_31_30          MOD_SEL2_31 \
 507                                                 MOD_SEL2_30 \
 508                         MOD_SEL1_29_28_27       MOD_SEL2_29 \
 509 MOD_SEL0_28_27                                  MOD_SEL2_28_27 \
 510 MOD_SEL0_26_25_24       MOD_SEL1_26             MOD_SEL2_26 \
 511                         MOD_SEL1_25_24          MOD_SEL2_25_24_23 \
 512 MOD_SEL0_23             MOD_SEL1_23_22_21 \
 513 MOD_SEL0_22 \
 514 MOD_SEL0_21                                     MOD_SEL2_21 \
 515 MOD_SEL0_20             MOD_SEL1_20             MOD_SEL2_20 \
 516 MOD_SEL0_19             MOD_SEL1_19             MOD_SEL2_19 \
 517 MOD_SEL0_18_17          MOD_SEL1_18_17          MOD_SEL2_18 \
 518                                                 MOD_SEL2_17 \
 519 MOD_SEL0_16             MOD_SEL1_16 \
 520                         MOD_SEL1_15_14 \
 521 MOD_SEL0_14_13 \
 522                         MOD_SEL1_13 \
 523 MOD_SEL0_12             MOD_SEL1_12 \
 524 MOD_SEL0_11             MOD_SEL1_11 \
 525 MOD_SEL0_10             MOD_SEL1_10 \
 526 MOD_SEL0_9_8            MOD_SEL1_9 \
 527 MOD_SEL0_7_6 \
 528                         MOD_SEL1_6 \
 529 MOD_SEL0_5              MOD_SEL1_5 \
 530 MOD_SEL0_4_3            MOD_SEL1_4 \
 531                         MOD_SEL1_3 \
 532                         MOD_SEL1_2 \
 533                         MOD_SEL1_1 \
 534                         MOD_SEL1_0              MOD_SEL2_0
 535
 536 /*
 537  * These pins are not able to be muxed but have other properties
 538  * that can be set, such as drive-strength or pull-up/pull-down enable.
 539  */
 540 #define PINMUX_STATIC \
 541         FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
 542         FM(QSPI0_IO2) FM(QSPI0_IO3) \
 543         FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
 544         FM(QSPI1_IO2) FM(QSPI1_IO3) \
 545         FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
 546         FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
 547         FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
 548         FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
 549         FM(PRESETOUT) \
 550         FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
 551         FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
 552
 553 enum {
 554         PINMUX_RESERVED = 0,
 555
 556         PINMUX_DATA_BEGIN,
 557         GP_ALL(DATA),
 558         PINMUX_DATA_END,
 559
 560 #define F_(x, y)
 561 #define FM(x)   FN_##x,
 562         PINMUX_FUNCTION_BEGIN,
 563         GP_ALL(FN),
 564         PINMUX_GPSR
 565         PINMUX_IPSR
 566         PINMUX_MOD_SELS
 567         PINMUX_FUNCTION_END,
 568 #undef F_
 569 #undef FM
 570
 571 #define F_(x, y)
 572 #define FM(x)   x##_MARK,
 573         PINMUX_MARK_BEGIN,
 574         PINMUX_GPSR
 575         PINMUX_IPSR
 576         PINMUX_MOD_SELS
 577         PINMUX_STATIC
 578         PINMUX_MARK_END,
 579 #undef F_
 580 #undef FM
 581 };
 582
 583 static const u16 pinmux_data[] = {
 584         PINMUX_DATA_GP_ALL(),
 585
 586         PINMUX_SINGLE(AVS1),
 587         PINMUX_SINGLE(AVS2),
 588         PINMUX_SINGLE(CLKOUT),
 589         PINMUX_SINGLE(HDMI0_CEC),
 590         PINMUX_SINGLE(HDMI1_CEC),
 591         PINMUX_SINGLE(I2C_SEL_0_1),
 592         PINMUX_SINGLE(I2C_SEL_3_1),
 593         PINMUX_SINGLE(I2C_SEL_5_1),
 594         PINMUX_SINGLE(MSIOF0_RXD),
 595         PINMUX_SINGLE(MSIOF0_SCK),
 596         PINMUX_SINGLE(MSIOF0_TXD),
 597         PINMUX_SINGLE(SSI_SCK5),
 598         PINMUX_SINGLE(SSI_SDATA5),
 599         PINMUX_SINGLE(SSI_WS5),
 600
 601         /* IPSR0 */
 602         PINMUX_IPSR_GPSR(IP0_3_0,       AVB_MDC),
 603         PINMUX_IPSR_MSEL(IP0_3_0,       MSIOF2_SS2_C,           SEL_MSIOF2_2),
 604
 605         PINMUX_IPSR_GPSR(IP0_7_4,       AVB_MAGIC),
 606         PINMUX_IPSR_MSEL(IP0_7_4,       MSIOF2_SS1_C,           SEL_MSIOF2_2),
 607         PINMUX_IPSR_MSEL(IP0_7_4,       SCK4_A,                 SEL_SCIF4_0),
 608
 609         PINMUX_IPSR_GPSR(IP0_11_8,      AVB_PHY_INT),
 610         PINMUX_IPSR_MSEL(IP0_11_8,      MSIOF2_SYNC_C,          SEL_MSIOF2_2),
 611         PINMUX_IPSR_MSEL(IP0_11_8,      RX4_A,                  SEL_SCIF4_0),
 612
 613         PINMUX_IPSR_GPSR(IP0_15_12,     AVB_LINK),
 614         PINMUX_IPSR_MSEL(IP0_15_12,     MSIOF2_SCK_C,           SEL_MSIOF2_2),
 615         PINMUX_IPSR_MSEL(IP0_15_12,     TX4_A,                  SEL_SCIF4_0),
 616
 617         PINMUX_IPSR_MSEL(IP0_19_16,     AVB_AVTP_MATCH_A,       SEL_ETHERAVB_0),
 618         PINMUX_IPSR_MSEL(IP0_19_16,     MSIOF2_RXD_C,           SEL_MSIOF2_2),
 619         PINMUX_IPSR_MSEL(IP0_19_16,     CTS4_N_A,               SEL_SCIF4_0),
 620         PINMUX_IPSR_GPSR(IP0_19_16,     FSCLKST2_N_A),
 621
 622         PINMUX_IPSR_MSEL(IP0_23_20,     AVB_AVTP_CAPTURE_A,     SEL_ETHERAVB_0),
 623         PINMUX_IPSR_MSEL(IP0_23_20,     MSIOF2_TXD_C,           SEL_MSIOF2_2),
 624         PINMUX_IPSR_MSEL(IP0_23_20,     RTS4_N_A,               SEL_SCIF4_0),
 625
 626         PINMUX_IPSR_GPSR(IP0_27_24,     IRQ0),
 627         PINMUX_IPSR_GPSR(IP0_27_24,     QPOLB),
 628         PINMUX_IPSR_GPSR(IP0_27_24,     DU_CDE),
 629         PINMUX_IPSR_MSEL(IP0_27_24,     VI4_DATA0_B,            SEL_VIN4_1),
 630         PINMUX_IPSR_MSEL(IP0_27_24,     CAN0_TX_B,              SEL_RCAN0_1),
 631         PINMUX_IPSR_MSEL(IP0_27_24,     CANFD0_TX_B,            SEL_CANFD0_1),
 632         PINMUX_IPSR_MSEL(IP0_27_24,     MSIOF3_SS2_E,           SEL_MSIOF3_4),
 633
 634         PINMUX_IPSR_GPSR(IP0_31_28,     IRQ1),
 635         PINMUX_IPSR_GPSR(IP0_31_28,     QPOLA),
 636         PINMUX_IPSR_GPSR(IP0_31_28,     DU_DISP),
 637         PINMUX_IPSR_MSEL(IP0_31_28,     VI4_DATA1_B,            SEL_VIN4_1),
 638         PINMUX_IPSR_MSEL(IP0_31_28,     CAN0_RX_B,              SEL_RCAN0_1),
 639         PINMUX_IPSR_MSEL(IP0_31_28,     CANFD0_RX_B,            SEL_CANFD0_1),
 640         PINMUX_IPSR_MSEL(IP0_31_28,     MSIOF3_SS1_E,           SEL_MSIOF3_4),
 641
 642         /* IPSR1 */
 643         PINMUX_IPSR_GPSR(IP1_3_0,       IRQ2),
 644         PINMUX_IPSR_GPSR(IP1_3_0,       QCPV_QDE),
 645         PINMUX_IPSR_GPSR(IP1_3_0,       DU_EXODDF_DU_ODDF_DISP_CDE),
 646         PINMUX_IPSR_MSEL(IP1_3_0,       VI4_DATA2_B,            SEL_VIN4_1),
 647         PINMUX_IPSR_MSEL(IP1_3_0,       PWM3_B,                 SEL_PWM3_1),
 648         PINMUX_IPSR_MSEL(IP1_3_0,       MSIOF3_SYNC_E,          SEL_MSIOF3_4),
 649
 650         PINMUX_IPSR_GPSR(IP1_7_4,       IRQ3),
 651         PINMUX_IPSR_GPSR(IP1_7_4,       QSTVB_QVE),
 652         PINMUX_IPSR_GPSR(IP1_7_4,       DU_DOTCLKOUT1),
 653         PINMUX_IPSR_MSEL(IP1_7_4,       VI4_DATA3_B,            SEL_VIN4_1),
 654         PINMUX_IPSR_MSEL(IP1_7_4,       PWM4_B,                 SEL_PWM4_1),
 655         PINMUX_IPSR_MSEL(IP1_7_4,       MSIOF3_SCK_E,           SEL_MSIOF3_4),
 656
 657         PINMUX_IPSR_GPSR(IP1_11_8,      IRQ4),
 658         PINMUX_IPSR_GPSR(IP1_11_8,      QSTH_QHS),
 659         PINMUX_IPSR_GPSR(IP1_11_8,      DU_EXHSYNC_DU_HSYNC),
 660         PINMUX_IPSR_MSEL(IP1_11_8,      VI4_DATA4_B,            SEL_VIN4_1),
 661         PINMUX_IPSR_MSEL(IP1_11_8,      PWM5_B,                 SEL_PWM5_1),
 662         PINMUX_IPSR_MSEL(IP1_11_8,      MSIOF3_RXD_E,           SEL_MSIOF3_4),
 663
 664         PINMUX_IPSR_GPSR(IP1_15_12,     IRQ5),
 665         PINMUX_IPSR_GPSR(IP1_15_12,     QSTB_QHE),
 666         PINMUX_IPSR_GPSR(IP1_15_12,     DU_EXVSYNC_DU_VSYNC),
 667         PINMUX_IPSR_MSEL(IP1_15_12,     VI4_DATA5_B,            SEL_VIN4_1),
 668         PINMUX_IPSR_MSEL(IP1_15_12,     PWM6_B,                 SEL_PWM6_1),
 669         PINMUX_IPSR_GPSR(IP1_15_12,     FSCLKST2_N_B),
 670         PINMUX_IPSR_MSEL(IP1_15_12,     MSIOF3_TXD_E,           SEL_MSIOF3_4),
 671
 672         PINMUX_IPSR_GPSR(IP1_19_16,     PWM0),
 673         PINMUX_IPSR_GPSR(IP1_19_16,     AVB_AVTP_PPS),
 674         PINMUX_IPSR_MSEL(IP1_19_16,     VI4_DATA6_B,            SEL_VIN4_1),
 675         PINMUX_IPSR_MSEL(IP1_19_16,     IECLK_B,                SEL_IEBUS_1),
 676
 677         PINMUX_IPSR_MSEL(IP1_23_20,     PWM1_A,                 SEL_PWM1_0),
 678         PINMUX_IPSR_MSEL(IP1_23_20,     HRX3_D,                 SEL_HSCIF3_3),
 679         PINMUX_IPSR_MSEL(IP1_23_20,     VI4_DATA7_B,            SEL_VIN4_1),
 680         PINMUX_IPSR_MSEL(IP1_23_20,     IERX_B,                 SEL_IEBUS_1),
 681
 682         PINMUX_IPSR_MSEL(IP1_27_24,     PWM2_A,                 SEL_PWM2_0),
 683         PINMUX_IPSR_MSEL(IP1_27_24,     HTX3_D,                 SEL_HSCIF3_3),
 684         PINMUX_IPSR_MSEL(IP1_27_24,     IETX_B,                 SEL_IEBUS_1),
 685
 686         PINMUX_IPSR_GPSR(IP1_31_28,     A0),
 687         PINMUX_IPSR_GPSR(IP1_31_28,     LCDOUT16),
 688         PINMUX_IPSR_MSEL(IP1_31_28,     MSIOF3_SYNC_B,          SEL_MSIOF3_1),
 689         PINMUX_IPSR_GPSR(IP1_31_28,     VI4_DATA8),
 690         PINMUX_IPSR_GPSR(IP1_31_28,     DU_DB0),
 691         PINMUX_IPSR_MSEL(IP1_31_28,     PWM3_A,                 SEL_PWM3_0),
 692
 693         /* IPSR2 */
 694         PINMUX_IPSR_GPSR(IP2_3_0,       A1),
 695         PINMUX_IPSR_GPSR(IP2_3_0,       LCDOUT17),
 696         PINMUX_IPSR_MSEL(IP2_3_0,       MSIOF3_TXD_B,           SEL_MSIOF3_1),
 697         PINMUX_IPSR_GPSR(IP2_3_0,       VI4_DATA9),
 698         PINMUX_IPSR_GPSR(IP2_3_0,       DU_DB1),
 699         PINMUX_IPSR_MSEL(IP2_3_0,       PWM4_A,                 SEL_PWM4_0),
 700
 701         PINMUX_IPSR_GPSR(IP2_7_4,       A2),
 702         PINMUX_IPSR_GPSR(IP2_7_4,       LCDOUT18),
 703         PINMUX_IPSR_MSEL(IP2_7_4,       MSIOF3_SCK_B,           SEL_MSIOF3_1),
 704         PINMUX_IPSR_GPSR(IP2_7_4,       VI4_DATA10),
 705         PINMUX_IPSR_GPSR(IP2_7_4,       DU_DB2),
 706         PINMUX_IPSR_MSEL(IP2_7_4,       PWM5_A,                 SEL_PWM5_0),
 707
 708         PINMUX_IPSR_GPSR(IP2_11_8,      A3),
 709         PINMUX_IPSR_GPSR(IP2_11_8,      LCDOUT19),
 710         PINMUX_IPSR_MSEL(IP2_11_8,      MSIOF3_RXD_B,           SEL_MSIOF3_1),
 711         PINMUX_IPSR_GPSR(IP2_11_8,      VI4_DATA11),
 712         PINMUX_IPSR_GPSR(IP2_11_8,      DU_DB3),
 713         PINMUX_IPSR_MSEL(IP2_11_8,      PWM6_A,                 SEL_PWM6_0),
 714
 715         PINMUX_IPSR_GPSR(IP2_15_12,     A4),
 716         PINMUX_IPSR_GPSR(IP2_15_12,     LCDOUT20),
 717         PINMUX_IPSR_MSEL(IP2_15_12,     MSIOF3_SS1_B,           SEL_MSIOF3_1),
 718         PINMUX_IPSR_GPSR(IP2_15_12,     VI4_DATA12),
 719         PINMUX_IPSR_GPSR(IP2_15_12,     VI5_DATA12),
 720         PINMUX_IPSR_GPSR(IP2_15_12,     DU_DB4),
 721
 722         PINMUX_IPSR_GPSR(IP2_19_16,     A5),
 723         PINMUX_IPSR_GPSR(IP2_19_16,     LCDOUT21),
 724         PINMUX_IPSR_MSEL(IP2_19_16,     MSIOF3_SS2_B,           SEL_MSIOF3_1),
 725         PINMUX_IPSR_MSEL(IP2_19_16,     SCK4_B,                 SEL_SCIF4_1),
 726         PINMUX_IPSR_GPSR(IP2_19_16,     VI4_DATA13),
 727         PINMUX_IPSR_GPSR(IP2_19_16,     VI5_DATA13),
 728         PINMUX_IPSR_GPSR(IP2_19_16,     DU_DB5),
 729
 730         PINMUX_IPSR_GPSR(IP2_23_20,     A6),
 731         PINMUX_IPSR_GPSR(IP2_23_20,     LCDOUT22),
 732         PINMUX_IPSR_MSEL(IP2_23_20,     MSIOF2_SS1_A,           SEL_MSIOF2_0),
 733         PINMUX_IPSR_MSEL(IP2_23_20,     RX4_B,                  SEL_SCIF4_1),
 734         PINMUX_IPSR_GPSR(IP2_23_20,     VI4_DATA14),
 735         PINMUX_IPSR_GPSR(IP2_23_20,     VI5_DATA14),
 736         PINMUX_IPSR_GPSR(IP2_23_20,     DU_DB6),
 737
 738         PINMUX_IPSR_GPSR(IP2_27_24,     A7),
 739         PINMUX_IPSR_GPSR(IP2_27_24,     LCDOUT23),
 740         PINMUX_IPSR_MSEL(IP2_27_24,     MSIOF2_SS2_A,           SEL_MSIOF2_0),
 741         PINMUX_IPSR_MSEL(IP2_27_24,     TX4_B,                  SEL_SCIF4_1),
 742         PINMUX_IPSR_GPSR(IP2_27_24,     VI4_DATA15),
 743         PINMUX_IPSR_GPSR(IP2_27_24,     VI5_DATA15),
 744         PINMUX_IPSR_GPSR(IP2_27_24,     DU_DB7),
 745
 746         PINMUX_IPSR_GPSR(IP2_31_28,     A8),
 747         PINMUX_IPSR_MSEL(IP2_31_28,     RX3_B,                  SEL_SCIF3_1),
 748         PINMUX_IPSR_MSEL(IP2_31_28,     MSIOF2_SYNC_A,          SEL_MSIOF2_0),
 749         PINMUX_IPSR_MSEL(IP2_31_28,     HRX4_B,                 SEL_HSCIF4_1),
 750         PINMUX_IPSR_MSEL(IP2_31_28,     SDA6_A,                 SEL_I2C6_0),
 751         PINMUX_IPSR_MSEL(IP2_31_28,     AVB_AVTP_MATCH_B,       SEL_ETHERAVB_1),
 752         PINMUX_IPSR_MSEL(IP2_31_28,     PWM1_B,                 SEL_PWM1_1),
 753
 754         /* IPSR3 */
 755         PINMUX_IPSR_GPSR(IP3_3_0,       A9),
 756         PINMUX_IPSR_MSEL(IP3_3_0,       MSIOF2_SCK_A,           SEL_MSIOF2_0),
 757         PINMUX_IPSR_MSEL(IP3_3_0,       CTS4_N_B,               SEL_SCIF4_1),
 758         PINMUX_IPSR_GPSR(IP3_3_0,       VI5_VSYNC_N),
 759
 760         PINMUX_IPSR_GPSR(IP3_7_4,       A10),
 761         PINMUX_IPSR_MSEL(IP3_7_4,       MSIOF2_RXD_A,           SEL_MSIOF2_0),
 762         PINMUX_IPSR_MSEL(IP3_7_4,       RTS4_N_B,               SEL_SCIF4_1),
 763         PINMUX_IPSR_GPSR(IP3_7_4,       VI5_HSYNC_N),
 764
 765         PINMUX_IPSR_GPSR(IP3_11_8,      A11),
 766         PINMUX_IPSR_MSEL(IP3_11_8,      TX3_B,                  SEL_SCIF3_1),
 767         PINMUX_IPSR_MSEL(IP3_11_8,      MSIOF2_TXD_A,           SEL_MSIOF2_0),
 768         PINMUX_IPSR_MSEL(IP3_11_8,      HTX4_B,                 SEL_HSCIF4_1),
 769         PINMUX_IPSR_GPSR(IP3_11_8,      HSCK4),
 770         PINMUX_IPSR_GPSR(IP3_11_8,      VI5_FIELD),
 771         PINMUX_IPSR_MSEL(IP3_11_8,      SCL6_A,                 SEL_I2C6_0),
 772         PINMUX_IPSR_MSEL(IP3_11_8,      AVB_AVTP_CAPTURE_B,     SEL_ETHERAVB_1),
 773         PINMUX_IPSR_MSEL(IP3_11_8,      PWM2_B,                 SEL_PWM2_1),
 774
 775         PINMUX_IPSR_GPSR(IP3_15_12,     A12),
 776         PINMUX_IPSR_GPSR(IP3_15_12,     LCDOUT12),
 777         PINMUX_IPSR_MSEL(IP3_15_12,     MSIOF3_SCK_C,           SEL_MSIOF3_2),
 778         PINMUX_IPSR_MSEL(IP3_15_12,     HRX4_A,                 SEL_HSCIF4_0),
 779         PINMUX_IPSR_GPSR(IP3_15_12,     VI5_DATA8),
 780         PINMUX_IPSR_GPSR(IP3_15_12,     DU_DG4),
 781
 782         PINMUX_IPSR_GPSR(IP3_19_16,     A13),
 783         PINMUX_IPSR_GPSR(IP3_19_16,     LCDOUT13),
 784         PINMUX_IPSR_MSEL(IP3_19_16,     MSIOF3_SYNC_C,          SEL_MSIOF3_2),
 785         PINMUX_IPSR_MSEL(IP3_19_16,     HTX4_A,                 SEL_HSCIF4_0),
 786         PINMUX_IPSR_GPSR(IP3_19_16,     VI5_DATA9),
 787         PINMUX_IPSR_GPSR(IP3_19_16,     DU_DG5),
 788
 789         PINMUX_IPSR_GPSR(IP3_23_20,     A14),
 790         PINMUX_IPSR_GPSR(IP3_23_20,     LCDOUT14),
 791         PINMUX_IPSR_MSEL(IP3_23_20,     MSIOF3_RXD_C,           SEL_MSIOF3_2),
 792         PINMUX_IPSR_GPSR(IP3_23_20,     HCTS4_N),
 793         PINMUX_IPSR_GPSR(IP3_23_20,     VI5_DATA10),
 794         PINMUX_IPSR_GPSR(IP3_23_20,     DU_DG6),
 795
 796         PINMUX_IPSR_GPSR(IP3_27_24,     A15),
 797         PINMUX_IPSR_GPSR(IP3_27_24,     LCDOUT15),
 798         PINMUX_IPSR_MSEL(IP3_27_24,     MSIOF3_TXD_C,           SEL_MSIOF3_2),
 799         PINMUX_IPSR_GPSR(IP3_27_24,     HRTS4_N),
 800         PINMUX_IPSR_GPSR(IP3_27_24,     VI5_DATA11),
 801         PINMUX_IPSR_GPSR(IP3_27_24,     DU_DG7),
 802
 803         PINMUX_IPSR_GPSR(IP3_31_28,     A16),
 804         PINMUX_IPSR_GPSR(IP3_31_28,     LCDOUT8),
 805         PINMUX_IPSR_GPSR(IP3_31_28,     VI4_FIELD),
 806         PINMUX_IPSR_GPSR(IP3_31_28,     DU_DG0),
 807
 808         /* IPSR4 */
 809         PINMUX_IPSR_GPSR(IP4_3_0,       A17),
 810         PINMUX_IPSR_GPSR(IP4_3_0,       LCDOUT9),
 811         PINMUX_IPSR_GPSR(IP4_3_0,       VI4_VSYNC_N),
 812         PINMUX_IPSR_GPSR(IP4_3_0,       DU_DG1),
 813
 814         PINMUX_IPSR_GPSR(IP4_7_4,       A18),
 815         PINMUX_IPSR_GPSR(IP4_7_4,       LCDOUT10),
 816         PINMUX_IPSR_GPSR(IP4_7_4,       VI4_HSYNC_N),
 817         PINMUX_IPSR_GPSR(IP4_7_4,       DU_DG2),
 818
 819         PINMUX_IPSR_GPSR(IP4_11_8,      A19),
 820         PINMUX_IPSR_GPSR(IP4_11_8,      LCDOUT11),
 821         PINMUX_IPSR_GPSR(IP4_11_8,      VI4_CLKENB),
 822         PINMUX_IPSR_GPSR(IP4_11_8,      DU_DG3),
 823
 824         PINMUX_IPSR_GPSR(IP4_15_12,     CS0_N),
 825         PINMUX_IPSR_GPSR(IP4_15_12,     VI5_CLKENB),
 826
 827         PINMUX_IPSR_GPSR(IP4_19_16,     CS1_N),
 828         PINMUX_IPSR_GPSR(IP4_19_16,     VI5_CLK),
 829         PINMUX_IPSR_MSEL(IP4_19_16,     EX_WAIT0_B,             SEL_LBSC_1),
 830
 831         PINMUX_IPSR_GPSR(IP4_23_20,     BS_N),
 832         PINMUX_IPSR_GPSR(IP4_23_20,     QSTVA_QVS),
 833         PINMUX_IPSR_MSEL(IP4_23_20,     MSIOF3_SCK_D,           SEL_MSIOF3_3),
 834         PINMUX_IPSR_GPSR(IP4_23_20,     SCK3),
 835         PINMUX_IPSR_GPSR(IP4_23_20,     HSCK3),
 836         PINMUX_IPSR_GPSR(IP4_23_20,     CAN1_TX),
 837         PINMUX_IPSR_GPSR(IP4_23_20,     CANFD1_TX),
 838         PINMUX_IPSR_MSEL(IP4_23_20,     IETX_A,                 SEL_IEBUS_0),
 839
 840         PINMUX_IPSR_GPSR(IP4_27_24,     RD_N),
 841         PINMUX_IPSR_MSEL(IP4_27_24,     MSIOF3_SYNC_D,          SEL_MSIOF3_3),
 842         PINMUX_IPSR_MSEL(IP4_27_24,     RX3_A,                  SEL_SCIF3_0),
 843         PINMUX_IPSR_MSEL(IP4_27_24,     HRX3_A,                 SEL_HSCIF3_0),
 844         PINMUX_IPSR_MSEL(IP4_27_24,     CAN0_TX_A,              SEL_RCAN0_0),
 845         PINMUX_IPSR_MSEL(IP4_27_24,     CANFD0_TX_A,            SEL_CANFD0_0),
 846
 847         PINMUX_IPSR_GPSR(IP4_31_28,     RD_WR_N),
 848         PINMUX_IPSR_MSEL(IP4_31_28,     MSIOF3_RXD_D,           SEL_MSIOF3_3),
 849         PINMUX_IPSR_MSEL(IP4_31_28,     TX3_A,                  SEL_SCIF3_0),
 850         PINMUX_IPSR_MSEL(IP4_31_28,     HTX3_A,                 SEL_HSCIF3_0),
 851         PINMUX_IPSR_MSEL(IP4_31_28,     CAN0_RX_A,              SEL_RCAN0_0),
 852         PINMUX_IPSR_MSEL(IP4_31_28,     CANFD0_RX_A,            SEL_CANFD0_0),
 853
 854         /* IPSR5 */
 855         PINMUX_IPSR_GPSR(IP5_3_0,       WE0_N),
 856         PINMUX_IPSR_MSEL(IP5_3_0,       MSIOF3_TXD_D,           SEL_MSIOF3_3),
 857         PINMUX_IPSR_GPSR(IP5_3_0,       CTS3_N),
 858         PINMUX_IPSR_GPSR(IP5_3_0,       HCTS3_N),
 859         PINMUX_IPSR_MSEL(IP5_3_0,       SCL6_B,                 SEL_I2C6_1),
 860         PINMUX_IPSR_GPSR(IP5_3_0,       CAN_CLK),
 861         PINMUX_IPSR_MSEL(IP5_3_0,       IECLK_A,                SEL_IEBUS_0),
 862
 863         PINMUX_IPSR_GPSR(IP5_7_4,       WE1_N),
 864         PINMUX_IPSR_MSEL(IP5_7_4,       MSIOF3_SS1_D,           SEL_MSIOF3_3),
 865         PINMUX_IPSR_GPSR(IP5_7_4,       RTS3_N),
 866         PINMUX_IPSR_GPSR(IP5_7_4,       HRTS3_N),
 867         PINMUX_IPSR_MSEL(IP5_7_4,       SDA6_B,                 SEL_I2C6_1),
 868         PINMUX_IPSR_GPSR(IP5_7_4,       CAN1_RX),
 869         PINMUX_IPSR_GPSR(IP5_7_4,       CANFD1_RX),
 870         PINMUX_IPSR_MSEL(IP5_7_4,       IERX_A,                 SEL_IEBUS_0),
 871
 872         PINMUX_IPSR_MSEL(IP5_11_8,      EX_WAIT0_A,             SEL_LBSC_0),
 873         PINMUX_IPSR_GPSR(IP5_11_8,      QCLK),
 874         PINMUX_IPSR_GPSR(IP5_11_8,      VI4_CLK),
 875         PINMUX_IPSR_GPSR(IP5_11_8,      DU_DOTCLKOUT0),
 876
 877         PINMUX_IPSR_GPSR(IP5_15_12,     D0),
 878         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF2_SS1_B,           SEL_MSIOF2_1),
 879         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF3_SCK_A,           SEL_MSIOF3_0),
 880         PINMUX_IPSR_GPSR(IP5_15_12,     VI4_DATA16),
 881         PINMUX_IPSR_GPSR(IP5_15_12,     VI5_DATA0),
 882
 883         PINMUX_IPSR_GPSR(IP5_19_16,     D1),
 884         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF2_SS2_B,           SEL_MSIOF2_1),
 885         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF3_SYNC_A,          SEL_MSIOF3_0),
 886         PINMUX_IPSR_GPSR(IP5_19_16,     VI4_DATA17),
 887         PINMUX_IPSR_GPSR(IP5_19_16,     VI5_DATA1),
 888
 889         PINMUX_IPSR_GPSR(IP5_23_20,     D2),
 890         PINMUX_IPSR_MSEL(IP5_23_20,     MSIOF3_RXD_A,           SEL_MSIOF3_0),
 891         PINMUX_IPSR_GPSR(IP5_23_20,     VI4_DATA18),
 892         PINMUX_IPSR_GPSR(IP5_23_20,     VI5_DATA2),
 893
 894         PINMUX_IPSR_GPSR(IP5_27_24,     D3),
 895         PINMUX_IPSR_MSEL(IP5_27_24,     MSIOF3_TXD_A,           SEL_MSIOF3_0),
 896         PINMUX_IPSR_GPSR(IP5_27_24,     VI4_DATA19),
 897         PINMUX_IPSR_GPSR(IP5_27_24,     VI5_DATA3),
 898
 899         PINMUX_IPSR_GPSR(IP5_31_28,     D4),
 900         PINMUX_IPSR_MSEL(IP5_31_28,     MSIOF2_SCK_B,           SEL_MSIOF2_1),
 901         PINMUX_IPSR_GPSR(IP5_31_28,     VI4_DATA20),
 902         PINMUX_IPSR_GPSR(IP5_31_28,     VI5_DATA4),
 903
 904         /* IPSR6 */
 905         PINMUX_IPSR_GPSR(IP6_3_0,       D5),
 906         PINMUX_IPSR_MSEL(IP6_3_0,       MSIOF2_SYNC_B,          SEL_MSIOF2_1),
 907         PINMUX_IPSR_GPSR(IP6_3_0,       VI4_DATA21),
 908         PINMUX_IPSR_GPSR(IP6_3_0,       VI5_DATA5),
 909
 910         PINMUX_IPSR_GPSR(IP6_7_4,       D6),
 911         PINMUX_IPSR_MSEL(IP6_7_4,       MSIOF2_RXD_B,           SEL_MSIOF2_1),
 912         PINMUX_IPSR_GPSR(IP6_7_4,       VI4_DATA22),
 913         PINMUX_IPSR_GPSR(IP6_7_4,       VI5_DATA6),
 914
 915         PINMUX_IPSR_GPSR(IP6_11_8,      D7),
 916         PINMUX_IPSR_MSEL(IP6_11_8,      MSIOF2_TXD_B,           SEL_MSIOF2_1),
 917         PINMUX_IPSR_GPSR(IP6_11_8,      VI4_DATA23),
 918         PINMUX_IPSR_GPSR(IP6_11_8,      VI5_DATA7),
 919
 920         PINMUX_IPSR_GPSR(IP6_15_12,     D8),
 921         PINMUX_IPSR_GPSR(IP6_15_12,     LCDOUT0),
 922         PINMUX_IPSR_MSEL(IP6_15_12,     MSIOF2_SCK_D,           SEL_MSIOF2_3),
 923         PINMUX_IPSR_MSEL(IP6_15_12,     SCK4_C,                 SEL_SCIF4_2),
 924         PINMUX_IPSR_MSEL(IP6_15_12,     VI4_DATA0_A,            SEL_VIN4_0),
 925         PINMUX_IPSR_GPSR(IP6_15_12,     DU_DR0),
 926
 927         PINMUX_IPSR_GPSR(IP6_19_16,     D9),
 928         PINMUX_IPSR_GPSR(IP6_19_16,     LCDOUT1),
 929         PINMUX_IPSR_MSEL(IP6_19_16,     MSIOF2_SYNC_D,          SEL_MSIOF2_3),
 930         PINMUX_IPSR_MSEL(IP6_19_16,     VI4_DATA1_A,            SEL_VIN4_0),
 931         PINMUX_IPSR_GPSR(IP6_19_16,     DU_DR1),
 932
 933         PINMUX_IPSR_GPSR(IP6_23_20,     D10),
 934         PINMUX_IPSR_GPSR(IP6_23_20,     LCDOUT2),
 935         PINMUX_IPSR_MSEL(IP6_23_20,     MSIOF2_RXD_D,           SEL_MSIOF2_3),
 936         PINMUX_IPSR_MSEL(IP6_23_20,     HRX3_B,                 SEL_HSCIF3_1),
 937         PINMUX_IPSR_MSEL(IP6_23_20,     VI4_DATA2_A,            SEL_VIN4_0),
 938         PINMUX_IPSR_MSEL(IP6_23_20,     CTS4_N_C,               SEL_SCIF4_2),
 939         PINMUX_IPSR_GPSR(IP6_23_20,     DU_DR2),
 940
 941         PINMUX_IPSR_GPSR(IP6_27_24,     D11),
 942         PINMUX_IPSR_GPSR(IP6_27_24,     LCDOUT3),
 943         PINMUX_IPSR_MSEL(IP6_27_24,     MSIOF2_TXD_D,           SEL_MSIOF2_3),
 944         PINMUX_IPSR_MSEL(IP6_27_24,     HTX3_B,                 SEL_HSCIF3_1),
 945         PINMUX_IPSR_MSEL(IP6_27_24,     VI4_DATA3_A,            SEL_VIN4_0),
 946         PINMUX_IPSR_MSEL(IP6_27_24,     RTS4_N_C,               SEL_SCIF4_2),
 947         PINMUX_IPSR_GPSR(IP6_27_24,     DU_DR3),
 948
 949         PINMUX_IPSR_GPSR(IP6_31_28,     D12),
 950         PINMUX_IPSR_GPSR(IP6_31_28,     LCDOUT4),
 951         PINMUX_IPSR_MSEL(IP6_31_28,     MSIOF2_SS1_D,           SEL_MSIOF2_3),
 952         PINMUX_IPSR_MSEL(IP6_31_28,     RX4_C,                  SEL_SCIF4_2),
 953         PINMUX_IPSR_MSEL(IP6_31_28,     VI4_DATA4_A,            SEL_VIN4_0),
 954         PINMUX_IPSR_GPSR(IP6_31_28,     DU_DR4),
 955
 956         /* IPSR7 */
 957         PINMUX_IPSR_GPSR(IP7_3_0,       D13),
 958         PINMUX_IPSR_GPSR(IP7_3_0,       LCDOUT5),
 959         PINMUX_IPSR_MSEL(IP7_3_0,       MSIOF2_SS2_D,           SEL_MSIOF2_3),
 960         PINMUX_IPSR_MSEL(IP7_3_0,       TX4_C,                  SEL_SCIF4_2),
 961         PINMUX_IPSR_MSEL(IP7_3_0,       VI4_DATA5_A,            SEL_VIN4_0),
 962         PINMUX_IPSR_GPSR(IP7_3_0,       DU_DR5),
 963
 964         PINMUX_IPSR_GPSR(IP7_7_4,       D14),
 965         PINMUX_IPSR_GPSR(IP7_7_4,       LCDOUT6),
 966         PINMUX_IPSR_MSEL(IP7_7_4,       MSIOF3_SS1_A,           SEL_MSIOF3_0),
 967         PINMUX_IPSR_MSEL(IP7_7_4,       HRX3_C,                 SEL_HSCIF3_2),
 968         PINMUX_IPSR_MSEL(IP7_7_4,       VI4_DATA6_A,            SEL_VIN4_0),
 969         PINMUX_IPSR_GPSR(IP7_7_4,       DU_DR6),
 970         PINMUX_IPSR_MSEL(IP7_7_4,       SCL6_C,                 SEL_I2C6_2),
 971
 972         PINMUX_IPSR_GPSR(IP7_11_8,      D15),
 973         PINMUX_IPSR_GPSR(IP7_11_8,      LCDOUT7),
 974         PINMUX_IPSR_MSEL(IP7_11_8,      MSIOF3_SS2_A,           SEL_MSIOF3_0),
 975         PINMUX_IPSR_MSEL(IP7_11_8,      HTX3_C,                 SEL_HSCIF3_2),
 976         PINMUX_IPSR_MSEL(IP7_11_8,      VI4_DATA7_A,            SEL_VIN4_0),
 977         PINMUX_IPSR_GPSR(IP7_11_8,      DU_DR7),
 978         PINMUX_IPSR_MSEL(IP7_11_8,      SDA6_C,                 SEL_I2C6_2),
 979
 980         PINMUX_IPSR_GPSR(IP7_19_16,     SD0_CLK),
 981         PINMUX_IPSR_MSEL(IP7_19_16,     MSIOF1_SCK_E,           SEL_MSIOF1_4),
 982         PINMUX_IPSR_MSEL(IP7_19_16,     STP_OPWM_0_B,           SEL_SSP1_0_1),
 983
 984         PINMUX_IPSR_GPSR(IP7_23_20,     SD0_CMD),
 985         PINMUX_IPSR_MSEL(IP7_23_20,     MSIOF1_SYNC_E,          SEL_MSIOF1_4),
 986         PINMUX_IPSR_MSEL(IP7_23_20,     STP_IVCXO27_0_B,        SEL_SSP1_0_1),
 987
 988         PINMUX_IPSR_GPSR(IP7_27_24,     SD0_DAT0),
 989         PINMUX_IPSR_MSEL(IP7_27_24,     MSIOF1_RXD_E,           SEL_MSIOF1_4),
 990         PINMUX_IPSR_MSEL(IP7_27_24,     TS_SCK0_B,              SEL_TSIF0_1),
 991         PINMUX_IPSR_MSEL(IP7_27_24,     STP_ISCLK_0_B,          SEL_SSP1_0_1),
 992
 993         PINMUX_IPSR_GPSR(IP7_31_28,     SD0_DAT1),
 994         PINMUX_IPSR_MSEL(IP7_31_28,     MSIOF1_TXD_E,           SEL_MSIOF1_4),
 995         PINMUX_IPSR_MSEL(IP7_31_28,     TS_SPSYNC0_B,           SEL_TSIF0_1),
 996         PINMUX_IPSR_MSEL(IP7_31_28,     STP_ISSYNC_0_B,         SEL_SSP1_0_1),
 997
 998         /* IPSR8 */
 999         PINMUX_IPSR_GPSR(IP8_3_0,       SD0_DAT2),
1000         PINMUX_IPSR_MSEL(IP8_3_0,       MSIOF1_SS1_E,           SEL_MSIOF1_4),
1001         PINMUX_IPSR_MSEL(IP8_3_0,       TS_SDAT0_B,             SEL_TSIF0_1),
1002         PINMUX_IPSR_MSEL(IP8_3_0,       STP_ISD_0_B,            SEL_SSP1_0_1),
1003
1004         PINMUX_IPSR_GPSR(IP8_7_4,       SD0_DAT3),
1005         PINMUX_IPSR_MSEL(IP8_7_4,       MSIOF1_SS2_E,           SEL_MSIOF1_4),
1006         PINMUX_IPSR_MSEL(IP8_7_4,       TS_SDEN0_B,             SEL_TSIF0_1),
1007         PINMUX_IPSR_MSEL(IP8_7_4,       STP_ISEN_0_B,           SEL_SSP1_0_1),
1008
1009         PINMUX_IPSR_GPSR(IP8_11_8,      SD1_CLK),
1010         PINMUX_IPSR_MSEL(IP8_11_8,      MSIOF1_SCK_G,           SEL_MSIOF1_6),
1011         PINMUX_IPSR_MSEL(IP8_11_8,      SIM0_CLK_A,             SEL_SIMCARD_0),
1012
1013         PINMUX_IPSR_GPSR(IP8_15_12,     SD1_CMD),
1014         PINMUX_IPSR_MSEL(IP8_15_12,     MSIOF1_SYNC_G,          SEL_MSIOF1_6),
1015         PINMUX_IPSR_GPSR(IP8_15_12,     NFCE_N_B),
1016         PINMUX_IPSR_MSEL(IP8_15_12,     SIM0_D_A,               SEL_SIMCARD_0),
1017         PINMUX_IPSR_MSEL(IP8_15_12,     STP_IVCXO27_1_B,        SEL_SSP1_1_1),
1018
1019         PINMUX_IPSR_GPSR(IP8_19_16,     SD1_DAT0),
1020         PINMUX_IPSR_GPSR(IP8_19_16,     SD2_DAT4),
1021         PINMUX_IPSR_MSEL(IP8_19_16,     MSIOF1_RXD_G,           SEL_MSIOF1_6),
1022         PINMUX_IPSR_GPSR(IP8_19_16,     NFWP_N_B),
1023         PINMUX_IPSR_MSEL(IP8_19_16,     TS_SCK1_B,              SEL_TSIF1_1),
1024         PINMUX_IPSR_MSEL(IP8_19_16,     STP_ISCLK_1_B,          SEL_SSP1_1_1),
1025
1026         PINMUX_IPSR_GPSR(IP8_23_20,     SD1_DAT1),
1027         PINMUX_IPSR_GPSR(IP8_23_20,     SD2_DAT5),
1028         PINMUX_IPSR_MSEL(IP8_23_20,     MSIOF1_TXD_G,           SEL_MSIOF1_6),
1029         PINMUX_IPSR_GPSR(IP8_23_20,     NFDATA14_B),
1030         PINMUX_IPSR_MSEL(IP8_23_20,     TS_SPSYNC1_B,           SEL_TSIF1_1),
1031         PINMUX_IPSR_MSEL(IP8_23_20,     STP_ISSYNC_1_B,         SEL_SSP1_1_1),
1032
1033         PINMUX_IPSR_GPSR(IP8_27_24,     SD1_DAT2),
1034         PINMUX_IPSR_GPSR(IP8_27_24,     SD2_DAT6),
1035         PINMUX_IPSR_MSEL(IP8_27_24,     MSIOF1_SS1_G,           SEL_MSIOF1_6),
1036         PINMUX_IPSR_GPSR(IP8_27_24,     NFDATA15_B),
1037         PINMUX_IPSR_MSEL(IP8_27_24,     TS_SDAT1_B,             SEL_TSIF1_1),
1038         PINMUX_IPSR_MSEL(IP8_27_24,     STP_ISD_1_B,            SEL_SSP1_1_1),
1039
1040         PINMUX_IPSR_GPSR(IP8_31_28,     SD1_DAT3),
1041         PINMUX_IPSR_GPSR(IP8_31_28,     SD2_DAT7),
1042         PINMUX_IPSR_MSEL(IP8_31_28,     MSIOF1_SS2_G,           SEL_MSIOF1_6),
1043         PINMUX_IPSR_GPSR(IP8_31_28,     NFRB_N_B),
1044         PINMUX_IPSR_MSEL(IP8_31_28,     TS_SDEN1_B,             SEL_TSIF1_1),
1045         PINMUX_IPSR_MSEL(IP8_31_28,     STP_ISEN_1_B,           SEL_SSP1_1_1),
1046
1047         /* IPSR9 */
1048         PINMUX_IPSR_GPSR(IP9_3_0,       SD2_CLK),
1049         PINMUX_IPSR_GPSR(IP9_3_0,       NFDATA8),
1050
1051         PINMUX_IPSR_GPSR(IP9_7_4,       SD2_CMD),
1052         PINMUX_IPSR_GPSR(IP9_7_4,       NFDATA9),
1053
1054         PINMUX_IPSR_GPSR(IP9_11_8,      SD2_DAT0),
1055         PINMUX_IPSR_GPSR(IP9_11_8,      NFDATA10),
1056
1057         PINMUX_IPSR_GPSR(IP9_15_12,     SD2_DAT1),
1058         PINMUX_IPSR_GPSR(IP9_15_12,     NFDATA11),
1059
1060         PINMUX_IPSR_GPSR(IP9_19_16,     SD2_DAT2),
1061         PINMUX_IPSR_GPSR(IP9_19_16,     NFDATA12),
1062
1063         PINMUX_IPSR_GPSR(IP9_23_20,     SD2_DAT3),
1064         PINMUX_IPSR_GPSR(IP9_23_20,     NFDATA13),
1065
1066         PINMUX_IPSR_GPSR(IP9_27_24,     SD2_DS),
1067         PINMUX_IPSR_GPSR(IP9_27_24,     NFALE),
1068         PINMUX_IPSR_GPSR(IP9_27_24,     SATA_DEVSLP_B),
1069
1070         PINMUX_IPSR_GPSR(IP9_31_28,     SD3_CLK),
1071         PINMUX_IPSR_GPSR(IP9_31_28,     NFWE_N),
1072
1073         /* IPSR10 */
1074         PINMUX_IPSR_GPSR(IP10_3_0,      SD3_CMD),
1075         PINMUX_IPSR_GPSR(IP10_3_0,      NFRE_N),
1076
1077         PINMUX_IPSR_GPSR(IP10_7_4,      SD3_DAT0),
1078         PINMUX_IPSR_GPSR(IP10_7_4,      NFDATA0),
1079
1080         PINMUX_IPSR_GPSR(IP10_11_8,     SD3_DAT1),
1081         PINMUX_IPSR_GPSR(IP10_11_8,     NFDATA1),
1082
1083         PINMUX_IPSR_GPSR(IP10_15_12,    SD3_DAT2),
1084         PINMUX_IPSR_GPSR(IP10_15_12,    NFDATA2),
1085
1086         PINMUX_IPSR_GPSR(IP10_19_16,    SD3_DAT3),
1087         PINMUX_IPSR_GPSR(IP10_19_16,    NFDATA3),
1088
1089         PINMUX_IPSR_GPSR(IP10_23_20,    SD3_DAT4),
1090         PINMUX_IPSR_MSEL(IP10_23_20,    SD2_CD_A,               SEL_SDHI2_0),
1091         PINMUX_IPSR_GPSR(IP10_23_20,    NFDATA4),
1092
1093         PINMUX_IPSR_GPSR(IP10_27_24,    SD3_DAT5),
1094         PINMUX_IPSR_MSEL(IP10_27_24,    SD2_WP_A,               SEL_SDHI2_0),
1095         PINMUX_IPSR_GPSR(IP10_27_24,    NFDATA5),
1096
1097         PINMUX_IPSR_GPSR(IP10_31_28,    SD3_DAT6),
1098         PINMUX_IPSR_GPSR(IP10_31_28,    SD3_CD),
1099         PINMUX_IPSR_GPSR(IP10_31_28,    NFDATA6),
1100
1101         /* IPSR11 */
1102         PINMUX_IPSR_GPSR(IP11_3_0,      SD3_DAT7),
1103         PINMUX_IPSR_GPSR(IP11_3_0,      SD3_WP),
1104         PINMUX_IPSR_GPSR(IP11_3_0,      NFDATA7),
1105
1106         PINMUX_IPSR_GPSR(IP11_7_4,      SD3_DS),
1107         PINMUX_IPSR_GPSR(IP11_7_4,      NFCLE),
1108
1109         PINMUX_IPSR_GPSR(IP11_11_8,     SD0_CD),
1110         PINMUX_IPSR_MSEL(IP11_11_8,     SCL2_B,                 SEL_I2C2_1),
1111         PINMUX_IPSR_MSEL(IP11_11_8,     SIM0_RST_A,             SEL_SIMCARD_0),
1112
1113         PINMUX_IPSR_GPSR(IP11_15_12,    SD0_WP),
1114         PINMUX_IPSR_MSEL(IP11_15_12,    SDA2_B,                 SEL_I2C2_1),
1115
1116         PINMUX_IPSR_GPSR(IP11_19_16,    SD1_CD),
1117         PINMUX_IPSR_MSEL(IP11_19_16,    SIM0_CLK_B,             SEL_SIMCARD_1),
1118
1119         PINMUX_IPSR_GPSR(IP11_23_20,    SD1_WP),
1120         PINMUX_IPSR_MSEL(IP11_23_20,    SIM0_D_B,               SEL_SIMCARD_1),
1121
1122         PINMUX_IPSR_GPSR(IP11_27_24,    SCK0),
1123         PINMUX_IPSR_MSEL(IP11_27_24,    HSCK1_B,                SEL_HSCIF1_1),
1124         PINMUX_IPSR_MSEL(IP11_27_24,    MSIOF1_SS2_B,           SEL_MSIOF1_1),
1125         PINMUX_IPSR_MSEL(IP11_27_24,    AUDIO_CLKC_B,           SEL_ADG_C_1),
1126         PINMUX_IPSR_MSEL(IP11_27_24,    SDA2_A,                 SEL_I2C2_0),
1127         PINMUX_IPSR_MSEL(IP11_27_24,    SIM0_RST_B,             SEL_SIMCARD_1),
1128         PINMUX_IPSR_MSEL(IP11_27_24,    STP_OPWM_0_C,           SEL_SSP1_0_2),
1129         PINMUX_IPSR_MSEL(IP11_27_24,    RIF0_CLK_B,             SEL_DRIF0_1),
1130         PINMUX_IPSR_GPSR(IP11_27_24,    ADICHS2),
1131         PINMUX_IPSR_MSEL(IP11_27_24,    SCK5_B,                 SEL_SCIF5_1),
1132
1133         PINMUX_IPSR_GPSR(IP11_31_28,    RX0),
1134         PINMUX_IPSR_MSEL(IP11_31_28,    HRX1_B,                 SEL_HSCIF1_1),
1135         PINMUX_IPSR_MSEL(IP11_31_28,    TS_SCK0_C,              SEL_TSIF0_2),
1136         PINMUX_IPSR_MSEL(IP11_31_28,    STP_ISCLK_0_C,          SEL_SSP1_0_2),
1137         PINMUX_IPSR_MSEL(IP11_31_28,    RIF0_D0_B,              SEL_DRIF0_1),
1138
1139         /* IPSR12 */
1140         PINMUX_IPSR_GPSR(IP12_3_0,      TX0),
1141         PINMUX_IPSR_MSEL(IP12_3_0,      HTX1_B,                 SEL_HSCIF1_1),
1142         PINMUX_IPSR_MSEL(IP12_3_0,      TS_SPSYNC0_C,           SEL_TSIF0_2),
1143         PINMUX_IPSR_MSEL(IP12_3_0,      STP_ISSYNC_0_C,         SEL_SSP1_0_2),
1144         PINMUX_IPSR_MSEL(IP12_3_0,      RIF0_D1_B,              SEL_DRIF0_1),
1145
1146         PINMUX_IPSR_GPSR(IP12_7_4,      CTS0_N),
1147         PINMUX_IPSR_MSEL(IP12_7_4,      HCTS1_N_B,              SEL_HSCIF1_1),
1148         PINMUX_IPSR_MSEL(IP12_7_4,      MSIOF1_SYNC_B,          SEL_MSIOF1_1),
1149         PINMUX_IPSR_MSEL(IP12_7_4,      TS_SPSYNC1_C,           SEL_TSIF1_2),
1150         PINMUX_IPSR_MSEL(IP12_7_4,      STP_ISSYNC_1_C,         SEL_SSP1_1_2),
1151         PINMUX_IPSR_MSEL(IP12_7_4,      RIF1_SYNC_B,            SEL_DRIF1_1),
1152         PINMUX_IPSR_GPSR(IP12_7_4,      AUDIO_CLKOUT_C),
1153         PINMUX_IPSR_GPSR(IP12_7_4,      ADICS_SAMP),
1154
1155         PINMUX_IPSR_GPSR(IP12_11_8,     RTS0_N),
1156         PINMUX_IPSR_MSEL(IP12_11_8,     HRTS1_N_B,              SEL_HSCIF1_1),
1157         PINMUX_IPSR_MSEL(IP12_11_8,     MSIOF1_SS1_B,           SEL_MSIOF1_1),
1158         PINMUX_IPSR_MSEL(IP12_11_8,     AUDIO_CLKA_B,           SEL_ADG_A_1),
1159         PINMUX_IPSR_MSEL(IP12_11_8,     SCL2_A,                 SEL_I2C2_0),
1160         PINMUX_IPSR_MSEL(IP12_11_8,     STP_IVCXO27_1_C,        SEL_SSP1_1_2),
1161         PINMUX_IPSR_MSEL(IP12_11_8,     RIF0_SYNC_B,            SEL_DRIF0_1),
1162         PINMUX_IPSR_GPSR(IP12_11_8,     ADICHS1),
1163
1164         PINMUX_IPSR_MSEL(IP12_15_12,    RX1_A,                  SEL_SCIF1_0),
1165         PINMUX_IPSR_MSEL(IP12_15_12,    HRX1_A,                 SEL_HSCIF1_0),
1166         PINMUX_IPSR_MSEL(IP12_15_12,    TS_SDAT0_C,             SEL_TSIF0_2),
1167         PINMUX_IPSR_MSEL(IP12_15_12,    STP_ISD_0_C,            SEL_SSP1_0_2),
1168         PINMUX_IPSR_MSEL(IP12_15_12,    RIF1_CLK_C,             SEL_DRIF1_2),
1169
1170         PINMUX_IPSR_MSEL(IP12_19_16,    TX1_A,                  SEL_SCIF1_0),
1171         PINMUX_IPSR_MSEL(IP12_19_16,    HTX1_A,                 SEL_HSCIF1_0),
1172         PINMUX_IPSR_MSEL(IP12_19_16,    TS_SDEN0_C,             SEL_TSIF0_2),
1173         PINMUX_IPSR_MSEL(IP12_19_16,    STP_ISEN_0_C,           SEL_SSP1_0_2),
1174         PINMUX_IPSR_MSEL(IP12_19_16,    RIF1_D0_C,              SEL_DRIF1_2),
1175
1176         PINMUX_IPSR_GPSR(IP12_23_20,    CTS1_N),
1177         PINMUX_IPSR_MSEL(IP12_23_20,    HCTS1_N_A,              SEL_HSCIF1_0),
1178         PINMUX_IPSR_MSEL(IP12_23_20,    MSIOF1_RXD_B,           SEL_MSIOF1_1),
1179         PINMUX_IPSR_MSEL(IP12_23_20,    TS_SDEN1_C,             SEL_TSIF1_2),
1180         PINMUX_IPSR_MSEL(IP12_23_20,    STP_ISEN_1_C,           SEL_SSP1_1_2),
1181         PINMUX_IPSR_MSEL(IP12_23_20,    RIF1_D0_B,              SEL_DRIF1_1),
1182         PINMUX_IPSR_GPSR(IP12_23_20,    ADIDATA),
1183
1184         PINMUX_IPSR_GPSR(IP12_27_24,    RTS1_N),
1185         PINMUX_IPSR_MSEL(IP12_27_24,    HRTS1_N_A,              SEL_HSCIF1_0),
1186         PINMUX_IPSR_MSEL(IP12_27_24,    MSIOF1_TXD_B,           SEL_MSIOF1_1),
1187         PINMUX_IPSR_MSEL(IP12_27_24,    TS_SDAT1_C,             SEL_TSIF1_2),
1188         PINMUX_IPSR_MSEL(IP12_27_24,    STP_ISD_1_C,            SEL_SSP1_1_2),
1189         PINMUX_IPSR_MSEL(IP12_27_24,    RIF1_D1_B,              SEL_DRIF1_1),
1190         PINMUX_IPSR_GPSR(IP12_27_24,    ADICHS0),
1191
1192         PINMUX_IPSR_GPSR(IP12_31_28,    SCK2),
1193         PINMUX_IPSR_MSEL(IP12_31_28,    SCIF_CLK_B,             SEL_SCIF_1),
1194         PINMUX_IPSR_MSEL(IP12_31_28,    MSIOF1_SCK_B,           SEL_MSIOF1_1),
1195         PINMUX_IPSR_MSEL(IP12_31_28,    TS_SCK1_C,              SEL_TSIF1_2),
1196         PINMUX_IPSR_MSEL(IP12_31_28,    STP_ISCLK_1_C,          SEL_SSP1_1_2),
1197         PINMUX_IPSR_MSEL(IP12_31_28,    RIF1_CLK_B,             SEL_DRIF1_1),
1198         PINMUX_IPSR_GPSR(IP12_31_28,    ADICLK),
1199
1200         /* IPSR13 */
1201         PINMUX_IPSR_MSEL(IP13_3_0,      TX2_A,                  SEL_SCIF2_0),
1202         PINMUX_IPSR_MSEL(IP13_3_0,      SD2_CD_B,               SEL_SDHI2_1),
1203         PINMUX_IPSR_MSEL(IP13_3_0,      SCL1_A,                 SEL_I2C1_0),
1204         PINMUX_IPSR_MSEL(IP13_3_0,      FMCLK_A,                SEL_FM_0),
1205         PINMUX_IPSR_MSEL(IP13_3_0,      RIF1_D1_C,              SEL_DRIF1_2),
1206         PINMUX_IPSR_GPSR(IP13_3_0,      FSO_CFE_0_N),
1207
1208         PINMUX_IPSR_MSEL(IP13_7_4,      RX2_A,                  SEL_SCIF2_0),
1209         PINMUX_IPSR_MSEL(IP13_7_4,      SD2_WP_B,               SEL_SDHI2_1),
1210         PINMUX_IPSR_MSEL(IP13_7_4,      SDA1_A,                 SEL_I2C1_0),
1211         PINMUX_IPSR_MSEL(IP13_7_4,      FMIN_A,                 SEL_FM_0),
1212         PINMUX_IPSR_MSEL(IP13_7_4,      RIF1_SYNC_C,            SEL_DRIF1_2),
1213         PINMUX_IPSR_GPSR(IP13_7_4,      FSO_CFE_1_N),
1214
1215         PINMUX_IPSR_GPSR(IP13_11_8,     HSCK0),
1216         PINMUX_IPSR_MSEL(IP13_11_8,     MSIOF1_SCK_D,           SEL_MSIOF1_3),
1217         PINMUX_IPSR_MSEL(IP13_11_8,     AUDIO_CLKB_A,           SEL_ADG_B_0),
1218         PINMUX_IPSR_MSEL(IP13_11_8,     SSI_SDATA1_B,           SEL_SSI1_1),
1219         PINMUX_IPSR_MSEL(IP13_11_8,     TS_SCK0_D,              SEL_TSIF0_3),
1220         PINMUX_IPSR_MSEL(IP13_11_8,     STP_ISCLK_0_D,          SEL_SSP1_0_3),
1221         PINMUX_IPSR_MSEL(IP13_11_8,     RIF0_CLK_C,             SEL_DRIF0_2),
1222         PINMUX_IPSR_MSEL(IP13_11_8,     RX5_B,                  SEL_SCIF5_1),
1223
1224         PINMUX_IPSR_GPSR(IP13_15_12,    HRX0),
1225         PINMUX_IPSR_MSEL(IP13_15_12,    MSIOF1_RXD_D,           SEL_MSIOF1_3),
1226         PINMUX_IPSR_MSEL(IP13_15_12,    SSI_SDATA2_B,           SEL_SSI2_1),
1227         PINMUX_IPSR_MSEL(IP13_15_12,    TS_SDEN0_D,             SEL_TSIF0_3),
1228         PINMUX_IPSR_MSEL(IP13_15_12,    STP_ISEN_0_D,           SEL_SSP1_0_3),
1229         PINMUX_IPSR_MSEL(IP13_15_12,    RIF0_D0_C,              SEL_DRIF0_2),
1230
1231         PINMUX_IPSR_GPSR(IP13_19_16,    HTX0),
1232         PINMUX_IPSR_MSEL(IP13_19_16,    MSIOF1_TXD_D,           SEL_MSIOF1_3),
1233         PINMUX_IPSR_MSEL(IP13_19_16,    SSI_SDATA9_B,           SEL_SSI9_1),
1234         PINMUX_IPSR_MSEL(IP13_19_16,    TS_SDAT0_D,             SEL_TSIF0_3),
1235         PINMUX_IPSR_MSEL(IP13_19_16,    STP_ISD_0_D,            SEL_SSP1_0_3),
1236         PINMUX_IPSR_MSEL(IP13_19_16,    RIF0_D1_C,              SEL_DRIF0_2),
1237
1238         PINMUX_IPSR_GPSR(IP13_23_20,    HCTS0_N),
1239         PINMUX_IPSR_MSEL(IP13_23_20,    RX2_B,                  SEL_SCIF2_1),
1240         PINMUX_IPSR_MSEL(IP13_23_20,    MSIOF1_SYNC_D,          SEL_MSIOF1_3),
1241         PINMUX_IPSR_MSEL(IP13_23_20,    SSI_SCK9_A,             SEL_SSI9_0),
1242         PINMUX_IPSR_MSEL(IP13_23_20,    TS_SPSYNC0_D,           SEL_TSIF0_3),
1243         PINMUX_IPSR_MSEL(IP13_23_20,    STP_ISSYNC_0_D,         SEL_SSP1_0_3),
1244         PINMUX_IPSR_MSEL(IP13_23_20,    RIF0_SYNC_C,            SEL_DRIF0_2),
1245         PINMUX_IPSR_GPSR(IP13_23_20,    AUDIO_CLKOUT1_A),
1246
1247         PINMUX_IPSR_GPSR(IP13_27_24,    HRTS0_N),
1248         PINMUX_IPSR_MSEL(IP13_27_24,    TX2_B,                  SEL_SCIF2_1),
1249         PINMUX_IPSR_MSEL(IP13_27_24,    MSIOF1_SS1_D,           SEL_MSIOF1_3),
1250         PINMUX_IPSR_MSEL(IP13_27_24,    SSI_WS9_A,              SEL_SSI9_0),
1251         PINMUX_IPSR_MSEL(IP13_27_24,    STP_IVCXO27_0_D,        SEL_SSP1_0_3),
1252         PINMUX_IPSR_MSEL(IP13_27_24,    BPFCLK_A,               SEL_FM_0),
1253         PINMUX_IPSR_GPSR(IP13_27_24,    AUDIO_CLKOUT2_A),
1254
1255         PINMUX_IPSR_GPSR(IP13_31_28,    MSIOF0_SYNC),
1256         PINMUX_IPSR_GPSR(IP13_31_28,    AUDIO_CLKOUT_A),
1257         PINMUX_IPSR_MSEL(IP13_31_28,    TX5_B,                  SEL_SCIF5_1),
1258         PINMUX_IPSR_MSEL(IP13_31_28,    BPFCLK_D,               SEL_FM_3),
1259
1260         /* IPSR14 */
1261         PINMUX_IPSR_GPSR(IP14_3_0,      MSIOF0_SS1),
1262         PINMUX_IPSR_MSEL(IP14_3_0,      RX5_A,                  SEL_SCIF5_0),
1263         PINMUX_IPSR_GPSR(IP14_3_0,      NFWP_N_A),
1264         PINMUX_IPSR_MSEL(IP14_3_0,      AUDIO_CLKA_C,           SEL_ADG_A_2),
1265         PINMUX_IPSR_MSEL(IP14_3_0,      SSI_SCK2_A,             SEL_SSI2_0),
1266         PINMUX_IPSR_MSEL(IP14_3_0,      STP_IVCXO27_0_C,        SEL_SSP1_0_2),
1267         PINMUX_IPSR_GPSR(IP14_3_0,      AUDIO_CLKOUT3_A),
1268         PINMUX_IPSR_MSEL(IP14_3_0,      TCLK1_B,                SEL_TIMER_TMU1_1),
1269
1270         PINMUX_IPSR_GPSR(IP14_7_4,      MSIOF0_SS2),
1271         PINMUX_IPSR_MSEL(IP14_7_4,      TX5_A,                  SEL_SCIF5_0),
1272         PINMUX_IPSR_MSEL(IP14_7_4,      MSIOF1_SS2_D,           SEL_MSIOF1_3),
1273         PINMUX_IPSR_MSEL(IP14_7_4,      AUDIO_CLKC_A,           SEL_ADG_C_0),
1274         PINMUX_IPSR_MSEL(IP14_7_4,      SSI_WS2_A,              SEL_SSI2_0),
1275         PINMUX_IPSR_MSEL(IP14_7_4,      STP_OPWM_0_D,           SEL_SSP1_0_3),
1276         PINMUX_IPSR_GPSR(IP14_7_4,      AUDIO_CLKOUT_D),
1277         PINMUX_IPSR_MSEL(IP14_7_4,      SPEEDIN_B,              SEL_SPEED_PULSE_1),
1278
1279         PINMUX_IPSR_GPSR(IP14_11_8,     MLB_CLK),
1280         PINMUX_IPSR_MSEL(IP14_11_8,     MSIOF1_SCK_F,           SEL_MSIOF1_5),
1281         PINMUX_IPSR_MSEL(IP14_11_8,     SCL1_B,                 SEL_I2C1_1),
1282
1283         PINMUX_IPSR_GPSR(IP14_15_12,    MLB_SIG),
1284         PINMUX_IPSR_MSEL(IP14_15_12,    RX1_B,                  SEL_SCIF1_1),
1285         PINMUX_IPSR_MSEL(IP14_15_12,    MSIOF1_SYNC_F,          SEL_MSIOF1_5),
1286         PINMUX_IPSR_MSEL(IP14_15_12,    SDA1_B,                 SEL_I2C1_1),
1287
1288         PINMUX_IPSR_GPSR(IP14_19_16,    MLB_DAT),
1289         PINMUX_IPSR_MSEL(IP14_19_16,    TX1_B,                  SEL_SCIF1_1),
1290         PINMUX_IPSR_MSEL(IP14_19_16,    MSIOF1_RXD_F,           SEL_MSIOF1_5),
1291
1292         PINMUX_IPSR_GPSR(IP14_23_20,    SSI_SCK01239),
1293         PINMUX_IPSR_MSEL(IP14_23_20,    MSIOF1_TXD_F,           SEL_MSIOF1_5),
1294
1295         PINMUX_IPSR_GPSR(IP14_27_24,    SSI_WS01239),
1296         PINMUX_IPSR_MSEL(IP14_27_24,    MSIOF1_SS1_F,           SEL_MSIOF1_5),
1297
1298         PINMUX_IPSR_GPSR(IP14_31_28,    SSI_SDATA0),
1299         PINMUX_IPSR_MSEL(IP14_31_28,    MSIOF1_SS2_F,           SEL_MSIOF1_5),
1300
1301         /* IPSR15 */
1302         PINMUX_IPSR_MSEL(IP15_3_0,      SSI_SDATA1_A,           SEL_SSI1_0),
1303
1304         PINMUX_IPSR_MSEL(IP15_7_4,      SSI_SDATA2_A,           SEL_SSI2_0),
1305         PINMUX_IPSR_MSEL(IP15_7_4,      SSI_SCK1_B,             SEL_SSI1_1),
1306
1307         PINMUX_IPSR_GPSR(IP15_11_8,     SSI_SCK349),
1308         PINMUX_IPSR_MSEL(IP15_11_8,     MSIOF1_SS1_A,           SEL_MSIOF1_0),
1309         PINMUX_IPSR_MSEL(IP15_11_8,     STP_OPWM_0_A,           SEL_SSP1_0_0),
1310
1311         PINMUX_IPSR_GPSR(IP15_15_12,    SSI_WS349),
1312         PINMUX_IPSR_MSEL(IP15_15_12,    HCTS2_N_A,              SEL_HSCIF2_0),
1313         PINMUX_IPSR_MSEL(IP15_15_12,    MSIOF1_SS2_A,           SEL_MSIOF1_0),
1314         PINMUX_IPSR_MSEL(IP15_15_12,    STP_IVCXO27_0_A,        SEL_SSP1_0_0),
1315
1316         PINMUX_IPSR_GPSR(IP15_19_16,    SSI_SDATA3),
1317         PINMUX_IPSR_MSEL(IP15_19_16,    HRTS2_N_A,              SEL_HSCIF2_0),
1318         PINMUX_IPSR_MSEL(IP15_19_16,    MSIOF1_TXD_A,           SEL_MSIOF1_0),
1319         PINMUX_IPSR_MSEL(IP15_19_16,    TS_SCK0_A,              SEL_TSIF0_0),
1320         PINMUX_IPSR_MSEL(IP15_19_16,    STP_ISCLK_0_A,          SEL_SSP1_0_0),
1321         PINMUX_IPSR_MSEL(IP15_19_16,    RIF0_D1_A,              SEL_DRIF0_0),
1322         PINMUX_IPSR_MSEL(IP15_19_16,    RIF2_D0_A,              SEL_DRIF2_0),
1323
1324         PINMUX_IPSR_GPSR(IP15_23_20,    SSI_SCK4),
1325         PINMUX_IPSR_MSEL(IP15_23_20,    HRX2_A,                 SEL_HSCIF2_0),
1326         PINMUX_IPSR_MSEL(IP15_23_20,    MSIOF1_SCK_A,           SEL_MSIOF1_0),
1327         PINMUX_IPSR_MSEL(IP15_23_20,    TS_SDAT0_A,             SEL_TSIF0_0),
1328         PINMUX_IPSR_MSEL(IP15_23_20,    STP_ISD_0_A,            SEL_SSP1_0_0),
1329         PINMUX_IPSR_MSEL(IP15_23_20,    RIF0_CLK_A,             SEL_DRIF0_0),
1330         PINMUX_IPSR_MSEL(IP15_23_20,    RIF2_CLK_A,             SEL_DRIF2_0),
1331
1332         PINMUX_IPSR_GPSR(IP15_27_24,    SSI_WS4),
1333         PINMUX_IPSR_MSEL(IP15_27_24,    HTX2_A,                 SEL_HSCIF2_0),
1334         PINMUX_IPSR_MSEL(IP15_27_24,    MSIOF1_SYNC_A,          SEL_MSIOF1_0),
1335         PINMUX_IPSR_MSEL(IP15_27_24,    TS_SDEN0_A,             SEL_TSIF0_0),
1336         PINMUX_IPSR_MSEL(IP15_27_24,    STP_ISEN_0_A,           SEL_SSP1_0_0),
1337         PINMUX_IPSR_MSEL(IP15_27_24,    RIF0_SYNC_A,            SEL_DRIF0_0),
1338         PINMUX_IPSR_MSEL(IP15_27_24,    RIF2_SYNC_A,            SEL_DRIF2_0),
1339
1340         PINMUX_IPSR_GPSR(IP15_31_28,    SSI_SDATA4),
1341         PINMUX_IPSR_MSEL(IP15_31_28,    HSCK2_A,                SEL_HSCIF2_0),
1342         PINMUX_IPSR_MSEL(IP15_31_28,    MSIOF1_RXD_A,           SEL_MSIOF1_0),
1343         PINMUX_IPSR_MSEL(IP15_31_28,    TS_SPSYNC0_A,           SEL_TSIF0_0),
1344         PINMUX_IPSR_MSEL(IP15_31_28,    STP_ISSYNC_0_A,         SEL_SSP1_0_0),
1345         PINMUX_IPSR_MSEL(IP15_31_28,    RIF0_D0_A,              SEL_DRIF0_0),
1346         PINMUX_IPSR_MSEL(IP15_31_28,    RIF2_D1_A,              SEL_DRIF2_0),
1347
1348         /* IPSR16 */
1349         PINMUX_IPSR_GPSR(IP16_3_0,      SSI_SCK6),
1350         PINMUX_IPSR_GPSR(IP16_3_0,      USB2_PWEN),
1351         PINMUX_IPSR_MSEL(IP16_3_0,      SIM0_RST_D,             SEL_SIMCARD_3),
1352
1353         PINMUX_IPSR_GPSR(IP16_7_4,      SSI_WS6),
1354         PINMUX_IPSR_GPSR(IP16_7_4,      USB2_OVC),
1355         PINMUX_IPSR_MSEL(IP16_7_4,      SIM0_D_D,               SEL_SIMCARD_3),
1356
1357         PINMUX_IPSR_GPSR(IP16_11_8,     SSI_SDATA6),
1358         PINMUX_IPSR_MSEL(IP16_11_8,     SIM0_CLK_D,             SEL_SIMCARD_3),
1359         PINMUX_IPSR_GPSR(IP16_11_8,     SATA_DEVSLP_A),
1360
1361         PINMUX_IPSR_GPSR(IP16_15_12,    SSI_SCK78),
1362         PINMUX_IPSR_MSEL(IP16_15_12,    HRX2_B,                 SEL_HSCIF2_1),
1363         PINMUX_IPSR_MSEL(IP16_15_12,    MSIOF1_SCK_C,           SEL_MSIOF1_2),
1364         PINMUX_IPSR_MSEL(IP16_15_12,    TS_SCK1_A,              SEL_TSIF1_0),
1365         PINMUX_IPSR_MSEL(IP16_15_12,    STP_ISCLK_1_A,          SEL_SSP1_1_0),
1366         PINMUX_IPSR_MSEL(IP16_15_12,    RIF1_CLK_A,             SEL_DRIF1_0),
1367         PINMUX_IPSR_MSEL(IP16_15_12,    RIF3_CLK_A,             SEL_DRIF3_0),
1368
1369         PINMUX_IPSR_GPSR(IP16_19_16,    SSI_WS78),
1370         PINMUX_IPSR_MSEL(IP16_19_16,    HTX2_B,                 SEL_HSCIF2_1),
1371         PINMUX_IPSR_MSEL(IP16_19_16,    MSIOF1_SYNC_C,          SEL_MSIOF1_2),
1372         PINMUX_IPSR_MSEL(IP16_19_16,    TS_SDAT1_A,             SEL_TSIF1_0),
1373         PINMUX_IPSR_MSEL(IP16_19_16,    STP_ISD_1_A,            SEL_SSP1_1_0),
1374         PINMUX_IPSR_MSEL(IP16_19_16,    RIF1_SYNC_A,            SEL_DRIF1_0),
1375         PINMUX_IPSR_MSEL(IP16_19_16,    RIF3_SYNC_A,            SEL_DRIF3_0),
1376
1377         PINMUX_IPSR_GPSR(IP16_23_20,    SSI_SDATA7),
1378         PINMUX_IPSR_MSEL(IP16_23_20,    HCTS2_N_B,              SEL_HSCIF2_1),
1379         PINMUX_IPSR_MSEL(IP16_23_20,    MSIOF1_RXD_C,           SEL_MSIOF1_2),
1380         PINMUX_IPSR_MSEL(IP16_23_20,    TS_SDEN1_A,             SEL_TSIF1_0),
1381         PINMUX_IPSR_MSEL(IP16_23_20,    STP_ISEN_1_A,           SEL_SSP1_1_0),
1382         PINMUX_IPSR_MSEL(IP16_23_20,    RIF1_D0_A,              SEL_DRIF1_0),
1383         PINMUX_IPSR_MSEL(IP16_23_20,    RIF3_D0_A,              SEL_DRIF3_0),
1384         PINMUX_IPSR_MSEL(IP16_23_20,    TCLK2_A,                SEL_TIMER_TMU2_0),
1385
1386         PINMUX_IPSR_GPSR(IP16_27_24,    SSI_SDATA8),
1387         PINMUX_IPSR_MSEL(IP16_27_24,    HRTS2_N_B,              SEL_HSCIF2_1),
1388         PINMUX_IPSR_MSEL(IP16_27_24,    MSIOF1_TXD_C,           SEL_MSIOF1_2),
1389         PINMUX_IPSR_MSEL(IP16_27_24,    TS_SPSYNC1_A,           SEL_TSIF1_0),
1390         PINMUX_IPSR_MSEL(IP16_27_24,    STP_ISSYNC_1_A,         SEL_SSP1_1_0),
1391         PINMUX_IPSR_MSEL(IP16_27_24,    RIF1_D1_A,              SEL_DRIF1_0),
1392         PINMUX_IPSR_MSEL(IP16_27_24,    RIF3_D1_A,              SEL_DRIF3_0),
1393
1394         PINMUX_IPSR_MSEL(IP16_31_28,    SSI_SDATA9_A,           SEL_SSI9_0),
1395         PINMUX_IPSR_MSEL(IP16_31_28,    HSCK2_B,                SEL_HSCIF2_1),
1396         PINMUX_IPSR_MSEL(IP16_31_28,    MSIOF1_SS1_C,           SEL_MSIOF1_2),
1397         PINMUX_IPSR_MSEL(IP16_31_28,    HSCK1_A,                SEL_HSCIF1_0),
1398         PINMUX_IPSR_MSEL(IP16_31_28,    SSI_WS1_B,              SEL_SSI1_1),
1399         PINMUX_IPSR_GPSR(IP16_31_28,    SCK1),
1400         PINMUX_IPSR_MSEL(IP16_31_28,    STP_IVCXO27_1_A,        SEL_SSP1_1_0),
1401         PINMUX_IPSR_MSEL(IP16_31_28,    SCK5_A,                 SEL_SCIF5_0),
1402
1403         /* IPSR17 */
1404         PINMUX_IPSR_MSEL(IP17_3_0,      AUDIO_CLKA_A,           SEL_ADG_A_0),
1405         PINMUX_IPSR_GPSR(IP17_3_0,      CC5_OSCOUT),
1406
1407         PINMUX_IPSR_MSEL(IP17_7_4,      AUDIO_CLKB_B,           SEL_ADG_B_1),
1408         PINMUX_IPSR_MSEL(IP17_7_4,      SCIF_CLK_A,             SEL_SCIF_0),
1409         PINMUX_IPSR_MSEL(IP17_7_4,      STP_IVCXO27_1_D,        SEL_SSP1_1_3),
1410         PINMUX_IPSR_MSEL(IP17_7_4,      REMOCON_A,              SEL_REMOCON_0),
1411         PINMUX_IPSR_MSEL(IP17_7_4,      TCLK1_A,                SEL_TIMER_TMU1_0),
1412
1413         PINMUX_IPSR_GPSR(IP17_11_8,     USB0_PWEN),
1414         PINMUX_IPSR_MSEL(IP17_11_8,     SIM0_RST_C,             SEL_SIMCARD_2),
1415         PINMUX_IPSR_MSEL(IP17_11_8,     TS_SCK1_D,              SEL_TSIF1_3),
1416         PINMUX_IPSR_MSEL(IP17_11_8,     STP_ISCLK_1_D,          SEL_SSP1_1_3),
1417         PINMUX_IPSR_MSEL(IP17_11_8,     BPFCLK_B,               SEL_FM_1),
1418         PINMUX_IPSR_MSEL(IP17_11_8,     RIF3_CLK_B,             SEL_DRIF3_1),
1419         PINMUX_IPSR_MSEL(IP17_11_8,     HSCK2_C,                SEL_HSCIF2_2),
1420
1421         PINMUX_IPSR_GPSR(IP17_15_12,    USB0_OVC),
1422         PINMUX_IPSR_MSEL(IP17_15_12,    SIM0_D_C,               SEL_SIMCARD_2),
1423         PINMUX_IPSR_MSEL(IP17_15_12,    TS_SDAT1_D,             SEL_TSIF1_3),
1424         PINMUX_IPSR_MSEL(IP17_15_12,    STP_ISD_1_D,            SEL_SSP1_1_3),
1425         PINMUX_IPSR_MSEL(IP17_15_12,    RIF3_SYNC_B,            SEL_DRIF3_1),
1426         PINMUX_IPSR_MSEL(IP17_15_12,    HRX2_C,                 SEL_HSCIF2_2),
1427
1428         PINMUX_IPSR_GPSR(IP17_19_16,    USB1_PWEN),
1429         PINMUX_IPSR_MSEL(IP17_19_16,    SIM0_CLK_C,             SEL_SIMCARD_2),
1430         PINMUX_IPSR_MSEL(IP17_19_16,    SSI_SCK1_A,             SEL_SSI1_0),
1431         PINMUX_IPSR_MSEL(IP17_19_16,    TS_SCK0_E,              SEL_TSIF0_4),
1432         PINMUX_IPSR_MSEL(IP17_19_16,    STP_ISCLK_0_E,          SEL_SSP1_0_4),
1433         PINMUX_IPSR_MSEL(IP17_19_16,    FMCLK_B,                SEL_FM_1),
1434         PINMUX_IPSR_MSEL(IP17_19_16,    RIF2_CLK_B,             SEL_DRIF2_1),
1435         PINMUX_IPSR_MSEL(IP17_19_16,    SPEEDIN_A,              SEL_SPEED_PULSE_0),
1436         PINMUX_IPSR_MSEL(IP17_19_16,    HTX2_C,                 SEL_HSCIF2_2),
1437
1438         PINMUX_IPSR_GPSR(IP17_23_20,    USB1_OVC),
1439         PINMUX_IPSR_MSEL(IP17_23_20,    MSIOF1_SS2_C,           SEL_MSIOF1_2),
1440         PINMUX_IPSR_MSEL(IP17_23_20,    SSI_WS1_A,              SEL_SSI1_0),
1441         PINMUX_IPSR_MSEL(IP17_23_20,    TS_SDAT0_E,             SEL_TSIF0_4),
1442         PINMUX_IPSR_MSEL(IP17_23_20,    STP_ISD_0_E,            SEL_SSP1_0_4),
1443         PINMUX_IPSR_MSEL(IP17_23_20,    FMIN_B,                 SEL_FM_1),
1444         PINMUX_IPSR_MSEL(IP17_23_20,    RIF2_SYNC_B,            SEL_DRIF2_1),
1445         PINMUX_IPSR_MSEL(IP17_23_20,    REMOCON_B,              SEL_REMOCON_1),
1446         PINMUX_IPSR_MSEL(IP17_23_20,    HCTS2_N_C,              SEL_HSCIF2_2),
1447
1448         PINMUX_IPSR_GPSR(IP17_27_24,    USB30_PWEN),
1449         PINMUX_IPSR_GPSR(IP17_27_24,    AUDIO_CLKOUT_B),
1450         PINMUX_IPSR_MSEL(IP17_27_24,    SSI_SCK2_B,             SEL_SSI2_1),
1451         PINMUX_IPSR_MSEL(IP17_27_24,    TS_SDEN1_D,             SEL_TSIF1_3),
1452         PINMUX_IPSR_MSEL(IP17_27_24,    STP_ISEN_1_D,           SEL_SSP1_1_3),
1453         PINMUX_IPSR_MSEL(IP17_27_24,    STP_OPWM_0_E,           SEL_SSP1_0_4),
1454         PINMUX_IPSR_MSEL(IP17_27_24,    RIF3_D0_B,              SEL_DRIF3_1),
1455         PINMUX_IPSR_MSEL(IP17_27_24,    TCLK2_B,                SEL_TIMER_TMU2_1),
1456         PINMUX_IPSR_GPSR(IP17_27_24,    TPU0TO0),
1457         PINMUX_IPSR_MSEL(IP17_27_24,    BPFCLK_C,               SEL_FM_2),
1458         PINMUX_IPSR_MSEL(IP17_27_24,    HRTS2_N_C,              SEL_HSCIF2_2),
1459
1460         PINMUX_IPSR_GPSR(IP17_31_28,    USB30_OVC),
1461         PINMUX_IPSR_GPSR(IP17_31_28,    AUDIO_CLKOUT1_B),
1462         PINMUX_IPSR_MSEL(IP17_31_28,    SSI_WS2_B,              SEL_SSI2_1),
1463         PINMUX_IPSR_MSEL(IP17_31_28,    TS_SPSYNC1_D,           SEL_TSIF1_3),
1464         PINMUX_IPSR_MSEL(IP17_31_28,    STP_ISSYNC_1_D,         SEL_SSP1_1_3),
1465         PINMUX_IPSR_MSEL(IP17_31_28,    STP_IVCXO27_0_E,        SEL_SSP1_0_4),
1466         PINMUX_IPSR_MSEL(IP17_31_28,    RIF3_D1_B,              SEL_DRIF3_1),
1467         PINMUX_IPSR_GPSR(IP17_31_28,    FSO_TOE_N),
1468         PINMUX_IPSR_GPSR(IP17_31_28,    TPU0TO1),
1469
1470         /* IPSR18 */
1471         PINMUX_IPSR_GPSR(IP18_3_0,      USB2_CH3_PWEN),
1472         PINMUX_IPSR_GPSR(IP18_3_0,      AUDIO_CLKOUT2_B),
1473         PINMUX_IPSR_MSEL(IP18_3_0,      SSI_SCK9_B,             SEL_SSI9_1),
1474         PINMUX_IPSR_MSEL(IP18_3_0,      TS_SDEN0_E,             SEL_TSIF0_4),
1475         PINMUX_IPSR_MSEL(IP18_3_0,      STP_ISEN_0_E,           SEL_SSP1_0_4),
1476         PINMUX_IPSR_MSEL(IP18_3_0,      RIF2_D0_B,              SEL_DRIF2_1),
1477         PINMUX_IPSR_GPSR(IP18_3_0,      TPU0TO2),
1478         PINMUX_IPSR_MSEL(IP18_3_0,      FMCLK_C,                SEL_FM_2),
1479         PINMUX_IPSR_MSEL(IP18_3_0,      FMCLK_D,                SEL_FM_3),
1480
1481         PINMUX_IPSR_GPSR(IP18_7_4,      USB2_CH3_OVC),
1482         PINMUX_IPSR_GPSR(IP18_7_4,      AUDIO_CLKOUT3_B),
1483         PINMUX_IPSR_MSEL(IP18_7_4,      SSI_WS9_B,              SEL_SSI9_1),
1484         PINMUX_IPSR_MSEL(IP18_7_4,      TS_SPSYNC0_E,           SEL_TSIF0_4),
1485         PINMUX_IPSR_MSEL(IP18_7_4,      STP_ISSYNC_0_E,         SEL_SSP1_0_4),
1486         PINMUX_IPSR_MSEL(IP18_7_4,      RIF2_D1_B,              SEL_DRIF2_1),
1487         PINMUX_IPSR_GPSR(IP18_7_4,      TPU0TO3),
1488         PINMUX_IPSR_MSEL(IP18_7_4,      FMIN_C,                 SEL_FM_2),
1489         PINMUX_IPSR_MSEL(IP18_7_4,      FMIN_D,                 SEL_FM_3),
1490
1491 /*
1492  * Static pins can not be muxed between different functions but
1493  * still need mark entries in the pinmux list. Add each static
1494  * pin to the list without an associated function. The sh-pfc
1495  * core will do the right thing and skip trying to mux the pin
1496  * while still applying configuration to it.
1497  */
1498 #define FM(x)   PINMUX_DATA(x##_MARK, 0),
1499         PINMUX_STATIC
1500 #undef FM
1501 };
1502
1503 /*
1504  * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1505  * Physical layout rows: A - AW, cols: 1 - 39.
1506  */
1507 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1508 #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1509 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1510 #define PIN_NONE U16_MAX
1511
1512 static const struct sh_pfc_pin pinmux_pins[] = {
1513         PINMUX_GPIO_GP_ALL(),
1514
1515         /*
1516          * Pins not associated with a GPIO port.
1517          *
1518          * The pin positions are different between different r8a7795
1519          * packages, all that is needed for the pfc driver is a unique
1520          * number for each pin. To this end use the pin layout from
1521          * R-Car H3SiP to calculate a unique number for each pin.
1522          */
1523         SH_PFC_PIN_NAMED_CFG('A',  8, AVB_TX_CTL, CFG_FLAGS),
1524         SH_PFC_PIN_NAMED_CFG('A',  9, AVB_MDIO, CFG_FLAGS),
1525         SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1526         SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1527         SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1528         SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1529         SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1530         SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1531         SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1532         SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1533         SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1534         SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1535         SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1536         SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1537         SH_PFC_PIN_NAMED_CFG('C',  1, PRESETOUT#, CFG_FLAGS),
1538         SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1539         SH_PFC_PIN_NAMED_CFG('V',  3, QSPI1_SPCLK, CFG_FLAGS),
1540         SH_PFC_PIN_NAMED_CFG('V',  5, QSPI1_SSL, CFG_FLAGS),
1541         SH_PFC_PIN_NAMED_CFG('V',  6, RPC_WP#, CFG_FLAGS),
1542         SH_PFC_PIN_NAMED_CFG('V',  7, RPC_RESET#, CFG_FLAGS),
1543         SH_PFC_PIN_NAMED_CFG('W',  3, QSPI0_SPCLK, CFG_FLAGS),
1544         SH_PFC_PIN_NAMED_CFG('Y',  3, QSPI0_SSL, CFG_FLAGS),
1545         SH_PFC_PIN_NAMED_CFG('Y',  6, QSPI0_IO2, CFG_FLAGS),
1546         SH_PFC_PIN_NAMED_CFG('Y',  7, RPC_INT#, CFG_FLAGS),
1547         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  4, QSPI0_MISO_IO1, CFG_FLAGS),
1548         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  6, QSPI0_IO3, CFG_FLAGS),
1549         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  3, QSPI1_IO3, CFG_FLAGS),
1550         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  5, QSPI0_MOSI_IO0, CFG_FLAGS),
1551         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  7, QSPI1_MOSI_IO0, CFG_FLAGS),
1552         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
1553         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1554         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  4, QSPI1_IO2, CFG_FLAGS),
1555         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  5, QSPI1_MISO_IO1, CFG_FLAGS),
1556         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  7, DU_DOTCLKIN0, CFG_FLAGS),
1557         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  8, DU_DOTCLKIN1, CFG_FLAGS),
1558         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  7, DU_DOTCLKIN2, CFG_FLAGS),
1559         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  8, DU_DOTCLKIN3, CFG_FLAGS),
1560         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1561         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1562         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1563         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1564         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1565         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1566 };
1567
1568 /* - AUDIO CLOCK ------------------------------------------------------------ */
1569 static const unsigned int audio_clk_a_a_pins[] = {
1570         /* CLK A */
1571         RCAR_GP_PIN(6, 22),
1572 };
1573 static const unsigned int audio_clk_a_a_mux[] = {
1574         AUDIO_CLKA_A_MARK,
1575 };
1576 static const unsigned int audio_clk_a_b_pins[] = {
1577         /* CLK A */
1578         RCAR_GP_PIN(5, 4),
1579 };
1580 static const unsigned int audio_clk_a_b_mux[] = {
1581         AUDIO_CLKA_B_MARK,
1582 };
1583 static const unsigned int audio_clk_a_c_pins[] = {
1584         /* CLK A */
1585         RCAR_GP_PIN(5, 19),
1586 };
1587 static const unsigned int audio_clk_a_c_mux[] = {
1588         AUDIO_CLKA_C_MARK,
1589 };
1590 static const unsigned int audio_clk_b_a_pins[] = {
1591         /* CLK B */
1592         RCAR_GP_PIN(5, 12),
1593 };
1594 static const unsigned int audio_clk_b_a_mux[] = {
1595         AUDIO_CLKB_A_MARK,
1596 };
1597 static const unsigned int audio_clk_b_b_pins[] = {
1598         /* CLK B */
1599         RCAR_GP_PIN(6, 23),
1600 };
1601 static const unsigned int audio_clk_b_b_mux[] = {
1602         AUDIO_CLKB_B_MARK,
1603 };
1604 static const unsigned int audio_clk_c_a_pins[] = {
1605         /* CLK C */
1606         RCAR_GP_PIN(5, 21),
1607 };
1608 static const unsigned int audio_clk_c_a_mux[] = {
1609         AUDIO_CLKC_A_MARK,
1610 };
1611 static const unsigned int audio_clk_c_b_pins[] = {
1612         /* CLK C */
1613         RCAR_GP_PIN(5, 0),
1614 };
1615 static const unsigned int audio_clk_c_b_mux[] = {
1616         AUDIO_CLKC_B_MARK,
1617 };
1618 static const unsigned int audio_clkout_a_pins[] = {
1619         /* CLKOUT */
1620         RCAR_GP_PIN(5, 18),
1621 };
1622 static const unsigned int audio_clkout_a_mux[] = {
1623         AUDIO_CLKOUT_A_MARK,
1624 };
1625 static const unsigned int audio_clkout_b_pins[] = {
1626         /* CLKOUT */
1627         RCAR_GP_PIN(6, 28),
1628 };
1629 static const unsigned int audio_clkout_b_mux[] = {
1630         AUDIO_CLKOUT_B_MARK,
1631 };
1632 static const unsigned int audio_clkout_c_pins[] = {
1633         /* CLKOUT */
1634         RCAR_GP_PIN(5, 3),
1635 };
1636 static const unsigned int audio_clkout_c_mux[] = {
1637         AUDIO_CLKOUT_C_MARK,
1638 };
1639 static const unsigned int audio_clkout_d_pins[] = {
1640         /* CLKOUT */
1641         RCAR_GP_PIN(5, 21),
1642 };
1643 static const unsigned int audio_clkout_d_mux[] = {
1644         AUDIO_CLKOUT_D_MARK,
1645 };
1646 static const unsigned int audio_clkout1_a_pins[] = {
1647         /* CLKOUT1 */
1648         RCAR_GP_PIN(5, 15),
1649 };
1650 static const unsigned int audio_clkout1_a_mux[] = {
1651         AUDIO_CLKOUT1_A_MARK,
1652 };
1653 static const unsigned int audio_clkout1_b_pins[] = {
1654         /* CLKOUT1 */
1655         RCAR_GP_PIN(6, 29),
1656 };
1657 static const unsigned int audio_clkout1_b_mux[] = {
1658         AUDIO_CLKOUT1_B_MARK,
1659 };
1660 static const unsigned int audio_clkout2_a_pins[] = {
1661         /* CLKOUT2 */
1662         RCAR_GP_PIN(5, 16),
1663 };
1664 static const unsigned int audio_clkout2_a_mux[] = {
1665         AUDIO_CLKOUT2_A_MARK,
1666 };
1667 static const unsigned int audio_clkout2_b_pins[] = {
1668         /* CLKOUT2 */
1669         RCAR_GP_PIN(6, 30),
1670 };
1671 static const unsigned int audio_clkout2_b_mux[] = {
1672         AUDIO_CLKOUT2_B_MARK,
1673 };
1674 static const unsigned int audio_clkout3_a_pins[] = {
1675         /* CLKOUT3 */
1676         RCAR_GP_PIN(5, 19),
1677 };
1678 static const unsigned int audio_clkout3_a_mux[] = {
1679         AUDIO_CLKOUT3_A_MARK,
1680 };
1681 static const unsigned int audio_clkout3_b_pins[] = {
1682         /* CLKOUT3 */
1683         RCAR_GP_PIN(6, 31),
1684 };
1685 static const unsigned int audio_clkout3_b_mux[] = {
1686         AUDIO_CLKOUT3_B_MARK,
1687 };
1688
1689 /* - EtherAVB --------------------------------------------------------------- */
1690 static const unsigned int avb_link_pins[] = {
1691         /* AVB_LINK */
1692         RCAR_GP_PIN(2, 12),
1693 };
1694 static const unsigned int avb_link_mux[] = {
1695         AVB_LINK_MARK,
1696 };
1697 static const unsigned int avb_magic_pins[] = {
1698         /* AVB_MAGIC_ */
1699         RCAR_GP_PIN(2, 10),
1700 };
1701 static const unsigned int avb_magic_mux[] = {
1702         AVB_MAGIC_MARK,
1703 };
1704 static const unsigned int avb_phy_int_pins[] = {
1705         /* AVB_PHY_INT */
1706         RCAR_GP_PIN(2, 11),
1707 };
1708 static const unsigned int avb_phy_int_mux[] = {
1709         AVB_PHY_INT_MARK,
1710 };
1711 static const unsigned int avb_mdio_pins[] = {
1712         /* AVB_MDC, AVB_MDIO */
1713         RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1714 };
1715 static const unsigned int avb_mdio_mux[] = {
1716         AVB_MDC_MARK, AVB_MDIO_MARK,
1717 };
1718 static const unsigned int avb_mii_pins[] = {
1719         /*
1720          * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1721          * AVB_TD1, AVB_TD2, AVB_TD3,
1722          * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1723          * AVB_RD1, AVB_RD2, AVB_RD3,
1724          * AVB_TXCREFCLK
1725          */
1726         PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1727         PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1728         PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1729         PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1730         PIN_NUMBER('A', 12),
1731
1732 };
1733 static const unsigned int avb_mii_mux[] = {
1734         AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1735         AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1736         AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1737         AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1738         AVB_TXCREFCLK_MARK,
1739 };
1740 static const unsigned int avb_avtp_pps_pins[] = {
1741         /* AVB_AVTP_PPS */
1742         RCAR_GP_PIN(2, 6),
1743 };
1744 static const unsigned int avb_avtp_pps_mux[] = {
1745         AVB_AVTP_PPS_MARK,
1746 };
1747 static const unsigned int avb_avtp_match_a_pins[] = {
1748         /* AVB_AVTP_MATCH_A */
1749         RCAR_GP_PIN(2, 13),
1750 };
1751 static const unsigned int avb_avtp_match_a_mux[] = {
1752         AVB_AVTP_MATCH_A_MARK,
1753 };
1754 static const unsigned int avb_avtp_capture_a_pins[] = {
1755         /* AVB_AVTP_CAPTURE_A */
1756         RCAR_GP_PIN(2, 14),
1757 };
1758 static const unsigned int avb_avtp_capture_a_mux[] = {
1759         AVB_AVTP_CAPTURE_A_MARK,
1760 };
1761 static const unsigned int avb_avtp_match_b_pins[] = {
1762         /*  AVB_AVTP_MATCH_B */
1763         RCAR_GP_PIN(1, 8),
1764 };
1765 static const unsigned int avb_avtp_match_b_mux[] = {
1766         AVB_AVTP_MATCH_B_MARK,
1767 };
1768 static const unsigned int avb_avtp_capture_b_pins[] = {
1769         /* AVB_AVTP_CAPTURE_B */
1770         RCAR_GP_PIN(1, 11),
1771 };
1772 static const unsigned int avb_avtp_capture_b_mux[] = {
1773         AVB_AVTP_CAPTURE_B_MARK,
1774 };
1775
1776 /* - CAN ------------------------------------------------------------------ */
1777 static const unsigned int can0_data_a_pins[] = {
1778         /* TX, RX */
1779         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1780 };
1781 static const unsigned int can0_data_a_mux[] = {
1782         CAN0_TX_A_MARK,         CAN0_RX_A_MARK,
1783 };
1784 static const unsigned int can0_data_b_pins[] = {
1785         /* TX, RX */
1786         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1787 };
1788 static const unsigned int can0_data_b_mux[] = {
1789         CAN0_TX_B_MARK,         CAN0_RX_B_MARK,
1790 };
1791 static const unsigned int can1_data_pins[] = {
1792         /* TX, RX */
1793         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1794 };
1795 static const unsigned int can1_data_mux[] = {
1796         CAN1_TX_MARK,           CAN1_RX_MARK,
1797 };
1798
1799 /* - CAN Clock -------------------------------------------------------------- */
1800 static const unsigned int can_clk_pins[] = {
1801         /* CLK */
1802         RCAR_GP_PIN(1, 25),
1803 };
1804 static const unsigned int can_clk_mux[] = {
1805         CAN_CLK_MARK,
1806 };
1807
1808 /* - CAN FD --------------------------------------------------------------- */
1809 static const unsigned int canfd0_data_a_pins[] = {
1810         /* TX, RX */
1811         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1812 };
1813 static const unsigned int canfd0_data_a_mux[] = {
1814         CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
1815 };
1816 static const unsigned int canfd0_data_b_pins[] = {
1817         /* TX, RX */
1818         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1819 };
1820 static const unsigned int canfd0_data_b_mux[] = {
1821         CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
1822 };
1823 static const unsigned int canfd1_data_pins[] = {
1824         /* TX, RX */
1825         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1826 };
1827 static const unsigned int canfd1_data_mux[] = {
1828         CANFD1_TX_MARK,         CANFD1_RX_MARK,
1829 };
1830
1831 /* - DRIF0 --------------------------------------------------------------- */
1832 static const unsigned int drif0_ctrl_a_pins[] = {
1833         /* CLK, SYNC */
1834         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1835 };
1836 static const unsigned int drif0_ctrl_a_mux[] = {
1837         RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1838 };
1839 static const unsigned int drif0_data0_a_pins[] = {
1840         /* D0 */
1841         RCAR_GP_PIN(6, 10),
1842 };
1843 static const unsigned int drif0_data0_a_mux[] = {
1844         RIF0_D0_A_MARK,
1845 };
1846 static const unsigned int drif0_data1_a_pins[] = {
1847         /* D1 */
1848         RCAR_GP_PIN(6, 7),
1849 };
1850 static const unsigned int drif0_data1_a_mux[] = {
1851         RIF0_D1_A_MARK,
1852 };
1853 static const unsigned int drif0_ctrl_b_pins[] = {
1854         /* CLK, SYNC */
1855         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1856 };
1857 static const unsigned int drif0_ctrl_b_mux[] = {
1858         RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1859 };
1860 static const unsigned int drif0_data0_b_pins[] = {
1861         /* D0 */
1862         RCAR_GP_PIN(5, 1),
1863 };
1864 static const unsigned int drif0_data0_b_mux[] = {
1865         RIF0_D0_B_MARK,
1866 };
1867 static const unsigned int drif0_data1_b_pins[] = {
1868         /* D1 */
1869         RCAR_GP_PIN(5, 2),
1870 };
1871 static const unsigned int drif0_data1_b_mux[] = {
1872         RIF0_D1_B_MARK,
1873 };
1874 static const unsigned int drif0_ctrl_c_pins[] = {
1875         /* CLK, SYNC */
1876         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1877 };
1878 static const unsigned int drif0_ctrl_c_mux[] = {
1879         RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1880 };
1881 static const unsigned int drif0_data0_c_pins[] = {
1882         /* D0 */
1883         RCAR_GP_PIN(5, 13),
1884 };
1885 static const unsigned int drif0_data0_c_mux[] = {
1886         RIF0_D0_C_MARK,
1887 };
1888 static const unsigned int drif0_data1_c_pins[] = {
1889         /* D1 */
1890         RCAR_GP_PIN(5, 14),
1891 };
1892 static const unsigned int drif0_data1_c_mux[] = {
1893         RIF0_D1_C_MARK,
1894 };
1895 /* - DRIF1 --------------------------------------------------------------- */
1896 static const unsigned int drif1_ctrl_a_pins[] = {
1897         /* CLK, SYNC */
1898         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1899 };
1900 static const unsigned int drif1_ctrl_a_mux[] = {
1901         RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1902 };
1903 static const unsigned int drif1_data0_a_pins[] = {
1904         /* D0 */
1905         RCAR_GP_PIN(6, 19),
1906 };
1907 static const unsigned int drif1_data0_a_mux[] = {
1908         RIF1_D0_A_MARK,
1909 };
1910 static const unsigned int drif1_data1_a_pins[] = {
1911         /* D1 */
1912         RCAR_GP_PIN(6, 20),
1913 };
1914 static const unsigned int drif1_data1_a_mux[] = {
1915         RIF1_D1_A_MARK,
1916 };
1917 static const unsigned int drif1_ctrl_b_pins[] = {
1918         /* CLK, SYNC */
1919         RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1920 };
1921 static const unsigned int drif1_ctrl_b_mux[] = {
1922         RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1923 };
1924 static const unsigned int drif1_data0_b_pins[] = {
1925         /* D0 */
1926         RCAR_GP_PIN(5, 7),
1927 };
1928 static const unsigned int drif1_data0_b_mux[] = {
1929         RIF1_D0_B_MARK,
1930 };
1931 static const unsigned int drif1_data1_b_pins[] = {
1932         /* D1 */
1933         RCAR_GP_PIN(5, 8),
1934 };
1935 static const unsigned int drif1_data1_b_mux[] = {
1936         RIF1_D1_B_MARK,
1937 };
1938 static const unsigned int drif1_ctrl_c_pins[] = {
1939         /* CLK, SYNC */
1940         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1941 };
1942 static const unsigned int drif1_ctrl_c_mux[] = {
1943         RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1944 };
1945 static const unsigned int drif1_data0_c_pins[] = {
1946         /* D0 */
1947         RCAR_GP_PIN(5, 6),
1948 };
1949 static const unsigned int drif1_data0_c_mux[] = {
1950         RIF1_D0_C_MARK,
1951 };
1952 static const unsigned int drif1_data1_c_pins[] = {
1953         /* D1 */
1954         RCAR_GP_PIN(5, 10),
1955 };
1956 static const unsigned int drif1_data1_c_mux[] = {
1957         RIF1_D1_C_MARK,
1958 };
1959 /* - DRIF2 --------------------------------------------------------------- */
1960 static const unsigned int drif2_ctrl_a_pins[] = {
1961         /* CLK, SYNC */
1962         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1963 };
1964 static const unsigned int drif2_ctrl_a_mux[] = {
1965         RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1966 };
1967 static const unsigned int drif2_data0_a_pins[] = {
1968         /* D0 */
1969         RCAR_GP_PIN(6, 7),
1970 };
1971 static const unsigned int drif2_data0_a_mux[] = {
1972         RIF2_D0_A_MARK,
1973 };
1974 static const unsigned int drif2_data1_a_pins[] = {
1975         /* D1 */
1976         RCAR_GP_PIN(6, 10),
1977 };
1978 static const unsigned int drif2_data1_a_mux[] = {
1979         RIF2_D1_A_MARK,
1980 };
1981 static const unsigned int drif2_ctrl_b_pins[] = {
1982         /* CLK, SYNC */
1983         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1984 };
1985 static const unsigned int drif2_ctrl_b_mux[] = {
1986         RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1987 };
1988 static const unsigned int drif2_data0_b_pins[] = {
1989         /* D0 */
1990         RCAR_GP_PIN(6, 30),
1991 };
1992 static const unsigned int drif2_data0_b_mux[] = {
1993         RIF2_D0_B_MARK,
1994 };
1995 static const unsigned int drif2_data1_b_pins[] = {
1996         /* D1 */
1997         RCAR_GP_PIN(6, 31),
1998 };
1999 static const unsigned int drif2_data1_b_mux[] = {
2000         RIF2_D1_B_MARK,
2001 };
2002 /* - DRIF3 --------------------------------------------------------------- */
2003 static const unsigned int drif3_ctrl_a_pins[] = {
2004         /* CLK, SYNC */
2005         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2006 };
2007 static const unsigned int drif3_ctrl_a_mux[] = {
2008         RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2009 };
2010 static const unsigned int drif3_data0_a_pins[] = {
2011         /* D0 */
2012         RCAR_GP_PIN(6, 19),
2013 };
2014 static const unsigned int drif3_data0_a_mux[] = {
2015         RIF3_D0_A_MARK,
2016 };
2017 static const unsigned int drif3_data1_a_pins[] = {
2018         /* D1 */
2019         RCAR_GP_PIN(6, 20),
2020 };
2021 static const unsigned int drif3_data1_a_mux[] = {
2022         RIF3_D1_A_MARK,
2023 };
2024 static const unsigned int drif3_ctrl_b_pins[] = {
2025         /* CLK, SYNC */
2026         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2027 };
2028 static const unsigned int drif3_ctrl_b_mux[] = {
2029         RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2030 };
2031 static const unsigned int drif3_data0_b_pins[] = {
2032         /* D0 */
2033         RCAR_GP_PIN(6, 28),
2034 };
2035 static const unsigned int drif3_data0_b_mux[] = {
2036         RIF3_D0_B_MARK,
2037 };
2038 static const unsigned int drif3_data1_b_pins[] = {
2039         /* D1 */
2040         RCAR_GP_PIN(6, 29),
2041 };
2042 static const unsigned int drif3_data1_b_mux[] = {
2043         RIF3_D1_B_MARK,
2044 };
2045
2046 /* - DU --------------------------------------------------------------------- */
2047 static const unsigned int du_rgb666_pins[] = {
2048         /* R[7:2], G[7:2], B[7:2] */
2049         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2050         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2051         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2052         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2053         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2054         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2055 };
2056 static const unsigned int du_rgb666_mux[] = {
2057         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2058         DU_DR3_MARK, DU_DR2_MARK,
2059         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2060         DU_DG3_MARK, DU_DG2_MARK,
2061         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2062         DU_DB3_MARK, DU_DB2_MARK,
2063 };
2064 static const unsigned int du_rgb888_pins[] = {
2065         /* R[7:0], G[7:0], B[7:0] */
2066         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2067         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2068         RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),
2069         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2070         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2071         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2072         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2073         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2074         RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
2075 };
2076 static const unsigned int du_rgb888_mux[] = {
2077         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2078         DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2079         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2080         DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2081         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2082         DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2083 };
2084 static const unsigned int du_clk_out_0_pins[] = {
2085         /* CLKOUT */
2086         RCAR_GP_PIN(1, 27),
2087 };
2088 static const unsigned int du_clk_out_0_mux[] = {
2089         DU_DOTCLKOUT0_MARK
2090 };
2091 static const unsigned int du_clk_out_1_pins[] = {
2092         /* CLKOUT */
2093         RCAR_GP_PIN(2, 3),
2094 };
2095 static const unsigned int du_clk_out_1_mux[] = {
2096         DU_DOTCLKOUT1_MARK
2097 };
2098 static const unsigned int du_sync_pins[] = {
2099         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2100         RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2101 };
2102 static const unsigned int du_sync_mux[] = {
2103         DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2104 };
2105 static const unsigned int du_oddf_pins[] = {
2106         /* EXDISP/EXODDF/EXCDE */
2107         RCAR_GP_PIN(2, 2),
2108 };
2109 static const unsigned int du_oddf_mux[] = {
2110         DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2111 };
2112 static const unsigned int du_cde_pins[] = {
2113         /* CDE */
2114         RCAR_GP_PIN(2, 0),
2115 };
2116 static const unsigned int du_cde_mux[] = {
2117         DU_CDE_MARK,
2118 };
2119 static const unsigned int du_disp_pins[] = {
2120         /* DISP */
2121         RCAR_GP_PIN(2, 1),
2122 };
2123 static const unsigned int du_disp_mux[] = {
2124         DU_DISP_MARK,
2125 };
2126
2127 /* - HDMI ------------------------------------------------------------------- */
2128 static const unsigned int hdmi0_cec_pins[] = {
2129         /* HDMI0_CEC */
2130         RCAR_GP_PIN(7, 2),
2131 };
2132 static const unsigned int hdmi0_cec_mux[] = {
2133         HDMI0_CEC_MARK,
2134 };
2135 static const unsigned int hdmi1_cec_pins[] = {
2136         /* HDMI1_CEC */
2137         RCAR_GP_PIN(7, 3),
2138 };
2139 static const unsigned int hdmi1_cec_mux[] = {
2140         HDMI1_CEC_MARK,
2141 };
2142
2143 /* - HSCIF0 ----------------------------------------------------------------- */
2144 static const unsigned int hscif0_data_pins[] = {
2145         /* RX, TX */
2146         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2147 };
2148 static const unsigned int hscif0_data_mux[] = {
2149         HRX0_MARK, HTX0_MARK,
2150 };
2151 static const unsigned int hscif0_clk_pins[] = {
2152         /* SCK */
2153         RCAR_GP_PIN(5, 12),
2154 };
2155 static const unsigned int hscif0_clk_mux[] = {
2156         HSCK0_MARK,
2157 };
2158 static const unsigned int hscif0_ctrl_pins[] = {
2159         /* RTS, CTS */
2160         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2161 };
2162 static const unsigned int hscif0_ctrl_mux[] = {
2163         HRTS0_N_MARK, HCTS0_N_MARK,
2164 };
2165 /* - HSCIF1 ----------------------------------------------------------------- */
2166 static const unsigned int hscif1_data_a_pins[] = {
2167         /* RX, TX */
2168         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2169 };
2170 static const unsigned int hscif1_data_a_mux[] = {
2171         HRX1_A_MARK, HTX1_A_MARK,
2172 };
2173 static const unsigned int hscif1_clk_a_pins[] = {
2174         /* SCK */
2175         RCAR_GP_PIN(6, 21),
2176 };
2177 static const unsigned int hscif1_clk_a_mux[] = {
2178         HSCK1_A_MARK,
2179 };
2180 static const unsigned int hscif1_ctrl_a_pins[] = {
2181         /* RTS, CTS */
2182         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2183 };
2184 static const unsigned int hscif1_ctrl_a_mux[] = {
2185         HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2186 };
2187
2188 static const unsigned int hscif1_data_b_pins[] = {
2189         /* RX, TX */
2190         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2191 };
2192 static const unsigned int hscif1_data_b_mux[] = {
2193         HRX1_B_MARK, HTX1_B_MARK,
2194 };
2195 static const unsigned int hscif1_clk_b_pins[] = {
2196         /* SCK */
2197         RCAR_GP_PIN(5, 0),
2198 };
2199 static const unsigned int hscif1_clk_b_mux[] = {
2200         HSCK1_B_MARK,
2201 };
2202 static const unsigned int hscif1_ctrl_b_pins[] = {
2203         /* RTS, CTS */
2204         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2205 };
2206 static const unsigned int hscif1_ctrl_b_mux[] = {
2207         HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2208 };
2209 /* - HSCIF2 ----------------------------------------------------------------- */
2210 static const unsigned int hscif2_data_a_pins[] = {
2211         /* RX, TX */
2212         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2213 };
2214 static const unsigned int hscif2_data_a_mux[] = {
2215         HRX2_A_MARK, HTX2_A_MARK,
2216 };
2217 static const unsigned int hscif2_clk_a_pins[] = {
2218         /* SCK */
2219         RCAR_GP_PIN(6, 10),
2220 };
2221 static const unsigned int hscif2_clk_a_mux[] = {
2222         HSCK2_A_MARK,
2223 };
2224 static const unsigned int hscif2_ctrl_a_pins[] = {
2225         /* RTS, CTS */
2226         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2227 };
2228 static const unsigned int hscif2_ctrl_a_mux[] = {
2229         HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2230 };
2231
2232 static const unsigned int hscif2_data_b_pins[] = {
2233         /* RX, TX */
2234         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2235 };
2236 static const unsigned int hscif2_data_b_mux[] = {
2237         HRX2_B_MARK, HTX2_B_MARK,
2238 };
2239 static const unsigned int hscif2_clk_b_pins[] = {
2240         /* SCK */
2241         RCAR_GP_PIN(6, 21),
2242 };
2243 static const unsigned int hscif2_clk_b_mux[] = {
2244         HSCK2_B_MARK,
2245 };
2246 static const unsigned int hscif2_ctrl_b_pins[] = {
2247         /* RTS, CTS */
2248         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2249 };
2250 static const unsigned int hscif2_ctrl_b_mux[] = {
2251         HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2252 };
2253
2254 static const unsigned int hscif2_data_c_pins[] = {
2255         /* RX, TX */
2256         RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2257 };
2258 static const unsigned int hscif2_data_c_mux[] = {
2259         HRX2_C_MARK, HTX2_C_MARK,
2260 };
2261 static const unsigned int hscif2_clk_c_pins[] = {
2262         /* SCK */
2263         RCAR_GP_PIN(6, 24),
2264 };
2265 static const unsigned int hscif2_clk_c_mux[] = {
2266         HSCK2_C_MARK,
2267 };
2268 static const unsigned int hscif2_ctrl_c_pins[] = {
2269         /* RTS, CTS */
2270         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2271 };
2272 static const unsigned int hscif2_ctrl_c_mux[] = {
2273         HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2274 };
2275 /* - HSCIF3 ----------------------------------------------------------------- */
2276 static const unsigned int hscif3_data_a_pins[] = {
2277         /* RX, TX */
2278         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2279 };
2280 static const unsigned int hscif3_data_a_mux[] = {
2281         HRX3_A_MARK, HTX3_A_MARK,
2282 };
2283 static const unsigned int hscif3_clk_pins[] = {
2284         /* SCK */
2285         RCAR_GP_PIN(1, 22),
2286 };
2287 static const unsigned int hscif3_clk_mux[] = {
2288         HSCK3_MARK,
2289 };
2290 static const unsigned int hscif3_ctrl_pins[] = {
2291         /* RTS, CTS */
2292         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2293 };
2294 static const unsigned int hscif3_ctrl_mux[] = {
2295         HRTS3_N_MARK, HCTS3_N_MARK,
2296 };
2297
2298 static const unsigned int hscif3_data_b_pins[] = {
2299         /* RX, TX */
2300         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2301 };
2302 static const unsigned int hscif3_data_b_mux[] = {
2303         HRX3_B_MARK, HTX3_B_MARK,
2304 };
2305 static const unsigned int hscif3_data_c_pins[] = {
2306         /* RX, TX */
2307         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2308 };
2309 static const unsigned int hscif3_data_c_mux[] = {
2310         HRX3_C_MARK, HTX3_C_MARK,
2311 };
2312 static const unsigned int hscif3_data_d_pins[] = {
2313         /* RX, TX */
2314         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2315 };
2316 static const unsigned int hscif3_data_d_mux[] = {
2317         HRX3_D_MARK, HTX3_D_MARK,
2318 };
2319 /* - HSCIF4 ----------------------------------------------------------------- */
2320 static const unsigned int hscif4_data_a_pins[] = {
2321         /* RX, TX */
2322         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2323 };
2324 static const unsigned int hscif4_data_a_mux[] = {
2325         HRX4_A_MARK, HTX4_A_MARK,
2326 };
2327 static const unsigned int hscif4_clk_pins[] = {
2328         /* SCK */
2329         RCAR_GP_PIN(1, 11),
2330 };
2331 static const unsigned int hscif4_clk_mux[] = {
2332         HSCK4_MARK,
2333 };
2334 static const unsigned int hscif4_ctrl_pins[] = {
2335         /* RTS, CTS */
2336         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2337 };
2338 static const unsigned int hscif4_ctrl_mux[] = {
2339         HRTS4_N_MARK, HCTS4_N_MARK,
2340 };
2341
2342 static const unsigned int hscif4_data_b_pins[] = {
2343         /* RX, TX */
2344         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2345 };
2346 static const unsigned int hscif4_data_b_mux[] = {
2347         HRX4_B_MARK, HTX4_B_MARK,
2348 };
2349
2350 /* - I2C -------------------------------------------------------------------- */
2351 static const unsigned int i2c1_a_pins[] = {
2352         /* SDA, SCL */
2353         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2354 };
2355 static const unsigned int i2c1_a_mux[] = {
2356         SDA1_A_MARK, SCL1_A_MARK,
2357 };
2358 static const unsigned int i2c1_b_pins[] = {
2359         /* SDA, SCL */
2360         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2361 };
2362 static const unsigned int i2c1_b_mux[] = {
2363         SDA1_B_MARK, SCL1_B_MARK,
2364 };
2365 static const unsigned int i2c2_a_pins[] = {
2366         /* SDA, SCL */
2367         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2368 };
2369 static const unsigned int i2c2_a_mux[] = {
2370         SDA2_A_MARK, SCL2_A_MARK,
2371 };
2372 static const unsigned int i2c2_b_pins[] = {
2373         /* SDA, SCL */
2374         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2375 };
2376 static const unsigned int i2c2_b_mux[] = {
2377         SDA2_B_MARK, SCL2_B_MARK,
2378 };
2379 static const unsigned int i2c6_a_pins[] = {
2380         /* SDA, SCL */
2381         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2382 };
2383 static const unsigned int i2c6_a_mux[] = {
2384         SDA6_A_MARK, SCL6_A_MARK,
2385 };
2386 static const unsigned int i2c6_b_pins[] = {
2387         /* SDA, SCL */
2388         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2389 };
2390 static const unsigned int i2c6_b_mux[] = {
2391         SDA6_B_MARK, SCL6_B_MARK,
2392 };
2393 static const unsigned int i2c6_c_pins[] = {
2394         /* SDA, SCL */
2395         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2396 };
2397 static const unsigned int i2c6_c_mux[] = {
2398         SDA6_C_MARK, SCL6_C_MARK,
2399 };
2400
2401 /* - INTC-EX ---------------------------------------------------------------- */
2402 static const unsigned int intc_ex_irq0_pins[] = {
2403         /* IRQ0 */
2404         RCAR_GP_PIN(2, 0),
2405 };
2406 static const unsigned int intc_ex_irq0_mux[] = {
2407         IRQ0_MARK,
2408 };
2409 static const unsigned int intc_ex_irq1_pins[] = {
2410         /* IRQ1 */
2411         RCAR_GP_PIN(2, 1),
2412 };
2413 static const unsigned int intc_ex_irq1_mux[] = {
2414         IRQ1_MARK,
2415 };
2416 static const unsigned int intc_ex_irq2_pins[] = {
2417         /* IRQ2 */
2418         RCAR_GP_PIN(2, 2),
2419 };
2420 static const unsigned int intc_ex_irq2_mux[] = {
2421         IRQ2_MARK,
2422 };
2423 static const unsigned int intc_ex_irq3_pins[] = {
2424         /* IRQ3 */
2425         RCAR_GP_PIN(2, 3),
2426 };
2427 static const unsigned int intc_ex_irq3_mux[] = {
2428         IRQ3_MARK,
2429 };
2430 static const unsigned int intc_ex_irq4_pins[] = {
2431         /* IRQ4 */
2432         RCAR_GP_PIN(2, 4),
2433 };
2434 static const unsigned int intc_ex_irq4_mux[] = {
2435         IRQ4_MARK,
2436 };
2437 static const unsigned int intc_ex_irq5_pins[] = {
2438         /* IRQ5 */
2439         RCAR_GP_PIN(2, 5),
2440 };
2441 static const unsigned int intc_ex_irq5_mux[] = {
2442         IRQ5_MARK,
2443 };
2444
2445 /* - MSIOF0 ----------------------------------------------------------------- */
2446 static const unsigned int msiof0_clk_pins[] = {
2447         /* SCK */
2448         RCAR_GP_PIN(5, 17),
2449 };
2450 static const unsigned int msiof0_clk_mux[] = {
2451         MSIOF0_SCK_MARK,
2452 };
2453 static const unsigned int msiof0_sync_pins[] = {
2454         /* SYNC */
2455         RCAR_GP_PIN(5, 18),
2456 };
2457 static const unsigned int msiof0_sync_mux[] = {
2458         MSIOF0_SYNC_MARK,
2459 };
2460 static const unsigned int msiof0_ss1_pins[] = {
2461         /* SS1 */
2462         RCAR_GP_PIN(5, 19),
2463 };
2464 static const unsigned int msiof0_ss1_mux[] = {
2465         MSIOF0_SS1_MARK,
2466 };
2467 static const unsigned int msiof0_ss2_pins[] = {
2468         /* SS2 */
2469         RCAR_GP_PIN(5, 21),
2470 };
2471 static const unsigned int msiof0_ss2_mux[] = {
2472         MSIOF0_SS2_MARK,
2473 };
2474 static const unsigned int msiof0_txd_pins[] = {
2475         /* TXD */
2476         RCAR_GP_PIN(5, 20),
2477 };
2478 static const unsigned int msiof0_txd_mux[] = {
2479         MSIOF0_TXD_MARK,
2480 };
2481 static const unsigned int msiof0_rxd_pins[] = {
2482         /* RXD */
2483         RCAR_GP_PIN(5, 22),
2484 };
2485 static const unsigned int msiof0_rxd_mux[] = {
2486         MSIOF0_RXD_MARK,
2487 };
2488 /* - MSIOF1 ----------------------------------------------------------------- */
2489 static const unsigned int msiof1_clk_a_pins[] = {
2490         /* SCK */
2491         RCAR_GP_PIN(6, 8),
2492 };
2493 static const unsigned int msiof1_clk_a_mux[] = {
2494         MSIOF1_SCK_A_MARK,
2495 };
2496 static const unsigned int msiof1_sync_a_pins[] = {
2497         /* SYNC */
2498         RCAR_GP_PIN(6, 9),
2499 };
2500 static const unsigned int msiof1_sync_a_mux[] = {
2501         MSIOF1_SYNC_A_MARK,
2502 };
2503 static const unsigned int msiof1_ss1_a_pins[] = {
2504         /* SS1 */
2505         RCAR_GP_PIN(6, 5),
2506 };
2507 static const unsigned int msiof1_ss1_a_mux[] = {
2508         MSIOF1_SS1_A_MARK,
2509 };
2510 static const unsigned int msiof1_ss2_a_pins[] = {
2511         /* SS2 */
2512         RCAR_GP_PIN(6, 6),
2513 };
2514 static const unsigned int msiof1_ss2_a_mux[] = {
2515         MSIOF1_SS2_A_MARK,
2516 };
2517 static const unsigned int msiof1_txd_a_pins[] = {
2518         /* TXD */
2519         RCAR_GP_PIN(6, 7),
2520 };
2521 static const unsigned int msiof1_txd_a_mux[] = {
2522         MSIOF1_TXD_A_MARK,
2523 };
2524 static const unsigned int msiof1_rxd_a_pins[] = {
2525         /* RXD */
2526         RCAR_GP_PIN(6, 10),
2527 };
2528 static const unsigned int msiof1_rxd_a_mux[] = {
2529         MSIOF1_RXD_A_MARK,
2530 };
2531 static const unsigned int msiof1_clk_b_pins[] = {
2532         /* SCK */
2533         RCAR_GP_PIN(5, 9),
2534 };
2535 static const unsigned int msiof1_clk_b_mux[] = {
2536         MSIOF1_SCK_B_MARK,
2537 };
2538 static const unsigned int msiof1_sync_b_pins[] = {
2539         /* SYNC */
2540         RCAR_GP_PIN(5, 3),
2541 };
2542 static const unsigned int msiof1_sync_b_mux[] = {
2543         MSIOF1_SYNC_B_MARK,
2544 };
2545 static const unsigned int msiof1_ss1_b_pins[] = {
2546         /* SS1 */
2547         RCAR_GP_PIN(5, 4),
2548 };
2549 static const unsigned int msiof1_ss1_b_mux[] = {
2550         MSIOF1_SS1_B_MARK,
2551 };
2552 static const unsigned int msiof1_ss2_b_pins[] = {
2553         /* SS2 */
2554         RCAR_GP_PIN(5, 0),
2555 };
2556 static const unsigned int msiof1_ss2_b_mux[] = {
2557         MSIOF1_SS2_B_MARK,
2558 };
2559 static const unsigned int msiof1_txd_b_pins[] = {
2560         /* TXD */
2561         RCAR_GP_PIN(5, 8),
2562 };
2563 static const unsigned int msiof1_txd_b_mux[] = {
2564         MSIOF1_TXD_B_MARK,
2565 };
2566 static const unsigned int msiof1_rxd_b_pins[] = {
2567         /* RXD */
2568         RCAR_GP_PIN(5, 7),
2569 };
2570 static const unsigned int msiof1_rxd_b_mux[] = {
2571         MSIOF1_RXD_B_MARK,
2572 };
2573 static const unsigned int msiof1_clk_c_pins[] = {
2574         /* SCK */
2575         RCAR_GP_PIN(6, 17),
2576 };
2577 static const unsigned int msiof1_clk_c_mux[] = {
2578         MSIOF1_SCK_C_MARK,
2579 };
2580 static const unsigned int msiof1_sync_c_pins[] = {
2581         /* SYNC */
2582         RCAR_GP_PIN(6, 18),
2583 };
2584 static const unsigned int msiof1_sync_c_mux[] = {
2585         MSIOF1_SYNC_C_MARK,
2586 };
2587 static const unsigned int msiof1_ss1_c_pins[] = {
2588         /* SS1 */
2589         RCAR_GP_PIN(6, 21),
2590 };
2591 static const unsigned int msiof1_ss1_c_mux[] = {
2592         MSIOF1_SS1_C_MARK,
2593 };
2594 static const unsigned int msiof1_ss2_c_pins[] = {
2595         /* SS2 */
2596         RCAR_GP_PIN(6, 27),
2597 };
2598 static const unsigned int msiof1_ss2_c_mux[] = {
2599         MSIOF1_SS2_C_MARK,
2600 };
2601 static const unsigned int msiof1_txd_c_pins[] = {
2602         /* TXD */
2603         RCAR_GP_PIN(6, 20),
2604 };
2605 static const unsigned int msiof1_txd_c_mux[] = {
2606         MSIOF1_TXD_C_MARK,
2607 };
2608 static const unsigned int msiof1_rxd_c_pins[] = {
2609         /* RXD */
2610         RCAR_GP_PIN(6, 19),
2611 };
2612 static const unsigned int msiof1_rxd_c_mux[] = {
2613         MSIOF1_RXD_C_MARK,
2614 };
2615 static const unsigned int msiof1_clk_d_pins[] = {
2616         /* SCK */
2617         RCAR_GP_PIN(5, 12),
2618 };
2619 static const unsigned int msiof1_clk_d_mux[] = {
2620         MSIOF1_SCK_D_MARK,
2621 };
2622 static const unsigned int msiof1_sync_d_pins[] = {
2623         /* SYNC */
2624         RCAR_GP_PIN(5, 15),
2625 };
2626 static const unsigned int msiof1_sync_d_mux[] = {
2627         MSIOF1_SYNC_D_MARK,
2628 };
2629 static const unsigned int msiof1_ss1_d_pins[] = {
2630         /* SS1 */
2631         RCAR_GP_PIN(5, 16),
2632 };
2633 static const unsigned int msiof1_ss1_d_mux[] = {
2634         MSIOF1_SS1_D_MARK,
2635 };
2636 static const unsigned int msiof1_ss2_d_pins[] = {
2637         /* SS2 */
2638         RCAR_GP_PIN(5, 21),
2639 };
2640 static const unsigned int msiof1_ss2_d_mux[] = {
2641         MSIOF1_SS2_D_MARK,
2642 };
2643 static const unsigned int msiof1_txd_d_pins[] = {
2644         /* TXD */
2645         RCAR_GP_PIN(5, 14),
2646 };
2647 static const unsigned int msiof1_txd_d_mux[] = {
2648         MSIOF1_TXD_D_MARK,
2649 };
2650 static const unsigned int msiof1_rxd_d_pins[] = {
2651         /* RXD */
2652         RCAR_GP_PIN(5, 13),
2653 };
2654 static const unsigned int msiof1_rxd_d_mux[] = {
2655         MSIOF1_RXD_D_MARK,
2656 };
2657 static const unsigned int msiof1_clk_e_pins[] = {
2658         /* SCK */
2659         RCAR_GP_PIN(3, 0),
2660 };
2661 static const unsigned int msiof1_clk_e_mux[] = {
2662         MSIOF1_SCK_E_MARK,
2663 };
2664 static const unsigned int msiof1_sync_e_pins[] = {
2665         /* SYNC */
2666         RCAR_GP_PIN(3, 1),
2667 };
2668 static const unsigned int msiof1_sync_e_mux[] = {
2669         MSIOF1_SYNC_E_MARK,
2670 };
2671 static const unsigned int msiof1_ss1_e_pins[] = {
2672         /* SS1 */
2673         RCAR_GP_PIN(3, 4),
2674 };
2675 static const unsigned int msiof1_ss1_e_mux[] = {
2676         MSIOF1_SS1_E_MARK,
2677 };
2678 static const unsigned int msiof1_ss2_e_pins[] = {
2679         /* SS2 */
2680         RCAR_GP_PIN(3, 5),
2681 };
2682 static const unsigned int msiof1_ss2_e_mux[] = {
2683         MSIOF1_SS2_E_MARK,
2684 };
2685 static const unsigned int msiof1_txd_e_pins[] = {
2686         /* TXD */
2687         RCAR_GP_PIN(3, 3),
2688 };
2689 static const unsigned int msiof1_txd_e_mux[] = {
2690         MSIOF1_TXD_E_MARK,
2691 };
2692 static const unsigned int msiof1_rxd_e_pins[] = {
2693         /* RXD */
2694         RCAR_GP_PIN(3, 2),
2695 };
2696 static const unsigned int msiof1_rxd_e_mux[] = {
2697         MSIOF1_RXD_E_MARK,
2698 };
2699 static const unsigned int msiof1_clk_f_pins[] = {
2700         /* SCK */
2701         RCAR_GP_PIN(5, 23),
2702 };
2703 static const unsigned int msiof1_clk_f_mux[] = {
2704         MSIOF1_SCK_F_MARK,
2705 };
2706 static const unsigned int msiof1_sync_f_pins[] = {
2707         /* SYNC */
2708         RCAR_GP_PIN(5, 24),
2709 };
2710 static const unsigned int msiof1_sync_f_mux[] = {
2711         MSIOF1_SYNC_F_MARK,
2712 };
2713 static const unsigned int msiof1_ss1_f_pins[] = {
2714         /* SS1 */
2715         RCAR_GP_PIN(6, 1),
2716 };
2717 static const unsigned int msiof1_ss1_f_mux[] = {
2718         MSIOF1_SS1_F_MARK,
2719 };
2720 static const unsigned int msiof1_ss2_f_pins[] = {
2721         /* SS2 */
2722         RCAR_GP_PIN(6, 2),
2723 };
2724 static const unsigned int msiof1_ss2_f_mux[] = {
2725         MSIOF1_SS2_F_MARK,
2726 };
2727 static const unsigned int msiof1_txd_f_pins[] = {
2728         /* TXD */
2729         RCAR_GP_PIN(6, 0),
2730 };
2731 static const unsigned int msiof1_txd_f_mux[] = {
2732         MSIOF1_TXD_F_MARK,
2733 };
2734 static const unsigned int msiof1_rxd_f_pins[] = {
2735         /* RXD */
2736         RCAR_GP_PIN(5, 25),
2737 };
2738 static const unsigned int msiof1_rxd_f_mux[] = {
2739         MSIOF1_RXD_F_MARK,
2740 };
2741 static const unsigned int msiof1_clk_g_pins[] = {
2742         /* SCK */
2743         RCAR_GP_PIN(3, 6),
2744 };
2745 static const unsigned int msiof1_clk_g_mux[] = {
2746         MSIOF1_SCK_G_MARK,
2747 };
2748 static const unsigned int msiof1_sync_g_pins[] = {
2749         /* SYNC */
2750         RCAR_GP_PIN(3, 7),
2751 };
2752 static const unsigned int msiof1_sync_g_mux[] = {
2753         MSIOF1_SYNC_G_MARK,
2754 };
2755 static const unsigned int msiof1_ss1_g_pins[] = {
2756         /* SS1 */
2757         RCAR_GP_PIN(3, 10),
2758 };
2759 static const unsigned int msiof1_ss1_g_mux[] = {
2760         MSIOF1_SS1_G_MARK,
2761 };
2762 static const unsigned int msiof1_ss2_g_pins[] = {
2763         /* SS2 */
2764         RCAR_GP_PIN(3, 11),
2765 };
2766 static const unsigned int msiof1_ss2_g_mux[] = {
2767         MSIOF1_SS2_G_MARK,
2768 };
2769 static const unsigned int msiof1_txd_g_pins[] = {
2770         /* TXD */
2771         RCAR_GP_PIN(3, 9),
2772 };
2773 static const unsigned int msiof1_txd_g_mux[] = {
2774         MSIOF1_TXD_G_MARK,
2775 };
2776 static const unsigned int msiof1_rxd_g_pins[] = {
2777         /* RXD */
2778         RCAR_GP_PIN(3, 8),
2779 };
2780 static const unsigned int msiof1_rxd_g_mux[] = {
2781         MSIOF1_RXD_G_MARK,
2782 };
2783 /* - MSIOF2 ----------------------------------------------------------------- */
2784 static const unsigned int msiof2_clk_a_pins[] = {
2785         /* SCK */
2786         RCAR_GP_PIN(1, 9),
2787 };
2788 static const unsigned int msiof2_clk_a_mux[] = {
2789         MSIOF2_SCK_A_MARK,
2790 };
2791 static const unsigned int msiof2_sync_a_pins[] = {
2792         /* SYNC */
2793         RCAR_GP_PIN(1, 8),
2794 };
2795 static const unsigned int msiof2_sync_a_mux[] = {
2796         MSIOF2_SYNC_A_MARK,
2797 };
2798 static const unsigned int msiof2_ss1_a_pins[] = {
2799         /* SS1 */
2800         RCAR_GP_PIN(1, 6),
2801 };
2802 static const unsigned int msiof2_ss1_a_mux[] = {
2803         MSIOF2_SS1_A_MARK,
2804 };
2805 static const unsigned int msiof2_ss2_a_pins[] = {
2806         /* SS2 */
2807         RCAR_GP_PIN(1, 7),
2808 };
2809 static const unsigned int msiof2_ss2_a_mux[] = {
2810         MSIOF2_SS2_A_MARK,
2811 };
2812 static const unsigned int msiof2_txd_a_pins[] = {
2813         /* TXD */
2814         RCAR_GP_PIN(1, 11),
2815 };
2816 static const unsigned int msiof2_txd_a_mux[] = {
2817         MSIOF2_TXD_A_MARK,
2818 };
2819 static const unsigned int msiof2_rxd_a_pins[] = {
2820         /* RXD */
2821         RCAR_GP_PIN(1, 10),
2822 };
2823 static const unsigned int msiof2_rxd_a_mux[] = {
2824         MSIOF2_RXD_A_MARK,
2825 };
2826 static const unsigned int msiof2_clk_b_pins[] = {
2827         /* SCK */
2828         RCAR_GP_PIN(0, 4),
2829 };
2830 static const unsigned int msiof2_clk_b_mux[] = {
2831         MSIOF2_SCK_B_MARK,
2832 };
2833 static const unsigned int msiof2_sync_b_pins[] = {
2834         /* SYNC */
2835         RCAR_GP_PIN(0, 5),
2836 };
2837 static const unsigned int msiof2_sync_b_mux[] = {
2838         MSIOF2_SYNC_B_MARK,
2839 };
2840 static const unsigned int msiof2_ss1_b_pins[] = {
2841         /* SS1 */
2842         RCAR_GP_PIN(0, 0),
2843 };
2844 static const unsigned int msiof2_ss1_b_mux[] = {
2845         MSIOF2_SS1_B_MARK,
2846 };
2847 static const unsigned int msiof2_ss2_b_pins[] = {
2848         /* SS2 */
2849         RCAR_GP_PIN(0, 1),
2850 };
2851 static const unsigned int msiof2_ss2_b_mux[] = {
2852         MSIOF2_SS2_B_MARK,
2853 };
2854 static const unsigned int msiof2_txd_b_pins[] = {
2855         /* TXD */
2856         RCAR_GP_PIN(0, 7),
2857 };
2858 static const unsigned int msiof2_txd_b_mux[] = {
2859         MSIOF2_TXD_B_MARK,
2860 };
2861 static const unsigned int msiof2_rxd_b_pins[] = {
2862         /* RXD */
2863         RCAR_GP_PIN(0, 6),
2864 };
2865 static const unsigned int msiof2_rxd_b_mux[] = {
2866         MSIOF2_RXD_B_MARK,
2867 };
2868 static const unsigned int msiof2_clk_c_pins[] = {
2869         /* SCK */
2870         RCAR_GP_PIN(2, 12),
2871 };
2872 static const unsigned int msiof2_clk_c_mux[] = {
2873         MSIOF2_SCK_C_MARK,
2874 };
2875 static const unsigned int msiof2_sync_c_pins[] = {
2876         /* SYNC */
2877         RCAR_GP_PIN(2, 11),
2878 };
2879 static const unsigned int msiof2_sync_c_mux[] = {
2880         MSIOF2_SYNC_C_MARK,
2881 };
2882 static const unsigned int msiof2_ss1_c_pins[] = {
2883         /* SS1 */
2884         RCAR_GP_PIN(2, 10),
2885 };
2886 static const unsigned int msiof2_ss1_c_mux[] = {
2887         MSIOF2_SS1_C_MARK,
2888 };
2889 static const unsigned int msiof2_ss2_c_pins[] = {
2890         /* SS2 */
2891         RCAR_GP_PIN(2, 9),
2892 };
2893 static const unsigned int msiof2_ss2_c_mux[] = {
2894         MSIOF2_SS2_C_MARK,
2895 };
2896 static const unsigned int msiof2_txd_c_pins[] = {
2897         /* TXD */
2898         RCAR_GP_PIN(2, 14),
2899 };
2900 static const unsigned int msiof2_txd_c_mux[] = {
2901         MSIOF2_TXD_C_MARK,
2902 };
2903 static const unsigned int msiof2_rxd_c_pins[] = {
2904         /* RXD */
2905         RCAR_GP_PIN(2, 13),
2906 };
2907 static const unsigned int msiof2_rxd_c_mux[] = {
2908         MSIOF2_RXD_C_MARK,
2909 };
2910 static const unsigned int msiof2_clk_d_pins[] = {
2911         /* SCK */
2912         RCAR_GP_PIN(0, 8),
2913 };
2914 static const unsigned int msiof2_clk_d_mux[] = {
2915         MSIOF2_SCK_D_MARK,
2916 };
2917 static const unsigned int msiof2_sync_d_pins[] = {
2918         /* SYNC */
2919         RCAR_GP_PIN(0, 9),
2920 };
2921 static const unsigned int msiof2_sync_d_mux[] = {
2922         MSIOF2_SYNC_D_MARK,
2923 };
2924 static const unsigned int msiof2_ss1_d_pins[] = {
2925         /* SS1 */
2926         RCAR_GP_PIN(0, 12),
2927 };
2928 static const unsigned int msiof2_ss1_d_mux[] = {
2929         MSIOF2_SS1_D_MARK,
2930 };
2931 static const unsigned int msiof2_ss2_d_pins[] = {
2932         /* SS2 */
2933         RCAR_GP_PIN(0, 13),
2934 };
2935 static const unsigned int msiof2_ss2_d_mux[] = {
2936         MSIOF2_SS2_D_MARK,
2937 };
2938 static const unsigned int msiof2_txd_d_pins[] = {
2939         /* TXD */
2940         RCAR_GP_PIN(0, 11),
2941 };
2942 static const unsigned int msiof2_txd_d_mux[] = {
2943         MSIOF2_TXD_D_MARK,
2944 };
2945 static const unsigned int msiof2_rxd_d_pins[] = {
2946         /* RXD */
2947         RCAR_GP_PIN(0, 10),
2948 };
2949 static const unsigned int msiof2_rxd_d_mux[] = {
2950         MSIOF2_RXD_D_MARK,
2951 };
2952 /* - MSIOF3 ----------------------------------------------------------------- */
2953 static const unsigned int msiof3_clk_a_pins[] = {
2954         /* SCK */
2955         RCAR_GP_PIN(0, 0),
2956 };
2957 static const unsigned int msiof3_clk_a_mux[] = {
2958         MSIOF3_SCK_A_MARK,
2959 };
2960 static const unsigned int msiof3_sync_a_pins[] = {
2961         /* SYNC */
2962         RCAR_GP_PIN(0, 1),
2963 };
2964 static const unsigned int msiof3_sync_a_mux[] = {
2965         MSIOF3_SYNC_A_MARK,
2966 };
2967 static const unsigned int msiof3_ss1_a_pins[] = {
2968         /* SS1 */
2969         RCAR_GP_PIN(0, 14),
2970 };
2971 static const unsigned int msiof3_ss1_a_mux[] = {
2972         MSIOF3_SS1_A_MARK,
2973 };
2974 static const unsigned int msiof3_ss2_a_pins[] = {
2975         /* SS2 */
2976         RCAR_GP_PIN(0, 15),
2977 };
2978 static const unsigned int msiof3_ss2_a_mux[] = {
2979         MSIOF3_SS2_A_MARK,
2980 };
2981 static const unsigned int msiof3_txd_a_pins[] = {
2982         /* TXD */
2983         RCAR_GP_PIN(0, 3),
2984 };
2985 static const unsigned int msiof3_txd_a_mux[] = {
2986         MSIOF3_TXD_A_MARK,
2987 };
2988 static const unsigned int msiof3_rxd_a_pins[] = {
2989         /* RXD */
2990         RCAR_GP_PIN(0, 2),
2991 };
2992 static const unsigned int msiof3_rxd_a_mux[] = {
2993         MSIOF3_RXD_A_MARK,
2994 };
2995 static const unsigned int msiof3_clk_b_pins[] = {
2996         /* SCK */
2997         RCAR_GP_PIN(1, 2),
2998 };
2999 static const unsigned int msiof3_clk_b_mux[] = {
3000         MSIOF3_SCK_B_MARK,
3001 };
3002 static const unsigned int msiof3_sync_b_pins[] = {
3003         /* SYNC */
3004         RCAR_GP_PIN(1, 0),
3005 };
3006 static const unsigned int msiof3_sync_b_mux[] = {
3007         MSIOF3_SYNC_B_MARK,
3008 };
3009 static const unsigned int msiof3_ss1_b_pins[] = {
3010         /* SS1 */
3011         RCAR_GP_PIN(1, 4),
3012 };
3013 static const unsigned int msiof3_ss1_b_mux[] = {
3014         MSIOF3_SS1_B_MARK,
3015 };
3016 static const unsigned int msiof3_ss2_b_pins[] = {
3017         /* SS2 */
3018         RCAR_GP_PIN(1, 5),
3019 };
3020 static const unsigned int msiof3_ss2_b_mux[] = {
3021         MSIOF3_SS2_B_MARK,
3022 };
3023 static const unsigned int msiof3_txd_b_pins[] = {
3024         /* TXD */
3025         RCAR_GP_PIN(1, 1),
3026 };
3027 static const unsigned int msiof3_txd_b_mux[] = {
3028         MSIOF3_TXD_B_MARK,
3029 };
3030 static const unsigned int msiof3_rxd_b_pins[] = {
3031         /* RXD */
3032         RCAR_GP_PIN(1, 3),
3033 };
3034 static const unsigned int msiof3_rxd_b_mux[] = {
3035         MSIOF3_RXD_B_MARK,
3036 };
3037 static const unsigned int msiof3_clk_c_pins[] = {
3038         /* SCK */
3039         RCAR_GP_PIN(1, 12),
3040 };
3041 static const unsigned int msiof3_clk_c_mux[] = {
3042         MSIOF3_SCK_C_MARK,
3043 };
3044 static const unsigned int msiof3_sync_c_pins[] = {
3045         /* SYNC */
3046         RCAR_GP_PIN(1, 13),
3047 };
3048 static const unsigned int msiof3_sync_c_mux[] = {
3049         MSIOF3_SYNC_C_MARK,
3050 };
3051 static const unsigned int msiof3_txd_c_pins[] = {
3052         /* TXD */
3053         RCAR_GP_PIN(1, 15),
3054 };
3055 static const unsigned int msiof3_txd_c_mux[] = {
3056         MSIOF3_TXD_C_MARK,
3057 };
3058 static const unsigned int msiof3_rxd_c_pins[] = {
3059         /* RXD */
3060         RCAR_GP_PIN(1, 14),
3061 };
3062 static const unsigned int msiof3_rxd_c_mux[] = {
3063         MSIOF3_RXD_C_MARK,
3064 };
3065 static const unsigned int msiof3_clk_d_pins[] = {
3066         /* SCK */
3067         RCAR_GP_PIN(1, 22),
3068 };
3069 static const unsigned int msiof3_clk_d_mux[] = {
3070         MSIOF3_SCK_D_MARK,
3071 };
3072 static const unsigned int msiof3_sync_d_pins[] = {
3073         /* SYNC */
3074         RCAR_GP_PIN(1, 23),
3075 };
3076 static const unsigned int msiof3_sync_d_mux[] = {
3077         MSIOF3_SYNC_D_MARK,
3078 };
3079 static const unsigned int msiof3_ss1_d_pins[] = {
3080         /* SS1 */
3081         RCAR_GP_PIN(1, 26),
3082 };
3083 static const unsigned int msiof3_ss1_d_mux[] = {
3084         MSIOF3_SS1_D_MARK,
3085 };
3086 static const unsigned int msiof3_txd_d_pins[] = {
3087         /* TXD */
3088         RCAR_GP_PIN(1, 25),
3089 };
3090 static const unsigned int msiof3_txd_d_mux[] = {
3091         MSIOF3_TXD_D_MARK,
3092 };
3093 static const unsigned int msiof3_rxd_d_pins[] = {
3094         /* RXD */
3095         RCAR_GP_PIN(1, 24),
3096 };
3097 static const unsigned int msiof3_rxd_d_mux[] = {
3098         MSIOF3_RXD_D_MARK,
3099 };
3100 static const unsigned int msiof3_clk_e_pins[] = {
3101         /* SCK */
3102         RCAR_GP_PIN(2, 3),
3103 };
3104 static const unsigned int msiof3_clk_e_mux[] = {
3105         MSIOF3_SCK_E_MARK,
3106 };
3107 static const unsigned int msiof3_sync_e_pins[] = {
3108         /* SYNC */
3109         RCAR_GP_PIN(2, 2),
3110 };
3111 static const unsigned int msiof3_sync_e_mux[] = {
3112         MSIOF3_SYNC_E_MARK,
3113 };
3114 static const unsigned int msiof3_ss1_e_pins[] = {
3115         /* SS1 */
3116         RCAR_GP_PIN(2, 1),
3117 };
3118 static const unsigned int msiof3_ss1_e_mux[] = {
3119         MSIOF3_SS1_E_MARK,
3120 };
3121 static const unsigned int msiof3_ss2_e_pins[] = {
3122         /* SS2 */
3123         RCAR_GP_PIN(2, 0),
3124 };
3125 static const unsigned int msiof3_ss2_e_mux[] = {
3126         MSIOF3_SS2_E_MARK,
3127 };
3128 static const unsigned int msiof3_txd_e_pins[] = {
3129         /* TXD */
3130         RCAR_GP_PIN(2, 5),
3131 };
3132 static const unsigned int msiof3_txd_e_mux[] = {
3133         MSIOF3_TXD_E_MARK,
3134 };
3135 static const unsigned int msiof3_rxd_e_pins[] = {
3136         /* RXD */
3137         RCAR_GP_PIN(2, 4),
3138 };
3139 static const unsigned int msiof3_rxd_e_mux[] = {
3140         MSIOF3_RXD_E_MARK,
3141 };
3142
3143 /* - PWM0 --------------------------------------------------------------------*/
3144 static const unsigned int pwm0_pins[] = {
3145         /* PWM */
3146         RCAR_GP_PIN(2, 6),
3147 };
3148 static const unsigned int pwm0_mux[] = {
3149         PWM0_MARK,
3150 };
3151 /* - PWM1 --------------------------------------------------------------------*/
3152 static const unsigned int pwm1_a_pins[] = {
3153         /* PWM */
3154         RCAR_GP_PIN(2, 7),
3155 };
3156 static const unsigned int pwm1_a_mux[] = {
3157         PWM1_A_MARK,
3158 };
3159 static const unsigned int pwm1_b_pins[] = {
3160         /* PWM */
3161         RCAR_GP_PIN(1, 8),
3162 };
3163 static const unsigned int pwm1_b_mux[] = {
3164         PWM1_B_MARK,
3165 };
3166 /* - PWM2 --------------------------------------------------------------------*/
3167 static const unsigned int pwm2_a_pins[] = {
3168         /* PWM */
3169         RCAR_GP_PIN(2, 8),
3170 };
3171 static const unsigned int pwm2_a_mux[] = {
3172         PWM2_A_MARK,
3173 };
3174 static const unsigned int pwm2_b_pins[] = {
3175         /* PWM */
3176         RCAR_GP_PIN(1, 11),
3177 };
3178 static const unsigned int pwm2_b_mux[] = {
3179         PWM2_B_MARK,
3180 };
3181 /* - PWM3 --------------------------------------------------------------------*/
3182 static const unsigned int pwm3_a_pins[] = {
3183         /* PWM */
3184         RCAR_GP_PIN(1, 0),
3185 };
3186 static const unsigned int pwm3_a_mux[] = {
3187         PWM3_A_MARK,
3188 };
3189 static const unsigned int pwm3_b_pins[] = {
3190         /* PWM */
3191         RCAR_GP_PIN(2, 2),
3192 };
3193 static const unsigned int pwm3_b_mux[] = {
3194         PWM3_B_MARK,
3195 };
3196 /* - PWM4 --------------------------------------------------------------------*/
3197 static const unsigned int pwm4_a_pins[] = {
3198         /* PWM */
3199         RCAR_GP_PIN(1, 1),
3200 };
3201 static const unsigned int pwm4_a_mux[] = {
3202         PWM4_A_MARK,
3203 };
3204 static const unsigned int pwm4_b_pins[] = {
3205         /* PWM */
3206         RCAR_GP_PIN(2, 3),
3207 };
3208 static const unsigned int pwm4_b_mux[] = {
3209         PWM4_B_MARK,
3210 };
3211 /* - PWM5 --------------------------------------------------------------------*/
3212 static const unsigned int pwm5_a_pins[] = {
3213         /* PWM */
3214         RCAR_GP_PIN(1, 2),
3215 };
3216 static const unsigned int pwm5_a_mux[] = {
3217         PWM5_A_MARK,
3218 };
3219 static const unsigned int pwm5_b_pins[] = {
3220         /* PWM */
3221         RCAR_GP_PIN(2, 4),
3222 };
3223 static const unsigned int pwm5_b_mux[] = {
3224         PWM5_B_MARK,
3225 };
3226 /* - PWM6 --------------------------------------------------------------------*/
3227 static const unsigned int pwm6_a_pins[] = {
3228         /* PWM */
3229         RCAR_GP_PIN(1, 3),
3230 };
3231 static const unsigned int pwm6_a_mux[] = {
3232         PWM6_A_MARK,
3233 };
3234 static const unsigned int pwm6_b_pins[] = {
3235         /* PWM */
3236         RCAR_GP_PIN(2, 5),
3237 };
3238 static const unsigned int pwm6_b_mux[] = {
3239         PWM6_B_MARK,
3240 };
3241
3242 /* - SATA --------------------------------------------------------------------*/
3243 static const unsigned int sata0_devslp_a_pins[] = {
3244         /* DEVSLP */
3245         RCAR_GP_PIN(6, 16),
3246 };
3247 static const unsigned int sata0_devslp_a_mux[] = {
3248         SATA_DEVSLP_A_MARK,
3249 };
3250 static const unsigned int sata0_devslp_b_pins[] = {
3251         /* DEVSLP */
3252         RCAR_GP_PIN(4, 6),
3253 };
3254 static const unsigned int sata0_devslp_b_mux[] = {
3255         SATA_DEVSLP_B_MARK,
3256 };
3257
3258 /* - SCIF0 ------------------------------------------------------------------ */
3259 static const unsigned int scif0_data_pins[] = {
3260         /* RX, TX */
3261         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3262 };
3263 static const unsigned int scif0_data_mux[] = {
3264         RX0_MARK, TX0_MARK,
3265 };
3266 static const unsigned int scif0_clk_pins[] = {
3267         /* SCK */
3268         RCAR_GP_PIN(5, 0),
3269 };
3270 static const unsigned int scif0_clk_mux[] = {
3271         SCK0_MARK,
3272 };
3273 static const unsigned int scif0_ctrl_pins[] = {
3274         /* RTS, CTS */
3275         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3276 };
3277 static const unsigned int scif0_ctrl_mux[] = {
3278         RTS0_N_MARK, CTS0_N_MARK,
3279 };
3280 /* - SCIF1 ------------------------------------------------------------------ */
3281 static const unsigned int scif1_data_a_pins[] = {
3282         /* RX, TX */
3283         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3284 };
3285 static const unsigned int scif1_data_a_mux[] = {
3286         RX1_A_MARK, TX1_A_MARK,
3287 };
3288 static const unsigned int scif1_clk_pins[] = {
3289         /* SCK */
3290         RCAR_GP_PIN(6, 21),
3291 };
3292 static const unsigned int scif1_clk_mux[] = {
3293         SCK1_MARK,
3294 };
3295 static const unsigned int scif1_ctrl_pins[] = {
3296         /* RTS, CTS */
3297         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3298 };
3299 static const unsigned int scif1_ctrl_mux[] = {
3300         RTS1_N_MARK, CTS1_N_MARK,
3301 };
3302
3303 static const unsigned int scif1_data_b_pins[] = {
3304         /* RX, TX */
3305         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3306 };
3307 static const unsigned int scif1_data_b_mux[] = {
3308         RX1_B_MARK, TX1_B_MARK,
3309 };
3310 /* - SCIF2 ------------------------------------------------------------------ */
3311 static const unsigned int scif2_data_a_pins[] = {
3312         /* RX, TX */
3313         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3314 };
3315 static const unsigned int scif2_data_a_mux[] = {
3316         RX2_A_MARK, TX2_A_MARK,
3317 };
3318 static const unsigned int scif2_clk_pins[] = {
3319         /* SCK */
3320         RCAR_GP_PIN(5, 9),
3321 };
3322 static const unsigned int scif2_clk_mux[] = {
3323         SCK2_MARK,
3324 };
3325 static const unsigned int scif2_data_b_pins[] = {
3326         /* RX, TX */
3327         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3328 };
3329 static const unsigned int scif2_data_b_mux[] = {
3330         RX2_B_MARK, TX2_B_MARK,
3331 };
3332 /* - SCIF3 ------------------------------------------------------------------ */
3333 static const unsigned int scif3_data_a_pins[] = {
3334         /* RX, TX */
3335         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3336 };
3337 static const unsigned int scif3_data_a_mux[] = {
3338         RX3_A_MARK, TX3_A_MARK,
3339 };
3340 static const unsigned int scif3_clk_pins[] = {
3341         /* SCK */
3342         RCAR_GP_PIN(1, 22),
3343 };
3344 static const unsigned int scif3_clk_mux[] = {
3345         SCK3_MARK,
3346 };
3347 static const unsigned int scif3_ctrl_pins[] = {
3348         /* RTS, CTS */
3349         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3350 };
3351 static const unsigned int scif3_ctrl_mux[] = {
3352         RTS3_N_MARK, CTS3_N_MARK,
3353 };
3354 static const unsigned int scif3_data_b_pins[] = {
3355         /* RX, TX */
3356         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3357 };
3358 static const unsigned int scif3_data_b_mux[] = {
3359         RX3_B_MARK, TX3_B_MARK,
3360 };
3361 /* - SCIF4 ------------------------------------------------------------------ */
3362 static const unsigned int scif4_data_a_pins[] = {
3363         /* RX, TX */
3364         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3365 };
3366 static const unsigned int scif4_data_a_mux[] = {
3367         RX4_A_MARK, TX4_A_MARK,
3368 };
3369 static const unsigned int scif4_clk_a_pins[] = {
3370         /* SCK */
3371         RCAR_GP_PIN(2, 10),
3372 };
3373 static const unsigned int scif4_clk_a_mux[] = {
3374         SCK4_A_MARK,
3375 };
3376 static const unsigned int scif4_ctrl_a_pins[] = {
3377         /* RTS, CTS */
3378         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3379 };
3380 static const unsigned int scif4_ctrl_a_mux[] = {
3381         RTS4_N_A_MARK, CTS4_N_A_MARK,
3382 };
3383 static const unsigned int scif4_data_b_pins[] = {
3384         /* RX, TX */
3385         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3386 };
3387 static const unsigned int scif4_data_b_mux[] = {
3388         RX4_B_MARK, TX4_B_MARK,
3389 };
3390 static const unsigned int scif4_clk_b_pins[] = {
3391         /* SCK */
3392         RCAR_GP_PIN(1, 5),
3393 };
3394 static const unsigned int scif4_clk_b_mux[] = {
3395         SCK4_B_MARK,
3396 };
3397 static const unsigned int scif4_ctrl_b_pins[] = {
3398         /* RTS, CTS */
3399         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3400 };
3401 static const unsigned int scif4_ctrl_b_mux[] = {
3402         RTS4_N_B_MARK, CTS4_N_B_MARK,
3403 };
3404 static const unsigned int scif4_data_c_pins[] = {
3405         /* RX, TX */
3406         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3407 };
3408 static const unsigned int scif4_data_c_mux[] = {
3409         RX4_C_MARK, TX4_C_MARK,
3410 };
3411 static const unsigned int scif4_clk_c_pins[] = {
3412         /* SCK */
3413         RCAR_GP_PIN(0, 8),
3414 };
3415 static const unsigned int scif4_clk_c_mux[] = {
3416         SCK4_C_MARK,
3417 };
3418 static const unsigned int scif4_ctrl_c_pins[] = {
3419         /* RTS, CTS */
3420         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3421 };
3422 static const unsigned int scif4_ctrl_c_mux[] = {
3423         RTS4_N_C_MARK, CTS4_N_C_MARK,
3424 };
3425 /* - SCIF5 ------------------------------------------------------------------ */
3426 static const unsigned int scif5_data_a_pins[] = {
3427         /* RX, TX */
3428         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3429 };
3430 static const unsigned int scif5_data_a_mux[] = {
3431         RX5_A_MARK, TX5_A_MARK,
3432 };
3433 static const unsigned int scif5_clk_a_pins[] = {
3434         /* SCK */
3435         RCAR_GP_PIN(6, 21),
3436 };
3437 static const unsigned int scif5_clk_a_mux[] = {
3438         SCK5_A_MARK,
3439 };
3440 static const unsigned int scif5_data_b_pins[] = {
3441         /* RX, TX */
3442         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3443 };
3444 static const unsigned int scif5_data_b_mux[] = {
3445         RX5_B_MARK, TX5_B_MARK,
3446 };
3447 static const unsigned int scif5_clk_b_pins[] = {
3448         /* SCK */
3449         RCAR_GP_PIN(5, 0),
3450 };
3451 static const unsigned int scif5_clk_b_mux[] = {
3452         SCK5_B_MARK,
3453 };
3454
3455 /* - SCIF Clock ------------------------------------------------------------- */
3456 static const unsigned int scif_clk_a_pins[] = {
3457         /* SCIF_CLK */
3458         RCAR_GP_PIN(6, 23),
3459 };
3460 static const unsigned int scif_clk_a_mux[] = {
3461         SCIF_CLK_A_MARK,
3462 };
3463 static const unsigned int scif_clk_b_pins[] = {
3464         /* SCIF_CLK */
3465         RCAR_GP_PIN(5, 9),
3466 };
3467 static const unsigned int scif_clk_b_mux[] = {
3468         SCIF_CLK_B_MARK,
3469 };
3470
3471 /* - SDHI0 ------------------------------------------------------------------ */
3472 static const unsigned int sdhi0_data1_pins[] = {
3473         /* D0 */
3474         RCAR_GP_PIN(3, 2),
3475 };
3476 static const unsigned int sdhi0_data1_mux[] = {
3477         SD0_DAT0_MARK,
3478 };
3479 static const unsigned int sdhi0_data4_pins[] = {
3480         /* D[0:3] */
3481         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3482         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3483 };
3484 static const unsigned int sdhi0_data4_mux[] = {
3485         SD0_DAT0_MARK, SD0_DAT1_MARK,
3486         SD0_DAT2_MARK, SD0_DAT3_MARK,
3487 };
3488 static const unsigned int sdhi0_ctrl_pins[] = {
3489         /* CLK, CMD */
3490         RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3491 };
3492 static const unsigned int sdhi0_ctrl_mux[] = {
3493         SD0_CLK_MARK, SD0_CMD_MARK,
3494 };
3495 static const unsigned int sdhi0_cd_pins[] = {
3496         /* CD */
3497         RCAR_GP_PIN(3, 12),
3498 };
3499 static const unsigned int sdhi0_cd_mux[] = {
3500         SD0_CD_MARK,
3501 };
3502 static const unsigned int sdhi0_wp_pins[] = {
3503         /* WP */
3504         RCAR_GP_PIN(3, 13),
3505 };
3506 static const unsigned int sdhi0_wp_mux[] = {
3507         SD0_WP_MARK,
3508 };
3509 /* - SDHI1 ------------------------------------------------------------------ */
3510 static const unsigned int sdhi1_data1_pins[] = {
3511         /* D0 */
3512         RCAR_GP_PIN(3, 8),
3513 };
3514 static const unsigned int sdhi1_data1_mux[] = {
3515         SD1_DAT0_MARK,
3516 };
3517 static const unsigned int sdhi1_data4_pins[] = {
3518         /* D[0:3] */
3519         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3520         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3521 };
3522 static const unsigned int sdhi1_data4_mux[] = {
3523         SD1_DAT0_MARK, SD1_DAT1_MARK,
3524         SD1_DAT2_MARK, SD1_DAT3_MARK,
3525 };
3526 static const unsigned int sdhi1_ctrl_pins[] = {
3527         /* CLK, CMD */
3528         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3529 };
3530 static const unsigned int sdhi1_ctrl_mux[] = {
3531         SD1_CLK_MARK, SD1_CMD_MARK,
3532 };
3533 static const unsigned int sdhi1_cd_pins[] = {
3534         /* CD */
3535         RCAR_GP_PIN(3, 14),
3536 };
3537 static const unsigned int sdhi1_cd_mux[] = {
3538         SD1_CD_MARK,
3539 };
3540 static const unsigned int sdhi1_wp_pins[] = {
3541         /* WP */
3542         RCAR_GP_PIN(3, 15),
3543 };
3544 static const unsigned int sdhi1_wp_mux[] = {
3545         SD1_WP_MARK,
3546 };
3547 /* - SDHI2 ------------------------------------------------------------------ */
3548 static const unsigned int sdhi2_data1_pins[] = {
3549         /* D0 */
3550         RCAR_GP_PIN(4, 2),
3551 };
3552 static const unsigned int sdhi2_data1_mux[] = {
3553         SD2_DAT0_MARK,
3554 };
3555 static const unsigned int sdhi2_data4_pins[] = {
3556         /* D[0:3] */
3557         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3558         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3559 };
3560 static const unsigned int sdhi2_data4_mux[] = {
3561         SD2_DAT0_MARK, SD2_DAT1_MARK,
3562         SD2_DAT2_MARK, SD2_DAT3_MARK,
3563 };
3564 static const unsigned int sdhi2_data8_pins[] = {
3565         /* D[0:7] */
3566         RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
3567         RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
3568         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3569         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3570 };
3571 static const unsigned int sdhi2_data8_mux[] = {
3572         SD2_DAT0_MARK, SD2_DAT1_MARK,
3573         SD2_DAT2_MARK, SD2_DAT3_MARK,
3574         SD2_DAT4_MARK, SD2_DAT5_MARK,
3575         SD2_DAT6_MARK, SD2_DAT7_MARK,
3576 };
3577 static const unsigned int sdhi2_ctrl_pins[] = {
3578         /* CLK, CMD */
3579         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3580 };
3581 static const unsigned int sdhi2_ctrl_mux[] = {
3582         SD2_CLK_MARK, SD2_CMD_MARK,
3583 };
3584 static const unsigned int sdhi2_cd_a_pins[] = {
3585         /* CD */
3586         RCAR_GP_PIN(4, 13),
3587 };
3588 static const unsigned int sdhi2_cd_a_mux[] = {
3589         SD2_CD_A_MARK,
3590 };
3591 static const unsigned int sdhi2_cd_b_pins[] = {
3592         /* CD */
3593         RCAR_GP_PIN(5, 10),
3594 };
3595 static const unsigned int sdhi2_cd_b_mux[] = {
3596         SD2_CD_B_MARK,
3597 };
3598 static const unsigned int sdhi2_wp_a_pins[] = {
3599         /* WP */
3600         RCAR_GP_PIN(4, 14),
3601 };
3602 static const unsigned int sdhi2_wp_a_mux[] = {
3603         SD2_WP_A_MARK,
3604 };
3605 static const unsigned int sdhi2_wp_b_pins[] = {
3606         /* WP */
3607         RCAR_GP_PIN(5, 11),
3608 };
3609 static const unsigned int sdhi2_wp_b_mux[] = {
3610         SD2_WP_B_MARK,
3611 };
3612 static const unsigned int sdhi2_ds_pins[] = {
3613         /* DS */
3614         RCAR_GP_PIN(4, 6),
3615 };
3616 static const unsigned int sdhi2_ds_mux[] = {
3617         SD2_DS_MARK,
3618 };
3619 /* - SDHI3 ------------------------------------------------------------------ */
3620 static const unsigned int sdhi3_data1_pins[] = {
3621         /* D0 */
3622         RCAR_GP_PIN(4, 9),
3623 };
3624 static const unsigned int sdhi3_data1_mux[] = {
3625         SD3_DAT0_MARK,
3626 };
3627 static const unsigned int sdhi3_data4_pins[] = {
3628         /* D[0:3] */
3629         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3630         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3631 };
3632 static const unsigned int sdhi3_data4_mux[] = {
3633         SD3_DAT0_MARK, SD3_DAT1_MARK,
3634         SD3_DAT2_MARK, SD3_DAT3_MARK,
3635 };
3636 static const unsigned int sdhi3_data8_pins[] = {
3637         /* D[0:7] */
3638         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3639         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3640         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3641         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3642 };
3643 static const unsigned int sdhi3_data8_mux[] = {
3644         SD3_DAT0_MARK, SD3_DAT1_MARK,
3645         SD3_DAT2_MARK, SD3_DAT3_MARK,
3646         SD3_DAT4_MARK, SD3_DAT5_MARK,
3647         SD3_DAT6_MARK, SD3_DAT7_MARK,
3648 };
3649 static const unsigned int sdhi3_ctrl_pins[] = {
3650         /* CLK, CMD */
3651         RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3652 };
3653 static const unsigned int sdhi3_ctrl_mux[] = {
3654         SD3_CLK_MARK, SD3_CMD_MARK,
3655 };
3656 static const unsigned int sdhi3_cd_pins[] = {
3657         /* CD */
3658         RCAR_GP_PIN(4, 15),
3659 };
3660 static const unsigned int sdhi3_cd_mux[] = {
3661         SD3_CD_MARK,
3662 };
3663 static const unsigned int sdhi3_wp_pins[] = {
3664         /* WP */
3665         RCAR_GP_PIN(4, 16),
3666 };
3667 static const unsigned int sdhi3_wp_mux[] = {
3668         SD3_WP_MARK,
3669 };
3670 static const unsigned int sdhi3_ds_pins[] = {
3671         /* DS */
3672         RCAR_GP_PIN(4, 17),
3673 };
3674 static const unsigned int sdhi3_ds_mux[] = {
3675         SD3_DS_MARK,
3676 };
3677
3678 /* - SSI -------------------------------------------------------------------- */
3679 static const unsigned int ssi0_data_pins[] = {
3680         /* SDATA */
3681         RCAR_GP_PIN(6, 2),
3682 };
3683 static const unsigned int ssi0_data_mux[] = {
3684         SSI_SDATA0_MARK,
3685 };
3686 static const unsigned int ssi01239_ctrl_pins[] = {
3687         /* SCK, WS */
3688         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3689 };
3690 static const unsigned int ssi01239_ctrl_mux[] = {
3691         SSI_SCK01239_MARK, SSI_WS01239_MARK,
3692 };
3693 static const unsigned int ssi1_data_a_pins[] = {
3694         /* SDATA */
3695         RCAR_GP_PIN(6, 3),
3696 };
3697 static const unsigned int ssi1_data_a_mux[] = {
3698         SSI_SDATA1_A_MARK,
3699 };
3700 static const unsigned int ssi1_data_b_pins[] = {
3701         /* SDATA */
3702         RCAR_GP_PIN(5, 12),
3703 };
3704 static const unsigned int ssi1_data_b_mux[] = {
3705         SSI_SDATA1_B_MARK,
3706 };
3707 static const unsigned int ssi1_ctrl_a_pins[] = {
3708         /* SCK, WS */
3709         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3710 };
3711 static const unsigned int ssi1_ctrl_a_mux[] = {
3712         SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3713 };
3714 static const unsigned int ssi1_ctrl_b_pins[] = {
3715         /* SCK, WS */
3716         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3717 };
3718 static const unsigned int ssi1_ctrl_b_mux[] = {
3719         SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3720 };
3721 static const unsigned int ssi2_data_a_pins[] = {
3722         /* SDATA */
3723         RCAR_GP_PIN(6, 4),
3724 };
3725 static const unsigned int ssi2_data_a_mux[] = {
3726         SSI_SDATA2_A_MARK,
3727 };
3728 static const unsigned int ssi2_data_b_pins[] = {
3729         /* SDATA */
3730         RCAR_GP_PIN(5, 13),
3731 };
3732 static const unsigned int ssi2_data_b_mux[] = {
3733         SSI_SDATA2_B_MARK,
3734 };
3735 static const unsigned int ssi2_ctrl_a_pins[] = {
3736         /* SCK, WS */
3737         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3738 };
3739 static const unsigned int ssi2_ctrl_a_mux[] = {
3740         SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3741 };
3742 static const unsigned int ssi2_ctrl_b_pins[] = {
3743         /* SCK, WS */
3744         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3745 };
3746 static const unsigned int ssi2_ctrl_b_mux[] = {
3747         SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3748 };
3749 static const unsigned int ssi3_data_pins[] = {
3750         /* SDATA */
3751         RCAR_GP_PIN(6, 7),
3752 };
3753 static const unsigned int ssi3_data_mux[] = {
3754         SSI_SDATA3_MARK,
3755 };
3756 static const unsigned int ssi349_ctrl_pins[] = {
3757         /* SCK, WS */
3758         RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3759 };
3760 static const unsigned int ssi349_ctrl_mux[] = {
3761         SSI_SCK349_MARK, SSI_WS349_MARK,
3762 };
3763 static const unsigned int ssi4_data_pins[] = {
3764         /* SDATA */
3765         RCAR_GP_PIN(6, 10),
3766 };
3767 static const unsigned int ssi4_data_mux[] = {
3768         SSI_SDATA4_MARK,
3769 };
3770 static const unsigned int ssi4_ctrl_pins[] = {
3771         /* SCK, WS */
3772         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3773 };
3774 static const unsigned int ssi4_ctrl_mux[] = {
3775         SSI_SCK4_MARK, SSI_WS4_MARK,
3776 };
3777 static const unsigned int ssi5_data_pins[] = {
3778         /* SDATA */
3779         RCAR_GP_PIN(6, 13),
3780 };
3781 static const unsigned int ssi5_data_mux[] = {
3782         SSI_SDATA5_MARK,
3783 };
3784 static const unsigned int ssi5_ctrl_pins[] = {
3785         /* SCK, WS */
3786         RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3787 };
3788 static const unsigned int ssi5_ctrl_mux[] = {
3789         SSI_SCK5_MARK, SSI_WS5_MARK,
3790 };
3791 static const unsigned int ssi6_data_pins[] = {
3792         /* SDATA */
3793         RCAR_GP_PIN(6, 16),
3794 };
3795 static const unsigned int ssi6_data_mux[] = {
3796         SSI_SDATA6_MARK,
3797 };
3798 static const unsigned int ssi6_ctrl_pins[] = {
3799         /* SCK, WS */
3800         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3801 };
3802 static const unsigned int ssi6_ctrl_mux[] = {
3803         SSI_SCK6_MARK, SSI_WS6_MARK,
3804 };
3805 static const unsigned int ssi7_data_pins[] = {
3806         /* SDATA */
3807         RCAR_GP_PIN(6, 19),
3808 };
3809 static const unsigned int ssi7_data_mux[] = {
3810         SSI_SDATA7_MARK,
3811 };
3812 static const unsigned int ssi78_ctrl_pins[] = {
3813         /* SCK, WS */
3814         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3815 };
3816 static const unsigned int ssi78_ctrl_mux[] = {
3817         SSI_SCK78_MARK, SSI_WS78_MARK,
3818 };
3819 static const unsigned int ssi8_data_pins[] = {
3820         /* SDATA */
3821         RCAR_GP_PIN(6, 20),
3822 };
3823 static const unsigned int ssi8_data_mux[] = {
3824         SSI_SDATA8_MARK,
3825 };
3826 static const unsigned int ssi9_data_a_pins[] = {
3827         /* SDATA */
3828         RCAR_GP_PIN(6, 21),
3829 };
3830 static const unsigned int ssi9_data_a_mux[] = {
3831         SSI_SDATA9_A_MARK,
3832 };
3833 static const unsigned int ssi9_data_b_pins[] = {
3834         /* SDATA */
3835         RCAR_GP_PIN(5, 14),
3836 };
3837 static const unsigned int ssi9_data_b_mux[] = {
3838         SSI_SDATA9_B_MARK,
3839 };
3840 static const unsigned int ssi9_ctrl_a_pins[] = {
3841         /* SCK, WS */
3842         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3843 };
3844 static const unsigned int ssi9_ctrl_a_mux[] = {
3845         SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3846 };
3847 static const unsigned int ssi9_ctrl_b_pins[] = {
3848         /* SCK, WS */
3849         RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3850 };
3851 static const unsigned int ssi9_ctrl_b_mux[] = {
3852         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3853 };
3854
3855 /* - TMU -------------------------------------------------------------------- */
3856 static const unsigned int tmu_tclk1_a_pins[] = {
3857         /* TCLK */
3858         RCAR_GP_PIN(6, 23),
3859 };
3860 static const unsigned int tmu_tclk1_a_mux[] = {
3861         TCLK1_A_MARK,
3862 };
3863 static const unsigned int tmu_tclk1_b_pins[] = {
3864         /* TCLK */
3865         RCAR_GP_PIN(5, 19),
3866 };
3867 static const unsigned int tmu_tclk1_b_mux[] = {
3868         TCLK1_B_MARK,
3869 };
3870 static const unsigned int tmu_tclk2_a_pins[] = {
3871         /* TCLK */
3872         RCAR_GP_PIN(6, 19),
3873 };
3874 static const unsigned int tmu_tclk2_a_mux[] = {
3875         TCLK2_A_MARK,
3876 };
3877 static const unsigned int tmu_tclk2_b_pins[] = {
3878         /* TCLK */
3879         RCAR_GP_PIN(6, 28),
3880 };
3881 static const unsigned int tmu_tclk2_b_mux[] = {
3882         TCLK2_B_MARK,
3883 };
3884
3885 /* - USB0 ------------------------------------------------------------------- */
3886 static const unsigned int usb0_pins[] = {
3887         /* PWEN, OVC */
3888         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3889 };
3890 static const unsigned int usb0_mux[] = {
3891         USB0_PWEN_MARK, USB0_OVC_MARK,
3892 };
3893 /* - USB1 ------------------------------------------------------------------- */
3894 static const unsigned int usb1_pins[] = {
3895         /* PWEN, OVC */
3896         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3897 };
3898 static const unsigned int usb1_mux[] = {
3899         USB1_PWEN_MARK, USB1_OVC_MARK,
3900 };
3901 /* - USB2 ------------------------------------------------------------------- */
3902 static const unsigned int usb2_pins[] = {
3903         /* PWEN, OVC */
3904         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3905 };
3906 static const unsigned int usb2_mux[] = {
3907         USB2_PWEN_MARK, USB2_OVC_MARK,
3908 };
3909 /* - USB2_CH3 --------------------------------------------------------------- */
3910 static const unsigned int usb2_ch3_pins[] = {
3911         /* PWEN, OVC */
3912         RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3913 };
3914 static const unsigned int usb2_ch3_mux[] = {
3915         USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
3916 };
3917
3918 /* - USB30 ------------------------------------------------------------------ */
3919 static const unsigned int usb30_pins[] = {
3920         /* PWEN, OVC */
3921         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3922 };
3923 static const unsigned int usb30_mux[] = {
3924         USB30_PWEN_MARK, USB30_OVC_MARK,
3925 };
3926
3927 /* - VIN4 ------------------------------------------------------------------- */
3928 static const unsigned int vin4_data18_a_pins[] = {
3929         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3930         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3931         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3932         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3933         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3934         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3935         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3936         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3937         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3938 };
3939 static const unsigned int vin4_data18_a_mux[] = {
3940         VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3941         VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3942         VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3943         VI4_DATA10_MARK, VI4_DATA11_MARK,
3944         VI4_DATA12_MARK, VI4_DATA13_MARK,
3945         VI4_DATA14_MARK, VI4_DATA15_MARK,
3946         VI4_DATA18_MARK, VI4_DATA19_MARK,
3947         VI4_DATA20_MARK, VI4_DATA21_MARK,
3948         VI4_DATA22_MARK, VI4_DATA23_MARK,
3949 };
3950 static const unsigned int vin4_data18_b_pins[] = {
3951         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3952         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3953         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3954         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3955         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3956         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3957         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3958         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3959         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3960 };
3961 static const unsigned int vin4_data18_b_mux[] = {
3962         VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3963         VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3964         VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3965         VI4_DATA10_MARK, VI4_DATA11_MARK,
3966         VI4_DATA12_MARK, VI4_DATA13_MARK,
3967         VI4_DATA14_MARK, VI4_DATA15_MARK,
3968         VI4_DATA18_MARK, VI4_DATA19_MARK,
3969         VI4_DATA20_MARK, VI4_DATA21_MARK,
3970         VI4_DATA22_MARK, VI4_DATA23_MARK,
3971 };
3972 static const union vin_data vin4_data_a_pins = {
3973         .data24 = {
3974                 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3975                 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3976                 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3977                 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3978                 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3979                 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3980                 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3981                 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3982                 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3983                 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3984                 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3985                 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3986         },
3987 };
3988 static const union vin_data vin4_data_a_mux = {
3989         .data24 = {
3990                 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
3991                 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3992                 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3993                 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3994                 VI4_DATA8_MARK,  VI4_DATA9_MARK,
3995                 VI4_DATA10_MARK, VI4_DATA11_MARK,
3996                 VI4_DATA12_MARK, VI4_DATA13_MARK,
3997                 VI4_DATA14_MARK, VI4_DATA15_MARK,
3998                 VI4_DATA16_MARK, VI4_DATA17_MARK,
3999                 VI4_DATA18_MARK, VI4_DATA19_MARK,
4000                 VI4_DATA20_MARK, VI4_DATA21_MARK,
4001                 VI4_DATA22_MARK, VI4_DATA23_MARK,
4002         },
4003 };
4004 static const union vin_data vin4_data_b_pins = {
4005         .data24 = {
4006                 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4007                 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4008                 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4009                 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4010                 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4011                 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4012                 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4013                 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4014                 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4015                 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4016                 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4017                 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4018         },
4019 };
4020 static const union vin_data vin4_data_b_mux = {
4021         .data24 = {
4022                 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4023                 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4024                 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4025                 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4026                 VI4_DATA8_MARK,  VI4_DATA9_MARK,
4027                 VI4_DATA10_MARK, VI4_DATA11_MARK,
4028                 VI4_DATA12_MARK, VI4_DATA13_MARK,
4029                 VI4_DATA14_MARK, VI4_DATA15_MARK,
4030                 VI4_DATA16_MARK, VI4_DATA17_MARK,
4031                 VI4_DATA18_MARK, VI4_DATA19_MARK,
4032                 VI4_DATA20_MARK, VI4_DATA21_MARK,
4033                 VI4_DATA22_MARK, VI4_DATA23_MARK,
4034         },
4035 };
4036 static const unsigned int vin4_sync_pins[] = {
4037         /* HSYNC#, VSYNC# */
4038         RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4039 };
4040 static const unsigned int vin4_sync_mux[] = {
4041         VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4042 };
4043 static const unsigned int vin4_field_pins[] = {
4044         /* FIELD */
4045         RCAR_GP_PIN(1, 16),
4046 };
4047 static const unsigned int vin4_field_mux[] = {
4048         VI4_FIELD_MARK,
4049 };
4050 static const unsigned int vin4_clkenb_pins[] = {
4051         /* CLKENB */
4052         RCAR_GP_PIN(1, 19),
4053 };
4054 static const unsigned int vin4_clkenb_mux[] = {
4055         VI4_CLKENB_MARK,
4056 };
4057 static const unsigned int vin4_clk_pins[] = {
4058         /* CLK */
4059         RCAR_GP_PIN(1, 27),
4060 };
4061 static const unsigned int vin4_clk_mux[] = {
4062         VI4_CLK_MARK,
4063 };
4064
4065 /* - VIN5 ------------------------------------------------------------------- */
4066 static const unsigned int vin5_data8_pins[] = {
4067         RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4068         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4069         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4070         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4071 };
4072 static const unsigned int vin5_data8_mux[] = {
4073         VI5_DATA0_MARK, VI5_DATA1_MARK,
4074         VI5_DATA2_MARK, VI5_DATA3_MARK,
4075         VI5_DATA4_MARK, VI5_DATA5_MARK,
4076         VI5_DATA6_MARK, VI5_DATA7_MARK,
4077 };
4078 static const unsigned int vin5_data10_pins[] = {
4079         RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4080         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4081         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4082         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4083         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4084 };
4085 static const unsigned int vin5_data10_mux[] = {
4086         VI5_DATA0_MARK, VI5_DATA1_MARK,
4087         VI5_DATA2_MARK, VI5_DATA3_MARK,
4088         VI5_DATA4_MARK, VI5_DATA5_MARK,
4089         VI5_DATA6_MARK, VI5_DATA7_MARK,
4090         VI5_DATA8_MARK,  VI5_DATA9_MARK,
4091 };
4092 static const unsigned int vin5_data12_pins[] = {
4093         RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4094         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4095         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4096         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4097         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4098         RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4099 };
4100 static const unsigned int vin5_data12_mux[] = {
4101         VI5_DATA0_MARK, VI5_DATA1_MARK,
4102         VI5_DATA2_MARK, VI5_DATA3_MARK,
4103         VI5_DATA4_MARK, VI5_DATA5_MARK,
4104         VI5_DATA6_MARK, VI5_DATA7_MARK,
4105         VI5_DATA8_MARK,  VI5_DATA9_MARK,
4106         VI5_DATA10_MARK, VI5_DATA11_MARK,
4107 };
4108 static const unsigned int vin5_data16_pins[] = {
4109         RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4110         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4111         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4112         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4113         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4114         RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4115         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4116         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4117 };
4118 static const unsigned int vin5_data16_mux[] = {
4119         VI5_DATA0_MARK, VI5_DATA1_MARK,
4120         VI5_DATA2_MARK, VI5_DATA3_MARK,
4121         VI5_DATA4_MARK, VI5_DATA5_MARK,
4122         VI5_DATA6_MARK, VI5_DATA7_MARK,
4123         VI5_DATA8_MARK,  VI5_DATA9_MARK,
4124         VI5_DATA10_MARK, VI5_DATA11_MARK,
4125         VI5_DATA12_MARK, VI5_DATA13_MARK,
4126         VI5_DATA14_MARK, VI5_DATA15_MARK,
4127 };
4128 static const unsigned int vin5_sync_pins[] = {
4129         /* HSYNC#, VSYNC# */
4130         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4131 };
4132 static const unsigned int vin5_sync_mux[] = {
4133         VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4134 };
4135 static const unsigned int vin5_field_pins[] = {
4136         RCAR_GP_PIN(1, 11),
4137 };
4138 static const unsigned int vin5_field_mux[] = {
4139         /* FIELD */
4140         VI5_FIELD_MARK,
4141 };
4142 static const unsigned int vin5_clkenb_pins[] = {
4143         RCAR_GP_PIN(1, 20),
4144 };
4145 static const unsigned int vin5_clkenb_mux[] = {
4146         /* CLKENB */
4147         VI5_CLKENB_MARK,
4148 };
4149 static const unsigned int vin5_clk_pins[] = {
4150         RCAR_GP_PIN(1, 21),
4151 };
4152 static const unsigned int vin5_clk_mux[] = {
4153         /* CLK */
4154         VI5_CLK_MARK,
4155 };
4156
4157 static const struct sh_pfc_pin_group pinmux_groups[] = {
4158         SH_PFC_PIN_GROUP(audio_clk_a_a),
4159         SH_PFC_PIN_GROUP(audio_clk_a_b),
4160         SH_PFC_PIN_GROUP(audio_clk_a_c),
4161         SH_PFC_PIN_GROUP(audio_clk_b_a),
4162         SH_PFC_PIN_GROUP(audio_clk_b_b),
4163         SH_PFC_PIN_GROUP(audio_clk_c_a),
4164         SH_PFC_PIN_GROUP(audio_clk_c_b),
4165         SH_PFC_PIN_GROUP(audio_clkout_a),
4166         SH_PFC_PIN_GROUP(audio_clkout_b),
4167         SH_PFC_PIN_GROUP(audio_clkout_c),
4168         SH_PFC_PIN_GROUP(audio_clkout_d),
4169         SH_PFC_PIN_GROUP(audio_clkout1_a),
4170         SH_PFC_PIN_GROUP(audio_clkout1_b),
4171         SH_PFC_PIN_GROUP(audio_clkout2_a),
4172         SH_PFC_PIN_GROUP(audio_clkout2_b),
4173         SH_PFC_PIN_GROUP(audio_clkout3_a),
4174         SH_PFC_PIN_GROUP(audio_clkout3_b),
4175         SH_PFC_PIN_GROUP(avb_link),
4176         SH_PFC_PIN_GROUP(avb_magic),
4177         SH_PFC_PIN_GROUP(avb_phy_int),
4178         SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio),      /* Deprecated */
4179         SH_PFC_PIN_GROUP(avb_mdio),
4180         SH_PFC_PIN_GROUP(avb_mii),
4181         SH_PFC_PIN_GROUP(avb_avtp_pps),
4182         SH_PFC_PIN_GROUP(avb_avtp_match_a),
4183         SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4184         SH_PFC_PIN_GROUP(avb_avtp_match_b),
4185         SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4186         SH_PFC_PIN_GROUP(can0_data_a),
4187         SH_PFC_PIN_GROUP(can0_data_b),
4188         SH_PFC_PIN_GROUP(can1_data),
4189         SH_PFC_PIN_GROUP(can_clk),
4190         SH_PFC_PIN_GROUP(canfd0_data_a),
4191         SH_PFC_PIN_GROUP(canfd0_data_b),
4192         SH_PFC_PIN_GROUP(canfd1_data),
4193         SH_PFC_PIN_GROUP(drif0_ctrl_a),
4194         SH_PFC_PIN_GROUP(drif0_data0_a),
4195         SH_PFC_PIN_GROUP(drif0_data1_a),
4196         SH_PFC_PIN_GROUP(drif0_ctrl_b),
4197         SH_PFC_PIN_GROUP(drif0_data0_b),
4198         SH_PFC_PIN_GROUP(drif0_data1_b),
4199         SH_PFC_PIN_GROUP(drif0_ctrl_c),
4200         SH_PFC_PIN_GROUP(drif0_data0_c),
4201         SH_PFC_PIN_GROUP(drif0_data1_c),
4202         SH_PFC_PIN_GROUP(drif1_ctrl_a),
4203         SH_PFC_PIN_GROUP(drif1_data0_a),
4204         SH_PFC_PIN_GROUP(drif1_data1_a),
4205         SH_PFC_PIN_GROUP(drif1_ctrl_b),
4206         SH_PFC_PIN_GROUP(drif1_data0_b),
4207         SH_PFC_PIN_GROUP(drif1_data1_b),
4208         SH_PFC_PIN_GROUP(drif1_ctrl_c),
4209         SH_PFC_PIN_GROUP(drif1_data0_c),
4210         SH_PFC_PIN_GROUP(drif1_data1_c),
4211         SH_PFC_PIN_GROUP(drif2_ctrl_a),
4212         SH_PFC_PIN_GROUP(drif2_data0_a),
4213         SH_PFC_PIN_GROUP(drif2_data1_a),
4214         SH_PFC_PIN_GROUP(drif2_ctrl_b),
4215         SH_PFC_PIN_GROUP(drif2_data0_b),
4216         SH_PFC_PIN_GROUP(drif2_data1_b),
4217         SH_PFC_PIN_GROUP(drif3_ctrl_a),
4218         SH_PFC_PIN_GROUP(drif3_data0_a),
4219         SH_PFC_PIN_GROUP(drif3_data1_a),
4220         SH_PFC_PIN_GROUP(drif3_ctrl_b),
4221         SH_PFC_PIN_GROUP(drif3_data0_b),
4222         SH_PFC_PIN_GROUP(drif3_data1_b),
4223         SH_PFC_PIN_GROUP(du_rgb666),
4224         SH_PFC_PIN_GROUP(du_rgb888),
4225         SH_PFC_PIN_GROUP(du_clk_out_0),
4226         SH_PFC_PIN_GROUP(du_clk_out_1),
4227         SH_PFC_PIN_GROUP(du_sync),
4228         SH_PFC_PIN_GROUP(du_oddf),
4229         SH_PFC_PIN_GROUP(du_cde),
4230         SH_PFC_PIN_GROUP(du_disp),
4231         SH_PFC_PIN_GROUP(hdmi0_cec),
4232         SH_PFC_PIN_GROUP(hdmi1_cec),
4233         SH_PFC_PIN_GROUP(hscif0_data),
4234         SH_PFC_PIN_GROUP(hscif0_clk),
4235         SH_PFC_PIN_GROUP(hscif0_ctrl),
4236         SH_PFC_PIN_GROUP(hscif1_data_a),
4237         SH_PFC_PIN_GROUP(hscif1_clk_a),
4238         SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4239         SH_PFC_PIN_GROUP(hscif1_data_b),
4240         SH_PFC_PIN_GROUP(hscif1_clk_b),
4241         SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4242         SH_PFC_PIN_GROUP(hscif2_data_a),
4243         SH_PFC_PIN_GROUP(hscif2_clk_a),
4244         SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4245         SH_PFC_PIN_GROUP(hscif2_data_b),
4246         SH_PFC_PIN_GROUP(hscif2_clk_b),
4247         SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4248         SH_PFC_PIN_GROUP(hscif2_data_c),
4249         SH_PFC_PIN_GROUP(hscif2_clk_c),
4250         SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4251         SH_PFC_PIN_GROUP(hscif3_data_a),
4252         SH_PFC_PIN_GROUP(hscif3_clk),
4253         SH_PFC_PIN_GROUP(hscif3_ctrl),
4254         SH_PFC_PIN_GROUP(hscif3_data_b),
4255         SH_PFC_PIN_GROUP(hscif3_data_c),
4256         SH_PFC_PIN_GROUP(hscif3_data_d),
4257         SH_PFC_PIN_GROUP(hscif4_data_a),
4258         SH_PFC_PIN_GROUP(hscif4_clk),
4259         SH_PFC_PIN_GROUP(hscif4_ctrl),
4260         SH_PFC_PIN_GROUP(hscif4_data_b),
4261         SH_PFC_PIN_GROUP(i2c1_a),
4262         SH_PFC_PIN_GROUP(i2c1_b),
4263         SH_PFC_PIN_GROUP(i2c2_a),
4264         SH_PFC_PIN_GROUP(i2c2_b),
4265         SH_PFC_PIN_GROUP(i2c6_a),
4266         SH_PFC_PIN_GROUP(i2c6_b),
4267         SH_PFC_PIN_GROUP(i2c6_c),
4268         SH_PFC_PIN_GROUP(intc_ex_irq0),
4269         SH_PFC_PIN_GROUP(intc_ex_irq1),
4270         SH_PFC_PIN_GROUP(intc_ex_irq2),
4271         SH_PFC_PIN_GROUP(intc_ex_irq3),
4272         SH_PFC_PIN_GROUP(intc_ex_irq4),
4273         SH_PFC_PIN_GROUP(intc_ex_irq5),
4274         SH_PFC_PIN_GROUP(msiof0_clk),
4275         SH_PFC_PIN_GROUP(msiof0_sync),
4276         SH_PFC_PIN_GROUP(msiof0_ss1),
4277         SH_PFC_PIN_GROUP(msiof0_ss2),
4278         SH_PFC_PIN_GROUP(msiof0_txd),
4279         SH_PFC_PIN_GROUP(msiof0_rxd),
4280         SH_PFC_PIN_GROUP(msiof1_clk_a),
4281         SH_PFC_PIN_GROUP(msiof1_sync_a),
4282         SH_PFC_PIN_GROUP(msiof1_ss1_a),
4283         SH_PFC_PIN_GROUP(msiof1_ss2_a),
4284         SH_PFC_PIN_GROUP(msiof1_txd_a),
4285         SH_PFC_PIN_GROUP(msiof1_rxd_a),
4286         SH_PFC_PIN_GROUP(msiof1_clk_b),
4287         SH_PFC_PIN_GROUP(msiof1_sync_b),
4288         SH_PFC_PIN_GROUP(msiof1_ss1_b),
4289         SH_PFC_PIN_GROUP(msiof1_ss2_b),
4290         SH_PFC_PIN_GROUP(msiof1_txd_b),
4291         SH_PFC_PIN_GROUP(msiof1_rxd_b),
4292         SH_PFC_PIN_GROUP(msiof1_clk_c),
4293         SH_PFC_PIN_GROUP(msiof1_sync_c),
4294         SH_PFC_PIN_GROUP(msiof1_ss1_c),
4295         SH_PFC_PIN_GROUP(msiof1_ss2_c),
4296         SH_PFC_PIN_GROUP(msiof1_txd_c),
4297         SH_PFC_PIN_GROUP(msiof1_rxd_c),
4298         SH_PFC_PIN_GROUP(msiof1_clk_d),
4299         SH_PFC_PIN_GROUP(msiof1_sync_d),
4300         SH_PFC_PIN_GROUP(msiof1_ss1_d),
4301         SH_PFC_PIN_GROUP(msiof1_ss2_d),
4302         SH_PFC_PIN_GROUP(msiof1_txd_d),
4303         SH_PFC_PIN_GROUP(msiof1_rxd_d),
4304         SH_PFC_PIN_GROUP(msiof1_clk_e),
4305         SH_PFC_PIN_GROUP(msiof1_sync_e),
4306         SH_PFC_PIN_GROUP(msiof1_ss1_e),
4307         SH_PFC_PIN_GROUP(msiof1_ss2_e),
4308         SH_PFC_PIN_GROUP(msiof1_txd_e),
4309         SH_PFC_PIN_GROUP(msiof1_rxd_e),
4310         SH_PFC_PIN_GROUP(msiof1_clk_f),
4311         SH_PFC_PIN_GROUP(msiof1_sync_f),
4312         SH_PFC_PIN_GROUP(msiof1_ss1_f),
4313         SH_PFC_PIN_GROUP(msiof1_ss2_f),
4314         SH_PFC_PIN_GROUP(msiof1_txd_f),
4315         SH_PFC_PIN_GROUP(msiof1_rxd_f),
4316         SH_PFC_PIN_GROUP(msiof1_clk_g),
4317         SH_PFC_PIN_GROUP(msiof1_sync_g),
4318         SH_PFC_PIN_GROUP(msiof1_ss1_g),
4319         SH_PFC_PIN_GROUP(msiof1_ss2_g),
4320         SH_PFC_PIN_GROUP(msiof1_txd_g),
4321         SH_PFC_PIN_GROUP(msiof1_rxd_g),
4322         SH_PFC_PIN_GROUP(msiof2_clk_a),
4323         SH_PFC_PIN_GROUP(msiof2_sync_a),
4324         SH_PFC_PIN_GROUP(msiof2_ss1_a),
4325         SH_PFC_PIN_GROUP(msiof2_ss2_a),
4326         SH_PFC_PIN_GROUP(msiof2_txd_a),
4327         SH_PFC_PIN_GROUP(msiof2_rxd_a),
4328         SH_PFC_PIN_GROUP(msiof2_clk_b),
4329         SH_PFC_PIN_GROUP(msiof2_sync_b),
4330         SH_PFC_PIN_GROUP(msiof2_ss1_b),
4331         SH_PFC_PIN_GROUP(msiof2_ss2_b),
4332         SH_PFC_PIN_GROUP(msiof2_txd_b),
4333         SH_PFC_PIN_GROUP(msiof2_rxd_b),
4334         SH_PFC_PIN_GROUP(msiof2_clk_c),
4335         SH_PFC_PIN_GROUP(msiof2_sync_c),
4336         SH_PFC_PIN_GROUP(msiof2_ss1_c),
4337         SH_PFC_PIN_GROUP(msiof2_ss2_c),
4338         SH_PFC_PIN_GROUP(msiof2_txd_c),
4339         SH_PFC_PIN_GROUP(msiof2_rxd_c),
4340         SH_PFC_PIN_GROUP(msiof2_clk_d),
4341         SH_PFC_PIN_GROUP(msiof2_sync_d),
4342         SH_PFC_PIN_GROUP(msiof2_ss1_d),
4343         SH_PFC_PIN_GROUP(msiof2_ss2_d),
4344         SH_PFC_PIN_GROUP(msiof2_txd_d),
4345         SH_PFC_PIN_GROUP(msiof2_rxd_d),
4346         SH_PFC_PIN_GROUP(msiof3_clk_a),
4347         SH_PFC_PIN_GROUP(msiof3_sync_a),
4348         SH_PFC_PIN_GROUP(msiof3_ss1_a),
4349         SH_PFC_PIN_GROUP(msiof3_ss2_a),
4350         SH_PFC_PIN_GROUP(msiof3_txd_a),
4351         SH_PFC_PIN_GROUP(msiof3_rxd_a),
4352         SH_PFC_PIN_GROUP(msiof3_clk_b),
4353         SH_PFC_PIN_GROUP(msiof3_sync_b),
4354         SH_PFC_PIN_GROUP(msiof3_ss1_b),
4355         SH_PFC_PIN_GROUP(msiof3_ss2_b),
4356         SH_PFC_PIN_GROUP(msiof3_txd_b),
4357         SH_PFC_PIN_GROUP(msiof3_rxd_b),
4358         SH_PFC_PIN_GROUP(msiof3_clk_c),
4359         SH_PFC_PIN_GROUP(msiof3_sync_c),
4360         SH_PFC_PIN_GROUP(msiof3_txd_c),
4361         SH_PFC_PIN_GROUP(msiof3_rxd_c),
4362         SH_PFC_PIN_GROUP(msiof3_clk_d),
4363         SH_PFC_PIN_GROUP(msiof3_sync_d),
4364         SH_PFC_PIN_GROUP(msiof3_ss1_d),
4365         SH_PFC_PIN_GROUP(msiof3_txd_d),
4366         SH_PFC_PIN_GROUP(msiof3_rxd_d),
4367         SH_PFC_PIN_GROUP(msiof3_clk_e),
4368         SH_PFC_PIN_GROUP(msiof3_sync_e),
4369         SH_PFC_PIN_GROUP(msiof3_ss1_e),
4370         SH_PFC_PIN_GROUP(msiof3_ss2_e),
4371         SH_PFC_PIN_GROUP(msiof3_txd_e),
4372         SH_PFC_PIN_GROUP(msiof3_rxd_e),
4373         SH_PFC_PIN_GROUP(pwm0),
4374         SH_PFC_PIN_GROUP(pwm1_a),
4375         SH_PFC_PIN_GROUP(pwm1_b),
4376         SH_PFC_PIN_GROUP(pwm2_a),
4377         SH_PFC_PIN_GROUP(pwm2_b),
4378         SH_PFC_PIN_GROUP(pwm3_a),
4379         SH_PFC_PIN_GROUP(pwm3_b),
4380         SH_PFC_PIN_GROUP(pwm4_a),
4381         SH_PFC_PIN_GROUP(pwm4_b),
4382         SH_PFC_PIN_GROUP(pwm5_a),
4383         SH_PFC_PIN_GROUP(pwm5_b),
4384         SH_PFC_PIN_GROUP(pwm6_a),
4385         SH_PFC_PIN_GROUP(pwm6_b),
4386         SH_PFC_PIN_GROUP(sata0_devslp_a),
4387         SH_PFC_PIN_GROUP(sata0_devslp_b),
4388         SH_PFC_PIN_GROUP(scif0_data),
4389         SH_PFC_PIN_GROUP(scif0_clk),
4390         SH_PFC_PIN_GROUP(scif0_ctrl),
4391         SH_PFC_PIN_GROUP(scif1_data_a),
4392         SH_PFC_PIN_GROUP(scif1_clk),
4393         SH_PFC_PIN_GROUP(scif1_ctrl),
4394         SH_PFC_PIN_GROUP(scif1_data_b),
4395         SH_PFC_PIN_GROUP(scif2_data_a),
4396         SH_PFC_PIN_GROUP(scif2_clk),
4397         SH_PFC_PIN_GROUP(scif2_data_b),
4398         SH_PFC_PIN_GROUP(scif3_data_a),
4399         SH_PFC_PIN_GROUP(scif3_clk),
4400         SH_PFC_PIN_GROUP(scif3_ctrl),
4401         SH_PFC_PIN_GROUP(scif3_data_b),
4402         SH_PFC_PIN_GROUP(scif4_data_a),
4403         SH_PFC_PIN_GROUP(scif4_clk_a),
4404         SH_PFC_PIN_GROUP(scif4_ctrl_a),
4405         SH_PFC_PIN_GROUP(scif4_data_b),
4406         SH_PFC_PIN_GROUP(scif4_clk_b),
4407         SH_PFC_PIN_GROUP(scif4_ctrl_b),
4408         SH_PFC_PIN_GROUP(scif4_data_c),
4409         SH_PFC_PIN_GROUP(scif4_clk_c),
4410         SH_PFC_PIN_GROUP(scif4_ctrl_c),
4411         SH_PFC_PIN_GROUP(scif5_data_a),
4412         SH_PFC_PIN_GROUP(scif5_clk_a),
4413         SH_PFC_PIN_GROUP(scif5_data_b),
4414         SH_PFC_PIN_GROUP(scif5_clk_b),
4415         SH_PFC_PIN_GROUP(scif_clk_a),
4416         SH_PFC_PIN_GROUP(scif_clk_b),
4417         SH_PFC_PIN_GROUP(sdhi0_data1),
4418         SH_PFC_PIN_GROUP(sdhi0_data4),
4419         SH_PFC_PIN_GROUP(sdhi0_ctrl),
4420         SH_PFC_PIN_GROUP(sdhi0_cd),
4421         SH_PFC_PIN_GROUP(sdhi0_wp),
4422         SH_PFC_PIN_GROUP(sdhi1_data1),
4423         SH_PFC_PIN_GROUP(sdhi1_data4),
4424         SH_PFC_PIN_GROUP(sdhi1_ctrl),
4425         SH_PFC_PIN_GROUP(sdhi1_cd),
4426         SH_PFC_PIN_GROUP(sdhi1_wp),
4427         SH_PFC_PIN_GROUP(sdhi2_data1),
4428         SH_PFC_PIN_GROUP(sdhi2_data4),
4429         SH_PFC_PIN_GROUP(sdhi2_data8),
4430         SH_PFC_PIN_GROUP(sdhi2_ctrl),
4431         SH_PFC_PIN_GROUP(sdhi2_cd_a),
4432         SH_PFC_PIN_GROUP(sdhi2_wp_a),
4433         SH_PFC_PIN_GROUP(sdhi2_cd_b),
4434         SH_PFC_PIN_GROUP(sdhi2_wp_b),
4435         SH_PFC_PIN_GROUP(sdhi2_ds),
4436         SH_PFC_PIN_GROUP(sdhi3_data1),
4437         SH_PFC_PIN_GROUP(sdhi3_data4),
4438         SH_PFC_PIN_GROUP(sdhi3_data8),
4439         SH_PFC_PIN_GROUP(sdhi3_ctrl),
4440         SH_PFC_PIN_GROUP(sdhi3_cd),
4441         SH_PFC_PIN_GROUP(sdhi3_wp),
4442         SH_PFC_PIN_GROUP(sdhi3_ds),
4443         SH_PFC_PIN_GROUP(ssi0_data),
4444         SH_PFC_PIN_GROUP(ssi01239_ctrl),
4445         SH_PFC_PIN_GROUP(ssi1_data_a),
4446         SH_PFC_PIN_GROUP(ssi1_data_b),
4447         SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4448         SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4449         SH_PFC_PIN_GROUP(ssi2_data_a),
4450         SH_PFC_PIN_GROUP(ssi2_data_b),
4451         SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4452         SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4453         SH_PFC_PIN_GROUP(ssi3_data),
4454         SH_PFC_PIN_GROUP(ssi349_ctrl),
4455         SH_PFC_PIN_GROUP(ssi4_data),
4456         SH_PFC_PIN_GROUP(ssi4_ctrl),
4457         SH_PFC_PIN_GROUP(ssi5_data),
4458         SH_PFC_PIN_GROUP(ssi5_ctrl),
4459         SH_PFC_PIN_GROUP(ssi6_data),
4460         SH_PFC_PIN_GROUP(ssi6_ctrl),
4461         SH_PFC_PIN_GROUP(ssi7_data),
4462         SH_PFC_PIN_GROUP(ssi78_ctrl),
4463         SH_PFC_PIN_GROUP(ssi8_data),
4464         SH_PFC_PIN_GROUP(ssi9_data_a),
4465         SH_PFC_PIN_GROUP(ssi9_data_b),
4466         SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4467         SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4468         SH_PFC_PIN_GROUP(tmu_tclk1_a),
4469         SH_PFC_PIN_GROUP(tmu_tclk1_b),
4470         SH_PFC_PIN_GROUP(tmu_tclk2_a),
4471         SH_PFC_PIN_GROUP(tmu_tclk2_b),
4472         SH_PFC_PIN_GROUP(usb0),
4473         SH_PFC_PIN_GROUP(usb1),
4474         SH_PFC_PIN_GROUP(usb2),
4475         SH_PFC_PIN_GROUP(usb2_ch3),
4476         SH_PFC_PIN_GROUP(usb30),
4477         VIN_DATA_PIN_GROUP(vin4_data_a, 8),
4478         VIN_DATA_PIN_GROUP(vin4_data_a, 10),
4479         VIN_DATA_PIN_GROUP(vin4_data_a, 12),
4480         VIN_DATA_PIN_GROUP(vin4_data_a, 16),
4481         SH_PFC_PIN_GROUP(vin4_data18_a),
4482         VIN_DATA_PIN_GROUP(vin4_data_a, 20),
4483         VIN_DATA_PIN_GROUP(vin4_data_a, 24),
4484         VIN_DATA_PIN_GROUP(vin4_data_b, 8),
4485         VIN_DATA_PIN_GROUP(vin4_data_b, 10),
4486         VIN_DATA_PIN_GROUP(vin4_data_b, 12),
4487         VIN_DATA_PIN_GROUP(vin4_data_b, 16),
4488         SH_PFC_PIN_GROUP(vin4_data18_b),
4489         VIN_DATA_PIN_GROUP(vin4_data_b, 20),
4490         VIN_DATA_PIN_GROUP(vin4_data_b, 24),
4491         SH_PFC_PIN_GROUP(vin4_sync),
4492         SH_PFC_PIN_GROUP(vin4_field),
4493         SH_PFC_PIN_GROUP(vin4_clkenb),
4494         SH_PFC_PIN_GROUP(vin4_clk),
4495         SH_PFC_PIN_GROUP(vin5_data8),
4496         SH_PFC_PIN_GROUP(vin5_data10),
4497         SH_PFC_PIN_GROUP(vin5_data12),
4498         SH_PFC_PIN_GROUP(vin5_data16),
4499         SH_PFC_PIN_GROUP(vin5_sync),
4500         SH_PFC_PIN_GROUP(vin5_field),
4501         SH_PFC_PIN_GROUP(vin5_clkenb),
4502         SH_PFC_PIN_GROUP(vin5_clk),
4503 };
4504
4505 static const char * const audio_clk_groups[] = {
4506         "audio_clk_a_a",
4507         "audio_clk_a_b",
4508         "audio_clk_a_c",
4509         "audio_clk_b_a",
4510         "audio_clk_b_b",
4511         "audio_clk_c_a",
4512         "audio_clk_c_b",
4513         "audio_clkout_a",
4514         "audio_clkout_b",
4515         "audio_clkout_c",
4516         "audio_clkout_d",
4517         "audio_clkout1_a",
4518         "audio_clkout1_b",
4519         "audio_clkout2_a",
4520         "audio_clkout2_b",
4521         "audio_clkout3_a",
4522         "audio_clkout3_b",
4523 };
4524
4525 static const char * const avb_groups[] = {
4526         "avb_link",
4527         "avb_magic",
4528         "avb_phy_int",
4529         "avb_mdc",      /* Deprecated, please use "avb_mdio" instead */
4530         "avb_mdio",
4531         "avb_mii",
4532         "avb_avtp_pps",
4533         "avb_avtp_match_a",
4534         "avb_avtp_capture_a",
4535         "avb_avtp_match_b",
4536         "avb_avtp_capture_b",
4537 };
4538
4539 static const char * const can0_groups[] = {
4540         "can0_data_a",
4541         "can0_data_b",
4542 };
4543
4544 static const char * const can1_groups[] = {
4545         "can1_data",
4546 };
4547
4548 static const char * const can_clk_groups[] = {
4549         "can_clk",
4550 };
4551
4552 static const char * const canfd0_groups[] = {
4553         "canfd0_data_a",
4554         "canfd0_data_b",
4555 };
4556
4557 static const char * const canfd1_groups[] = {
4558         "canfd1_data",
4559 };
4560
4561 static const char * const drif0_groups[] = {
4562         "drif0_ctrl_a",
4563         "drif0_data0_a",
4564         "drif0_data1_a",
4565         "drif0_ctrl_b",
4566         "drif0_data0_b",
4567         "drif0_data1_b",
4568         "drif0_ctrl_c",
4569         "drif0_data0_c",
4570         "drif0_data1_c",
4571 };
4572
4573 static const char * const drif1_groups[] = {
4574         "drif1_ctrl_a",
4575         "drif1_data0_a",
4576         "drif1_data1_a",
4577         "drif1_ctrl_b",
4578         "drif1_data0_b",
4579         "drif1_data1_b",
4580         "drif1_ctrl_c",
4581         "drif1_data0_c",
4582         "drif1_data1_c",
4583 };
4584
4585 static const char * const drif2_groups[] = {
4586         "drif2_ctrl_a",
4587         "drif2_data0_a",
4588         "drif2_data1_a",
4589         "drif2_ctrl_b",
4590         "drif2_data0_b",
4591         "drif2_data1_b",
4592 };
4593
4594 static const char * const drif3_groups[] = {
4595         "drif3_ctrl_a",
4596         "drif3_data0_a",
4597         "drif3_data1_a",
4598         "drif3_ctrl_b",
4599         "drif3_data0_b",
4600         "drif3_data1_b",
4601 };
4602
4603 static const char * const du_groups[] = {
4604         "du_rgb666",
4605         "du_rgb888",
4606         "du_clk_out_0",
4607         "du_clk_out_1",
4608         "du_sync",
4609         "du_oddf",
4610         "du_cde",
4611         "du_disp",
4612 };
4613
4614 static const char * const hdmi0_groups[] = {
4615         "hdmi0_cec",
4616 };
4617
4618 static const char * const hdmi1_groups[] = {
4619         "hdmi1_cec",
4620 };
4621
4622 static const char * const hscif0_groups[] = {
4623         "hscif0_data",
4624         "hscif0_clk",
4625         "hscif0_ctrl",
4626 };
4627
4628 static const char * const hscif1_groups[] = {
4629         "hscif1_data_a",
4630         "hscif1_clk_a",
4631         "hscif1_ctrl_a",
4632         "hscif1_data_b",
4633         "hscif1_clk_b",
4634         "hscif1_ctrl_b",
4635 };
4636
4637 static const char * const hscif2_groups[] = {
4638         "hscif2_data_a",
4639         "hscif2_clk_a",
4640         "hscif2_ctrl_a",
4641         "hscif2_data_b",
4642         "hscif2_clk_b",
4643         "hscif2_ctrl_b",
4644         "hscif2_data_c",
4645         "hscif2_clk_c",
4646         "hscif2_ctrl_c",
4647 };
4648
4649 static const char * const hscif3_groups[] = {
4650         "hscif3_data_a",
4651         "hscif3_clk",
4652         "hscif3_ctrl",
4653         "hscif3_data_b",
4654         "hscif3_data_c",
4655         "hscif3_data_d",
4656 };
4657
4658 static const char * const hscif4_groups[] = {
4659         "hscif4_data_a",
4660         "hscif4_clk",
4661         "hscif4_ctrl",
4662         "hscif4_data_b",
4663 };
4664
4665 static const char * const i2c1_groups[] = {
4666         "i2c1_a",
4667         "i2c1_b",
4668 };
4669
4670 static const char * const i2c2_groups[] = {
4671         "i2c2_a",
4672         "i2c2_b",
4673 };
4674
4675 static const char * const i2c6_groups[] = {
4676         "i2c6_a",
4677         "i2c6_b",
4678         "i2c6_c",
4679 };
4680
4681 static const char * const intc_ex_groups[] = {
4682         "intc_ex_irq0",
4683         "intc_ex_irq1",
4684         "intc_ex_irq2",
4685         "intc_ex_irq3",
4686         "intc_ex_irq4",
4687         "intc_ex_irq5",
4688 };
4689
4690 static const char * const msiof0_groups[] = {
4691         "msiof0_clk",
4692         "msiof0_sync",
4693         "msiof0_ss1",
4694         "msiof0_ss2",
4695         "msiof0_txd",
4696         "msiof0_rxd",
4697 };
4698
4699 static const char * const msiof1_groups[] = {
4700         "msiof1_clk_a",
4701         "msiof1_sync_a",
4702         "msiof1_ss1_a",
4703         "msiof1_ss2_a",
4704         "msiof1_txd_a",
4705         "msiof1_rxd_a",
4706         "msiof1_clk_b",
4707         "msiof1_sync_b",
4708         "msiof1_ss1_b",
4709         "msiof1_ss2_b",
4710         "msiof1_txd_b",
4711         "msiof1_rxd_b",
4712         "msiof1_clk_c",
4713         "msiof1_sync_c",
4714         "msiof1_ss1_c",
4715         "msiof1_ss2_c",
4716         "msiof1_txd_c",
4717         "msiof1_rxd_c",
4718         "msiof1_clk_d",
4719         "msiof1_sync_d",
4720         "msiof1_ss1_d",
4721         "msiof1_ss2_d",
4722         "msiof1_txd_d",
4723         "msiof1_rxd_d",
4724         "msiof1_clk_e",
4725         "msiof1_sync_e",
4726         "msiof1_ss1_e",
4727         "msiof1_ss2_e",
4728         "msiof1_txd_e",
4729         "msiof1_rxd_e",
4730         "msiof1_clk_f",
4731         "msiof1_sync_f",
4732         "msiof1_ss1_f",
4733         "msiof1_ss2_f",
4734         "msiof1_txd_f",
4735         "msiof1_rxd_f",
4736         "msiof1_clk_g",
4737         "msiof1_sync_g",
4738         "msiof1_ss1_g",
4739         "msiof1_ss2_g",
4740         "msiof1_txd_g",
4741         "msiof1_rxd_g",
4742 };
4743
4744 static const char * const msiof2_groups[] = {
4745         "msiof2_clk_a",
4746         "msiof2_sync_a",
4747         "msiof2_ss1_a",
4748         "msiof2_ss2_a",
4749         "msiof2_txd_a",
4750         "msiof2_rxd_a",
4751         "msiof2_clk_b",
4752         "msiof2_sync_b",
4753         "msiof2_ss1_b",
4754         "msiof2_ss2_b",
4755         "msiof2_txd_b",
4756         "msiof2_rxd_b",
4757         "msiof2_clk_c",
4758         "msiof2_sync_c",
4759         "msiof2_ss1_c",
4760         "msiof2_ss2_c",
4761         "msiof2_txd_c",
4762         "msiof2_rxd_c",
4763         "msiof2_clk_d",
4764         "msiof2_sync_d",
4765         "msiof2_ss1_d",
4766         "msiof2_ss2_d",
4767         "msiof2_txd_d",
4768         "msiof2_rxd_d",
4769 };
4770
4771 static const char * const msiof3_groups[] = {
4772         "msiof3_clk_a",
4773         "msiof3_sync_a",
4774         "msiof3_ss1_a",
4775         "msiof3_ss2_a",
4776         "msiof3_txd_a",
4777         "msiof3_rxd_a",
4778         "msiof3_clk_b",
4779         "msiof3_sync_b",
4780         "msiof3_ss1_b",
4781         "msiof3_ss2_b",
4782         "msiof3_txd_b",
4783         "msiof3_rxd_b",
4784         "msiof3_clk_c",
4785         "msiof3_sync_c",
4786         "msiof3_txd_c",
4787         "msiof3_rxd_c",
4788         "msiof3_clk_d",
4789         "msiof3_sync_d",
4790         "msiof3_ss1_d",
4791         "msiof3_txd_d",
4792         "msiof3_rxd_d",
4793         "msiof3_clk_e",
4794         "msiof3_sync_e",
4795         "msiof3_ss1_e",
4796         "msiof3_ss2_e",
4797         "msiof3_txd_e",
4798         "msiof3_rxd_e",
4799 };
4800
4801 static const char * const pwm0_groups[] = {
4802         "pwm0",
4803 };
4804
4805 static const char * const pwm1_groups[] = {
4806         "pwm1_a",
4807         "pwm1_b",
4808 };
4809
4810 static const char * const pwm2_groups[] = {
4811         "pwm2_a",
4812         "pwm2_b",
4813 };
4814
4815 static const char * const pwm3_groups[] = {
4816         "pwm3_a",
4817         "pwm3_b",
4818 };
4819
4820 static const char * const pwm4_groups[] = {
4821         "pwm4_a",
4822         "pwm4_b",
4823 };
4824
4825 static const char * const pwm5_groups[] = {
4826         "pwm5_a",
4827         "pwm5_b",
4828 };
4829
4830 static const char * const pwm6_groups[] = {
4831         "pwm6_a",
4832         "pwm6_b",
4833 };
4834
4835 static const char * const sata0_groups[] = {
4836         "sata0_devslp_a",
4837         "sata0_devslp_b",
4838 };
4839
4840 static const char * const scif0_groups[] = {
4841         "scif0_data",
4842         "scif0_clk",
4843         "scif0_ctrl",
4844 };
4845
4846 static const char * const scif1_groups[] = {
4847         "scif1_data_a",
4848         "scif1_clk",
4849         "scif1_ctrl",
4850         "scif1_data_b",
4851 };
4852
4853 static const char * const scif2_groups[] = {
4854         "scif2_data_a",
4855         "scif2_clk",
4856         "scif2_data_b",
4857 };
4858
4859 static const char * const scif3_groups[] = {
4860         "scif3_data_a",
4861         "scif3_clk",
4862         "scif3_ctrl",
4863         "scif3_data_b",
4864 };
4865
4866 static const char * const scif4_groups[] = {
4867         "scif4_data_a",
4868         "scif4_clk_a",
4869         "scif4_ctrl_a",
4870         "scif4_data_b",
4871         "scif4_clk_b",
4872         "scif4_ctrl_b",
4873         "scif4_data_c",
4874         "scif4_clk_c",
4875         "scif4_ctrl_c",
4876 };
4877
4878 static const char * const scif5_groups[] = {
4879         "scif5_data_a",
4880         "scif5_clk_a",
4881         "scif5_data_b",
4882         "scif5_clk_b",
4883 };
4884
4885 static const char * const scif_clk_groups[] = {
4886         "scif_clk_a",
4887         "scif_clk_b",
4888 };
4889
4890 static const char * const sdhi0_groups[] = {
4891         "sdhi0_data1",
4892         "sdhi0_data4",
4893         "sdhi0_ctrl",
4894         "sdhi0_cd",
4895         "sdhi0_wp",
4896 };
4897
4898 static const char * const sdhi1_groups[] = {
4899         "sdhi1_data1",
4900         "sdhi1_data4",
4901         "sdhi1_ctrl",
4902         "sdhi1_cd",
4903         "sdhi1_wp",
4904 };
4905
4906 static const char * const sdhi2_groups[] = {
4907         "sdhi2_data1",
4908         "sdhi2_data4",
4909         "sdhi2_data8",
4910         "sdhi2_ctrl",
4911         "sdhi2_cd_a",
4912         "sdhi2_wp_a",
4913         "sdhi2_cd_b",
4914         "sdhi2_wp_b",
4915         "sdhi2_ds",
4916 };
4917
4918 static const char * const sdhi3_groups[] = {
4919         "sdhi3_data1",
4920         "sdhi3_data4",
4921         "sdhi3_data8",
4922         "sdhi3_ctrl",
4923         "sdhi3_cd",
4924         "sdhi3_wp",
4925         "sdhi3_ds",
4926 };
4927
4928 static const char * const ssi_groups[] = {
4929         "ssi0_data",
4930         "ssi01239_ctrl",
4931         "ssi1_data_a",
4932         "ssi1_data_b",
4933         "ssi1_ctrl_a",
4934         "ssi1_ctrl_b",
4935         "ssi2_data_a",
4936         "ssi2_data_b",
4937         "ssi2_ctrl_a",
4938         "ssi2_ctrl_b",
4939         "ssi3_data",
4940         "ssi349_ctrl",
4941         "ssi4_data",
4942         "ssi4_ctrl",
4943         "ssi5_data",
4944         "ssi5_ctrl",
4945         "ssi6_data",
4946         "ssi6_ctrl",
4947         "ssi7_data",
4948         "ssi78_ctrl",
4949         "ssi8_data",
4950         "ssi9_data_a",
4951         "ssi9_data_b",
4952         "ssi9_ctrl_a",
4953         "ssi9_ctrl_b",
4954 };
4955
4956 static const char * const tmu_groups[] = {
4957         "tmu_tclk1_a",
4958         "tmu_tclk1_b",
4959         "tmu_tclk2_a",
4960         "tmu_tclk2_b",
4961 };
4962
4963 static const char * const usb0_groups[] = {
4964         "usb0",
4965 };
4966
4967 static const char * const usb1_groups[] = {
4968         "usb1",
4969 };
4970
4971 static const char * const usb2_groups[] = {
4972         "usb2",
4973 };
4974
4975 static const char * const usb2_ch3_groups[] = {
4976         "usb2_ch3",
4977 };
4978
4979 static const char * const usb30_groups[] = {
4980         "usb30",
4981 };
4982
4983 static const char * const vin4_groups[] = {
4984         "vin4_data8_a",
4985         "vin4_data10_a",
4986         "vin4_data12_a",
4987         "vin4_data16_a",
4988         "vin4_data18_a",
4989         "vin4_data20_a",
4990         "vin4_data24_a",
4991         "vin4_data8_b",
4992         "vin4_data10_b",
4993         "vin4_data12_b",
4994         "vin4_data16_b",
4995         "vin4_data18_b",
4996         "vin4_data20_b",
4997         "vin4_data24_b",
4998         "vin4_sync",
4999         "vin4_field",
5000         "vin4_clkenb",
5001         "vin4_clk",
5002 };
5003
5004 static const char * const vin5_groups[] = {
5005         "vin5_data8",
5006         "vin5_data10",
5007         "vin5_data12",
5008         "vin5_data16",
5009         "vin5_sync",
5010         "vin5_field",
5011         "vin5_clkenb",
5012         "vin5_clk",
5013 };
5014
5015 static const struct sh_pfc_function pinmux_functions[] = {
5016         SH_PFC_FUNCTION(audio_clk),
5017         SH_PFC_FUNCTION(avb),
5018         SH_PFC_FUNCTION(can0),
5019         SH_PFC_FUNCTION(can1),
5020         SH_PFC_FUNCTION(can_clk),
5021         SH_PFC_FUNCTION(canfd0),
5022         SH_PFC_FUNCTION(canfd1),
5023         SH_PFC_FUNCTION(drif0),
5024         SH_PFC_FUNCTION(drif1),
5025         SH_PFC_FUNCTION(drif2),
5026         SH_PFC_FUNCTION(drif3),
5027         SH_PFC_FUNCTION(du),
5028         SH_PFC_FUNCTION(hdmi0),
5029         SH_PFC_FUNCTION(hdmi1),
5030         SH_PFC_FUNCTION(hscif0),
5031         SH_PFC_FUNCTION(hscif1),
5032         SH_PFC_FUNCTION(hscif2),
5033         SH_PFC_FUNCTION(hscif3),
5034         SH_PFC_FUNCTION(hscif4),
5035         SH_PFC_FUNCTION(i2c1),
5036         SH_PFC_FUNCTION(i2c2),
5037         SH_PFC_FUNCTION(i2c6),
5038         SH_PFC_FUNCTION(intc_ex),
5039         SH_PFC_FUNCTION(msiof0),
5040         SH_PFC_FUNCTION(msiof1),
5041         SH_PFC_FUNCTION(msiof2),
5042         SH_PFC_FUNCTION(msiof3),
5043         SH_PFC_FUNCTION(pwm0),
5044         SH_PFC_FUNCTION(pwm1),
5045         SH_PFC_FUNCTION(pwm2),
5046         SH_PFC_FUNCTION(pwm3),
5047         SH_PFC_FUNCTION(pwm4),
5048         SH_PFC_FUNCTION(pwm5),
5049         SH_PFC_FUNCTION(pwm6),
5050         SH_PFC_FUNCTION(sata0),
5051         SH_PFC_FUNCTION(scif0),
5052         SH_PFC_FUNCTION(scif1),
5053         SH_PFC_FUNCTION(scif2),
5054         SH_PFC_FUNCTION(scif3),
5055         SH_PFC_FUNCTION(scif4),
5056         SH_PFC_FUNCTION(scif5),
5057         SH_PFC_FUNCTION(scif_clk),
5058         SH_PFC_FUNCTION(sdhi0),
5059         SH_PFC_FUNCTION(sdhi1),
5060         SH_PFC_FUNCTION(sdhi2),
5061         SH_PFC_FUNCTION(sdhi3),
5062         SH_PFC_FUNCTION(ssi),
5063         SH_PFC_FUNCTION(tmu),
5064         SH_PFC_FUNCTION(usb0),
5065         SH_PFC_FUNCTION(usb1),
5066         SH_PFC_FUNCTION(usb2),
5067         SH_PFC_FUNCTION(usb2_ch3),
5068         SH_PFC_FUNCTION(usb30),
5069         SH_PFC_FUNCTION(vin4),
5070         SH_PFC_FUNCTION(vin5),
5071 };
5072
5073 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5074 #define F_(x, y)        FN_##y
5075 #define FM(x)           FN_##x
5076         { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
5077                 0, 0,
5078                 0, 0,
5079                 0, 0,
5080                 0, 0,
5081                 0, 0,
5082                 0, 0,
5083                 0, 0,
5084                 0, 0,
5085                 0, 0,
5086                 0, 0,
5087                 0, 0,
5088                 0, 0,
5089                 0, 0,
5090                 0, 0,
5091                 0, 0,
5092                 0, 0,
5093                 GP_0_15_FN,     GPSR0_15,
5094                 GP_0_14_FN,     GPSR0_14,
5095                 GP_0_13_FN,     GPSR0_13,
5096                 GP_0_12_FN,     GPSR0_12,
5097                 GP_0_11_FN,     GPSR0_11,
5098                 GP_0_10_FN,     GPSR0_10,
5099                 GP_0_9_FN,      GPSR0_9,
5100                 GP_0_8_FN,      GPSR0_8,
5101                 GP_0_7_FN,      GPSR0_7,
5102                 GP_0_6_FN,      GPSR0_6,
5103                 GP_0_5_FN,      GPSR0_5,
5104                 GP_0_4_FN,      GPSR0_4,
5105                 GP_0_3_FN,      GPSR0_3,
5106                 GP_0_2_FN,      GPSR0_2,
5107                 GP_0_1_FN,      GPSR0_1,
5108                 GP_0_0_FN,      GPSR0_0, }
5109         },
5110         { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
5111                 0, 0,
5112                 0, 0,
5113                 0, 0,
5114                 GP_1_28_FN,     GPSR1_28,
5115                 GP_1_27_FN,     GPSR1_27,
5116                 GP_1_26_FN,     GPSR1_26,
5117                 GP_1_25_FN,     GPSR1_25,
5118                 GP_1_24_FN,     GPSR1_24,
5119                 GP_1_23_FN,     GPSR1_23,
5120                 GP_1_22_FN,     GPSR1_22,
5121                 GP_1_21_FN,     GPSR1_21,
5122                 GP_1_20_FN,     GPSR1_20,
5123                 GP_1_19_FN,     GPSR1_19,
5124                 GP_1_18_FN,     GPSR1_18,
5125                 GP_1_17_FN,     GPSR1_17,
5126                 GP_1_16_FN,     GPSR1_16,
5127                 GP_1_15_FN,     GPSR1_15,
5128                 GP_1_14_FN,     GPSR1_14,
5129                 GP_1_13_FN,     GPSR1_13,
5130                 GP_1_12_FN,     GPSR1_12,
5131                 GP_1_11_FN,     GPSR1_11,
5132                 GP_1_10_FN,     GPSR1_10,
5133                 GP_1_9_FN,      GPSR1_9,
5134                 GP_1_8_FN,      GPSR1_8,
5135                 GP_1_7_FN,      GPSR1_7,
5136                 GP_1_6_FN,      GPSR1_6,
5137                 GP_1_5_FN,      GPSR1_5,
5138                 GP_1_4_FN,      GPSR1_4,
5139                 GP_1_3_FN,      GPSR1_3,
5140                 GP_1_2_FN,      GPSR1_2,
5141                 GP_1_1_FN,      GPSR1_1,
5142                 GP_1_0_FN,      GPSR1_0, }
5143         },
5144         { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
5145                 0, 0,
5146                 0, 0,
5147                 0, 0,
5148                 0, 0,
5149                 0, 0,
5150                 0, 0,
5151                 0, 0,
5152                 0, 0,
5153                 0, 0,
5154                 0, 0,
5155                 0, 0,
5156                 0, 0,
5157                 0, 0,
5158                 0, 0,
5159                 0, 0,
5160                 0, 0,
5161                 0, 0,
5162                 GP_2_14_FN,     GPSR2_14,
5163                 GP_2_13_FN,     GPSR2_13,
5164                 GP_2_12_FN,     GPSR2_12,
5165                 GP_2_11_FN,     GPSR2_11,
5166                 GP_2_10_FN,     GPSR2_10,
5167                 GP_2_9_FN,      GPSR2_9,
5168                 GP_2_8_FN,      GPSR2_8,
5169                 GP_2_7_FN,      GPSR2_7,
5170                 GP_2_6_FN,      GPSR2_6,
5171                 GP_2_5_FN,      GPSR2_5,
5172                 GP_2_4_FN,      GPSR2_4,
5173                 GP_2_3_FN,      GPSR2_3,
5174                 GP_2_2_FN,      GPSR2_2,
5175                 GP_2_1_FN,      GPSR2_1,
5176                 GP_2_0_FN,      GPSR2_0, }
5177         },
5178         { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
5179                 0, 0,
5180                 0, 0,
5181                 0, 0,
5182                 0, 0,
5183                 0, 0,
5184                 0, 0,
5185                 0, 0,
5186                 0, 0,
5187                 0, 0,
5188                 0, 0,
5189                 0, 0,
5190                 0, 0,
5191                 0, 0,
5192                 0, 0,
5193                 0, 0,
5194                 0, 0,
5195                 GP_3_15_FN,     GPSR3_15,
5196                 GP_3_14_FN,     GPSR3_14,
5197                 GP_3_13_FN,     GPSR3_13,
5198                 GP_3_12_FN,     GPSR3_12,
5199                 GP_3_11_FN,     GPSR3_11,
5200                 GP_3_10_FN,     GPSR3_10,
5201                 GP_3_9_FN,      GPSR3_9,
5202                 GP_3_8_FN,      GPSR3_8,
5203                 GP_3_7_FN,      GPSR3_7,
5204                 GP_3_6_FN,      GPSR3_6,
5205                 GP_3_5_FN,      GPSR3_5,
5206                 GP_3_4_FN,      GPSR3_4,
5207                 GP_3_3_FN,      GPSR3_3,
5208                 GP_3_2_FN,      GPSR3_2,
5209                 GP_3_1_FN,      GPSR3_1,
5210                 GP_3_0_FN,      GPSR3_0, }
5211         },
5212         { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
5213                 0, 0,
5214                 0, 0,
5215                 0, 0,
5216                 0, 0,
5217                 0, 0,
5218                 0, 0,
5219                 0, 0,
5220                 0, 0,
5221                 0, 0,
5222                 0, 0,
5223                 0, 0,
5224                 0, 0,
5225                 0, 0,
5226                 0, 0,
5227                 GP_4_17_FN,     GPSR4_17,
5228                 GP_4_16_FN,     GPSR4_16,
5229                 GP_4_15_FN,     GPSR4_15,
5230                 GP_4_14_FN,     GPSR4_14,
5231                 GP_4_13_FN,     GPSR4_13,
5232                 GP_4_12_FN,     GPSR4_12,
5233                 GP_4_11_FN,     GPSR4_11,
5234                 GP_4_10_FN,     GPSR4_10,
5235                 GP_4_9_FN,      GPSR4_9,
5236                 GP_4_8_FN,      GPSR4_8,
5237                 GP_4_7_FN,      GPSR4_7,
5238                 GP_4_6_FN,      GPSR4_6,
5239                 GP_4_5_FN,      GPSR4_5,
5240                 GP_4_4_FN,      GPSR4_4,
5241                 GP_4_3_FN,      GPSR4_3,
5242                 GP_4_2_FN,      GPSR4_2,
5243                 GP_4_1_FN,      GPSR4_1,
5244                 GP_4_0_FN,      GPSR4_0, }
5245         },
5246         { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
5247                 0, 0,
5248                 0, 0,
5249                 0, 0,
5250                 0, 0,
5251                 0, 0,
5252                 0, 0,
5253                 GP_5_25_FN,     GPSR5_25,
5254                 GP_5_24_FN,     GPSR5_24,
5255                 GP_5_23_FN,     GPSR5_23,
5256                 GP_5_22_FN,     GPSR5_22,
5257                 GP_5_21_FN,     GPSR5_21,
5258                 GP_5_20_FN,     GPSR5_20,
5259                 GP_5_19_FN,     GPSR5_19,
5260                 GP_5_18_FN,     GPSR5_18,
5261                 GP_5_17_FN,     GPSR5_17,
5262                 GP_5_16_FN,     GPSR5_16,
5263                 GP_5_15_FN,     GPSR5_15,
5264                 GP_5_14_FN,     GPSR5_14,
5265                 GP_5_13_FN,     GPSR5_13,
5266                 GP_5_12_FN,     GPSR5_12,
5267                 GP_5_11_FN,     GPSR5_11,
5268                 GP_5_10_FN,     GPSR5_10,
5269                 GP_5_9_FN,      GPSR5_9,
5270                 GP_5_8_FN,      GPSR5_8,
5271                 GP_5_7_FN,      GPSR5_7,
5272                 GP_5_6_FN,      GPSR5_6,
5273                 GP_5_5_FN,      GPSR5_5,
5274                 GP_5_4_FN,      GPSR5_4,
5275                 GP_5_3_FN,      GPSR5_3,
5276                 GP_5_2_FN,      GPSR5_2,
5277                 GP_5_1_FN,      GPSR5_1,
5278                 GP_5_0_FN,      GPSR5_0, }
5279         },
5280         { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
5281                 GP_6_31_FN,     GPSR6_31,
5282                 GP_6_30_FN,     GPSR6_30,
5283                 GP_6_29_FN,     GPSR6_29,
5284                 GP_6_28_FN,     GPSR6_28,
5285                 GP_6_27_FN,     GPSR6_27,
5286                 GP_6_26_FN,     GPSR6_26,
5287                 GP_6_25_FN,     GPSR6_25,
5288                 GP_6_24_FN,     GPSR6_24,
5289                 GP_6_23_FN,     GPSR6_23,
5290                 GP_6_22_FN,     GPSR6_22,
5291                 GP_6_21_FN,     GPSR6_21,
5292                 GP_6_20_FN,     GPSR6_20,
5293                 GP_6_19_FN,     GPSR6_19,
5294                 GP_6_18_FN,     GPSR6_18,
5295                 GP_6_17_FN,     GPSR6_17,
5296                 GP_6_16_FN,     GPSR6_16,
5297                 GP_6_15_FN,     GPSR6_15,
5298                 GP_6_14_FN,     GPSR6_14,
5299                 GP_6_13_FN,     GPSR6_13,
5300                 GP_6_12_FN,     GPSR6_12,
5301                 GP_6_11_FN,     GPSR6_11,
5302                 GP_6_10_FN,     GPSR6_10,
5303                 GP_6_9_FN,      GPSR6_9,
5304                 GP_6_8_FN,      GPSR6_8,
5305                 GP_6_7_FN,      GPSR6_7,
5306                 GP_6_6_FN,      GPSR6_6,
5307                 GP_6_5_FN,      GPSR6_5,
5308                 GP_6_4_FN,      GPSR6_4,
5309                 GP_6_3_FN,      GPSR6_3,
5310                 GP_6_2_FN,      GPSR6_2,
5311                 GP_6_1_FN,      GPSR6_1,
5312                 GP_6_0_FN,      GPSR6_0, }
5313         },
5314         { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
5315                 0, 0,
5316                 0, 0,
5317                 0, 0,
5318                 0, 0,
5319                 0, 0,
5320                 0, 0,
5321                 0, 0,
5322                 0, 0,
5323                 0, 0,
5324                 0, 0,
5325                 0, 0,
5326                 0, 0,
5327                 0, 0,
5328                 0, 0,
5329                 0, 0,
5330                 0, 0,
5331                 0, 0,
5332                 0, 0,
5333                 0, 0,
5334                 0, 0,
5335                 0, 0,
5336                 0, 0,
5337                 0, 0,
5338                 0, 0,
5339                 0, 0,
5340                 0, 0,
5341                 0, 0,
5342                 0, 0,
5343                 GP_7_3_FN, GPSR7_3,
5344                 GP_7_2_FN, GPSR7_2,
5345                 GP_7_1_FN, GPSR7_1,
5346                 GP_7_0_FN, GPSR7_0, }
5347         },
5348 #undef F_
5349 #undef FM
5350
5351 #define F_(x, y)        x,
5352 #define FM(x)           FN_##x,
5353         { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
5354                 IP0_31_28
5355                 IP0_27_24
5356                 IP0_23_20
5357                 IP0_19_16
5358                 IP0_15_12
5359                 IP0_11_8
5360                 IP0_7_4
5361                 IP0_3_0 }
5362         },
5363         { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
5364                 IP1_31_28
5365                 IP1_27_24
5366                 IP1_23_20
5367                 IP1_19_16
5368                 IP1_15_12
5369                 IP1_11_8
5370                 IP1_7_4
5371                 IP1_3_0 }
5372         },
5373         { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
5374                 IP2_31_28
5375                 IP2_27_24
5376                 IP2_23_20
5377                 IP2_19_16
5378                 IP2_15_12
5379                 IP2_11_8
5380                 IP2_7_4
5381                 IP2_3_0 }
5382         },
5383         { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
5384                 IP3_31_28
5385                 IP3_27_24
5386                 IP3_23_20
5387                 IP3_19_16
5388                 IP3_15_12
5389                 IP3_11_8
5390                 IP3_7_4
5391                 IP3_3_0 }
5392         },
5393         { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
5394                 IP4_31_28
5395                 IP4_27_24
5396                 IP4_23_20
5397                 IP4_19_16
5398                 IP4_15_12
5399                 IP4_11_8
5400                 IP4_7_4
5401                 IP4_3_0 }
5402         },
5403         { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
5404                 IP5_31_28
5405                 IP5_27_24
5406                 IP5_23_20
5407                 IP5_19_16
5408                 IP5_15_12
5409                 IP5_11_8
5410                 IP5_7_4
5411                 IP5_3_0 }
5412         },
5413         { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
5414                 IP6_31_28
5415                 IP6_27_24
5416                 IP6_23_20
5417                 IP6_19_16
5418                 IP6_15_12
5419                 IP6_11_8
5420                 IP6_7_4
5421                 IP6_3_0 }
5422         },
5423         { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
5424                 IP7_31_28
5425                 IP7_27_24
5426                 IP7_23_20
5427                 IP7_19_16
5428                 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5429                 IP7_11_8
5430                 IP7_7_4
5431                 IP7_3_0 }
5432         },
5433         { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
5434                 IP8_31_28
5435                 IP8_27_24
5436                 IP8_23_20
5437                 IP8_19_16
5438                 IP8_15_12
5439                 IP8_11_8
5440                 IP8_7_4
5441                 IP8_3_0 }
5442         },
5443         { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
5444                 IP9_31_28
5445                 IP9_27_24
5446                 IP9_23_20
5447                 IP9_19_16
5448                 IP9_15_12
5449                 IP9_11_8
5450                 IP9_7_4
5451                 IP9_3_0 }
5452         },
5453         { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
5454                 IP10_31_28
5455                 IP10_27_24
5456                 IP10_23_20
5457                 IP10_19_16
5458                 IP10_15_12
5459                 IP10_11_8
5460                 IP10_7_4
5461                 IP10_3_0 }
5462         },
5463         { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
5464                 IP11_31_28
5465                 IP11_27_24
5466                 IP11_23_20
5467                 IP11_19_16
5468                 IP11_15_12
5469                 IP11_11_8
5470                 IP11_7_4
5471                 IP11_3_0 }
5472         },
5473         { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
5474                 IP12_31_28
5475                 IP12_27_24
5476                 IP12_23_20
5477                 IP12_19_16
5478                 IP12_15_12
5479                 IP12_11_8
5480                 IP12_7_4
5481                 IP12_3_0 }
5482         },
5483         { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
5484                 IP13_31_28
5485                 IP13_27_24
5486                 IP13_23_20
5487                 IP13_19_16
5488                 IP13_15_12
5489                 IP13_11_8
5490                 IP13_7_4
5491                 IP13_3_0 }
5492         },
5493         { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5494                 IP14_31_28
5495                 IP14_27_24
5496                 IP14_23_20
5497                 IP14_19_16
5498                 IP14_15_12
5499                 IP14_11_8
5500                 IP14_7_4
5501                 IP14_3_0 }
5502         },
5503         { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5504                 IP15_31_28
5505                 IP15_27_24
5506                 IP15_23_20
5507                 IP15_19_16
5508                 IP15_15_12
5509                 IP15_11_8
5510                 IP15_7_4
5511                 IP15_3_0 }
5512         },
5513         { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
5514                 IP16_31_28
5515                 IP16_27_24
5516                 IP16_23_20
5517                 IP16_19_16
5518                 IP16_15_12
5519                 IP16_11_8
5520                 IP16_7_4
5521                 IP16_3_0 }
5522         },
5523         { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
5524                 IP17_31_28
5525                 IP17_27_24
5526                 IP17_23_20
5527                 IP17_19_16
5528                 IP17_15_12
5529                 IP17_11_8
5530                 IP17_7_4
5531                 IP17_3_0 }
5532         },
5533         { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
5534                 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5535                 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5536                 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5537                 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5538                 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5539                 /* IP18_11_8  */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5540                 IP18_7_4
5541                 IP18_3_0 }
5542         },
5543 #undef F_
5544 #undef FM
5545
5546 #define F_(x, y)        x,
5547 #define FM(x)           FN_##x,
5548         { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5549                              3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
5550                              1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
5551                 MOD_SEL0_31_30_29
5552                 MOD_SEL0_28_27
5553                 MOD_SEL0_26_25_24
5554                 MOD_SEL0_23
5555                 MOD_SEL0_22
5556                 MOD_SEL0_21
5557                 MOD_SEL0_20
5558                 MOD_SEL0_19
5559                 MOD_SEL0_18_17
5560                 MOD_SEL0_16
5561                 0, 0, /* RESERVED 15 */
5562                 MOD_SEL0_14_13
5563                 MOD_SEL0_12
5564                 MOD_SEL0_11
5565                 MOD_SEL0_10
5566                 MOD_SEL0_9_8
5567                 MOD_SEL0_7_6
5568                 MOD_SEL0_5
5569                 MOD_SEL0_4_3
5570                 /* RESERVED 2, 1, 0 */
5571                 0, 0, 0, 0, 0, 0, 0, 0 }
5572         },
5573         { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5574                              2, 3, 1, 2, 3, 1, 1, 2, 1,
5575                              2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
5576                 MOD_SEL1_31_30
5577                 MOD_SEL1_29_28_27
5578                 MOD_SEL1_26
5579                 MOD_SEL1_25_24
5580                 MOD_SEL1_23_22_21
5581                 MOD_SEL1_20
5582                 MOD_SEL1_19
5583                 MOD_SEL1_18_17
5584                 MOD_SEL1_16
5585                 MOD_SEL1_15_14
5586                 MOD_SEL1_13
5587                 MOD_SEL1_12
5588                 MOD_SEL1_11
5589                 MOD_SEL1_10
5590                 MOD_SEL1_9
5591                 0, 0, 0, 0, /* RESERVED 8, 7 */
5592                 MOD_SEL1_6
5593                 MOD_SEL1_5
5594                 MOD_SEL1_4
5595                 MOD_SEL1_3
5596                 MOD_SEL1_2
5597                 MOD_SEL1_1
5598                 MOD_SEL1_0 }
5599         },
5600         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5601                              1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
5602                              4, 4, 4, 3, 1) {
5603                 MOD_SEL2_31
5604                 MOD_SEL2_30
5605                 MOD_SEL2_29
5606                 MOD_SEL2_28_27
5607                 MOD_SEL2_26
5608                 MOD_SEL2_25_24_23
5609                 /* RESERVED 22 */
5610                 0, 0,
5611                 MOD_SEL2_21
5612                 MOD_SEL2_20
5613                 MOD_SEL2_19
5614                 MOD_SEL2_18
5615                 MOD_SEL2_17
5616                 /* RESERVED 16 */
5617                 0, 0,
5618                 /* RESERVED 15, 14, 13, 12 */
5619                 0, 0, 0, 0, 0, 0, 0, 0,
5620                 0, 0, 0, 0, 0, 0, 0, 0,
5621                 /* RESERVED 11, 10, 9, 8 */
5622                 0, 0, 0, 0, 0, 0, 0, 0,
5623                 0, 0, 0, 0, 0, 0, 0, 0,
5624                 /* RESERVED 7, 6, 5, 4 */
5625                 0, 0, 0, 0, 0, 0, 0, 0,
5626                 0, 0, 0, 0, 0, 0, 0, 0,
5627                 /* RESERVED 3, 2, 1 */
5628                 0, 0, 0, 0, 0, 0, 0, 0,
5629                 MOD_SEL2_0 }
5630         },
5631         { },
5632 };
5633
5634 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5635         { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5636                 { PIN_NUMBER('W', 3),   28, 2 },        /* QSPI0_SPCLK */
5637                 { PIN_A_NUMBER('C', 5), 24, 2 },        /* QSPI0_MOSI_IO0 */
5638                 { PIN_A_NUMBER('B', 4), 20, 2 },        /* QSPI0_MISO_IO1 */
5639                 { PIN_NUMBER('Y', 6),   16, 2 },        /* QSPI0_IO2 */
5640                 { PIN_A_NUMBER('B', 6), 12, 2 },        /* QSPI0_IO3 */
5641                 { PIN_NUMBER('Y', 3),    8, 2 },        /* QSPI0_SSL */
5642                 { PIN_NUMBER('V', 3),    4, 2 },        /* QSPI1_SPCLK */
5643                 { PIN_A_NUMBER('C', 7),  0, 2 },        /* QSPI1_MOSI_IO0 */
5644         } },
5645         { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5646                 { PIN_A_NUMBER('E', 5), 28, 2 },        /* QSPI1_MISO_IO1 */
5647                 { PIN_A_NUMBER('E', 4), 24, 2 },        /* QSPI1_IO2 */
5648                 { PIN_A_NUMBER('C', 3), 20, 2 },        /* QSPI1_IO3 */
5649                 { PIN_NUMBER('V', 5),   16, 2 },        /* QSPI1_SSL */
5650                 { PIN_NUMBER('Y', 7),   12, 2 },        /* RPC_INT# */
5651                 { PIN_NUMBER('V', 6),    8, 2 },        /* RPC_WP# */
5652                 { PIN_NUMBER('V', 7),    4, 2 },        /* RPC_RESET# */
5653                 { PIN_NUMBER('A', 16),   0, 3 },        /* AVB_RX_CTL */
5654         } },
5655         { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5656                 { PIN_NUMBER('B', 19),  28, 3 },        /* AVB_RXC */
5657                 { PIN_NUMBER('A', 13),  24, 3 },        /* AVB_RD0 */
5658                 { PIN_NUMBER('B', 13),  20, 3 },        /* AVB_RD1 */
5659                 { PIN_NUMBER('A', 14),  16, 3 },        /* AVB_RD2 */
5660                 { PIN_NUMBER('B', 14),  12, 3 },        /* AVB_RD3 */
5661                 { PIN_NUMBER('A', 8),    8, 3 },        /* AVB_TX_CTL */
5662                 { PIN_NUMBER('A', 19),   4, 3 },        /* AVB_TXC */
5663                 { PIN_NUMBER('A', 18),   0, 3 },        /* AVB_TD0 */
5664         } },
5665         { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5666                 { PIN_NUMBER('B', 18),  28, 3 },        /* AVB_TD1 */
5667                 { PIN_NUMBER('A', 17),  24, 3 },        /* AVB_TD2 */
5668                 { PIN_NUMBER('B', 17),  20, 3 },        /* AVB_TD3 */
5669                 { PIN_NUMBER('A', 12),  16, 3 },        /* AVB_TXCREFCLK */
5670                 { PIN_NUMBER('A', 9),   12, 3 },        /* AVB_MDIO */
5671                 { RCAR_GP_PIN(2,  9),    8, 3 },        /* AVB_MDC */
5672                 { RCAR_GP_PIN(2, 10),    4, 3 },        /* AVB_MAGIC */
5673                 { RCAR_GP_PIN(2, 11),    0, 3 },        /* AVB_PHY_INT */
5674         } },
5675         { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5676                 { RCAR_GP_PIN(2, 12), 28, 3 },  /* AVB_LINK */
5677                 { RCAR_GP_PIN(2, 13), 24, 3 },  /* AVB_AVTP_MATCH */
5678                 { RCAR_GP_PIN(2, 14), 20, 3 },  /* AVB_AVTP_CAPTURE */
5679                 { RCAR_GP_PIN(2,  0), 16, 3 },  /* IRQ0 */
5680                 { RCAR_GP_PIN(2,  1), 12, 3 },  /* IRQ1 */
5681                 { RCAR_GP_PIN(2,  2),  8, 3 },  /* IRQ2 */
5682                 { RCAR_GP_PIN(2,  3),  4, 3 },  /* IRQ3 */
5683                 { RCAR_GP_PIN(2,  4),  0, 3 },  /* IRQ4 */
5684         } },
5685         { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5686                 { RCAR_GP_PIN(2,  5), 28, 3 },  /* IRQ5 */
5687                 { RCAR_GP_PIN(2,  6), 24, 3 },  /* PWM0 */
5688                 { RCAR_GP_PIN(2,  7), 20, 3 },  /* PWM1 */
5689                 { RCAR_GP_PIN(2,  8), 16, 3 },  /* PWM2 */
5690                 { RCAR_GP_PIN(1,  0), 12, 3 },  /* A0 */
5691                 { RCAR_GP_PIN(1,  1),  8, 3 },  /* A1 */
5692                 { RCAR_GP_PIN(1,  2),  4, 3 },  /* A2 */
5693                 { RCAR_GP_PIN(1,  3),  0, 3 },  /* A3 */
5694         } },
5695         { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5696                 { RCAR_GP_PIN(1,  4), 28, 3 },  /* A4 */
5697                 { RCAR_GP_PIN(1,  5), 24, 3 },  /* A5 */
5698                 { RCAR_GP_PIN(1,  6), 20, 3 },  /* A6 */
5699                 { RCAR_GP_PIN(1,  7), 16, 3 },  /* A7 */
5700                 { RCAR_GP_PIN(1,  8), 12, 3 },  /* A8 */
5701                 { RCAR_GP_PIN(1,  9),  8, 3 },  /* A9 */
5702                 { RCAR_GP_PIN(1, 10),  4, 3 },  /* A10 */
5703                 { RCAR_GP_PIN(1, 11),  0, 3 },  /* A11 */
5704         } },
5705         { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5706                 { RCAR_GP_PIN(1, 12), 28, 3 },  /* A12 */
5707                 { RCAR_GP_PIN(1, 13), 24, 3 },  /* A13 */
5708                 { RCAR_GP_PIN(1, 14), 20, 3 },  /* A14 */
5709                 { RCAR_GP_PIN(1, 15), 16, 3 },  /* A15 */
5710                 { RCAR_GP_PIN(1, 16), 12, 3 },  /* A16 */
5711                 { RCAR_GP_PIN(1, 17),  8, 3 },  /* A17 */
5712                 { RCAR_GP_PIN(1, 18),  4, 3 },  /* A18 */
5713                 { RCAR_GP_PIN(1, 19),  0, 3 },  /* A19 */
5714         } },
5715         { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5716                 { RCAR_GP_PIN(1, 28), 28, 3 },  /* CLKOUT */
5717                 { RCAR_GP_PIN(1, 20), 24, 3 },  /* CS0 */
5718                 { RCAR_GP_PIN(1, 21), 20, 3 },  /* CS1_A26 */
5719                 { RCAR_GP_PIN(1, 22), 16, 3 },  /* BS */
5720                 { RCAR_GP_PIN(1, 23), 12, 3 },  /* RD */
5721                 { RCAR_GP_PIN(1, 24),  8, 3 },  /* RD_WR */
5722                 { RCAR_GP_PIN(1, 25),  4, 3 },  /* WE0 */
5723                 { RCAR_GP_PIN(1, 26),  0, 3 },  /* WE1 */
5724         } },
5725         { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5726                 { RCAR_GP_PIN(1, 27), 28, 3 },  /* EX_WAIT0 */
5727                 { PIN_NUMBER('C', 1), 24, 3 },  /* PRESETOUT# */
5728                 { RCAR_GP_PIN(0,  0), 20, 3 },  /* D0 */
5729                 { RCAR_GP_PIN(0,  1), 16, 3 },  /* D1 */
5730                 { RCAR_GP_PIN(0,  2), 12, 3 },  /* D2 */
5731                 { RCAR_GP_PIN(0,  3),  8, 3 },  /* D3 */
5732                 { RCAR_GP_PIN(0,  4),  4, 3 },  /* D4 */
5733                 { RCAR_GP_PIN(0,  5),  0, 3 },  /* D5 */
5734         } },
5735         { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5736                 { RCAR_GP_PIN(0,  6), 28, 3 },  /* D6 */
5737                 { RCAR_GP_PIN(0,  7), 24, 3 },  /* D7 */
5738                 { RCAR_GP_PIN(0,  8), 20, 3 },  /* D8 */
5739                 { RCAR_GP_PIN(0,  9), 16, 3 },  /* D9 */
5740                 { RCAR_GP_PIN(0, 10), 12, 3 },  /* D10 */
5741                 { RCAR_GP_PIN(0, 11),  8, 3 },  /* D11 */
5742                 { RCAR_GP_PIN(0, 12),  4, 3 },  /* D12 */
5743                 { RCAR_GP_PIN(0, 13),  0, 3 },  /* D13 */
5744         } },
5745         { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5746                 { RCAR_GP_PIN(0, 14),   28, 3 },        /* D14 */
5747                 { RCAR_GP_PIN(0, 15),   24, 3 },        /* D15 */
5748                 { RCAR_GP_PIN(7,  0),   20, 3 },        /* AVS1 */
5749                 { RCAR_GP_PIN(7,  1),   16, 3 },        /* AVS2 */
5750                 { RCAR_GP_PIN(7,  2),   12, 3 },        /* HDMI0_CEC */
5751                 { RCAR_GP_PIN(7,  3),    8, 3 },        /* HDMI1_CEC */
5752                 { PIN_A_NUMBER('P', 7),  4, 2 },        /* DU_DOTCLKIN0 */
5753                 { PIN_A_NUMBER('P', 8),  0, 2 },        /* DU_DOTCLKIN1 */
5754         } },
5755         { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5756                 { PIN_A_NUMBER('R', 7),  28, 2 },       /* DU_DOTCLKIN2 */
5757                 { PIN_A_NUMBER('R', 8),  24, 2 },       /* DU_DOTCLKIN3 */
5758                 { PIN_A_NUMBER('D', 38), 20, 2 },       /* FSCLKST# */
5759                 { PIN_A_NUMBER('R', 30),  4, 2 },       /* TMS */
5760         } },
5761         { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5762                 { PIN_A_NUMBER('T', 28), 28, 2 },       /* TDO */
5763                 { PIN_A_NUMBER('T', 30), 24, 2 },       /* ASEBRK */
5764                 { RCAR_GP_PIN(3,  0),    20, 3 },       /* SD0_CLK */
5765                 { RCAR_GP_PIN(3,  1),    16, 3 },       /* SD0_CMD */
5766                 { RCAR_GP_PIN(3,  2),    12, 3 },       /* SD0_DAT0 */
5767                 { RCAR_GP_PIN(3,  3),     8, 3 },       /* SD0_DAT1 */
5768                 { RCAR_GP_PIN(3,  4),     4, 3 },       /* SD0_DAT2 */
5769                 { RCAR_GP_PIN(3,  5),     0, 3 },       /* SD0_DAT3 */
5770         } },
5771         { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5772                 { RCAR_GP_PIN(3,  6), 28, 3 },  /* SD1_CLK */
5773                 { RCAR_GP_PIN(3,  7), 24, 3 },  /* SD1_CMD */
5774                 { RCAR_GP_PIN(3,  8), 20, 3 },  /* SD1_DAT0 */
5775                 { RCAR_GP_PIN(3,  9), 16, 3 },  /* SD1_DAT1 */
5776                 { RCAR_GP_PIN(3, 10), 12, 3 },  /* SD1_DAT2 */
5777                 { RCAR_GP_PIN(3, 11),  8, 3 },  /* SD1_DAT3 */
5778                 { RCAR_GP_PIN(4,  0),  4, 3 },  /* SD2_CLK */
5779                 { RCAR_GP_PIN(4,  1),  0, 3 },  /* SD2_CMD */
5780         } },
5781         { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5782                 { RCAR_GP_PIN(4,  2), 28, 3 },  /* SD2_DAT0 */
5783                 { RCAR_GP_PIN(4,  3), 24, 3 },  /* SD2_DAT1 */
5784                 { RCAR_GP_PIN(4,  4), 20, 3 },  /* SD2_DAT2 */
5785                 { RCAR_GP_PIN(4,  5), 16, 3 },  /* SD2_DAT3 */
5786                 { RCAR_GP_PIN(4,  6), 12, 3 },  /* SD2_DS */
5787                 { RCAR_GP_PIN(4,  7),  8, 3 },  /* SD3_CLK */
5788                 { RCAR_GP_PIN(4,  8),  4, 3 },  /* SD3_CMD */
5789                 { RCAR_GP_PIN(4,  9),  0, 3 },  /* SD3_DAT0 */
5790         } },
5791         { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5792                 { RCAR_GP_PIN(4, 10), 28, 3 },  /* SD3_DAT1 */
5793                 { RCAR_GP_PIN(4, 11), 24, 3 },  /* SD3_DAT2 */
5794                 { RCAR_GP_PIN(4, 12), 20, 3 },  /* SD3_DAT3 */
5795                 { RCAR_GP_PIN(4, 13), 16, 3 },  /* SD3_DAT4 */
5796                 { RCAR_GP_PIN(4, 14), 12, 3 },  /* SD3_DAT5 */
5797                 { RCAR_GP_PIN(4, 15),  8, 3 },  /* SD3_DAT6 */
5798                 { RCAR_GP_PIN(4, 16),  4, 3 },  /* SD3_DAT7 */
5799                 { RCAR_GP_PIN(4, 17),  0, 3 },  /* SD3_DS */
5800         } },
5801         { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5802                 { RCAR_GP_PIN(3, 12), 28, 3 },  /* SD0_CD */
5803                 { RCAR_GP_PIN(3, 13), 24, 3 },  /* SD0_WP */
5804                 { RCAR_GP_PIN(3, 14), 20, 3 },  /* SD1_CD */
5805                 { RCAR_GP_PIN(3, 15), 16, 3 },  /* SD1_WP */
5806                 { RCAR_GP_PIN(5,  0), 12, 3 },  /* SCK0 */
5807                 { RCAR_GP_PIN(5,  1),  8, 3 },  /* RX0 */
5808                 { RCAR_GP_PIN(5,  2),  4, 3 },  /* TX0 */
5809                 { RCAR_GP_PIN(5,  3),  0, 3 },  /* CTS0 */
5810         } },
5811         { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5812                 { RCAR_GP_PIN(5,  4), 28, 3 },  /* RTS0 */
5813                 { RCAR_GP_PIN(5,  5), 24, 3 },  /* RX1 */
5814                 { RCAR_GP_PIN(5,  6), 20, 3 },  /* TX1 */
5815                 { RCAR_GP_PIN(5,  7), 16, 3 },  /* CTS1 */
5816                 { RCAR_GP_PIN(5,  8), 12, 3 },  /* RTS1 */
5817                 { RCAR_GP_PIN(5,  9),  8, 3 },  /* SCK2 */
5818                 { RCAR_GP_PIN(5, 10),  4, 3 },  /* TX2 */
5819                 { RCAR_GP_PIN(5, 11),  0, 3 },  /* RX2 */
5820         } },
5821         { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5822                 { RCAR_GP_PIN(5, 12), 28, 3 },  /* HSCK0 */
5823                 { RCAR_GP_PIN(5, 13), 24, 3 },  /* HRX0 */
5824                 { RCAR_GP_PIN(5, 14), 20, 3 },  /* HTX0 */
5825                 { RCAR_GP_PIN(5, 15), 16, 3 },  /* HCTS0 */
5826                 { RCAR_GP_PIN(5, 16), 12, 3 },  /* HRTS0 */
5827                 { RCAR_GP_PIN(5, 17),  8, 3 },  /* MSIOF0_SCK */
5828                 { RCAR_GP_PIN(5, 18),  4, 3 },  /* MSIOF0_SYNC */
5829                 { RCAR_GP_PIN(5, 19),  0, 3 },  /* MSIOF0_SS1 */
5830         } },
5831         { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5832                 { RCAR_GP_PIN(5, 20), 28, 3 },  /* MSIOF0_TXD */
5833                 { RCAR_GP_PIN(5, 21), 24, 3 },  /* MSIOF0_SS2 */
5834                 { RCAR_GP_PIN(5, 22), 20, 3 },  /* MSIOF0_RXD */
5835                 { RCAR_GP_PIN(5, 23), 16, 3 },  /* MLB_CLK */
5836                 { RCAR_GP_PIN(5, 24), 12, 3 },  /* MLB_SIG */
5837                 { RCAR_GP_PIN(5, 25),  8, 3 },  /* MLB_DAT */
5838                 { PIN_NUMBER('H', 37),  4, 3 }, /* MLB_REF */
5839                 { RCAR_GP_PIN(6,  0),  0, 3 },  /* SSI_SCK01239 */
5840         } },
5841         { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5842                 { RCAR_GP_PIN(6,  1), 28, 3 },  /* SSI_WS01239 */
5843                 { RCAR_GP_PIN(6,  2), 24, 3 },  /* SSI_SDATA0 */
5844                 { RCAR_GP_PIN(6,  3), 20, 3 },  /* SSI_SDATA1 */
5845                 { RCAR_GP_PIN(6,  4), 16, 3 },  /* SSI_SDATA2 */
5846                 { RCAR_GP_PIN(6,  5), 12, 3 },  /* SSI_SCK349 */
5847                 { RCAR_GP_PIN(6,  6),  8, 3 },  /* SSI_WS349 */
5848                 { RCAR_GP_PIN(6,  7),  4, 3 },  /* SSI_SDATA3 */
5849                 { RCAR_GP_PIN(6,  8),  0, 3 },  /* SSI_SCK4 */
5850         } },
5851         { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5852                 { RCAR_GP_PIN(6,  9), 28, 3 },  /* SSI_WS4 */
5853                 { RCAR_GP_PIN(6, 10), 24, 3 },  /* SSI_SDATA4 */
5854                 { RCAR_GP_PIN(6, 11), 20, 3 },  /* SSI_SCK5 */
5855                 { RCAR_GP_PIN(6, 12), 16, 3 },  /* SSI_WS5 */
5856                 { RCAR_GP_PIN(6, 13), 12, 3 },  /* SSI_SDATA5 */
5857                 { RCAR_GP_PIN(6, 14),  8, 3 },  /* SSI_SCK6 */
5858                 { RCAR_GP_PIN(6, 15),  4, 3 },  /* SSI_WS6 */
5859                 { RCAR_GP_PIN(6, 16),  0, 3 },  /* SSI_SDATA6 */
5860         } },
5861         { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5862                 { RCAR_GP_PIN(6, 17), 28, 3 },  /* SSI_SCK78 */
5863                 { RCAR_GP_PIN(6, 18), 24, 3 },  /* SSI_WS78 */
5864                 { RCAR_GP_PIN(6, 19), 20, 3 },  /* SSI_SDATA7 */
5865                 { RCAR_GP_PIN(6, 20), 16, 3 },  /* SSI_SDATA8 */
5866                 { RCAR_GP_PIN(6, 21), 12, 3 },  /* SSI_SDATA9 */
5867                 { RCAR_GP_PIN(6, 22),  8, 3 },  /* AUDIO_CLKA */
5868                 { RCAR_GP_PIN(6, 23),  4, 3 },  /* AUDIO_CLKB */
5869                 { RCAR_GP_PIN(6, 24),  0, 3 },  /* USB0_PWEN */
5870         } },
5871         { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5872                 { RCAR_GP_PIN(6, 25), 28, 3 },  /* USB0_OVC */
5873                 { RCAR_GP_PIN(6, 26), 24, 3 },  /* USB1_PWEN */
5874                 { RCAR_GP_PIN(6, 27), 20, 3 },  /* USB1_OVC */
5875                 { RCAR_GP_PIN(6, 28), 16, 3 },  /* USB30_PWEN */
5876                 { RCAR_GP_PIN(6, 29), 12, 3 },  /* USB30_OVC */
5877                 { RCAR_GP_PIN(6, 30),  8, 3 },  /* USB2_CH3_PWEN */
5878                 { RCAR_GP_PIN(6, 31),  4, 3 },  /* USB2_CH3_OVC */
5879         } },
5880         { },
5881 };
5882
5883 enum ioctrl_regs {
5884         POCCTRL,
5885 };
5886
5887 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5888         [POCCTRL] = { 0xe6060380, },
5889         { /* sentinel */ },
5890 };
5891
5892 static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5893 {
5894         int bit = -EINVAL;
5895
5896         *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5897
5898         if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5899                 bit = pin & 0x1f;
5900
5901         if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5902                 bit = (pin & 0x1f) + 12;
5903
5904         return bit;
5905 }
5906
5907 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5908         { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5909                 [ 0] = PIN_NUMBER('W', 3),      /* QSPI0_SPCLK */
5910                 [ 1] = PIN_A_NUMBER('C', 5),    /* QSPI0_MOSI_IO0 */
5911                 [ 2] = PIN_A_NUMBER('B', 4),    /* QSPI0_MISO_IO1 */
5912                 [ 3] = PIN_NUMBER('Y', 6),      /* QSPI0_IO2 */
5913                 [ 4] = PIN_A_NUMBER('B', 6),    /* QSPI0_IO3 */
5914                 [ 5] = PIN_NUMBER('Y', 3),      /* QSPI0_SSL */
5915                 [ 6] = PIN_NUMBER('V', 3),      /* QSPI1_SPCLK */
5916                 [ 7] = PIN_A_NUMBER('C', 7),    /* QSPI1_MOSI_IO0 */
5917                 [ 8] = PIN_A_NUMBER('E', 5),    /* QSPI1_MISO_IO1 */
5918                 [ 9] = PIN_A_NUMBER('E', 4),    /* QSPI1_IO2 */
5919                 [10] = PIN_A_NUMBER('C', 3),    /* QSPI1_IO3 */
5920                 [11] = PIN_NUMBER('V', 5),      /* QSPI1_SSL */
5921                 [12] = PIN_NUMBER('Y', 7),      /* RPC_INT# */
5922                 [13] = PIN_NUMBER('V', 6),      /* RPC_WP# */
5923                 [14] = PIN_NUMBER('V', 7),      /* RPC_RESET# */
5924                 [15] = PIN_NUMBER('A', 16),     /* AVB_RX_CTL */
5925                 [16] = PIN_NUMBER('B', 19),     /* AVB_RXC */
5926                 [17] = PIN_NUMBER('A', 13),     /* AVB_RD0 */
5927                 [18] = PIN_NUMBER('B', 13),     /* AVB_RD1 */
5928                 [19] = PIN_NUMBER('A', 14),     /* AVB_RD2 */
5929                 [20] = PIN_NUMBER('B', 14),     /* AVB_RD3 */
5930                 [21] = PIN_NUMBER('A', 8),      /* AVB_TX_CTL */
5931                 [22] = PIN_NUMBER('A', 19),     /* AVB_TXC */
5932                 [23] = PIN_NUMBER('A', 18),     /* AVB_TD0 */
5933                 [24] = PIN_NUMBER('B', 18),     /* AVB_TD1 */
5934                 [25] = PIN_NUMBER('A', 17),     /* AVB_TD2 */
5935                 [26] = PIN_NUMBER('B', 17),     /* AVB_TD3 */
5936                 [27] = PIN_NUMBER('A', 12),     /* AVB_TXCREFCLK */
5937                 [28] = PIN_NUMBER('A', 9),      /* AVB_MDIO */
5938                 [29] = RCAR_GP_PIN(2,  9),      /* AVB_MDC */
5939                 [30] = RCAR_GP_PIN(2, 10),      /* AVB_MAGIC */
5940                 [31] = RCAR_GP_PIN(2, 11),      /* AVB_PHY_INT */
5941         } },
5942         { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5943                 [ 0] = RCAR_GP_PIN(2, 12),      /* AVB_LINK */
5944                 [ 1] = RCAR_GP_PIN(2, 13),      /* AVB_AVTP_MATCH_A */
5945                 [ 2] = RCAR_GP_PIN(2, 14),      /* AVB_AVTP_CAPTURE_A */
5946                 [ 3] = RCAR_GP_PIN(2,  0),      /* IRQ0 */
5947                 [ 4] = RCAR_GP_PIN(2,  1),      /* IRQ1 */
5948                 [ 5] = RCAR_GP_PIN(2,  2),      /* IRQ2 */
5949                 [ 6] = RCAR_GP_PIN(2,  3),      /* IRQ3 */
5950                 [ 7] = RCAR_GP_PIN(2,  4),      /* IRQ4 */
5951                 [ 8] = RCAR_GP_PIN(2,  5),      /* IRQ5 */
5952                 [ 9] = RCAR_GP_PIN(2,  6),      /* PWM0 */
5953                 [10] = RCAR_GP_PIN(2,  7),      /* PWM1_A */
5954                 [11] = RCAR_GP_PIN(2,  8),      /* PWM2_A */
5955                 [12] = RCAR_GP_PIN(1,  0),      /* A0 */
5956                 [13] = RCAR_GP_PIN(1,  1),      /* A1 */
5957                 [14] = RCAR_GP_PIN(1,  2),      /* A2 */
5958                 [15] = RCAR_GP_PIN(1,  3),      /* A3 */
5959                 [16] = RCAR_GP_PIN(1,  4),      /* A4 */
5960                 [17] = RCAR_GP_PIN(1,  5),      /* A5 */
5961                 [18] = RCAR_GP_PIN(1,  6),      /* A6 */
5962                 [19] = RCAR_GP_PIN(1,  7),      /* A7 */
5963                 [20] = RCAR_GP_PIN(1,  8),      /* A8 */
5964                 [21] = RCAR_GP_PIN(1,  9),      /* A9 */
5965                 [22] = RCAR_GP_PIN(1, 10),      /* A10 */
5966                 [23] = RCAR_GP_PIN(1, 11),      /* A11 */
5967                 [24] = RCAR_GP_PIN(1, 12),      /* A12 */
5968                 [25] = RCAR_GP_PIN(1, 13),      /* A13 */
5969                 [26] = RCAR_GP_PIN(1, 14),      /* A14 */
5970                 [27] = RCAR_GP_PIN(1, 15),      /* A15 */
5971                 [28] = RCAR_GP_PIN(1, 16),      /* A16 */
5972                 [29] = RCAR_GP_PIN(1, 17),      /* A17 */
5973                 [30] = RCAR_GP_PIN(1, 18),      /* A18 */
5974                 [31] = RCAR_GP_PIN(1, 19),      /* A19 */
5975         } },
5976         { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5977                 [ 0] = RCAR_GP_PIN(1, 28),      /* CLKOUT */
5978                 [ 1] = RCAR_GP_PIN(1, 20),      /* CS0_N */
5979                 [ 2] = RCAR_GP_PIN(1, 21),      /* CS1_N */
5980                 [ 3] = RCAR_GP_PIN(1, 22),      /* BS_N */
5981                 [ 4] = RCAR_GP_PIN(1, 23),      /* RD_N */
5982                 [ 5] = RCAR_GP_PIN(1, 24),      /* RD_WR_N */
5983                 [ 6] = RCAR_GP_PIN(1, 25),      /* WE0_N */
5984                 [ 7] = RCAR_GP_PIN(1, 26),      /* WE1_N */
5985                 [ 8] = RCAR_GP_PIN(1, 27),      /* EX_WAIT0_A */
5986                 [ 9] = PIN_NUMBER('C', 1),      /* PRESETOUT# */
5987                 [10] = RCAR_GP_PIN(0,  0),      /* D0 */
5988                 [11] = RCAR_GP_PIN(0,  1),      /* D1 */
5989                 [12] = RCAR_GP_PIN(0,  2),      /* D2 */
5990                 [13] = RCAR_GP_PIN(0,  3),      /* D3 */
5991                 [14] = RCAR_GP_PIN(0,  4),      /* D4 */
5992                 [15] = RCAR_GP_PIN(0,  5),      /* D5 */
5993                 [16] = RCAR_GP_PIN(0,  6),      /* D6 */
5994                 [17] = RCAR_GP_PIN(0,  7),      /* D7 */
5995                 [18] = RCAR_GP_PIN(0,  8),      /* D8 */
5996                 [19] = RCAR_GP_PIN(0,  9),      /* D9 */
5997                 [20] = RCAR_GP_PIN(0, 10),      /* D10 */
5998                 [21] = RCAR_GP_PIN(0, 11),      /* D11 */
5999                 [22] = RCAR_GP_PIN(0, 12),      /* D12 */
6000                 [23] = RCAR_GP_PIN(0, 13),      /* D13 */
6001                 [24] = RCAR_GP_PIN(0, 14),      /* D14 */
6002                 [25] = RCAR_GP_PIN(0, 15),      /* D15 */
6003                 [26] = RCAR_GP_PIN(7,  0),      /* AVS1 */
6004                 [27] = RCAR_GP_PIN(7,  1),      /* AVS2 */
6005                 [28] = RCAR_GP_PIN(7,  2),      /* HDMI0_CEC */
6006                 [29] = RCAR_GP_PIN(7,  3),      /* HDMI1_CEC */
6007                 [30] = PIN_A_NUMBER('P', 7),    /* DU_DOTCLKIN0 */
6008                 [31] = PIN_A_NUMBER('P', 8),    /* DU_DOTCLKIN1 */
6009         } },
6010         { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
6011                 [ 0] = PIN_A_NUMBER('R', 7),    /* DU_DOTCLKIN2 */
6012                 [ 1] = PIN_A_NUMBER('R', 8),    /* DU_DOTCLKIN3 */
6013                 [ 2] = PIN_A_NUMBER('D', 38),   /* FSCLKST# */
6014                 [ 3] = PIN_A_NUMBER('D', 39),   /* EXTALR*/
6015                 [ 4] = PIN_A_NUMBER('R', 26),   /* TRST# */
6016                 [ 5] = PIN_A_NUMBER('T', 27),   /* TCK */
6017                 [ 6] = PIN_A_NUMBER('R', 30),   /* TMS */
6018                 [ 7] = PIN_A_NUMBER('R', 29),   /* TDI */
6019                 [ 8] = PIN_NONE,
6020                 [ 9] = PIN_A_NUMBER('T', 30),   /* ASEBRK */
6021                 [10] = RCAR_GP_PIN(3,  0),      /* SD0_CLK */
6022                 [11] = RCAR_GP_PIN(3,  1),      /* SD0_CMD */
6023                 [12] = RCAR_GP_PIN(3,  2),      /* SD0_DAT0 */
6024                 [13] = RCAR_GP_PIN(3,  3),      /* SD0_DAT1 */
6025                 [14] = RCAR_GP_PIN(3,  4),      /* SD0_DAT2 */
6026                 [15] = RCAR_GP_PIN(3,  5),      /* SD0_DAT3 */
6027                 [16] = RCAR_GP_PIN(3,  6),      /* SD1_CLK */
6028                 [17] = RCAR_GP_PIN(3,  7),      /* SD1_CMD */
6029                 [18] = RCAR_GP_PIN(3,  8),      /* SD1_DAT0 */
6030                 [19] = RCAR_GP_PIN(3,  9),      /* SD1_DAT1 */
6031                 [20] = RCAR_GP_PIN(3, 10),      /* SD1_DAT2 */
6032                 [21] = RCAR_GP_PIN(3, 11),      /* SD1_DAT3 */
6033                 [22] = RCAR_GP_PIN(4,  0),      /* SD2_CLK */
6034                 [23] = RCAR_GP_PIN(4,  1),      /* SD2_CMD */
6035                 [24] = RCAR_GP_PIN(4,  2),      /* SD2_DAT0 */
6036                 [25] = RCAR_GP_PIN(4,  3),      /* SD2_DAT1 */
6037                 [26] = RCAR_GP_PIN(4,  4),      /* SD2_DAT2 */
6038                 [27] = RCAR_GP_PIN(4,  5),      /* SD2_DAT3 */
6039                 [28] = RCAR_GP_PIN(4,  6),      /* SD2_DS */
6040                 [29] = RCAR_GP_PIN(4,  7),      /* SD3_CLK */
6041                 [30] = RCAR_GP_PIN(4,  8),      /* SD3_CMD */
6042                 [31] = RCAR_GP_PIN(4,  9),      /* SD3_DAT0 */
6043         } },
6044         { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6045                 [ 0] = RCAR_GP_PIN(4, 10),      /* SD3_DAT1 */
6046                 [ 1] = RCAR_GP_PIN(4, 11),      /* SD3_DAT2 */
6047                 [ 2] = RCAR_GP_PIN(4, 12),      /* SD3_DAT3 */
6048                 [ 3] = RCAR_GP_PIN(4, 13),      /* SD3_DAT4 */
6049                 [ 4] = RCAR_GP_PIN(4, 14),      /* SD3_DAT5 */
6050                 [ 5] = RCAR_GP_PIN(4, 15),      /* SD3_DAT6 */
6051                 [ 6] = RCAR_GP_PIN(4, 16),      /* SD3_DAT7 */
6052                 [ 7] = RCAR_GP_PIN(4, 17),      /* SD3_DS */
6053                 [ 8] = RCAR_GP_PIN(3, 12),      /* SD0_CD */
6054                 [ 9] = RCAR_GP_PIN(3, 13),      /* SD0_WP */
6055                 [10] = RCAR_GP_PIN(3, 14),      /* SD1_CD */
6056                 [11] = RCAR_GP_PIN(3, 15),      /* SD1_WP */
6057                 [12] = RCAR_GP_PIN(5,  0),      /* SCK0 */
6058                 [13] = RCAR_GP_PIN(5,  1),      /* RX0 */
6059                 [14] = RCAR_GP_PIN(5,  2),      /* TX0 */
6060                 [15] = RCAR_GP_PIN(5,  3),      /* CTS0_N */
6061                 [16] = RCAR_GP_PIN(5,  4),      /* RTS0_N */
6062                 [17] = RCAR_GP_PIN(5,  5),      /* RX1_A */
6063                 [18] = RCAR_GP_PIN(5,  6),      /* TX1_A */
6064                 [19] = RCAR_GP_PIN(5,  7),      /* CTS1_N */
6065                 [20] = RCAR_GP_PIN(5,  8),      /* RTS1_N */
6066                 [21] = RCAR_GP_PIN(5,  9),      /* SCK2 */
6067                 [22] = RCAR_GP_PIN(5, 10),      /* TX2_A */
6068                 [23] = RCAR_GP_PIN(5, 11),      /* RX2_A */
6069                 [24] = RCAR_GP_PIN(5, 12),      /* HSCK0 */
6070                 [25] = RCAR_GP_PIN(5, 13),      /* HRX0 */
6071                 [26] = RCAR_GP_PIN(5, 14),      /* HTX0 */
6072                 [27] = RCAR_GP_PIN(5, 15),      /* HCTS0_N */
6073                 [28] = RCAR_GP_PIN(5, 16),      /* HRTS0_N */
6074                 [29] = RCAR_GP_PIN(5, 17),      /* MSIOF0_SCK */
6075                 [30] = RCAR_GP_PIN(5, 18),      /* MSIOF0_SYNC */
6076                 [31] = RCAR_GP_PIN(5, 19),      /* MSIOF0_SS1 */
6077         } },
6078         { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6079                 [ 0] = RCAR_GP_PIN(5, 20),      /* MSIOF0_TXD */
6080                 [ 1] = RCAR_GP_PIN(5, 21),      /* MSIOF0_SS2 */
6081                 [ 2] = RCAR_GP_PIN(5, 22),      /* MSIOF0_RXD */
6082                 [ 3] = RCAR_GP_PIN(5, 23),      /* MLB_CLK */
6083                 [ 4] = RCAR_GP_PIN(5, 24),      /* MLB_SIG */
6084                 [ 5] = RCAR_GP_PIN(5, 25),      /* MLB_DAT */
6085                 [ 6] = PIN_NUMBER('H', 37),     /* MLB_REF */
6086                 [ 7] = RCAR_GP_PIN(6,  0),      /* SSI_SCK01239 */
6087                 [ 8] = RCAR_GP_PIN(6,  1),      /* SSI_WS01239 */
6088                 [ 9] = RCAR_GP_PIN(6,  2),      /* SSI_SDATA0 */
6089                 [10] = RCAR_GP_PIN(6,  3),      /* SSI_SDATA1_A */
6090                 [11] = RCAR_GP_PIN(6,  4),      /* SSI_SDATA2_A */
6091                 [12] = RCAR_GP_PIN(6,  5),      /* SSI_SCK349 */
6092                 [13] = RCAR_GP_PIN(6,  6),      /* SSI_WS349 */
6093                 [14] = RCAR_GP_PIN(6,  7),      /* SSI_SDATA3 */
6094                 [15] = RCAR_GP_PIN(6,  8),      /* SSI_SCK4 */
6095                 [16] = RCAR_GP_PIN(6,  9),      /* SSI_WS4 */
6096                 [17] = RCAR_GP_PIN(6, 10),      /* SSI_SDATA4 */
6097                 [18] = RCAR_GP_PIN(6, 11),      /* SSI_SCK5 */
6098                 [19] = RCAR_GP_PIN(6, 12),      /* SSI_WS5 */
6099                 [20] = RCAR_GP_PIN(6, 13),      /* SSI_SDATA5 */
6100                 [21] = RCAR_GP_PIN(6, 14),      /* SSI_SCK6 */
6101                 [22] = RCAR_GP_PIN(6, 15),      /* SSI_WS6 */
6102                 [23] = RCAR_GP_PIN(6, 16),      /* SSI_SDATA6 */
6103                 [24] = RCAR_GP_PIN(6, 17),      /* SSI_SCK78 */
6104                 [25] = RCAR_GP_PIN(6, 18),      /* SSI_WS78 */
6105                 [26] = RCAR_GP_PIN(6, 19),      /* SSI_SDATA7 */
6106                 [27] = RCAR_GP_PIN(6, 20),      /* SSI_SDATA8 */
6107                 [28] = RCAR_GP_PIN(6, 21),      /* SSI_SDATA9_A */
6108                 [29] = RCAR_GP_PIN(6, 22),      /* AUDIO_CLKA_A */
6109                 [30] = RCAR_GP_PIN(6, 23),      /* AUDIO_CLKB_B */
6110                 [31] = RCAR_GP_PIN(6, 24),      /* USB0_PWEN */
6111         } },
6112         { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6113                 [ 0] = RCAR_GP_PIN(6, 25),      /* USB0_OVC */
6114                 [ 1] = RCAR_GP_PIN(6, 26),      /* USB1_PWEN */
6115                 [ 2] = RCAR_GP_PIN(6, 27),      /* USB1_OVC */
6116                 [ 3] = RCAR_GP_PIN(6, 28),      /* USB30_PWEN */
6117                 [ 4] = RCAR_GP_PIN(6, 29),      /* USB30_OVC */
6118                 [ 5] = RCAR_GP_PIN(6, 30),      /* USB2_CH3_PWEN */
6119                 [ 6] = RCAR_GP_PIN(6, 31),      /* USB2_CH3_OVC */
6120                 [ 7] = PIN_NONE,
6121                 [ 8] = PIN_NONE,
6122                 [ 9] = PIN_NONE,
6123                 [10] = PIN_NONE,
6124                 [11] = PIN_NONE,
6125                 [12] = PIN_NONE,
6126                 [13] = PIN_NONE,
6127                 [14] = PIN_NONE,
6128                 [15] = PIN_NONE,
6129                 [16] = PIN_NONE,
6130                 [17] = PIN_NONE,
6131                 [18] = PIN_NONE,
6132                 [19] = PIN_NONE,
6133                 [20] = PIN_NONE,
6134                 [21] = PIN_NONE,
6135                 [22] = PIN_NONE,
6136                 [23] = PIN_NONE,
6137                 [24] = PIN_NONE,
6138                 [25] = PIN_NONE,
6139                 [26] = PIN_NONE,
6140                 [27] = PIN_NONE,
6141                 [28] = PIN_NONE,
6142                 [29] = PIN_NONE,
6143                 [30] = PIN_NONE,
6144                 [31] = PIN_NONE,
6145         } },
6146         { /* sentinel */ },
6147 };
6148
6149 static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
6150                                             unsigned int pin)
6151 {
6152         const struct pinmux_bias_reg *reg;
6153         unsigned int bit;
6154
6155         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6156         if (!reg)
6157                 return PIN_CONFIG_BIAS_DISABLE;
6158
6159         if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
6160                 return PIN_CONFIG_BIAS_DISABLE;
6161         else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
6162                 return PIN_CONFIG_BIAS_PULL_UP;
6163         else
6164                 return PIN_CONFIG_BIAS_PULL_DOWN;
6165 }
6166
6167 static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
6168                                    unsigned int bias)
6169 {
6170         const struct pinmux_bias_reg *reg;
6171         u32 enable, updown;
6172         unsigned int bit;
6173
6174         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6175         if (!reg)
6176                 return;
6177
6178         enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
6179         if (bias != PIN_CONFIG_BIAS_DISABLE)
6180                 enable |= BIT(bit);
6181
6182         updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
6183         if (bias == PIN_CONFIG_BIAS_PULL_UP)
6184                 updown |= BIT(bit);
6185
6186         sh_pfc_write(pfc, reg->pud, updown);
6187         sh_pfc_write(pfc, reg->puen, enable);
6188 }
6189
6190 static const struct soc_device_attribute r8a7795es1[] = {
6191         { .soc_id = "r8a7795", .revision = "ES1.*" },
6192         { /* sentinel */ }
6193 };
6194
6195 static int r8a7795_pinmux_init(struct sh_pfc *pfc)
6196 {
6197         if (soc_device_match(r8a7795es1))
6198                 pfc->info = &r8a7795es1_pinmux_info;
6199
6200         return 0;
6201 }
6202
6203 static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
6204         .init = r8a7795_pinmux_init,
6205         .pin_to_pocctrl = r8a7795_pin_to_pocctrl,
6206         .get_bias = r8a7795_pinmux_get_bias,
6207         .set_bias = r8a7795_pinmux_set_bias,
6208 };
6209
6210 const struct sh_pfc_soc_info r8a7795_pinmux_info = {
6211         .name = "r8a77951_pfc",
6212         .ops = &r8a7795_pinmux_ops,
6213         .unlock_reg = 0xe6060000, /* PMMR */
6214
6215         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6216
6217         .pins = pinmux_pins,
6218         .nr_pins = ARRAY_SIZE(pinmux_pins),
6219         .groups = pinmux_groups,
6220         .nr_groups = ARRAY_SIZE(pinmux_groups),
6221         .functions = pinmux_functions,
6222         .nr_functions = ARRAY_SIZE(pinmux_functions),
6223
6224         .cfg_regs = pinmux_config_regs,
6225         .drive_regs = pinmux_drive_regs,
6226         .bias_regs = pinmux_bias_regs,
6227         .ioctrl_regs = pinmux_ioctrl_regs,
6228
6229         .pinmux_data = pinmux_data,
6230         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6231 };