2 * R8A7795 ES2.0+ processor support - PFC hardware block.
4 * Copyright (C) 2015-2016 Renesas Electronics Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
11 #include <linux/kernel.h>
12 #include <linux/sys_soc.h>
17 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
18 SH_PFC_PIN_CFG_PULL_UP | \
19 SH_PFC_PIN_CFG_PULL_DOWN)
21 #define CPU_ALL_PORT(fn, sfx) \
22 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
26 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
31 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
35 * F_() : just information
36 * FM() : macro for FN_xxx / xxx_MARK
40 #define GPSR0_15 F_(D15, IP7_11_8)
41 #define GPSR0_14 F_(D14, IP7_7_4)
42 #define GPSR0_13 F_(D13, IP7_3_0)
43 #define GPSR0_12 F_(D12, IP6_31_28)
44 #define GPSR0_11 F_(D11, IP6_27_24)
45 #define GPSR0_10 F_(D10, IP6_23_20)
46 #define GPSR0_9 F_(D9, IP6_19_16)
47 #define GPSR0_8 F_(D8, IP6_15_12)
48 #define GPSR0_7 F_(D7, IP6_11_8)
49 #define GPSR0_6 F_(D6, IP6_7_4)
50 #define GPSR0_5 F_(D5, IP6_3_0)
51 #define GPSR0_4 F_(D4, IP5_31_28)
52 #define GPSR0_3 F_(D3, IP5_27_24)
53 #define GPSR0_2 F_(D2, IP5_23_20)
54 #define GPSR0_1 F_(D1, IP5_19_16)
55 #define GPSR0_0 F_(D0, IP5_15_12)
58 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
59 #define GPSR1_26 F_(WE1_N, IP5_7_4)
60 #define GPSR1_25 F_(WE0_N, IP5_3_0)
61 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
62 #define GPSR1_23 F_(RD_N, IP4_27_24)
63 #define GPSR1_22 F_(BS_N, IP4_23_20)
64 #define GPSR1_21 F_(CS1_N_A26, IP4_19_16)
65 #define GPSR1_20 F_(CS0_N, IP4_15_12)
66 #define GPSR1_19 F_(A19, IP4_11_8)
67 #define GPSR1_18 F_(A18, IP4_7_4)
68 #define GPSR1_17 F_(A17, IP4_3_0)
69 #define GPSR1_16 F_(A16, IP3_31_28)
70 #define GPSR1_15 F_(A15, IP3_27_24)
71 #define GPSR1_14 F_(A14, IP3_23_20)
72 #define GPSR1_13 F_(A13, IP3_19_16)
73 #define GPSR1_12 F_(A12, IP3_15_12)
74 #define GPSR1_11 F_(A11, IP3_11_8)
75 #define GPSR1_10 F_(A10, IP3_7_4)
76 #define GPSR1_9 F_(A9, IP3_3_0)
77 #define GPSR1_8 F_(A8, IP2_31_28)
78 #define GPSR1_7 F_(A7, IP2_27_24)
79 #define GPSR1_6 F_(A6, IP2_23_20)
80 #define GPSR1_5 F_(A5, IP2_19_16)
81 #define GPSR1_4 F_(A4, IP2_15_12)
82 #define GPSR1_3 F_(A3, IP2_11_8)
83 #define GPSR1_2 F_(A2, IP2_7_4)
84 #define GPSR1_1 F_(A1, IP2_3_0)
85 #define GPSR1_0 F_(A0, IP1_31_28)
88 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
89 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
90 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
91 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
92 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
93 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
94 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
95 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
96 #define GPSR2_6 F_(PWM0, IP1_19_16)
97 #define GPSR2_5 F_(IRQ5, IP1_15_12)
98 #define GPSR2_4 F_(IRQ4, IP1_11_8)
99 #define GPSR2_3 F_(IRQ3, IP1_7_4)
100 #define GPSR2_2 F_(IRQ2, IP1_3_0)
101 #define GPSR2_1 F_(IRQ1, IP0_31_28)
102 #define GPSR2_0 F_(IRQ0, IP0_27_24)
105 #define GPSR3_15 F_(SD1_WP, IP11_23_20)
106 #define GPSR3_14 F_(SD1_CD, IP11_19_16)
107 #define GPSR3_13 F_(SD0_WP, IP11_15_12)
108 #define GPSR3_12 F_(SD0_CD, IP11_11_8)
109 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
110 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
111 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
112 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
113 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
114 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
115 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
116 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
117 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
118 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
119 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
120 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
123 #define GPSR4_17 F_(SD3_DS, IP11_7_4)
124 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
125 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
126 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
127 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
128 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
129 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
130 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
131 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
132 #define GPSR4_8 F_(SD3_CMD, IP10_3_0)
133 #define GPSR4_7 F_(SD3_CLK, IP9_31_28)
134 #define GPSR4_6 F_(SD2_DS, IP9_27_24)
135 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
136 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
137 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
138 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
139 #define GPSR4_1 F_(SD2_CMD, IP9_7_4)
140 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
143 #define GPSR5_25 F_(MLB_DAT, IP14_19_16)
144 #define GPSR5_24 F_(MLB_SIG, IP14_15_12)
145 #define GPSR5_23 F_(MLB_CLK, IP14_11_8)
146 #define GPSR5_22 FM(MSIOF0_RXD)
147 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
148 #define GPSR5_20 FM(MSIOF0_TXD)
149 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
150 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
151 #define GPSR5_17 FM(MSIOF0_SCK)
152 #define GPSR5_16 F_(HRTS0_N, IP13_27_24)
153 #define GPSR5_15 F_(HCTS0_N, IP13_23_20)
154 #define GPSR5_14 F_(HTX0, IP13_19_16)
155 #define GPSR5_13 F_(HRX0, IP13_15_12)
156 #define GPSR5_12 F_(HSCK0, IP13_11_8)
157 #define GPSR5_11 F_(RX2_A, IP13_7_4)
158 #define GPSR5_10 F_(TX2_A, IP13_3_0)
159 #define GPSR5_9 F_(SCK2, IP12_31_28)
160 #define GPSR5_8 F_(RTS1_N_TANS, IP12_27_24)
161 #define GPSR5_7 F_(CTS1_N, IP12_23_20)
162 #define GPSR5_6 F_(TX1_A, IP12_19_16)
163 #define GPSR5_5 F_(RX1_A, IP12_15_12)
164 #define GPSR5_4 F_(RTS0_N_TANS, IP12_11_8)
165 #define GPSR5_3 F_(CTS0_N, IP12_7_4)
166 #define GPSR5_2 F_(TX0, IP12_3_0)
167 #define GPSR5_1 F_(RX0, IP11_31_28)
168 #define GPSR5_0 F_(SCK0, IP11_27_24)
171 #define GPSR6_31 F_(USB3_OVC, IP18_7_4)
172 #define GPSR6_30 F_(USB3_PWEN, IP18_3_0)
173 #define GPSR6_29 F_(USB30_OVC, IP17_31_28)
174 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
175 #define GPSR6_27 F_(USB1_OVC, IP17_23_20)
176 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
177 #define GPSR6_25 F_(USB0_OVC, IP17_15_12)
178 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
179 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
180 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
181 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
182 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
183 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
184 #define GPSR6_18 F_(SSI_WS78, IP16_19_16)
185 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
186 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
187 #define GPSR6_15 F_(SSI_WS6, IP16_7_4)
188 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
189 #define GPSR6_13 FM(SSI_SDATA5)
190 #define GPSR6_12 FM(SSI_WS5)
191 #define GPSR6_11 FM(SSI_SCK5)
192 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
193 #define GPSR6_9 F_(SSI_WS4, IP15_27_24)
194 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
195 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
196 #define GPSR6_6 F_(SSI_WS349, IP15_15_12)
197 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
198 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
199 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
200 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
201 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
202 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
205 #define GPSR7_3 FM(HDMI1_CEC)
206 #define GPSR7_2 FM(HDMI0_CEC)
207 #define GPSR7_1 FM(AVS2)
208 #define GPSR7_0 FM(AVS1)
211 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
212 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
233 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
277 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP9_27_24 FM(SD2_DS) F_(0, 0) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP11_7_4 FM(SD3_DS) F_(0, 0) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
309 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
330 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
339 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
359 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
360 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
361 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
362 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
363 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364 #define IP18_3_0 FM(USB3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) F_(0, 0) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0)
365 #define IP18_7_4 FM(USB3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) F_(0, 0) FM(FMIN_C) FM(FMIN_D) F_(0, 0)
367 #define PINMUX_GPSR \
375 GPSR1_25 GPSR5_25 GPSR6_25 \
376 GPSR1_24 GPSR5_24 GPSR6_24 \
377 GPSR1_23 GPSR5_23 GPSR6_23 \
378 GPSR1_22 GPSR5_22 GPSR6_22 \
379 GPSR1_21 GPSR5_21 GPSR6_21 \
380 GPSR1_20 GPSR5_20 GPSR6_20 \
381 GPSR1_19 GPSR5_19 GPSR6_19 \
382 GPSR1_18 GPSR5_18 GPSR6_18 \
383 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
384 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
385 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
386 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
387 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
388 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
389 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
390 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
391 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
392 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
393 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
394 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
395 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
396 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
397 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
398 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
399 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
400 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
402 #define PINMUX_IPSR \
404 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
405 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
406 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
407 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
408 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
409 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
410 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
411 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
413 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
414 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
415 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
416 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
417 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
418 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
419 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
420 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
422 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
423 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
424 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
425 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
426 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
427 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
428 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
429 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
431 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
432 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
433 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
434 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
435 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
436 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
437 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
438 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
440 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
441 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
442 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
443 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
444 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
445 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
446 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
447 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
449 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
450 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
451 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
452 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
453 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
454 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
455 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
456 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
457 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
458 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
459 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
460 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
461 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
462 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
463 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
464 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
465 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
466 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
467 #define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
469 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
470 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
471 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
472 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
473 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
474 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
475 #define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
476 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
477 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
478 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
479 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
480 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
481 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
482 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
483 #define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1)
484 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
485 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
486 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
487 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
488 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
489 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
490 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
491 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
493 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
494 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
495 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
496 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
497 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
498 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
499 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
500 #define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
501 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
502 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
503 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
504 #define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
505 #define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
506 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
508 #define PINMUX_MOD_SELS \
510 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
512 MOD_SEL1_29_28_27 MOD_SEL2_29 \
513 MOD_SEL0_28_27 MOD_SEL2_28_27 \
514 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
515 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
516 MOD_SEL0_23 MOD_SEL1_23_22_21 \
517 MOD_SEL0_22 MOD_SEL2_22 \
518 MOD_SEL0_21 MOD_SEL2_21 \
519 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
520 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
521 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
523 MOD_SEL0_16 MOD_SEL1_16 \
527 MOD_SEL0_12 MOD_SEL1_12 \
528 MOD_SEL0_11 MOD_SEL1_11 \
529 MOD_SEL0_10 MOD_SEL1_10 \
530 MOD_SEL0_9_8 MOD_SEL1_9 \
533 MOD_SEL0_5 MOD_SEL1_5 \
534 MOD_SEL0_4_3 MOD_SEL1_4 \
538 MOD_SEL1_0 MOD_SEL2_0
541 * These pins are not able to be muxed but have other properties
542 * that can be set, such as drive-strength or pull-up/pull-down enable.
544 #define PINMUX_STATIC \
545 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
546 FM(QSPI0_IO2) FM(QSPI0_IO3) \
547 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
548 FM(QSPI1_IO2) FM(QSPI1_IO3) \
549 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
550 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
551 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
552 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
553 FM(CLKOUT) FM(PRESETOUT) \
554 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
555 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
565 #define FM(x) FN_##x,
566 PINMUX_FUNCTION_BEGIN,
576 #define FM(x) x##_MARK,
587 static const u16 pinmux_data[] = {
588 PINMUX_DATA_GP_ALL(),
592 PINMUX_SINGLE(HDMI0_CEC),
593 PINMUX_SINGLE(HDMI1_CEC),
594 PINMUX_SINGLE(I2C_SEL_0_1),
595 PINMUX_SINGLE(I2C_SEL_3_1),
596 PINMUX_SINGLE(I2C_SEL_5_1),
597 PINMUX_SINGLE(MSIOF0_RXD),
598 PINMUX_SINGLE(MSIOF0_SCK),
599 PINMUX_SINGLE(MSIOF0_TXD),
600 PINMUX_SINGLE(SSI_SCK5),
601 PINMUX_SINGLE(SSI_SDATA5),
602 PINMUX_SINGLE(SSI_WS5),
605 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
606 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
608 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
609 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
610 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
612 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
613 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
614 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
616 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
617 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
618 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
620 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
621 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
622 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
623 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
625 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
626 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
627 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
629 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
630 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
631 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
632 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
633 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
634 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
635 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
637 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
638 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
639 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
640 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
641 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
642 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
643 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
646 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
647 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
648 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
649 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
650 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
651 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
653 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
654 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
655 PINMUX_IPSR_GPSR(IP1_7_4, A25),
656 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
657 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
658 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
659 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
661 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
662 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
663 PINMUX_IPSR_GPSR(IP1_11_8, A24),
664 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
665 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
666 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
667 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
669 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
670 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
671 PINMUX_IPSR_GPSR(IP1_15_12, A23),
672 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
673 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
674 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
675 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
676 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
678 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
679 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
680 PINMUX_IPSR_GPSR(IP1_19_16, A22),
681 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
682 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
684 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
685 PINMUX_IPSR_GPSR(IP1_23_20, A21),
686 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
687 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
688 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
690 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
691 PINMUX_IPSR_GPSR(IP1_27_24, A20),
692 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
693 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
695 PINMUX_IPSR_GPSR(IP1_31_28, A0),
696 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
697 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
698 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
699 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
700 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
703 PINMUX_IPSR_GPSR(IP2_3_0, A1),
704 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
705 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
706 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
707 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
708 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
710 PINMUX_IPSR_GPSR(IP2_7_4, A2),
711 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
712 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
713 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
714 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
715 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
717 PINMUX_IPSR_GPSR(IP2_11_8, A3),
718 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
719 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
720 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
721 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
722 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
724 PINMUX_IPSR_GPSR(IP2_15_12, A4),
725 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
726 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
727 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
728 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
729 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
731 PINMUX_IPSR_GPSR(IP2_19_16, A5),
732 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
733 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
734 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
735 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
736 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
737 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
739 PINMUX_IPSR_GPSR(IP2_23_20, A6),
740 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
741 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
742 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
743 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
744 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
745 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
747 PINMUX_IPSR_GPSR(IP2_27_24, A7),
748 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
749 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
750 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
751 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
752 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
753 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
755 PINMUX_IPSR_GPSR(IP2_31_28, A8),
756 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
757 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
758 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
759 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
760 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
761 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
764 PINMUX_IPSR_GPSR(IP3_3_0, A9),
765 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
766 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
767 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
769 PINMUX_IPSR_GPSR(IP3_7_4, A10),
770 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
771 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
772 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
774 PINMUX_IPSR_GPSR(IP3_11_8, A11),
775 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
776 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
777 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
778 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
779 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
780 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
781 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
782 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
784 PINMUX_IPSR_GPSR(IP3_15_12, A12),
785 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
786 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
787 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
788 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
789 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
791 PINMUX_IPSR_GPSR(IP3_19_16, A13),
792 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
793 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
794 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
795 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
796 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
798 PINMUX_IPSR_GPSR(IP3_23_20, A14),
799 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
800 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
801 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
802 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
803 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
805 PINMUX_IPSR_GPSR(IP3_27_24, A15),
806 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
807 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
808 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
809 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
810 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
812 PINMUX_IPSR_GPSR(IP3_31_28, A16),
813 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
814 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
815 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
818 PINMUX_IPSR_GPSR(IP4_3_0, A17),
819 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
820 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
821 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
823 PINMUX_IPSR_GPSR(IP4_7_4, A18),
824 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
825 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
826 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
828 PINMUX_IPSR_GPSR(IP4_11_8, A19),
829 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
830 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
831 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
833 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
834 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
836 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26),
837 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
838 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
840 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
841 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
842 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
843 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
844 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
845 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
846 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
847 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
849 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
850 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
851 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
852 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
853 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
854 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
856 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
857 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
858 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
859 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
860 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
861 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
864 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
865 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
866 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
867 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
868 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
869 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
870 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
872 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
873 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
874 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS),
875 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
876 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
877 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
878 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
879 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
881 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
882 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
883 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
884 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
886 PINMUX_IPSR_GPSR(IP5_15_12, D0),
887 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
888 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
889 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
890 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
892 PINMUX_IPSR_GPSR(IP5_19_16, D1),
893 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
894 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
895 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
896 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
898 PINMUX_IPSR_GPSR(IP5_23_20, D2),
899 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
900 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
901 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
903 PINMUX_IPSR_GPSR(IP5_27_24, D3),
904 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
905 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
906 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
908 PINMUX_IPSR_GPSR(IP5_31_28, D4),
909 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
910 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
911 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
914 PINMUX_IPSR_GPSR(IP6_3_0, D5),
915 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
916 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
917 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
919 PINMUX_IPSR_GPSR(IP6_7_4, D6),
920 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
921 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
922 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
924 PINMUX_IPSR_GPSR(IP6_11_8, D7),
925 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
926 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
927 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
929 PINMUX_IPSR_GPSR(IP6_15_12, D8),
930 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
931 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
932 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
933 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
934 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
936 PINMUX_IPSR_GPSR(IP6_19_16, D9),
937 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
938 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
939 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
940 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
942 PINMUX_IPSR_GPSR(IP6_23_20, D10),
943 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
944 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
945 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
946 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
947 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
948 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
950 PINMUX_IPSR_GPSR(IP6_27_24, D11),
951 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
952 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
953 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
954 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
955 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
956 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
958 PINMUX_IPSR_GPSR(IP6_31_28, D12),
959 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
960 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
961 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
962 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
963 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
966 PINMUX_IPSR_GPSR(IP7_3_0, D13),
967 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
968 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
969 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
970 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
971 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
973 PINMUX_IPSR_GPSR(IP7_7_4, D14),
974 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
975 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
976 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
977 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
978 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
979 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
981 PINMUX_IPSR_GPSR(IP7_11_8, D15),
982 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
983 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
984 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
985 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
986 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
987 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
989 PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST),
991 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
992 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
993 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
995 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
996 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
997 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
999 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
1000 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1001 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1002 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
1004 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1005 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1006 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1007 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1010 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1011 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1012 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1013 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1015 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1016 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1017 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1018 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1020 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1021 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1022 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1024 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1025 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1026 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
1027 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1028 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1030 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1031 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1032 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1033 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
1034 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1035 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1037 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1038 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1039 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1040 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
1041 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1042 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1044 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1045 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1046 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1047 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
1048 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1049 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1051 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1052 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1053 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1054 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
1055 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1056 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1059 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1060 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1062 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1063 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1065 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1066 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1068 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1069 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1071 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1072 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1074 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1075 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1077 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1078 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1079 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
1081 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1082 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1085 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1086 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1088 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1089 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1091 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1092 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1094 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1095 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1097 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1098 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1100 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1101 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1102 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1104 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1105 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1106 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1108 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1109 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1110 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1113 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1114 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1115 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1117 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1118 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1120 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1121 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1122 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1124 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1125 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1127 PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
1128 PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1130 PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
1131 PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
1133 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1134 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1135 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1136 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
1137 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1138 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1139 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1140 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1141 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1142 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1144 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1145 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1146 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1147 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1148 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1151 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1152 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1153 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1154 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1155 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1157 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1158 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1159 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1160 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1161 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1162 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1163 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1164 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1166 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N_TANS),
1167 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1168 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1169 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
1170 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1171 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1172 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1173 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1175 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1176 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1177 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1178 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1179 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1181 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1182 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1183 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1184 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1185 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1187 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1188 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1189 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1190 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1191 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1192 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1193 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1195 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N_TANS),
1196 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1197 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1198 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1199 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1200 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1201 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1203 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1204 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF1_1),
1205 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1206 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1207 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1208 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1209 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1212 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1213 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1214 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1215 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1216 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1217 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1219 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1220 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1221 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1222 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1223 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1224 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1226 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1227 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1228 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
1229 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1),
1230 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1231 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1232 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1233 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1235 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1236 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1237 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1),
1238 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1239 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1240 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1242 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1243 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1244 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1),
1245 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1246 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1247 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1249 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1250 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1251 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1252 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0),
1253 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1254 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1255 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1256 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1258 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1259 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1260 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1261 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0),
1262 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1263 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1264 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1266 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1267 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1268 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1269 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1272 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1273 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1274 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
1275 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
1276 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0),
1277 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1278 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1279 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1281 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1282 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1283 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1284 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
1285 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0),
1286 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1287 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1288 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1290 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1291 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1292 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1294 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1295 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1296 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1297 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1299 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1300 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1301 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1303 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1304 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1306 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1307 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1309 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1310 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1313 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0),
1315 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0),
1316 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1),
1318 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1319 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1320 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1322 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1323 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1324 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1325 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1327 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1328 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1329 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1330 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1331 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1332 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1333 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1335 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1336 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1337 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1338 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1339 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1340 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1341 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1343 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1344 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1345 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1346 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1347 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1348 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1349 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1351 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1352 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1353 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1354 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1355 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1356 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1357 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1360 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1361 PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN),
1362 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1364 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1365 PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC),
1366 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1368 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1369 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1370 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1372 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1373 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1374 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1375 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1376 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1377 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1378 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1380 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1381 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1382 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1383 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1384 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1385 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1386 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1388 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1389 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1390 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1391 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1392 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1393 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1394 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1395 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU_0),
1397 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1398 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1399 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1400 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1401 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1402 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1403 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1405 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0),
1406 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1407 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1408 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1409 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1),
1410 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1411 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1412 PINMUX_IPSR_GPSR(IP16_31_28, SCK5_A),
1415 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1416 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1418 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
1419 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF1_0),
1420 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1421 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1422 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1424 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1425 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1426 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1427 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1428 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1429 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1430 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1432 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1433 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1434 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1435 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1436 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1437 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1439 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1440 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1441 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0),
1442 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1443 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1444 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1445 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1446 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1447 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1449 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1450 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1451 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0),
1452 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1453 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1454 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1455 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1456 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1457 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1459 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1460 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1461 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1),
1462 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1463 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_2),
1464 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1465 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1466 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU_1),
1467 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1468 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1469 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1471 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1472 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1473 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1),
1474 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1475 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1476 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1477 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1478 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1479 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1482 PINMUX_IPSR_GPSR(IP18_3_0, USB3_PWEN),
1483 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1484 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1),
1485 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1486 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1487 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1488 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1489 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1490 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1492 PINMUX_IPSR_GPSR(IP18_7_4, USB3_OVC),
1493 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1494 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1),
1495 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1496 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1497 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1498 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1499 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1500 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1503 * Static pins can not be muxed between different functions but
1504 * still needs a mark entry in the pinmux list. Add each static
1505 * pin to the list without an associated function. The sh-pfc
1506 * core will do the right thing and skip trying to mux then pin
1507 * while still applying configuration to it
1509 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1515 * R8A7795 has 8 banks with 32 PGIOS in each => 256 GPIOs.
1516 * Physical layout rows: A - AW, cols: 1 - 39.
1518 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1519 #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1520 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1522 static const struct sh_pfc_pin pinmux_pins[] = {
1523 PINMUX_GPIO_GP_ALL(),
1526 * Pins not associated with a GPIO port.
1528 * The pin positions are different between different r8a7795
1529 * packages, all that is needed for the pfc driver is a unique
1530 * number for each pin. To this end use the pin layout from
1531 * R-Car H3SiP to calculate a unique number for each pin.
1533 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1534 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1535 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1536 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1537 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1538 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1539 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1540 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1573 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1574 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1575 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1576 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1579 /* - EtherAVB --------------------------------------------------------------- */
1580 static const unsigned int avb_link_pins[] = {
1584 static const unsigned int avb_link_mux[] = {
1587 static const unsigned int avb_magic_pins[] = {
1591 static const unsigned int avb_magic_mux[] = {
1594 static const unsigned int avb_phy_int_pins[] = {
1598 static const unsigned int avb_phy_int_mux[] = {
1601 static const unsigned int avb_mdc_pins[] = {
1602 /* AVB_MDC, AVB_MDIO */
1603 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1605 static const unsigned int avb_mdc_mux[] = {
1606 AVB_MDC_MARK, AVB_MDIO_MARK,
1608 static const unsigned int avb_mii_pins[] = {
1610 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1611 * AVB_TD1, AVB_TD2, AVB_TD3,
1612 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1613 * AVB_RD1, AVB_RD2, AVB_RD3,
1616 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1617 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1618 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1619 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1620 PIN_NUMBER('A', 12),
1623 static const unsigned int avb_mii_mux[] = {
1624 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1625 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1626 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1627 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1630 static const unsigned int avb_avtp_pps_pins[] = {
1634 static const unsigned int avb_avtp_pps_mux[] = {
1637 static const unsigned int avb_avtp_match_a_pins[] = {
1638 /* AVB_AVTP_MATCH_A */
1641 static const unsigned int avb_avtp_match_a_mux[] = {
1642 AVB_AVTP_MATCH_A_MARK,
1644 static const unsigned int avb_avtp_capture_a_pins[] = {
1645 /* AVB_AVTP_CAPTURE_A */
1648 static const unsigned int avb_avtp_capture_a_mux[] = {
1649 AVB_AVTP_CAPTURE_A_MARK,
1651 static const unsigned int avb_avtp_match_b_pins[] = {
1652 /* AVB_AVTP_MATCH_B */
1655 static const unsigned int avb_avtp_match_b_mux[] = {
1656 AVB_AVTP_MATCH_B_MARK,
1658 static const unsigned int avb_avtp_capture_b_pins[] = {
1659 /* AVB_AVTP_CAPTURE_B */
1662 static const unsigned int avb_avtp_capture_b_mux[] = {
1663 AVB_AVTP_CAPTURE_B_MARK,
1666 /* - SCIF0 ------------------------------------------------------------------ */
1667 static const unsigned int scif0_data_pins[] = {
1669 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1671 static const unsigned int scif0_data_mux[] = {
1674 static const unsigned int scif0_clk_pins[] = {
1678 static const unsigned int scif0_clk_mux[] = {
1681 static const unsigned int scif0_ctrl_pins[] = {
1683 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
1685 static const unsigned int scif0_ctrl_mux[] = {
1686 RTS0_N_TANS_MARK, CTS0_N_MARK,
1688 /* - SCIF1 ------------------------------------------------------------------ */
1689 static const unsigned int scif1_data_a_pins[] = {
1691 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
1693 static const unsigned int scif1_data_a_mux[] = {
1694 RX1_A_MARK, TX1_A_MARK,
1696 static const unsigned int scif1_clk_pins[] = {
1700 static const unsigned int scif1_clk_mux[] = {
1703 static const unsigned int scif1_ctrl_pins[] = {
1705 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
1707 static const unsigned int scif1_ctrl_mux[] = {
1708 RTS1_N_TANS_MARK, CTS1_N_MARK,
1711 static const unsigned int scif1_data_b_pins[] = {
1713 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
1715 static const unsigned int scif1_data_b_mux[] = {
1716 RX1_B_MARK, TX1_B_MARK,
1718 /* - SCIF2 ------------------------------------------------------------------ */
1719 static const unsigned int scif2_data_a_pins[] = {
1721 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
1723 static const unsigned int scif2_data_a_mux[] = {
1724 RX2_A_MARK, TX2_A_MARK,
1726 static const unsigned int scif2_clk_pins[] = {
1730 static const unsigned int scif2_clk_mux[] = {
1733 static const unsigned int scif2_data_b_pins[] = {
1735 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
1737 static const unsigned int scif2_data_b_mux[] = {
1738 RX2_B_MARK, TX2_B_MARK,
1740 /* - SCIF3 ------------------------------------------------------------------ */
1741 static const unsigned int scif3_data_a_pins[] = {
1743 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1745 static const unsigned int scif3_data_a_mux[] = {
1746 RX3_A_MARK, TX3_A_MARK,
1748 static const unsigned int scif3_clk_pins[] = {
1752 static const unsigned int scif3_clk_mux[] = {
1755 static const unsigned int scif3_ctrl_pins[] = {
1757 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
1759 static const unsigned int scif3_ctrl_mux[] = {
1760 RTS3_N_TANS_MARK, CTS3_N_MARK,
1762 static const unsigned int scif3_data_b_pins[] = {
1764 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
1766 static const unsigned int scif3_data_b_mux[] = {
1767 RX3_B_MARK, TX3_B_MARK,
1769 /* - SCIF4 ------------------------------------------------------------------ */
1770 static const unsigned int scif4_data_a_pins[] = {
1772 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1774 static const unsigned int scif4_data_a_mux[] = {
1775 RX4_A_MARK, TX4_A_MARK,
1777 static const unsigned int scif4_clk_a_pins[] = {
1781 static const unsigned int scif4_clk_a_mux[] = {
1784 static const unsigned int scif4_ctrl_a_pins[] = {
1786 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1788 static const unsigned int scif4_ctrl_a_mux[] = {
1789 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
1791 static const unsigned int scif4_data_b_pins[] = {
1793 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
1795 static const unsigned int scif4_data_b_mux[] = {
1796 RX4_B_MARK, TX4_B_MARK,
1798 static const unsigned int scif4_clk_b_pins[] = {
1802 static const unsigned int scif4_clk_b_mux[] = {
1805 static const unsigned int scif4_ctrl_b_pins[] = {
1807 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
1809 static const unsigned int scif4_ctrl_b_mux[] = {
1810 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
1812 static const unsigned int scif4_data_c_pins[] = {
1814 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1816 static const unsigned int scif4_data_c_mux[] = {
1817 RX4_C_MARK, TX4_C_MARK,
1819 static const unsigned int scif4_clk_c_pins[] = {
1823 static const unsigned int scif4_clk_c_mux[] = {
1826 static const unsigned int scif4_ctrl_c_pins[] = {
1828 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1830 static const unsigned int scif4_ctrl_c_mux[] = {
1831 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
1833 /* - SCIF5 ------------------------------------------------------------------ */
1834 static const unsigned int scif5_data_a_pins[] = {
1836 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
1838 static const unsigned int scif5_data_a_mux[] = {
1839 RX5_A_MARK, TX5_A_MARK,
1841 static const unsigned int scif5_clk_a_pins[] = {
1845 static const unsigned int scif5_clk_a_mux[] = {
1848 static const unsigned int scif5_data_b_pins[] = {
1850 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
1852 static const unsigned int scif5_data_b_mux[] = {
1853 RX5_B_MARK, TX5_B_MARK,
1855 static const unsigned int scif5_clk_b_pins[] = {
1859 static const unsigned int scif5_clk_b_mux[] = {
1863 /* - SCIF Clock ------------------------------------------------------------- */
1864 static const unsigned int scif_clk_a_pins[] = {
1868 static const unsigned int scif_clk_a_mux[] = {
1871 static const unsigned int scif_clk_b_pins[] = {
1875 static const unsigned int scif_clk_b_mux[] = {
1879 static const struct sh_pfc_pin_group pinmux_groups[] = {
1880 SH_PFC_PIN_GROUP(avb_link),
1881 SH_PFC_PIN_GROUP(avb_magic),
1882 SH_PFC_PIN_GROUP(avb_phy_int),
1883 SH_PFC_PIN_GROUP(avb_mdc),
1884 SH_PFC_PIN_GROUP(avb_mii),
1885 SH_PFC_PIN_GROUP(avb_avtp_pps),
1886 SH_PFC_PIN_GROUP(avb_avtp_match_a),
1887 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
1888 SH_PFC_PIN_GROUP(avb_avtp_match_b),
1889 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
1890 SH_PFC_PIN_GROUP(scif0_data),
1891 SH_PFC_PIN_GROUP(scif0_clk),
1892 SH_PFC_PIN_GROUP(scif0_ctrl),
1893 SH_PFC_PIN_GROUP(scif1_data_a),
1894 SH_PFC_PIN_GROUP(scif1_clk),
1895 SH_PFC_PIN_GROUP(scif1_ctrl),
1896 SH_PFC_PIN_GROUP(scif1_data_b),
1897 SH_PFC_PIN_GROUP(scif2_data_a),
1898 SH_PFC_PIN_GROUP(scif2_clk),
1899 SH_PFC_PIN_GROUP(scif2_data_b),
1900 SH_PFC_PIN_GROUP(scif3_data_a),
1901 SH_PFC_PIN_GROUP(scif3_clk),
1902 SH_PFC_PIN_GROUP(scif3_ctrl),
1903 SH_PFC_PIN_GROUP(scif3_data_b),
1904 SH_PFC_PIN_GROUP(scif4_data_a),
1905 SH_PFC_PIN_GROUP(scif4_clk_a),
1906 SH_PFC_PIN_GROUP(scif4_ctrl_a),
1907 SH_PFC_PIN_GROUP(scif4_data_b),
1908 SH_PFC_PIN_GROUP(scif4_clk_b),
1909 SH_PFC_PIN_GROUP(scif4_ctrl_b),
1910 SH_PFC_PIN_GROUP(scif4_data_c),
1911 SH_PFC_PIN_GROUP(scif4_clk_c),
1912 SH_PFC_PIN_GROUP(scif4_ctrl_c),
1913 SH_PFC_PIN_GROUP(scif5_data_a),
1914 SH_PFC_PIN_GROUP(scif5_clk_a),
1915 SH_PFC_PIN_GROUP(scif5_data_b),
1916 SH_PFC_PIN_GROUP(scif5_clk_b),
1917 SH_PFC_PIN_GROUP(scif_clk_a),
1918 SH_PFC_PIN_GROUP(scif_clk_b),
1921 static const char * const avb_groups[] = {
1929 "avb_avtp_capture_a",
1931 "avb_avtp_capture_b",
1934 static const char * const scif0_groups[] = {
1940 static const char * const scif1_groups[] = {
1947 static const char * const scif2_groups[] = {
1953 static const char * const scif3_groups[] = {
1960 static const char * const scif4_groups[] = {
1972 static const char * const scif5_groups[] = {
1979 static const char * const scif_clk_groups[] = {
1984 static const struct sh_pfc_function pinmux_functions[] = {
1985 SH_PFC_FUNCTION(avb),
1986 SH_PFC_FUNCTION(scif0),
1987 SH_PFC_FUNCTION(scif1),
1988 SH_PFC_FUNCTION(scif2),
1989 SH_PFC_FUNCTION(scif3),
1990 SH_PFC_FUNCTION(scif4),
1991 SH_PFC_FUNCTION(scif5),
1992 SH_PFC_FUNCTION(scif_clk),
1995 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1996 #define F_(x, y) FN_##y
1997 #define FM(x) FN_##x
1998 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
2015 GP_0_15_FN, GPSR0_15,
2016 GP_0_14_FN, GPSR0_14,
2017 GP_0_13_FN, GPSR0_13,
2018 GP_0_12_FN, GPSR0_12,
2019 GP_0_11_FN, GPSR0_11,
2020 GP_0_10_FN, GPSR0_10,
2030 GP_0_0_FN, GPSR0_0, }
2032 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
2037 GP_1_27_FN, GPSR1_27,
2038 GP_1_26_FN, GPSR1_26,
2039 GP_1_25_FN, GPSR1_25,
2040 GP_1_24_FN, GPSR1_24,
2041 GP_1_23_FN, GPSR1_23,
2042 GP_1_22_FN, GPSR1_22,
2043 GP_1_21_FN, GPSR1_21,
2044 GP_1_20_FN, GPSR1_20,
2045 GP_1_19_FN, GPSR1_19,
2046 GP_1_18_FN, GPSR1_18,
2047 GP_1_17_FN, GPSR1_17,
2048 GP_1_16_FN, GPSR1_16,
2049 GP_1_15_FN, GPSR1_15,
2050 GP_1_14_FN, GPSR1_14,
2051 GP_1_13_FN, GPSR1_13,
2052 GP_1_12_FN, GPSR1_12,
2053 GP_1_11_FN, GPSR1_11,
2054 GP_1_10_FN, GPSR1_10,
2064 GP_1_0_FN, GPSR1_0, }
2066 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
2084 GP_2_14_FN, GPSR2_14,
2085 GP_2_13_FN, GPSR2_13,
2086 GP_2_12_FN, GPSR2_12,
2087 GP_2_11_FN, GPSR2_11,
2088 GP_2_10_FN, GPSR2_10,
2098 GP_2_0_FN, GPSR2_0, }
2100 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
2117 GP_3_15_FN, GPSR3_15,
2118 GP_3_14_FN, GPSR3_14,
2119 GP_3_13_FN, GPSR3_13,
2120 GP_3_12_FN, GPSR3_12,
2121 GP_3_11_FN, GPSR3_11,
2122 GP_3_10_FN, GPSR3_10,
2132 GP_3_0_FN, GPSR3_0, }
2134 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
2149 GP_4_17_FN, GPSR4_17,
2150 GP_4_16_FN, GPSR4_16,
2151 GP_4_15_FN, GPSR4_15,
2152 GP_4_14_FN, GPSR4_14,
2153 GP_4_13_FN, GPSR4_13,
2154 GP_4_12_FN, GPSR4_12,
2155 GP_4_11_FN, GPSR4_11,
2156 GP_4_10_FN, GPSR4_10,
2166 GP_4_0_FN, GPSR4_0, }
2168 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
2175 GP_5_25_FN, GPSR5_25,
2176 GP_5_24_FN, GPSR5_24,
2177 GP_5_23_FN, GPSR5_23,
2178 GP_5_22_FN, GPSR5_22,
2179 GP_5_21_FN, GPSR5_21,
2180 GP_5_20_FN, GPSR5_20,
2181 GP_5_19_FN, GPSR5_19,
2182 GP_5_18_FN, GPSR5_18,
2183 GP_5_17_FN, GPSR5_17,
2184 GP_5_16_FN, GPSR5_16,
2185 GP_5_15_FN, GPSR5_15,
2186 GP_5_14_FN, GPSR5_14,
2187 GP_5_13_FN, GPSR5_13,
2188 GP_5_12_FN, GPSR5_12,
2189 GP_5_11_FN, GPSR5_11,
2190 GP_5_10_FN, GPSR5_10,
2200 GP_5_0_FN, GPSR5_0, }
2202 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
2203 GP_6_31_FN, GPSR6_31,
2204 GP_6_30_FN, GPSR6_30,
2205 GP_6_29_FN, GPSR6_29,
2206 GP_6_28_FN, GPSR6_28,
2207 GP_6_27_FN, GPSR6_27,
2208 GP_6_26_FN, GPSR6_26,
2209 GP_6_25_FN, GPSR6_25,
2210 GP_6_24_FN, GPSR6_24,
2211 GP_6_23_FN, GPSR6_23,
2212 GP_6_22_FN, GPSR6_22,
2213 GP_6_21_FN, GPSR6_21,
2214 GP_6_20_FN, GPSR6_20,
2215 GP_6_19_FN, GPSR6_19,
2216 GP_6_18_FN, GPSR6_18,
2217 GP_6_17_FN, GPSR6_17,
2218 GP_6_16_FN, GPSR6_16,
2219 GP_6_15_FN, GPSR6_15,
2220 GP_6_14_FN, GPSR6_14,
2221 GP_6_13_FN, GPSR6_13,
2222 GP_6_12_FN, GPSR6_12,
2223 GP_6_11_FN, GPSR6_11,
2224 GP_6_10_FN, GPSR6_10,
2234 GP_6_0_FN, GPSR6_0, }
2236 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
2268 GP_7_0_FN, GPSR7_0, }
2274 #define FM(x) FN_##x,
2275 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
2285 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
2295 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
2305 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
2315 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
2325 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
2335 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
2345 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
2355 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
2365 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
2375 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
2385 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
2395 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
2405 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
2415 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
2425 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
2435 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
2445 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
2455 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
2456 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2457 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2458 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2459 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2460 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2461 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2469 #define FM(x) FN_##x,
2470 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2471 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
2472 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
2483 0, 0, /* RESERVED 15 */
2492 /* RESERVED 2, 1, 0 */
2493 0, 0, 0, 0, 0, 0, 0, 0 }
2495 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
2496 2, 3, 1, 2, 3, 1, 1, 2, 1,
2497 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
2513 0, 0, 0, 0, /* RESERVED 8, 7 */
2522 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
2523 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
2539 /* RESERVED 15, 14, 13, 12 */
2540 0, 0, 0, 0, 0, 0, 0, 0,
2541 0, 0, 0, 0, 0, 0, 0, 0,
2542 /* RESERVED 11, 10, 9, 8 */
2543 0, 0, 0, 0, 0, 0, 0, 0,
2544 0, 0, 0, 0, 0, 0, 0, 0,
2545 /* RESERVED 7, 6, 5, 4 */
2546 0, 0, 0, 0, 0, 0, 0, 0,
2547 0, 0, 0, 0, 0, 0, 0, 0,
2548 /* RESERVED 3, 2, 1 */
2549 0, 0, 0, 0, 0, 0, 0, 0,
2555 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
2556 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
2557 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
2558 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
2559 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
2560 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
2561 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
2562 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
2563 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
2564 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
2566 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
2567 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
2568 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
2569 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
2570 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
2571 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
2572 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
2573 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
2574 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
2576 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
2577 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
2578 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
2579 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
2580 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
2581 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
2582 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
2583 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
2584 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
2586 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
2587 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
2588 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
2589 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
2590 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
2591 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
2592 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
2593 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
2594 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
2596 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
2597 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
2598 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
2599 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
2600 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
2601 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
2602 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
2603 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
2604 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
2606 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
2607 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
2608 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
2609 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
2610 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
2611 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
2612 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
2613 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
2614 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
2616 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
2617 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
2618 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
2619 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
2620 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
2621 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
2622 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
2623 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
2624 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
2626 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
2627 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
2628 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
2629 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
2630 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
2631 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
2632 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
2633 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
2634 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
2636 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
2637 { PIN_NUMBER('F', 1), 28, 3 }, /* CLKOUT */
2638 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
2639 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
2640 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
2641 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
2642 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
2643 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
2644 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
2646 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
2647 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
2648 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
2649 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
2650 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
2651 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
2652 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
2653 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
2654 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
2656 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
2657 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
2658 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
2659 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
2660 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
2661 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
2662 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
2663 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
2664 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
2666 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
2667 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
2668 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
2669 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
2670 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
2671 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
2672 { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
2673 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
2674 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
2676 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
2677 { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */
2678 { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */
2679 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */
2680 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
2682 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
2683 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
2684 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
2685 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
2686 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
2687 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
2688 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
2689 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
2690 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
2692 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
2693 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
2694 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
2695 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
2696 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
2697 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
2698 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
2699 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
2700 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
2702 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
2703 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
2704 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
2705 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
2706 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
2707 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
2708 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
2709 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
2710 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
2712 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
2713 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
2714 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
2715 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
2716 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
2717 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
2718 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
2719 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
2720 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
2722 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
2723 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
2724 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
2725 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
2726 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
2727 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
2728 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
2729 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
2730 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
2732 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
2733 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */
2734 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
2735 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
2736 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
2737 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */
2738 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
2739 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
2740 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
2742 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
2743 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
2744 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
2745 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
2746 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
2747 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
2748 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
2749 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
2750 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
2752 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
2753 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
2754 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
2755 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
2756 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
2757 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
2758 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
2759 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
2760 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
2762 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
2763 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
2764 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
2765 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
2766 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
2767 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
2768 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
2769 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
2770 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
2772 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
2773 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
2774 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
2775 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
2776 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
2777 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
2778 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
2779 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
2780 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
2782 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
2783 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
2784 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
2785 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
2786 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
2787 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
2788 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
2789 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
2790 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
2792 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
2793 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
2794 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
2795 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
2796 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
2797 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
2798 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB3_PWEN */
2799 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB3_OVC */
2804 static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
2808 *pocctrl = 0xe6060380;
2810 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
2813 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
2814 bit = (pin & 0x1f) + 12;
2819 #define PUEN 0xe6060400
2820 #define PUD 0xe6060440
2830 static const struct sh_pfc_bias_info bias_info[] = {
2831 { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */
2832 { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */
2833 { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */
2834 { PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */
2835 { PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */
2836 { PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */
2837 { PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */
2838 { PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */
2839 { PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */
2840 { PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */
2841 { PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */
2842 { PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */
2843 { PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */
2844 { PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */
2845 { PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */
2846 { PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */
2847 { PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */
2848 { PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */
2849 { PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */
2850 { PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */
2851 { PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */
2852 { PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */
2853 { PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */
2854 { PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */
2855 { PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */
2856 { PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */
2857 { PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */
2858 { PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */
2859 { PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */
2860 { PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */
2861 { PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */
2862 { PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */
2864 { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */
2865 { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */
2866 { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */
2867 { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */
2868 { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */
2869 { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */
2870 { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */
2871 { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */
2872 { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */
2873 { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */
2874 { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */
2875 { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */
2876 { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */
2877 { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */
2878 { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */
2879 { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */
2880 { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */
2881 { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */
2882 { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */
2883 { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */
2884 { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */
2885 { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */
2886 { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */
2887 { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */
2888 { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */
2889 { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */
2890 { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */
2891 { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */
2892 { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */
2893 { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
2894 { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */
2895 { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */
2897 { PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */
2898 { PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */
2899 { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */
2900 { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */
2901 { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */
2902 { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */
2903 { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */
2904 { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */
2905 { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */
2906 { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */
2907 { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */
2908 { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */
2909 { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */
2910 { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */
2911 { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */
2912 { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */
2913 { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */
2914 { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */
2915 { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */
2916 { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */
2917 { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */
2918 { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */
2919 { PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */
2920 { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */
2921 { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */
2922 { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */
2923 { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
2924 { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
2925 { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
2926 { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */
2927 { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
2928 { PIN_NUMBER('F', 1), PU2, 0 }, /* CLKOUT */
2930 { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */
2931 { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */
2932 { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */
2933 { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */
2934 { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */
2935 { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */
2936 { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */
2937 { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */
2938 { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */
2939 { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */
2940 { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */
2941 { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */
2942 { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */
2943 { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */
2944 { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */
2945 { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */
2946 { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */
2947 { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */
2948 { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */
2949 { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */
2950 { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */
2951 { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */
2952 { PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */
2954 { PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */
2955 { PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */
2956 { PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */
2957 { PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */
2958 { PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/
2959 { PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST# */
2960 { PIN_A_NUMBER('R', 8), PU3, 1 }, /* DU_DOTCLKIN3 */
2961 { PIN_A_NUMBER('R', 7), PU3, 0 }, /* DU_DOTCLKIN2 */
2963 { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */
2964 { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */
2965 { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */
2966 { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */
2967 { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */
2968 { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */
2969 { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */
2970 { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */
2971 { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */
2972 { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */
2973 { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */
2974 { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */
2975 { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */
2976 { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */
2977 { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */
2978 { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */
2979 { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */
2980 { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */
2981 { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */
2982 { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */
2983 { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */
2984 { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */
2985 { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */
2986 { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */
2987 { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */
2988 { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */
2989 { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */
2990 { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */
2991 { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */
2992 { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */
2993 { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */
2994 { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */
2996 { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */
2997 { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */
2998 { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */
2999 { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */
3000 { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */
3001 { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */
3002 { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */
3003 { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */
3004 { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */
3005 { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */
3006 { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */
3007 { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */
3008 { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */
3009 { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */
3010 { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */
3011 { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
3012 { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
3013 { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
3014 { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS349 */
3015 { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK349 */
3016 { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
3017 { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
3018 { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
3019 { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */
3020 { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */
3021 { PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */
3022 { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */
3023 { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */
3024 { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */
3025 { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */
3026 { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */
3027 { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */
3029 { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB3_OVC */
3030 { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB3_PWEN */
3031 { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */
3032 { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */
3033 { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */
3034 { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */
3035 { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */
3038 static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
3041 const struct sh_pfc_bias_info *info;
3045 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
3047 return PIN_CONFIG_BIAS_DISABLE;
3050 bit = BIT(info->bit);
3052 if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
3053 return PIN_CONFIG_BIAS_DISABLE;
3054 else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
3055 return PIN_CONFIG_BIAS_PULL_UP;
3057 return PIN_CONFIG_BIAS_PULL_DOWN;
3060 static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3063 const struct sh_pfc_bias_info *info;
3068 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
3073 bit = BIT(info->bit);
3075 enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
3076 if (bias != PIN_CONFIG_BIAS_DISABLE)
3079 updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit;
3080 if (bias == PIN_CONFIG_BIAS_PULL_UP)
3083 sh_pfc_write_reg(pfc, PUD + reg, 32, updown);
3084 sh_pfc_write_reg(pfc, PUEN + reg, 32, enable);
3087 static const struct soc_device_attribute r8a7795es1[] = {
3088 { .soc_id = "r8a7795", .revision = "ES1.*" },
3092 static int r8a7795_pinmux_init(struct sh_pfc *pfc)
3094 if (soc_device_match(r8a7795es1))
3095 pfc->info = &r8a7795es1_pinmux_info;
3100 static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
3101 .init = r8a7795_pinmux_init,
3102 .pin_to_pocctrl = r8a7795_pin_to_pocctrl,
3103 .get_bias = r8a7795_pinmux_get_bias,
3104 .set_bias = r8a7795_pinmux_set_bias,
3107 const struct sh_pfc_soc_info r8a7795_pinmux_info = {
3108 .name = "r8a77951_pfc",
3109 .ops = &r8a7795_pinmux_ops,
3110 .unlock_reg = 0xe6060000, /* PMMR */
3112 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3114 .pins = pinmux_pins,
3115 .nr_pins = ARRAY_SIZE(pinmux_pins),
3116 .groups = pinmux_groups,
3117 .nr_groups = ARRAY_SIZE(pinmux_groups),
3118 .functions = pinmux_functions,
3119 .nr_functions = ARRAY_SIZE(pinmux_functions),
3121 .cfg_regs = pinmux_config_regs,
3122 .drive_regs = pinmux_drive_regs,
3124 .pinmux_data = pinmux_data,
3125 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
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