drivers/pinctrl/sh-pfc/pfc-r8a77965.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * R8A77965 processor support - PFC hardware block.
   4  *
   5  * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
   6  * Copyright (C) 2016 Renesas Electronics Corp.
   7  *
   8  * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
   9  *
  10  * R-Car Gen3 processor support - PFC hardware block.
  11  *
  12  * Copyright (C) 2015  Renesas Electronics Corporation
  13  */
  14
  15 #include <linux/kernel.h>
  16
  17 #include "core.h"
  18 #include "sh_pfc.h"
  19
  20 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
  21                    SH_PFC_PIN_CFG_PULL_UP | \
  22                    SH_PFC_PIN_CFG_PULL_DOWN)
  23
  24 #define CPU_ALL_PORT(fn, sfx)                                           \
  25         PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),  \
  26         PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS),  \
  27         PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),  \
  28         PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  29         PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),       \
  30         PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),       \
  31         PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),       \
  32         PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),       \
  33         PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  34         PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),  \
  35         PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),  \
  36         PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
  37 /*
  38  * F_() : just information
  39  * FM() : macro for FN_xxx / xxx_MARK
  40  */
  41
  42 /* GPSR0 */
  43 #define GPSR0_15        F_(D15,                 IP7_11_8)
  44 #define GPSR0_14        F_(D14,                 IP7_7_4)
  45 #define GPSR0_13        F_(D13,                 IP7_3_0)
  46 #define GPSR0_12        F_(D12,                 IP6_31_28)
  47 #define GPSR0_11        F_(D11,                 IP6_27_24)
  48 #define GPSR0_10        F_(D10,                 IP6_23_20)
  49 #define GPSR0_9         F_(D9,                  IP6_19_16)
  50 #define GPSR0_8         F_(D8,                  IP6_15_12)
  51 #define GPSR0_7         F_(D7,                  IP6_11_8)
  52 #define GPSR0_6         F_(D6,                  IP6_7_4)
  53 #define GPSR0_5         F_(D5,                  IP6_3_0)
  54 #define GPSR0_4         F_(D4,                  IP5_31_28)
  55 #define GPSR0_3         F_(D3,                  IP5_27_24)
  56 #define GPSR0_2         F_(D2,                  IP5_23_20)
  57 #define GPSR0_1         F_(D1,                  IP5_19_16)
  58 #define GPSR0_0         F_(D0,                  IP5_15_12)
  59
  60 /* GPSR1 */
  61 #define GPSR1_28        FM(CLKOUT)
  62 #define GPSR1_27        F_(EX_WAIT0_A,          IP5_11_8)
  63 #define GPSR1_26        F_(WE1_N,               IP5_7_4)
  64 #define GPSR1_25        F_(WE0_N,               IP5_3_0)
  65 #define GPSR1_24        F_(RD_WR_N,             IP4_31_28)
  66 #define GPSR1_23        F_(RD_N,                IP4_27_24)
  67 #define GPSR1_22        F_(BS_N,                IP4_23_20)
  68 #define GPSR1_21        F_(CS1_N,               IP4_19_16)
  69 #define GPSR1_20        F_(CS0_N,               IP4_15_12)
  70 #define GPSR1_19        F_(A19,                 IP4_11_8)
  71 #define GPSR1_18        F_(A18,                 IP4_7_4)
  72 #define GPSR1_17        F_(A17,                 IP4_3_0)
  73 #define GPSR1_16        F_(A16,                 IP3_31_28)
  74 #define GPSR1_15        F_(A15,                 IP3_27_24)
  75 #define GPSR1_14        F_(A14,                 IP3_23_20)
  76 #define GPSR1_13        F_(A13,                 IP3_19_16)
  77 #define GPSR1_12        F_(A12,                 IP3_15_12)
  78 #define GPSR1_11        F_(A11,                 IP3_11_8)
  79 #define GPSR1_10        F_(A10,                 IP3_7_4)
  80 #define GPSR1_9         F_(A9,                  IP3_3_0)
  81 #define GPSR1_8         F_(A8,                  IP2_31_28)
  82 #define GPSR1_7         F_(A7,                  IP2_27_24)
  83 #define GPSR1_6         F_(A6,                  IP2_23_20)
  84 #define GPSR1_5         F_(A5,                  IP2_19_16)
  85 #define GPSR1_4         F_(A4,                  IP2_15_12)
  86 #define GPSR1_3         F_(A3,                  IP2_11_8)
  87 #define GPSR1_2         F_(A2,                  IP2_7_4)
  88 #define GPSR1_1         F_(A1,                  IP2_3_0)
  89 #define GPSR1_0         F_(A0,                  IP1_31_28)
  90
  91 /* GPSR2 */
  92 #define GPSR2_14        F_(AVB_AVTP_CAPTURE_A,  IP0_23_20)
  93 #define GPSR2_13        F_(AVB_AVTP_MATCH_A,    IP0_19_16)
  94 #define GPSR2_12        F_(AVB_LINK,            IP0_15_12)
  95 #define GPSR2_11        F_(AVB_PHY_INT,         IP0_11_8)
  96 #define GPSR2_10        F_(AVB_MAGIC,           IP0_7_4)
  97 #define GPSR2_9         F_(AVB_MDC,             IP0_3_0)
  98 #define GPSR2_8         F_(PWM2_A,              IP1_27_24)
  99 #define GPSR2_7         F_(PWM1_A,              IP1_23_20)
 100 #define GPSR2_6         F_(PWM0,                IP1_19_16)
 101 #define GPSR2_5         F_(IRQ5,                IP1_15_12)
 102 #define GPSR2_4         F_(IRQ4,                IP1_11_8)
 103 #define GPSR2_3         F_(IRQ3,                IP1_7_4)
 104 #define GPSR2_2         F_(IRQ2,                IP1_3_0)
 105 #define GPSR2_1         F_(IRQ1,                IP0_31_28)
 106 #define GPSR2_0         F_(IRQ0,                IP0_27_24)
 107
 108 /* GPSR3 */
 109 #define GPSR3_15        F_(SD1_WP,              IP11_23_20)
 110 #define GPSR3_14        F_(SD1_CD,              IP11_19_16)
 111 #define GPSR3_13        F_(SD0_WP,              IP11_15_12)
 112 #define GPSR3_12        F_(SD0_CD,              IP11_11_8)
 113 #define GPSR3_11        F_(SD1_DAT3,            IP8_31_28)
 114 #define GPSR3_10        F_(SD1_DAT2,            IP8_27_24)
 115 #define GPSR3_9         F_(SD1_DAT1,            IP8_23_20)
 116 #define GPSR3_8         F_(SD1_DAT0,            IP8_19_16)
 117 #define GPSR3_7         F_(SD1_CMD,             IP8_15_12)
 118 #define GPSR3_6         F_(SD1_CLK,             IP8_11_8)
 119 #define GPSR3_5         F_(SD0_DAT3,            IP8_7_4)
 120 #define GPSR3_4         F_(SD0_DAT2,            IP8_3_0)
 121 #define GPSR3_3         F_(SD0_DAT1,            IP7_31_28)
 122 #define GPSR3_2         F_(SD0_DAT0,            IP7_27_24)
 123 #define GPSR3_1         F_(SD0_CMD,             IP7_23_20)
 124 #define GPSR3_0         F_(SD0_CLK,             IP7_19_16)
 125
 126 /* GPSR4 */
 127 #define GPSR4_17        F_(SD3_DS,              IP11_7_4)
 128 #define GPSR4_16        F_(SD3_DAT7,            IP11_3_0)
 129 #define GPSR4_15        F_(SD3_DAT6,            IP10_31_28)
 130 #define GPSR4_14        F_(SD3_DAT5,            IP10_27_24)
 131 #define GPSR4_13        F_(SD3_DAT4,            IP10_23_20)
 132 #define GPSR4_12        F_(SD3_DAT3,            IP10_19_16)
 133 #define GPSR4_11        F_(SD3_DAT2,            IP10_15_12)
 134 #define GPSR4_10        F_(SD3_DAT1,            IP10_11_8)
 135 #define GPSR4_9         F_(SD3_DAT0,            IP10_7_4)
 136 #define GPSR4_8         F_(SD3_CMD,             IP10_3_0)
 137 #define GPSR4_7         F_(SD3_CLK,             IP9_31_28)
 138 #define GPSR4_6         F_(SD2_DS,              IP9_27_24)
 139 #define GPSR4_5         F_(SD2_DAT3,            IP9_23_20)
 140 #define GPSR4_4         F_(SD2_DAT2,            IP9_19_16)
 141 #define GPSR4_3         F_(SD2_DAT1,            IP9_15_12)
 142 #define GPSR4_2         F_(SD2_DAT0,            IP9_11_8)
 143 #define GPSR4_1         F_(SD2_CMD,             IP9_7_4)
 144 #define GPSR4_0         F_(SD2_CLK,             IP9_3_0)
 145
 146 /* GPSR5 */
 147 #define GPSR5_25        F_(MLB_DAT,             IP14_19_16)
 148 #define GPSR5_24        F_(MLB_SIG,             IP14_15_12)
 149 #define GPSR5_23        F_(MLB_CLK,             IP14_11_8)
 150 #define GPSR5_22        FM(MSIOF0_RXD)
 151 #define GPSR5_21        F_(MSIOF0_SS2,          IP14_7_4)
 152 #define GPSR5_20        FM(MSIOF0_TXD)
 153 #define GPSR5_19        F_(MSIOF0_SS1,          IP14_3_0)
 154 #define GPSR5_18        F_(MSIOF0_SYNC,         IP13_31_28)
 155 #define GPSR5_17        FM(MSIOF0_SCK)
 156 #define GPSR5_16        F_(HRTS0_N,             IP13_27_24)
 157 #define GPSR5_15        F_(HCTS0_N,             IP13_23_20)
 158 #define GPSR5_14        F_(HTX0,                IP13_19_16)
 159 #define GPSR5_13        F_(HRX0,                IP13_15_12)
 160 #define GPSR5_12        F_(HSCK0,               IP13_11_8)
 161 #define GPSR5_11        F_(RX2_A,               IP13_7_4)
 162 #define GPSR5_10        F_(TX2_A,               IP13_3_0)
 163 #define GPSR5_9         F_(SCK2,                IP12_31_28)
 164 #define GPSR5_8         F_(RTS1_N,              IP12_27_24)
 165 #define GPSR5_7         F_(CTS1_N,              IP12_23_20)
 166 #define GPSR5_6         F_(TX1_A,               IP12_19_16)
 167 #define GPSR5_5         F_(RX1_A,               IP12_15_12)
 168 #define GPSR5_4         F_(RTS0_N,              IP12_11_8)
 169 #define GPSR5_3         F_(CTS0_N,              IP12_7_4)
 170 #define GPSR5_2         F_(TX0,                 IP12_3_0)
 171 #define GPSR5_1         F_(RX0,                 IP11_31_28)
 172 #define GPSR5_0         F_(SCK0,                IP11_27_24)
 173
 174 /* GPSR6 */
 175 #define GPSR6_31        F_(GP6_31,              IP18_7_4)
 176 #define GPSR6_30        F_(GP6_30,              IP18_3_0)
 177 #define GPSR6_29        F_(USB30_OVC,           IP17_31_28)
 178 #define GPSR6_28        F_(USB30_PWEN,          IP17_27_24)
 179 #define GPSR6_27        F_(USB1_OVC,            IP17_23_20)
 180 #define GPSR6_26        F_(USB1_PWEN,           IP17_19_16)
 181 #define GPSR6_25        F_(USB0_OVC,            IP17_15_12)
 182 #define GPSR6_24        F_(USB0_PWEN,           IP17_11_8)
 183 #define GPSR6_23        F_(AUDIO_CLKB_B,        IP17_7_4)
 184 #define GPSR6_22        F_(AUDIO_CLKA_A,        IP17_3_0)
 185 #define GPSR6_21        F_(SSI_SDATA9_A,        IP16_31_28)
 186 #define GPSR6_20        F_(SSI_SDATA8,          IP16_27_24)
 187 #define GPSR6_19        F_(SSI_SDATA7,          IP16_23_20)
 188 #define GPSR6_18        F_(SSI_WS78,            IP16_19_16)
 189 #define GPSR6_17        F_(SSI_SCK78,           IP16_15_12)
 190 #define GPSR6_16        F_(SSI_SDATA6,          IP16_11_8)
 191 #define GPSR6_15        F_(SSI_WS6,             IP16_7_4)
 192 #define GPSR6_14        F_(SSI_SCK6,            IP16_3_0)
 193 #define GPSR6_13        FM(SSI_SDATA5)
 194 #define GPSR6_12        FM(SSI_WS5)
 195 #define GPSR6_11        FM(SSI_SCK5)
 196 #define GPSR6_10        F_(SSI_SDATA4,          IP15_31_28)
 197 #define GPSR6_9         F_(SSI_WS4,             IP15_27_24)
 198 #define GPSR6_8         F_(SSI_SCK4,            IP15_23_20)
 199 #define GPSR6_7         F_(SSI_SDATA3,          IP15_19_16)
 200 #define GPSR6_6         F_(SSI_WS349,           IP15_15_12)
 201 #define GPSR6_5         F_(SSI_SCK349,          IP15_11_8)
 202 #define GPSR6_4         F_(SSI_SDATA2_A,        IP15_7_4)
 203 #define GPSR6_3         F_(SSI_SDATA1_A,        IP15_3_0)
 204 #define GPSR6_2         F_(SSI_SDATA0,          IP14_31_28)
 205 #define GPSR6_1         F_(SSI_WS01239,         IP14_27_24)
 206 #define GPSR6_0         F_(SSI_SCK01239,        IP14_23_20)
 207
 208 /* GPSR7 */
 209 #define GPSR7_3         FM(GP7_03)
 210 #define GPSR7_2         FM(HDMI0_CEC)
 211 #define GPSR7_1         FM(AVS2)
 212 #define GPSR7_0         FM(AVS1)
 213
 214
 215 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 216 #define IP0_3_0         FM(AVB_MDC)             F_(0, 0)        FM(MSIOF2_SS2_C)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 217 #define IP0_7_4         FM(AVB_MAGIC)           F_(0, 0)        FM(MSIOF2_SS1_C)        FM(SCK4_A)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 218 #define IP0_11_8        FM(AVB_PHY_INT)         F_(0, 0)        FM(MSIOF2_SYNC_C)       FM(RX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 219 #define IP0_15_12       FM(AVB_LINK)            F_(0, 0)        FM(MSIOF2_SCK_C)        FM(TX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 220 #define IP0_19_16       FM(AVB_AVTP_MATCH_A)    F_(0, 0)        FM(MSIOF2_RXD_C)        FM(CTS4_N_A)                    F_(0, 0)        FM(FSCLKST2_N_A) F_(0, 0)               F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 221 #define IP0_23_20       FM(AVB_AVTP_CAPTURE_A)  F_(0, 0)        FM(MSIOF2_TXD_C)        FM(RTS4_N_A)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 222 #define IP0_27_24       FM(IRQ0)                FM(QPOLB)       F_(0, 0)                FM(DU_CDE)                      FM(VI4_DATA0_B) FM(CAN0_TX_B)   FM(CANFD0_TX_B)         FM(MSIOF3_SS2_E) F_(0, 0)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 223 #define IP0_31_28       FM(IRQ1)                FM(QPOLA)       F_(0, 0)                FM(DU_DISP)                     FM(VI4_DATA1_B) FM(CAN0_RX_B)   FM(CANFD0_RX_B)         FM(MSIOF3_SS1_E) F_(0, 0)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 224 #define IP1_3_0         FM(IRQ2)                FM(QCPV_QDE)    F_(0, 0)                FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(VI4_DATA2_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_SYNC_E) F_(0, 0)              FM(PWM3_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 225 #define IP1_7_4         FM(IRQ3)                FM(QSTVB_QVE)   F_(0, 0)                FM(DU_DOTCLKOUT1)               FM(VI4_DATA3_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_SCK_E) F_(0, 0)               FM(PWM4_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 226 #define IP1_11_8        FM(IRQ4)                FM(QSTH_QHS)    F_(0, 0)                FM(DU_EXHSYNC_DU_HSYNC)         FM(VI4_DATA4_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_RXD_E) F_(0, 0)               FM(PWM5_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 227 #define IP1_15_12       FM(IRQ5)                FM(QSTB_QHE)    F_(0, 0)                FM(DU_EXVSYNC_DU_VSYNC)         FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0)               FM(MSIOF3_TXD_E) F_(0, 0)               FM(PWM6_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 228 #define IP1_19_16       FM(PWM0)                FM(AVB_AVTP_PPS)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA6_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IECLK_B)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 229 #define IP1_23_20       FM(PWM1_A)              F_(0, 0)        F_(0, 0)                FM(HRX3_D)                      FM(VI4_DATA7_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IERX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 230 #define IP1_27_24       FM(PWM2_A)              F_(0, 0)        F_(0, 0)                FM(HTX3_D)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IETX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 231 #define IP1_31_28       FM(A0)                  FM(LCDOUT16)    FM(MSIOF3_SYNC_B)       F_(0, 0)                        FM(VI4_DATA8)   F_(0, 0)        FM(DU_DB0)              F_(0, 0)        F_(0, 0)                FM(PWM3_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 232 #define IP2_3_0         FM(A1)                  FM(LCDOUT17)    FM(MSIOF3_TXD_B)        F_(0, 0)                        FM(VI4_DATA9)   F_(0, 0)        FM(DU_DB1)              F_(0, 0)        F_(0, 0)                FM(PWM4_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 233 #define IP2_7_4         FM(A2)                  FM(LCDOUT18)    FM(MSIOF3_SCK_B)        F_(0, 0)                        FM(VI4_DATA10)  F_(0, 0)        FM(DU_DB2)              F_(0, 0)        F_(0, 0)                FM(PWM5_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 234 #define IP2_11_8        FM(A3)                  FM(LCDOUT19)    FM(MSIOF3_RXD_B)        F_(0, 0)                        FM(VI4_DATA11)  F_(0, 0)        FM(DU_DB3)              F_(0, 0)        F_(0, 0)                FM(PWM6_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 235 #define IP2_15_12       FM(A4)                  FM(LCDOUT20)    FM(MSIOF3_SS1_B)        F_(0, 0)                        FM(VI4_DATA12)  FM(VI5_DATA12)  FM(DU_DB4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 236 #define IP2_19_16       FM(A5)                  FM(LCDOUT21)    FM(MSIOF3_SS2_B)        FM(SCK4_B)                      FM(VI4_DATA13)  FM(VI5_DATA13)  FM(DU_DB5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 237 #define IP2_23_20       FM(A6)                  FM(LCDOUT22)    FM(MSIOF2_SS1_A)        FM(RX4_B)                       FM(VI4_DATA14)  FM(VI5_DATA14)  FM(DU_DB6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 238 #define IP2_27_24       FM(A7)                  FM(LCDOUT23)    FM(MSIOF2_SS2_A)        FM(TX4_B)                       FM(VI4_DATA15)  FM(VI5_DATA15)  FM(DU_DB7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 239 #define IP2_31_28       FM(A8)                  FM(RX3_B)       FM(MSIOF2_SYNC_A)       FM(HRX4_B)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                FM(SDA6_A)      FM(AVB_AVTP_MATCH_B)    FM(PWM1_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 240 #define IP3_3_0         FM(A9)                  F_(0, 0)        FM(MSIOF2_SCK_A)        FM(CTS4_N_B)                    F_(0, 0)        FM(VI5_VSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 241 #define IP3_7_4         FM(A10)                 F_(0, 0)        FM(MSIOF2_RXD_A)        FM(RTS4_N_B)                    F_(0, 0)        FM(VI5_HSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 242 #define IP3_11_8        FM(A11)                 FM(TX3_B)       FM(MSIOF2_TXD_A)        FM(HTX4_B)                      FM(HSCK4)       FM(VI5_FIELD)   F_(0, 0)                FM(SCL6_A)      FM(AVB_AVTP_CAPTURE_B)  FM(PWM2_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 243
 244 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 245 #define IP3_15_12       FM(A12)                 FM(LCDOUT12)    FM(MSIOF3_SCK_C)        F_(0, 0)                        FM(HRX4_A)      FM(VI5_DATA8)   FM(DU_DG4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 246 #define IP3_19_16       FM(A13)                 FM(LCDOUT13)    FM(MSIOF3_SYNC_C)       F_(0, 0)                        FM(HTX4_A)      FM(VI5_DATA9)   FM(DU_DG5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 247 #define IP3_23_20       FM(A14)                 FM(LCDOUT14)    FM(MSIOF3_RXD_C)        F_(0, 0)                        FM(HCTS4_N)     FM(VI5_DATA10)  FM(DU_DG6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 248 #define IP3_27_24       FM(A15)                 FM(LCDOUT15)    FM(MSIOF3_TXD_C)        F_(0, 0)                        FM(HRTS4_N)     FM(VI5_DATA11)  FM(DU_DG7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 249 #define IP3_31_28       FM(A16)                 FM(LCDOUT8)     F_(0, 0)                F_(0, 0)                        FM(VI4_FIELD)   F_(0, 0)        FM(DU_DG0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 250 #define IP4_3_0         FM(A17)                 FM(LCDOUT9)     F_(0, 0)                F_(0, 0)                        FM(VI4_VSYNC_N) F_(0, 0)        FM(DU_DG1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 251 #define IP4_7_4         FM(A18)                 FM(LCDOUT10)    F_(0, 0)                F_(0, 0)                        FM(VI4_HSYNC_N) F_(0, 0)        FM(DU_DG2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 252 #define IP4_11_8        FM(A19)                 FM(LCDOUT11)    F_(0, 0)                F_(0, 0)                        FM(VI4_CLKENB)  F_(0, 0)        FM(DU_DG3)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 253 #define IP4_15_12       FM(CS0_N)               F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLKENB)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 254 #define IP4_19_16       FM(CS1_N)               F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLK)     F_(0, 0)                FM(EX_WAIT0_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 255 #define IP4_23_20       FM(BS_N)                FM(QSTVA_QVS)   FM(MSIOF3_SCK_D)        FM(SCK3)                        FM(HSCK3)       F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN1_TX)             FM(CANFD1_TX)   FM(IETX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 256 #define IP4_27_24       FM(RD_N)                F_(0, 0)        FM(MSIOF3_SYNC_D)       FM(RX3_A)                       FM(HRX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_TX_A)           FM(CANFD0_TX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 257 #define IP4_31_28       FM(RD_WR_N)             F_(0, 0)        FM(MSIOF3_RXD_D)        FM(TX3_A)                       FM(HTX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_RX_A)           FM(CANFD0_RX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 258 #define IP5_3_0         FM(WE0_N)               F_(0, 0)        FM(MSIOF3_TXD_D)        FM(CTS3_N)                      FM(HCTS3_N)     F_(0, 0)        F_(0, 0)                FM(SCL6_B)      FM(CAN_CLK)             F_(0, 0)        FM(IECLK_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 259 #define IP5_7_4         FM(WE1_N)               F_(0, 0)        FM(MSIOF3_SS1_D)        FM(RTS3_N)                      FM(HRTS3_N)     F_(0, 0)        F_(0, 0)                FM(SDA6_B)      FM(CAN1_RX)             FM(CANFD1_RX)   FM(IERX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 260 #define IP5_11_8        FM(EX_WAIT0_A)          FM(QCLK)        F_(0, 0)                F_(0, 0)                        FM(VI4_CLK)     F_(0, 0)        FM(DU_DOTCLKOUT0)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 261 #define IP5_15_12       FM(D0)                  FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)        F_(0, 0)                        FM(VI4_DATA16)  FM(VI5_DATA0)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 262 #define IP5_19_16       FM(D1)                  FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)       F_(0, 0)                        FM(VI4_DATA17)  FM(VI5_DATA1)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 263 #define IP5_23_20       FM(D2)                  F_(0, 0)        FM(MSIOF3_RXD_A)        F_(0, 0)                        FM(VI4_DATA18)  FM(VI5_DATA2)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 264 #define IP5_27_24       FM(D3)                  F_(0, 0)        FM(MSIOF3_TXD_A)        F_(0, 0)                        FM(VI4_DATA19)  FM(VI5_DATA3)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 265 #define IP5_31_28       FM(D4)                  FM(MSIOF2_SCK_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA20)  FM(VI5_DATA4)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 266 #define IP6_3_0         FM(D5)                  FM(MSIOF2_SYNC_B)F_(0, 0)               F_(0, 0)                        FM(VI4_DATA21)  FM(VI5_DATA5)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 267 #define IP6_7_4         FM(D6)                  FM(MSIOF2_RXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA22)  FM(VI5_DATA6)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 268 #define IP6_11_8        FM(D7)                  FM(MSIOF2_TXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA23)  FM(VI5_DATA7)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 269 #define IP6_15_12       FM(D8)                  FM(LCDOUT0)     FM(MSIOF2_SCK_D)        FM(SCK4_C)                      FM(VI4_DATA0_A) F_(0, 0)        FM(DU_DR0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 270 #define IP6_19_16       FM(D9)                  FM(LCDOUT1)     FM(MSIOF2_SYNC_D)       F_(0, 0)                        FM(VI4_DATA1_A) F_(0, 0)        FM(DU_DR1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 271 #define IP6_23_20       FM(D10)                 FM(LCDOUT2)     FM(MSIOF2_RXD_D)        FM(HRX3_B)                      FM(VI4_DATA2_A) FM(CTS4_N_C)    FM(DU_DR2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 272 #define IP6_27_24       FM(D11)                 FM(LCDOUT3)     FM(MSIOF2_TXD_D)        FM(HTX3_B)                      FM(VI4_DATA3_A) FM(RTS4_N_C)    FM(DU_DR3)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 273 #define IP6_31_28       FM(D12)                 FM(LCDOUT4)     FM(MSIOF2_SS1_D)        FM(RX4_C)                       FM(VI4_DATA4_A) F_(0, 0)        FM(DU_DR4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 274
 275 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 276 #define IP7_3_0         FM(D13)                 FM(LCDOUT5)     FM(MSIOF2_SS2_D)        FM(TX4_C)                       FM(VI4_DATA5_A) F_(0, 0)        FM(DU_DR5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 277 #define IP7_7_4         FM(D14)                 FM(LCDOUT6)     FM(MSIOF3_SS1_A)        FM(HRX3_C)                      FM(VI4_DATA6_A) F_(0, 0)        FM(DU_DR6)              FM(SCL6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 278 #define IP7_11_8        FM(D15)                 FM(LCDOUT7)     FM(MSIOF3_SS2_A)        FM(HTX3_C)                      FM(VI4_DATA7_A) F_(0, 0)        FM(DU_DR7)              FM(SDA6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 279 #define IP7_19_16       FM(SD0_CLK)             F_(0, 0)        FM(MSIOF1_SCK_E)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 280 #define IP7_23_20       FM(SD0_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_E)       F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 281 #define IP7_27_24       FM(SD0_DAT0)            F_(0, 0)        FM(MSIOF1_RXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_B)   FM(STP_ISCLK_0_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 282 #define IP7_31_28       FM(SD0_DAT1)            F_(0, 0)        FM(MSIOF1_TXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 283 #define IP8_3_0         FM(SD0_DAT2)            F_(0, 0)        FM(MSIOF1_SS1_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_B)  FM(STP_ISD_0_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 284 #define IP8_7_4         FM(SD0_DAT3)            F_(0, 0)        FM(MSIOF1_SS2_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_B)  FM(STP_ISEN_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 285 #define IP8_11_8        FM(SD1_CLK)             F_(0, 0)        FM(MSIOF1_SCK_G)        F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 286 #define IP8_15_12       FM(SD1_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_G)       FM(NFCE_N_B)                    F_(0, 0)        FM(SIM0_D_A)    FM(STP_IVCXO27_1_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 287 #define IP8_19_16       FM(SD1_DAT0)            FM(SD2_DAT4)    FM(MSIOF1_RXD_G)        FM(NFWP_N_B)                    F_(0, 0)        FM(TS_SCK1_B)   FM(STP_ISCLK_1_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 288 #define IP8_23_20       FM(SD1_DAT1)            FM(SD2_DAT5)    FM(MSIOF1_TXD_G)        FM(NFDATA14_B)                  F_(0, 0)        FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 289 #define IP8_27_24       FM(SD1_DAT2)            FM(SD2_DAT6)    FM(MSIOF1_SS1_G)        FM(NFDATA15_B)                  F_(0, 0)        FM(TS_SDAT1_B)  FM(STP_ISD_1_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 290 #define IP8_31_28       FM(SD1_DAT3)            FM(SD2_DAT7)    FM(MSIOF1_SS2_G)        FM(NFRB_N_B)                    F_(0, 0)        FM(TS_SDEN1_B)  FM(STP_ISEN_1_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 291 #define IP9_3_0         FM(SD2_CLK)             F_(0, 0)        FM(NFDATA8)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 292 #define IP9_7_4         FM(SD2_CMD)             F_(0, 0)        FM(NFDATA9)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 293 #define IP9_11_8        FM(SD2_DAT0)            F_(0, 0)        FM(NFDATA10)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 294 #define IP9_15_12       FM(SD2_DAT1)            F_(0, 0)        FM(NFDATA11)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 295 #define IP9_19_16       FM(SD2_DAT2)            F_(0, 0)        FM(NFDATA12)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 296 #define IP9_23_20       FM(SD2_DAT3)            F_(0, 0)        FM(NFDATA13)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 297 #define IP9_27_24       FM(SD2_DS)              F_(0, 0)        FM(NFALE)               F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(SATA_DEVSLP_B)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 298 #define IP9_31_28       FM(SD3_CLK)             F_(0, 0)        FM(NFWE_N)              F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 299 #define IP10_3_0        FM(SD3_CMD)             F_(0, 0)        FM(NFRE_N)              F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 300 #define IP10_7_4        FM(SD3_DAT0)            F_(0, 0)        FM(NFDATA0)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 301 #define IP10_11_8       FM(SD3_DAT1)            F_(0, 0)        FM(NFDATA1)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 302 #define IP10_15_12      FM(SD3_DAT2)            F_(0, 0)        FM(NFDATA2)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 303 #define IP10_19_16      FM(SD3_DAT3)            F_(0, 0)        FM(NFDATA3)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 304 #define IP10_23_20      FM(SD3_DAT4)            FM(SD2_CD_A)    FM(NFDATA4)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 305 #define IP10_27_24      FM(SD3_DAT5)            FM(SD2_WP_A)    FM(NFDATA5)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 306 #define IP10_31_28      FM(SD3_DAT6)            FM(SD3_CD)      FM(NFDATA6)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 307 #define IP11_3_0        FM(SD3_DAT7)            FM(SD3_WP)      FM(NFDATA7)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 308 #define IP11_7_4        FM(SD3_DS)              F_(0, 0)        FM(NFCLE)               F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 309 #define IP11_11_8       FM(SD0_CD)              F_(0, 0)        FM(NFDATA14_A)          F_(0, 0)                        FM(SCL2_B)      FM(SIM0_RST_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 310
 311 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 312 #define IP11_15_12      FM(SD0_WP)              F_(0, 0)        FM(NFDATA15_A)          F_(0, 0)                        FM(SDA2_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 313 #define IP11_19_16      FM(SD1_CD)              F_(0, 0)        FM(NFRB_N_A)            F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 314 #define IP11_23_20      FM(SD1_WP)              F_(0, 0)        FM(NFCE_N_A)            F_(0, 0)                        F_(0, 0)        FM(SIM0_D_B)    F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 315 #define IP11_27_24      FM(SCK0)                FM(HSCK1_B)     FM(MSIOF1_SS2_B)        FM(AUDIO_CLKC_B)                FM(SDA2_A)      FM(SIM0_RST_B)  FM(STP_OPWM_0_C)        FM(RIF0_CLK_B)  F_(0, 0)                FM(ADICHS2)     FM(SCK5_B)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 316 #define IP11_31_28      FM(RX0)                 FM(HRX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_C)   FM(STP_ISCLK_0_C)       FM(RIF0_D0_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 317 #define IP12_3_0        FM(TX0)                 FM(HTX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)      FM(RIF0_D1_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 318 #define IP12_7_4        FM(CTS0_N)              FM(HCTS1_N_B)   FM(MSIOF1_SYNC_B)       F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)      FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C)      FM(ADICS_SAMP)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 319 #define IP12_11_8       FM(RTS0_N)              FM(HRTS1_N_B)   FM(MSIOF1_SS1_B)        FM(AUDIO_CLKA_B)                FM(SCL2_A)      F_(0, 0)        FM(STP_IVCXO27_1_C)     FM(RIF0_SYNC_B) F_(0, 0)                FM(ADICHS1)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 320 #define IP12_15_12      FM(RX1_A)               FM(HRX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_C)  FM(STP_ISD_0_C)         FM(RIF1_CLK_C)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 321 #define IP12_19_16      FM(TX1_A)               FM(HTX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_C)  FM(STP_ISEN_0_C)        FM(RIF1_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 322 #define IP12_23_20      FM(CTS1_N)              FM(HCTS1_N_A)   FM(MSIOF1_RXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_C)  FM(STP_ISEN_1_C)        FM(RIF1_D0_B)   F_(0, 0)                FM(ADIDATA)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 323 #define IP12_27_24      FM(RTS1_N)              FM(HRTS1_N_A)   FM(MSIOF1_TXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_C)  FM(STP_ISD_1_C)         FM(RIF1_D1_B)   F_(0, 0)                FM(ADICHS0)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 324 #define IP12_31_28      FM(SCK2)                FM(SCIF_CLK_B)  FM(MSIOF1_SCK_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_C)   FM(STP_ISCLK_1_C)       FM(RIF1_CLK_B)  F_(0, 0)                FM(ADICLK)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 325 #define IP13_3_0        FM(TX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_CD_B)                    FM(SCL1_A)      F_(0, 0)        FM(FMCLK_A)             FM(RIF1_D1_C)   F_(0, 0)                FM(FSO_CFE_0_N) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 326 #define IP13_7_4        FM(RX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_WP_B)                    FM(SDA1_A)      F_(0, 0)        FM(FMIN_A)              FM(RIF1_SYNC_C) F_(0, 0)                FM(FSO_CFE_1_N) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 327 #define IP13_11_8       FM(HSCK0)               F_(0, 0)        FM(MSIOF1_SCK_D)        FM(AUDIO_CLKB_A)                FM(SSI_SDATA1_B)FM(TS_SCK0_D)   FM(STP_ISCLK_0_D)       FM(RIF0_CLK_C)  F_(0, 0)                F_(0, 0)        FM(RX5_B)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 328 #define IP13_15_12      FM(HRX0)                F_(0, 0)        FM(MSIOF1_RXD_D)        F_(0, 0)                        FM(SSI_SDATA2_B)FM(TS_SDEN0_D)  FM(STP_ISEN_0_D)        FM(RIF0_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 329 #define IP13_19_16      FM(HTX0)                F_(0, 0)        FM(MSIOF1_TXD_D)        F_(0, 0)                        FM(SSI_SDATA9_B)FM(TS_SDAT0_D)  FM(STP_ISD_0_D)         FM(RIF0_D1_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 330 #define IP13_23_20      FM(HCTS0_N)             FM(RX2_B)       FM(MSIOF1_SYNC_D)       F_(0, 0)                        FM(SSI_SCK9_A)  FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D)      FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 331 #define IP13_27_24      FM(HRTS0_N)             FM(TX2_B)       FM(MSIOF1_SS1_D)        F_(0, 0)                        FM(SSI_WS9_A)   F_(0, 0)        FM(STP_IVCXO27_0_D)     FM(BPFCLK_A)    FM(AUDIO_CLKOUT2_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 332 #define IP13_31_28      FM(MSIOF0_SYNC)         F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(AUDIO_CLKOUT_A)      F_(0, 0)        FM(TX5_B)       F_(0, 0)        F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
 333 #define IP14_3_0        FM(MSIOF0_SS1)          FM(RX5_A)       FM(NFWP_N_A)            FM(AUDIO_CLKA_C)                FM(SSI_SCK2_A)  F_(0, 0)        FM(STP_IVCXO27_0_C)     F_(0, 0)        FM(AUDIO_CLKOUT3_A)     F_(0, 0)        FM(TCLK1_B)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 334 #define IP14_7_4        FM(MSIOF0_SS2)          FM(TX5_A)       FM(MSIOF1_SS2_D)        FM(AUDIO_CLKC_A)                FM(SSI_WS2_A)   F_(0, 0)        FM(STP_OPWM_0_D)        F_(0, 0)        FM(AUDIO_CLKOUT_D)      F_(0, 0)        FM(SPEEDIN_B)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 335 #define IP14_11_8       FM(MLB_CLK)             F_(0, 0)        FM(MSIOF1_SCK_F)        F_(0, 0)                        FM(SCL1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 336 #define IP14_15_12      FM(MLB_SIG)             FM(RX1_B)       FM(MSIOF1_SYNC_F)       F_(0, 0)                        FM(SDA1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 337 #define IP14_19_16      FM(MLB_DAT)             FM(TX1_B)       FM(MSIOF1_RXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 338 #define IP14_23_20      FM(SSI_SCK01239)        F_(0, 0)        FM(MSIOF1_TXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 339 #define IP14_27_24      FM(SSI_WS01239)         F_(0, 0)        FM(MSIOF1_SS1_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 340
 341 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 342 #define IP14_31_28      FM(SSI_SDATA0)          F_(0, 0)        FM(MSIOF1_SS2_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 343 #define IP15_3_0        FM(SSI_SDATA1_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 344 #define IP15_7_4        FM(SSI_SDATA2_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        FM(SSI_SCK1_B)  F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 345 #define IP15_11_8       FM(SSI_SCK349)          F_(0, 0)        FM(MSIOF1_SS1_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 346 #define IP15_15_12      FM(SSI_WS349)           FM(HCTS2_N_A)   FM(MSIOF1_SS2_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_A)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 347 #define IP15_19_16      FM(SSI_SDATA3)          FM(HRTS2_N_A)   FM(MSIOF1_TXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_A)   FM(STP_ISCLK_0_A)       FM(RIF0_D1_A)   FM(RIF2_D0_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 348 #define IP15_23_20      FM(SSI_SCK4)            FM(HRX2_A)      FM(MSIOF1_SCK_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_A)  FM(STP_ISD_0_A)         FM(RIF0_CLK_A)  FM(RIF2_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 349 #define IP15_27_24      FM(SSI_WS4)             FM(HTX2_A)      FM(MSIOF1_SYNC_A)       F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_A)  FM(STP_ISEN_0_A)        FM(RIF0_SYNC_A) FM(RIF2_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 350 #define IP15_31_28      FM(SSI_SDATA4)          FM(HSCK2_A)     FM(MSIOF1_RXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)      FM(RIF0_D0_A)   FM(RIF2_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 351 #define IP16_3_0        FM(SSI_SCK6)            F_(0, 0)        F_(0, 0)                FM(SIM0_RST_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 352 #define IP16_7_4        FM(SSI_WS6)             F_(0, 0)        F_(0, 0)                FM(SIM0_D_D)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 353 #define IP16_11_8       FM(SSI_SDATA6)          F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(SATA_DEVSLP_A)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 354 #define IP16_15_12      FM(SSI_SCK78)           FM(HRX2_B)      FM(MSIOF1_SCK_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_A)   FM(STP_ISCLK_1_A)       FM(RIF1_CLK_A)  FM(RIF3_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 355 #define IP16_19_16      FM(SSI_WS78)            FM(HTX2_B)      FM(MSIOF1_SYNC_C)       F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_A)  FM(STP_ISD_1_A)         FM(RIF1_SYNC_A) FM(RIF3_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 356 #define IP16_23_20      FM(SSI_SDATA7)          FM(HCTS2_N_B)   FM(MSIOF1_RXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_A)  FM(STP_ISEN_1_A)        FM(RIF1_D0_A)   FM(RIF3_D0_A)           F_(0, 0)        FM(TCLK2_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 357 #define IP16_27_24      FM(SSI_SDATA8)          FM(HRTS2_N_B)   FM(MSIOF1_TXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A)      FM(RIF1_D1_A)   FM(RIF3_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 358 #define IP16_31_28      FM(SSI_SDATA9_A)        FM(HSCK2_B)     FM(MSIOF1_SS1_C)        FM(HSCK1_A)                     FM(SSI_WS1_B)   FM(SCK1)        FM(STP_IVCXO27_1_A)     FM(SCK5_A)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 359 #define IP17_3_0        FM(AUDIO_CLKA_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        FM(CC5_OSCOUT)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 360 #define IP17_7_4        FM(AUDIO_CLKB_B)        FM(SCIF_CLK_A)  F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_1_D)     FM(REMOCON_A)   F_(0, 0)                F_(0, 0)        FM(TCLK1_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 361 #define IP17_11_8       FM(USB0_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_RST_C)                  F_(0, 0)        FM(TS_SCK1_D)   FM(STP_ISCLK_1_D)       FM(BPFCLK_B)    FM(RIF3_CLK_B)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
 362 #define IP17_15_12      FM(USB0_OVC)            F_(0, 0)        F_(0, 0)                FM(SIM0_D_C)                    F_(0, 0)        FM(TS_SDAT1_D)  FM(STP_ISD_1_D)         F_(0, 0)        FM(RIF3_SYNC_B)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
 363 #define IP17_19_16      FM(USB1_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_C)                  FM(SSI_SCK1_A)  FM(TS_SCK0_E)   FM(STP_ISCLK_0_E)       FM(FMCLK_B)     FM(RIF2_CLK_B)          F_(0, 0)        FM(SPEEDIN_A)   F_(0, 0)        F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
 364 #define IP17_23_20      FM(USB1_OVC)            F_(0, 0)        FM(MSIOF1_SS2_C)        F_(0, 0)                        FM(SSI_WS1_A)   FM(TS_SDAT0_E)  FM(STP_ISD_0_E)         FM(FMIN_B)      FM(RIF2_SYNC_B)         F_(0, 0)        FM(REMOCON_B)   F_(0, 0)        F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
 365 #define IP17_27_24      FM(USB30_PWEN)          F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT_B)              FM(SSI_SCK2_B)  FM(TS_SDEN1_D)  FM(STP_ISEN_1_D)        FM(STP_OPWM_0_E)FM(RIF3_D0_B)           F_(0, 0)        FM(TCLK2_B)     FM(TPU0TO0)     FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
 366 #define IP17_31_28      FM(USB30_OVC)           F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT1_B)             FM(SSI_WS2_B)   FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)      FM(STP_IVCXO27_0_E)FM(RIF3_D1_B)        F_(0, 0)        FM(FSO_TOE_N)   FM(TPU0TO1)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 367 #define IP18_3_0        FM(GP6_30)              F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT2_B)             FM(SSI_SCK9_B)  FM(TS_SDEN0_E)  FM(STP_ISEN_0_E)        F_(0, 0)        FM(RIF2_D0_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO2)     FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
 368 #define IP18_7_4        FM(GP6_31)              F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT3_B)             FM(SSI_WS9_B)   FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)      F_(0, 0)        FM(RIF2_D1_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO3)     FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
 369
 370 #define PINMUX_GPSR     \
 371 \
 372                                                                                                 GPSR6_31 \
 373                                                                                                 GPSR6_30 \
 374                                                                                                 GPSR6_29 \
 375                 GPSR1_28                                                                        GPSR6_28 \
 376                 GPSR1_27                                                                        GPSR6_27 \
 377                 GPSR1_26                                                                        GPSR6_26 \
 378                 GPSR1_25                                                        GPSR5_25        GPSR6_25 \
 379                 GPSR1_24                                                        GPSR5_24        GPSR6_24 \
 380                 GPSR1_23                                                        GPSR5_23        GPSR6_23 \
 381                 GPSR1_22                                                        GPSR5_22        GPSR6_22 \
 382                 GPSR1_21                                                        GPSR5_21        GPSR6_21 \
 383                 GPSR1_20                                                        GPSR5_20        GPSR6_20 \
 384                 GPSR1_19                                                        GPSR5_19        GPSR6_19 \
 385                 GPSR1_18                                                        GPSR5_18        GPSR6_18 \
 386                 GPSR1_17                                        GPSR4_17        GPSR5_17        GPSR6_17 \
 387                 GPSR1_16                                        GPSR4_16        GPSR5_16        GPSR6_16 \
 388 GPSR0_15        GPSR1_15                        GPSR3_15        GPSR4_15        GPSR5_15        GPSR6_15 \
 389 GPSR0_14        GPSR1_14        GPSR2_14        GPSR3_14        GPSR4_14        GPSR5_14        GPSR6_14 \
 390 GPSR0_13        GPSR1_13        GPSR2_13        GPSR3_13        GPSR4_13        GPSR5_13        GPSR6_13 \
 391 GPSR0_12        GPSR1_12        GPSR2_12        GPSR3_12        GPSR4_12        GPSR5_12        GPSR6_12 \
 392 GPSR0_11        GPSR1_11        GPSR2_11        GPSR3_11        GPSR4_11        GPSR5_11        GPSR6_11 \
 393 GPSR0_10        GPSR1_10        GPSR2_10        GPSR3_10        GPSR4_10        GPSR5_10        GPSR6_10 \
 394 GPSR0_9         GPSR1_9         GPSR2_9         GPSR3_9         GPSR4_9         GPSR5_9         GPSR6_9 \
 395 GPSR0_8         GPSR1_8         GPSR2_8         GPSR3_8         GPSR4_8         GPSR5_8         GPSR6_8 \
 396 GPSR0_7         GPSR1_7         GPSR2_7         GPSR3_7         GPSR4_7         GPSR5_7         GPSR6_7 \
 397 GPSR0_6         GPSR1_6         GPSR2_6         GPSR3_6         GPSR4_6         GPSR5_6         GPSR6_6 \
 398 GPSR0_5         GPSR1_5         GPSR2_5         GPSR3_5         GPSR4_5         GPSR5_5         GPSR6_5 \
 399 GPSR0_4         GPSR1_4         GPSR2_4         GPSR3_4         GPSR4_4         GPSR5_4         GPSR6_4 \
 400 GPSR0_3         GPSR1_3         GPSR2_3         GPSR3_3         GPSR4_3         GPSR5_3         GPSR6_3         GPSR7_3 \
 401 GPSR0_2         GPSR1_2         GPSR2_2         GPSR3_2         GPSR4_2         GPSR5_2         GPSR6_2         GPSR7_2 \
 402 GPSR0_1         GPSR1_1         GPSR2_1         GPSR3_1         GPSR4_1         GPSR5_1         GPSR6_1         GPSR7_1 \
 403 GPSR0_0         GPSR1_0         GPSR2_0         GPSR3_0         GPSR4_0         GPSR5_0         GPSR6_0         GPSR7_0
 404
 405 #define PINMUX_IPSR                             \
 406 \
 407 FM(IP0_3_0)     IP0_3_0         FM(IP1_3_0)     IP1_3_0         FM(IP2_3_0)     IP2_3_0         FM(IP3_3_0)     IP3_3_0 \
 408 FM(IP0_7_4)     IP0_7_4         FM(IP1_7_4)     IP1_7_4         FM(IP2_7_4)     IP2_7_4         FM(IP3_7_4)     IP3_7_4 \
 409 FM(IP0_11_8)    IP0_11_8        FM(IP1_11_8)    IP1_11_8        FM(IP2_11_8)    IP2_11_8        FM(IP3_11_8)    IP3_11_8 \
 410 FM(IP0_15_12)   IP0_15_12       FM(IP1_15_12)   IP1_15_12       FM(IP2_15_12)   IP2_15_12       FM(IP3_15_12)   IP3_15_12 \
 411 FM(IP0_19_16)   IP0_19_16       FM(IP1_19_16)   IP1_19_16       FM(IP2_19_16)   IP2_19_16       FM(IP3_19_16)   IP3_19_16 \
 412 FM(IP0_23_20)   IP0_23_20       FM(IP1_23_20)   IP1_23_20       FM(IP2_23_20)   IP2_23_20       FM(IP3_23_20)   IP3_23_20 \
 413 FM(IP0_27_24)   IP0_27_24       FM(IP1_27_24)   IP1_27_24       FM(IP2_27_24)   IP2_27_24       FM(IP3_27_24)   IP3_27_24 \
 414 FM(IP0_31_28)   IP0_31_28       FM(IP1_31_28)   IP1_31_28       FM(IP2_31_28)   IP2_31_28       FM(IP3_31_28)   IP3_31_28 \
 415 \
 416 FM(IP4_3_0)     IP4_3_0         FM(IP5_3_0)     IP5_3_0         FM(IP6_3_0)     IP6_3_0         FM(IP7_3_0)     IP7_3_0 \
 417 FM(IP4_7_4)     IP4_7_4         FM(IP5_7_4)     IP5_7_4         FM(IP6_7_4)     IP6_7_4         FM(IP7_7_4)     IP7_7_4 \
 418 FM(IP4_11_8)    IP4_11_8        FM(IP5_11_8)    IP5_11_8        FM(IP6_11_8)    IP6_11_8        FM(IP7_11_8)    IP7_11_8 \
 419 FM(IP4_15_12)   IP4_15_12       FM(IP5_15_12)   IP5_15_12       FM(IP6_15_12)   IP6_15_12 \
 420 FM(IP4_19_16)   IP4_19_16       FM(IP5_19_16)   IP5_19_16       FM(IP6_19_16)   IP6_19_16       FM(IP7_19_16)   IP7_19_16 \
 421 FM(IP4_23_20)   IP4_23_20       FM(IP5_23_20)   IP5_23_20       FM(IP6_23_20)   IP6_23_20       FM(IP7_23_20)   IP7_23_20 \
 422 FM(IP4_27_24)   IP4_27_24       FM(IP5_27_24)   IP5_27_24       FM(IP6_27_24)   IP6_27_24       FM(IP7_27_24)   IP7_27_24 \
 423 FM(IP4_31_28)   IP4_31_28       FM(IP5_31_28)   IP5_31_28       FM(IP6_31_28)   IP6_31_28       FM(IP7_31_28)   IP7_31_28 \
 424 \
 425 FM(IP8_3_0)     IP8_3_0         FM(IP9_3_0)     IP9_3_0         FM(IP10_3_0)    IP10_3_0        FM(IP11_3_0)    IP11_3_0 \
 426 FM(IP8_7_4)     IP8_7_4         FM(IP9_7_4)     IP9_7_4         FM(IP10_7_4)    IP10_7_4        FM(IP11_7_4)    IP11_7_4 \
 427 FM(IP8_11_8)    IP8_11_8        FM(IP9_11_8)    IP9_11_8        FM(IP10_11_8)   IP10_11_8       FM(IP11_11_8)   IP11_11_8 \
 428 FM(IP8_15_12)   IP8_15_12       FM(IP9_15_12)   IP9_15_12       FM(IP10_15_12)  IP10_15_12      FM(IP11_15_12)  IP11_15_12 \
 429 FM(IP8_19_16)   IP8_19_16       FM(IP9_19_16)   IP9_19_16       FM(IP10_19_16)  IP10_19_16      FM(IP11_19_16)  IP11_19_16 \
 430 FM(IP8_23_20)   IP8_23_20       FM(IP9_23_20)   IP9_23_20       FM(IP10_23_20)  IP10_23_20      FM(IP11_23_20)  IP11_23_20 \
 431 FM(IP8_27_24)   IP8_27_24       FM(IP9_27_24)   IP9_27_24       FM(IP10_27_24)  IP10_27_24      FM(IP11_27_24)  IP11_27_24 \
 432 FM(IP8_31_28)   IP8_31_28       FM(IP9_31_28)   IP9_31_28       FM(IP10_31_28)  IP10_31_28      FM(IP11_31_28)  IP11_31_28 \
 433 \
 434 FM(IP12_3_0)    IP12_3_0        FM(IP13_3_0)    IP13_3_0        FM(IP14_3_0)    IP14_3_0        FM(IP15_3_0)    IP15_3_0 \
 435 FM(IP12_7_4)    IP12_7_4        FM(IP13_7_4)    IP13_7_4        FM(IP14_7_4)    IP14_7_4        FM(IP15_7_4)    IP15_7_4 \
 436 FM(IP12_11_8)   IP12_11_8       FM(IP13_11_8)   IP13_11_8       FM(IP14_11_8)   IP14_11_8       FM(IP15_11_8)   IP15_11_8 \
 437 FM(IP12_15_12)  IP12_15_12      FM(IP13_15_12)  IP13_15_12      FM(IP14_15_12)  IP14_15_12      FM(IP15_15_12)  IP15_15_12 \
 438 FM(IP12_19_16)  IP12_19_16      FM(IP13_19_16)  IP13_19_16      FM(IP14_19_16)  IP14_19_16      FM(IP15_19_16)  IP15_19_16 \
 439 FM(IP12_23_20)  IP12_23_20      FM(IP13_23_20)  IP13_23_20      FM(IP14_23_20)  IP14_23_20      FM(IP15_23_20)  IP15_23_20 \
 440 FM(IP12_27_24)  IP12_27_24      FM(IP13_27_24)  IP13_27_24      FM(IP14_27_24)  IP14_27_24      FM(IP15_27_24)  IP15_27_24 \
 441 FM(IP12_31_28)  IP12_31_28      FM(IP13_31_28)  IP13_31_28      FM(IP14_31_28)  IP14_31_28      FM(IP15_31_28)  IP15_31_28 \
 442 \
 443 FM(IP16_3_0)    IP16_3_0        FM(IP17_3_0)    IP17_3_0        FM(IP18_3_0)    IP18_3_0 \
 444 FM(IP16_7_4)    IP16_7_4        FM(IP17_7_4)    IP17_7_4        FM(IP18_7_4)    IP18_7_4 \
 445 FM(IP16_11_8)   IP16_11_8       FM(IP17_11_8)   IP17_11_8 \
 446 FM(IP16_15_12)  IP16_15_12      FM(IP17_15_12)  IP17_15_12 \
 447 FM(IP16_19_16)  IP16_19_16      FM(IP17_19_16)  IP17_19_16 \
 448 FM(IP16_23_20)  IP16_23_20      FM(IP17_23_20)  IP17_23_20 \
 449 FM(IP16_27_24)  IP16_27_24      FM(IP17_27_24)  IP17_27_24 \
 450 FM(IP16_31_28)  IP16_31_28      FM(IP17_31_28)  IP17_31_28
 451
 452 /* MOD_SEL0 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 453 #define MOD_SEL0_31_30_29       FM(SEL_MSIOF3_0)        FM(SEL_MSIOF3_1)        FM(SEL_MSIOF3_2)        FM(SEL_MSIOF3_3)        FM(SEL_MSIOF3_4)        F_(0, 0)                F_(0, 0)                F_(0, 0)
 454 #define MOD_SEL0_28_27          FM(SEL_MSIOF2_0)        FM(SEL_MSIOF2_1)        FM(SEL_MSIOF2_2)        FM(SEL_MSIOF2_3)
 455 #define MOD_SEL0_26_25_24       FM(SEL_MSIOF1_0)        FM(SEL_MSIOF1_1)        FM(SEL_MSIOF1_2)        FM(SEL_MSIOF1_3)        FM(SEL_MSIOF1_4)        FM(SEL_MSIOF1_5)        FM(SEL_MSIOF1_6)        F_(0, 0)
 456 #define MOD_SEL0_23             FM(SEL_LBSC_0)          FM(SEL_LBSC_1)
 457 #define MOD_SEL0_22             FM(SEL_IEBUS_0)         FM(SEL_IEBUS_1)
 458 #define MOD_SEL0_21             FM(SEL_I2C2_0)          FM(SEL_I2C2_1)
 459 #define MOD_SEL0_20             FM(SEL_I2C1_0)          FM(SEL_I2C1_1)
 460 #define MOD_SEL0_19             FM(SEL_HSCIF4_0)        FM(SEL_HSCIF4_1)
 461 #define MOD_SEL0_18_17          FM(SEL_HSCIF3_0)        FM(SEL_HSCIF3_1)        FM(SEL_HSCIF3_2)        FM(SEL_HSCIF3_3)
 462 #define MOD_SEL0_16             FM(SEL_HSCIF1_0)        FM(SEL_HSCIF1_1)
 463 #define MOD_SEL0_14_13          FM(SEL_HSCIF2_0)        FM(SEL_HSCIF2_1)        FM(SEL_HSCIF2_2)        F_(0, 0)
 464 #define MOD_SEL0_12             FM(SEL_ETHERAVB_0)      FM(SEL_ETHERAVB_1)
 465 #define MOD_SEL0_11             FM(SEL_DRIF3_0)         FM(SEL_DRIF3_1)
 466 #define MOD_SEL0_10             FM(SEL_DRIF2_0)         FM(SEL_DRIF2_1)
 467 #define MOD_SEL0_9_8            FM(SEL_DRIF1_0)         FM(SEL_DRIF1_1)         FM(SEL_DRIF1_2)         F_(0, 0)
 468 #define MOD_SEL0_7_6            FM(SEL_DRIF0_0)         FM(SEL_DRIF0_1)         FM(SEL_DRIF0_2)         F_(0, 0)
 469 #define MOD_SEL0_5              FM(SEL_CANFD0_0)        FM(SEL_CANFD0_1)
 470 #define MOD_SEL0_4_3            FM(SEL_ADG_A_0)         FM(SEL_ADG_A_1)         FM(SEL_ADG_A_2)         FM(SEL_ADG_A_3)
 471
 472 /* MOD_SEL1 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 473 #define MOD_SEL1_31_30          FM(SEL_TSIF1_0)         FM(SEL_TSIF1_1)         FM(SEL_TSIF1_2)         FM(SEL_TSIF1_3)
 474 #define MOD_SEL1_29_28_27       FM(SEL_TSIF0_0)         FM(SEL_TSIF0_1)         FM(SEL_TSIF0_2)         FM(SEL_TSIF0_3)         FM(SEL_TSIF0_4)         F_(0, 0)                F_(0, 0)                F_(0, 0)
 475 #define MOD_SEL1_26             FM(SEL_TIMER_TMU_0)     FM(SEL_TIMER_TMU_1)
 476 #define MOD_SEL1_25_24          FM(SEL_SSP1_1_0)        FM(SEL_SSP1_1_1)        FM(SEL_SSP1_1_2)        FM(SEL_SSP1_1_3)
 477 #define MOD_SEL1_23_22_21       FM(SEL_SSP1_0_0)        FM(SEL_SSP1_0_1)        FM(SEL_SSP1_0_2)        FM(SEL_SSP1_0_3)        FM(SEL_SSP1_0_4)        F_(0, 0)                F_(0, 0)                F_(0, 0)
 478 #define MOD_SEL1_20             FM(SEL_SSI1_0)          FM(SEL_SSI1_1)
 479 #define MOD_SEL1_19             FM(SEL_SPEED_PULSE_0)   FM(SEL_SPEED_PULSE_1)
 480 #define MOD_SEL1_18_17          FM(SEL_SIMCARD_0)       FM(SEL_SIMCARD_1)       FM(SEL_SIMCARD_2)       FM(SEL_SIMCARD_3)
 481 #define MOD_SEL1_16             FM(SEL_SDHI2_0)         FM(SEL_SDHI2_1)
 482 #define MOD_SEL1_15_14          FM(SEL_SCIF4_0)         FM(SEL_SCIF4_1)         FM(SEL_SCIF4_2)         F_(0, 0)
 483 #define MOD_SEL1_13             FM(SEL_SCIF3_0)         FM(SEL_SCIF3_1)
 484 #define MOD_SEL1_12             FM(SEL_SCIF2_0)         FM(SEL_SCIF2_1)
 485 #define MOD_SEL1_11             FM(SEL_SCIF1_0)         FM(SEL_SCIF1_1)
 486 #define MOD_SEL1_10             FM(SEL_SCIF_0)          FM(SEL_SCIF_1)
 487 #define MOD_SEL1_9              FM(SEL_REMOCON_0)       FM(SEL_REMOCON_1)
 488 #define MOD_SEL1_6              FM(SEL_RCAN0_0)         FM(SEL_RCAN0_1)
 489 #define MOD_SEL1_5              FM(SEL_PWM6_0)          FM(SEL_PWM6_1)
 490 #define MOD_SEL1_4              FM(SEL_PWM5_0)          FM(SEL_PWM5_1)
 491 #define MOD_SEL1_3              FM(SEL_PWM4_0)          FM(SEL_PWM4_1)
 492 #define MOD_SEL1_2              FM(SEL_PWM3_0)          FM(SEL_PWM3_1)
 493 #define MOD_SEL1_1              FM(SEL_PWM2_0)          FM(SEL_PWM2_1)
 494 #define MOD_SEL1_0              FM(SEL_PWM1_0)          FM(SEL_PWM1_1)
 495
 496 /* MOD_SEL2 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 497 #define MOD_SEL2_31             FM(I2C_SEL_5_0)         FM(I2C_SEL_5_1)
 498 #define MOD_SEL2_30             FM(I2C_SEL_3_0)         FM(I2C_SEL_3_1)
 499 #define MOD_SEL2_29             FM(I2C_SEL_0_0)         FM(I2C_SEL_0_1)
 500 #define MOD_SEL2_28_27          FM(SEL_FM_0)            FM(SEL_FM_1)            FM(SEL_FM_2)            FM(SEL_FM_3)
 501 #define MOD_SEL2_26             FM(SEL_SCIF5_0)         FM(SEL_SCIF5_1)
 502 #define MOD_SEL2_25_24_23       FM(SEL_I2C6_0)          FM(SEL_I2C6_1)          FM(SEL_I2C6_2)          F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)
 503 #define MOD_SEL2_22             FM(SEL_NDFC_0)          FM(SEL_NDFC_1)
 504 #define MOD_SEL2_21             FM(SEL_SSI2_0)          FM(SEL_SSI2_1)
 505 #define MOD_SEL2_20             FM(SEL_SSI9_0)          FM(SEL_SSI9_1)
 506 #define MOD_SEL2_19             FM(SEL_TIMER_TMU2_0)    FM(SEL_TIMER_TMU2_1)
 507 #define MOD_SEL2_18             FM(SEL_ADG_B_0)         FM(SEL_ADG_B_1)
 508 #define MOD_SEL2_17             FM(SEL_ADG_C_0)         FM(SEL_ADG_C_1)
 509 #define MOD_SEL2_0              FM(SEL_VIN4_0)          FM(SEL_VIN4_1)
 510
 511 #define PINMUX_MOD_SELS \
 512 \
 513 MOD_SEL0_31_30_29       MOD_SEL1_31_30          MOD_SEL2_31 \
 514                                                 MOD_SEL2_30 \
 515                         MOD_SEL1_29_28_27       MOD_SEL2_29 \
 516 MOD_SEL0_28_27                                  MOD_SEL2_28_27 \
 517 MOD_SEL0_26_25_24       MOD_SEL1_26             MOD_SEL2_26 \
 518                         MOD_SEL1_25_24          MOD_SEL2_25_24_23 \
 519 MOD_SEL0_23             MOD_SEL1_23_22_21 \
 520 MOD_SEL0_22                                     MOD_SEL2_22 \
 521 MOD_SEL0_21                                     MOD_SEL2_21 \
 522 MOD_SEL0_20             MOD_SEL1_20             MOD_SEL2_20 \
 523 MOD_SEL0_19             MOD_SEL1_19             MOD_SEL2_19 \
 524 MOD_SEL0_18_17          MOD_SEL1_18_17          MOD_SEL2_18 \
 525                                                 MOD_SEL2_17 \
 526 MOD_SEL0_16             MOD_SEL1_16 \
 527                         MOD_SEL1_15_14 \
 528 MOD_SEL0_14_13 \
 529                         MOD_SEL1_13 \
 530 MOD_SEL0_12             MOD_SEL1_12 \
 531 MOD_SEL0_11             MOD_SEL1_11 \
 532 MOD_SEL0_10             MOD_SEL1_10 \
 533 MOD_SEL0_9_8            MOD_SEL1_9 \
 534 MOD_SEL0_7_6 \
 535                         MOD_SEL1_6 \
 536 MOD_SEL0_5              MOD_SEL1_5 \
 537 MOD_SEL0_4_3            MOD_SEL1_4 \
 538                         MOD_SEL1_3 \
 539                         MOD_SEL1_2 \
 540                         MOD_SEL1_1 \
 541                         MOD_SEL1_0              MOD_SEL2_0
 542
 543 /*
 544  * These pins are not able to be muxed but have other properties
 545  * that can be set, such as drive-strength or pull-up/pull-down enable.
 546  */
 547 #define PINMUX_STATIC \
 548         FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
 549         FM(QSPI0_IO2) FM(QSPI0_IO3) \
 550         FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
 551         FM(QSPI1_IO2) FM(QSPI1_IO3) \
 552         FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
 553         FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
 554         FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
 555         FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
 556         FM(PRESETOUT) \
 557         FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
 558         FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
 559
 560 enum {
 561         PINMUX_RESERVED = 0,
 562
 563         PINMUX_DATA_BEGIN,
 564         GP_ALL(DATA),
 565         PINMUX_DATA_END,
 566
 567 #define F_(x, y)
 568 #define FM(x)   FN_##x,
 569         PINMUX_FUNCTION_BEGIN,
 570         GP_ALL(FN),
 571         PINMUX_GPSR
 572         PINMUX_IPSR
 573         PINMUX_MOD_SELS
 574         PINMUX_FUNCTION_END,
 575 #undef F_
 576 #undef FM
 577
 578 #define F_(x, y)
 579 #define FM(x)   x##_MARK,
 580         PINMUX_MARK_BEGIN,
 581         PINMUX_GPSR
 582         PINMUX_IPSR
 583         PINMUX_MOD_SELS
 584         PINMUX_STATIC
 585         PINMUX_MARK_END,
 586 #undef F_
 587 #undef FM
 588 };
 589
 590 static const u16 pinmux_data[] = {
 591         PINMUX_DATA_GP_ALL(),
 592
 593         PINMUX_SINGLE(AVS1),
 594         PINMUX_SINGLE(AVS2),
 595         PINMUX_SINGLE(CLKOUT),
 596         PINMUX_SINGLE(GP7_03),
 597         PINMUX_SINGLE(HDMI0_CEC),
 598         PINMUX_SINGLE(MSIOF0_RXD),
 599         PINMUX_SINGLE(MSIOF0_SCK),
 600         PINMUX_SINGLE(MSIOF0_TXD),
 601         PINMUX_SINGLE(SSI_SCK5),
 602         PINMUX_SINGLE(SSI_SDATA5),
 603         PINMUX_SINGLE(SSI_WS5),
 604
 605         /* IPSR0 */
 606         PINMUX_IPSR_GPSR(IP0_3_0,       AVB_MDC),
 607         PINMUX_IPSR_MSEL(IP0_3_0,       MSIOF2_SS2_C,           SEL_MSIOF2_2),
 608
 609         PINMUX_IPSR_GPSR(IP0_7_4,       AVB_MAGIC),
 610         PINMUX_IPSR_MSEL(IP0_7_4,       MSIOF2_SS1_C,           SEL_MSIOF2_2),
 611         PINMUX_IPSR_MSEL(IP0_7_4,       SCK4_A,                 SEL_SCIF4_0),
 612
 613         PINMUX_IPSR_GPSR(IP0_11_8,      AVB_PHY_INT),
 614         PINMUX_IPSR_MSEL(IP0_11_8,      MSIOF2_SYNC_C,          SEL_MSIOF2_2),
 615         PINMUX_IPSR_MSEL(IP0_11_8,      RX4_A,                  SEL_SCIF4_0),
 616
 617         PINMUX_IPSR_GPSR(IP0_15_12,     AVB_LINK),
 618         PINMUX_IPSR_MSEL(IP0_15_12,     MSIOF2_SCK_C,           SEL_MSIOF2_2),
 619         PINMUX_IPSR_MSEL(IP0_15_12,     TX4_A,                  SEL_SCIF4_0),
 620         PINMUX_IPSR_GPSR(IP0_19_16,     FSCLKST2_N_A),
 621
 622         PINMUX_IPSR_MSEL(IP0_19_16,     AVB_AVTP_MATCH_A,       SEL_ETHERAVB_0),
 623         PINMUX_IPSR_MSEL(IP0_19_16,     MSIOF2_RXD_C,           SEL_MSIOF2_2),
 624         PINMUX_IPSR_MSEL(IP0_19_16,     CTS4_N_A,               SEL_SCIF4_0),
 625
 626         PINMUX_IPSR_MSEL(IP0_23_20,     AVB_AVTP_CAPTURE_A,     SEL_ETHERAVB_0),
 627         PINMUX_IPSR_MSEL(IP0_23_20,     MSIOF2_TXD_C,           SEL_MSIOF2_2),
 628         PINMUX_IPSR_MSEL(IP0_23_20,     RTS4_N_A,               SEL_SCIF4_0),
 629
 630         PINMUX_IPSR_GPSR(IP0_27_24,     IRQ0),
 631         PINMUX_IPSR_GPSR(IP0_27_24,     QPOLB),
 632         PINMUX_IPSR_GPSR(IP0_27_24,     DU_CDE),
 633         PINMUX_IPSR_MSEL(IP0_27_24,     VI4_DATA0_B,            SEL_VIN4_1),
 634         PINMUX_IPSR_MSEL(IP0_27_24,     CAN0_TX_B,              SEL_RCAN0_1),
 635         PINMUX_IPSR_MSEL(IP0_27_24,     CANFD0_TX_B,            SEL_CANFD0_1),
 636         PINMUX_IPSR_MSEL(IP0_27_24,     MSIOF3_SS2_E,           SEL_MSIOF3_4),
 637
 638         PINMUX_IPSR_GPSR(IP0_31_28,     IRQ1),
 639         PINMUX_IPSR_GPSR(IP0_31_28,     QPOLA),
 640         PINMUX_IPSR_GPSR(IP0_31_28,     DU_DISP),
 641         PINMUX_IPSR_MSEL(IP0_31_28,     VI4_DATA1_B,            SEL_VIN4_1),
 642         PINMUX_IPSR_MSEL(IP0_31_28,     CAN0_RX_B,              SEL_RCAN0_1),
 643         PINMUX_IPSR_MSEL(IP0_31_28,     CANFD0_RX_B,            SEL_CANFD0_1),
 644         PINMUX_IPSR_MSEL(IP0_31_28,     MSIOF3_SS1_E,           SEL_MSIOF3_4),
 645
 646         /* IPSR1 */
 647         PINMUX_IPSR_GPSR(IP1_3_0,       IRQ2),
 648         PINMUX_IPSR_GPSR(IP1_3_0,       QCPV_QDE),
 649         PINMUX_IPSR_GPSR(IP1_3_0,       DU_EXODDF_DU_ODDF_DISP_CDE),
 650         PINMUX_IPSR_MSEL(IP1_3_0,       VI4_DATA2_B,            SEL_VIN4_1),
 651         PINMUX_IPSR_MSEL(IP1_3_0,       PWM3_B,                 SEL_PWM3_1),
 652         PINMUX_IPSR_MSEL(IP1_3_0,       MSIOF3_SYNC_E,          SEL_MSIOF3_4),
 653
 654         PINMUX_IPSR_GPSR(IP1_7_4,       IRQ3),
 655         PINMUX_IPSR_GPSR(IP1_7_4,       QSTVB_QVE),
 656         PINMUX_IPSR_GPSR(IP1_7_4,       DU_DOTCLKOUT1),
 657         PINMUX_IPSR_MSEL(IP1_7_4,       VI4_DATA3_B,            SEL_VIN4_1),
 658         PINMUX_IPSR_MSEL(IP1_7_4,       PWM4_B,                 SEL_PWM4_1),
 659         PINMUX_IPSR_MSEL(IP1_7_4,       MSIOF3_SCK_E,           SEL_MSIOF3_4),
 660
 661         PINMUX_IPSR_GPSR(IP1_11_8,      IRQ4),
 662         PINMUX_IPSR_GPSR(IP1_11_8,      QSTH_QHS),
 663         PINMUX_IPSR_GPSR(IP1_11_8,      DU_EXHSYNC_DU_HSYNC),
 664         PINMUX_IPSR_MSEL(IP1_11_8,      VI4_DATA4_B,            SEL_VIN4_1),
 665         PINMUX_IPSR_MSEL(IP1_11_8,      PWM5_B,                 SEL_PWM5_1),
 666         PINMUX_IPSR_MSEL(IP1_11_8,      MSIOF3_RXD_E,           SEL_MSIOF3_4),
 667
 668         PINMUX_IPSR_GPSR(IP1_15_12,     IRQ5),
 669         PINMUX_IPSR_GPSR(IP1_15_12,     QSTB_QHE),
 670         PINMUX_IPSR_GPSR(IP1_15_12,     DU_EXVSYNC_DU_VSYNC),
 671         PINMUX_IPSR_MSEL(IP1_15_12,     VI4_DATA5_B,            SEL_VIN4_1),
 672         PINMUX_IPSR_MSEL(IP1_15_12,     PWM6_B,                 SEL_PWM6_1),
 673         PINMUX_IPSR_GPSR(IP1_15_12,     FSCLKST2_N_B),
 674         PINMUX_IPSR_MSEL(IP1_15_12,     MSIOF3_TXD_E,           SEL_MSIOF3_4),
 675
 676         PINMUX_IPSR_GPSR(IP1_19_16,     PWM0),
 677         PINMUX_IPSR_GPSR(IP1_19_16,     AVB_AVTP_PPS),
 678         PINMUX_IPSR_MSEL(IP1_19_16,     VI4_DATA6_B,            SEL_VIN4_1),
 679         PINMUX_IPSR_MSEL(IP1_19_16,     IECLK_B,                SEL_IEBUS_1),
 680
 681         PINMUX_IPSR_MSEL(IP1_23_20,     PWM1_A,                 SEL_PWM1_0),
 682         PINMUX_IPSR_MSEL(IP1_23_20,     HRX3_D,                 SEL_HSCIF3_3),
 683         PINMUX_IPSR_MSEL(IP1_23_20,     VI4_DATA7_B,            SEL_VIN4_1),
 684         PINMUX_IPSR_MSEL(IP1_23_20,     IERX_B,                 SEL_IEBUS_1),
 685
 686         PINMUX_IPSR_MSEL(IP1_27_24,     PWM2_A,                 SEL_PWM2_0),
 687         PINMUX_IPSR_MSEL(IP1_27_24,     HTX3_D,                 SEL_HSCIF3_3),
 688         PINMUX_IPSR_MSEL(IP1_27_24,     IETX_B,                 SEL_IEBUS_1),
 689
 690         PINMUX_IPSR_GPSR(IP1_31_28,     A0),
 691         PINMUX_IPSR_GPSR(IP1_31_28,     LCDOUT16),
 692         PINMUX_IPSR_MSEL(IP1_31_28,     MSIOF3_SYNC_B,          SEL_MSIOF3_1),
 693         PINMUX_IPSR_GPSR(IP1_31_28,     VI4_DATA8),
 694         PINMUX_IPSR_GPSR(IP1_31_28,     DU_DB0),
 695         PINMUX_IPSR_MSEL(IP1_31_28,     PWM3_A,                 SEL_PWM3_0),
 696
 697         /* IPSR2 */
 698         PINMUX_IPSR_GPSR(IP2_3_0,       A1),
 699         PINMUX_IPSR_GPSR(IP2_3_0,       LCDOUT17),
 700         PINMUX_IPSR_MSEL(IP2_3_0,       MSIOF3_TXD_B,           SEL_MSIOF3_1),
 701         PINMUX_IPSR_GPSR(IP2_3_0,       VI4_DATA9),
 702         PINMUX_IPSR_GPSR(IP2_3_0,       DU_DB1),
 703         PINMUX_IPSR_MSEL(IP2_3_0,       PWM4_A,                 SEL_PWM4_0),
 704
 705         PINMUX_IPSR_GPSR(IP2_7_4,       A2),
 706         PINMUX_IPSR_GPSR(IP2_7_4,       LCDOUT18),
 707         PINMUX_IPSR_MSEL(IP2_7_4,       MSIOF3_SCK_B,           SEL_MSIOF3_1),
 708         PINMUX_IPSR_GPSR(IP2_7_4,       VI4_DATA10),
 709         PINMUX_IPSR_GPSR(IP2_7_4,       DU_DB2),
 710         PINMUX_IPSR_MSEL(IP2_7_4,       PWM5_A,                 SEL_PWM5_0),
 711
 712         PINMUX_IPSR_GPSR(IP2_11_8,      A3),
 713         PINMUX_IPSR_GPSR(IP2_11_8,      LCDOUT19),
 714         PINMUX_IPSR_MSEL(IP2_11_8,      MSIOF3_RXD_B,           SEL_MSIOF3_1),
 715         PINMUX_IPSR_GPSR(IP2_11_8,      VI4_DATA11),
 716         PINMUX_IPSR_GPSR(IP2_11_8,      DU_DB3),
 717         PINMUX_IPSR_MSEL(IP2_11_8,      PWM6_A,                 SEL_PWM6_0),
 718
 719         PINMUX_IPSR_GPSR(IP2_15_12,     A4),
 720         PINMUX_IPSR_GPSR(IP2_15_12,     LCDOUT20),
 721         PINMUX_IPSR_MSEL(IP2_15_12,     MSIOF3_SS1_B,           SEL_MSIOF3_1),
 722         PINMUX_IPSR_GPSR(IP2_15_12,     VI4_DATA12),
 723         PINMUX_IPSR_GPSR(IP2_15_12,     VI5_DATA12),
 724         PINMUX_IPSR_GPSR(IP2_15_12,     DU_DB4),
 725
 726         PINMUX_IPSR_GPSR(IP2_19_16,     A5),
 727         PINMUX_IPSR_GPSR(IP2_19_16,     LCDOUT21),
 728         PINMUX_IPSR_MSEL(IP2_19_16,     MSIOF3_SS2_B,           SEL_MSIOF3_1),
 729         PINMUX_IPSR_MSEL(IP2_19_16,     SCK4_B,                 SEL_SCIF4_1),
 730         PINMUX_IPSR_GPSR(IP2_19_16,     VI4_DATA13),
 731         PINMUX_IPSR_GPSR(IP2_19_16,     VI5_DATA13),
 732         PINMUX_IPSR_GPSR(IP2_19_16,     DU_DB5),
 733
 734         PINMUX_IPSR_GPSR(IP2_23_20,     A6),
 735         PINMUX_IPSR_GPSR(IP2_23_20,     LCDOUT22),
 736         PINMUX_IPSR_MSEL(IP2_23_20,     MSIOF2_SS1_A,           SEL_MSIOF2_0),
 737         PINMUX_IPSR_MSEL(IP2_23_20,     RX4_B,                  SEL_SCIF4_1),
 738         PINMUX_IPSR_GPSR(IP2_23_20,     VI4_DATA14),
 739         PINMUX_IPSR_GPSR(IP2_23_20,     VI5_DATA14),
 740         PINMUX_IPSR_GPSR(IP2_23_20,     DU_DB6),
 741
 742         PINMUX_IPSR_GPSR(IP2_27_24,     A7),
 743         PINMUX_IPSR_GPSR(IP2_27_24,     LCDOUT23),
 744         PINMUX_IPSR_MSEL(IP2_27_24,     MSIOF2_SS2_A,           SEL_MSIOF2_0),
 745         PINMUX_IPSR_MSEL(IP2_27_24,     TX4_B,                  SEL_SCIF4_1),
 746         PINMUX_IPSR_GPSR(IP2_27_24,     VI4_DATA15),
 747         PINMUX_IPSR_GPSR(IP2_27_24,     VI5_DATA15),
 748         PINMUX_IPSR_GPSR(IP2_27_24,     DU_DB7),
 749
 750         PINMUX_IPSR_GPSR(IP2_31_28,     A8),
 751         PINMUX_IPSR_MSEL(IP2_31_28,     RX3_B,                  SEL_SCIF3_1),
 752         PINMUX_IPSR_MSEL(IP2_31_28,     MSIOF2_SYNC_A,          SEL_MSIOF2_0),
 753         PINMUX_IPSR_MSEL(IP2_31_28,     HRX4_B,                 SEL_HSCIF4_1),
 754         PINMUX_IPSR_MSEL(IP2_31_28,     SDA6_A,                 SEL_I2C6_0),
 755         PINMUX_IPSR_MSEL(IP2_31_28,     AVB_AVTP_MATCH_B,       SEL_ETHERAVB_1),
 756         PINMUX_IPSR_MSEL(IP2_31_28,     PWM1_B,                 SEL_PWM1_1),
 757
 758         /* IPSR3 */
 759         PINMUX_IPSR_GPSR(IP3_3_0,       A9),
 760         PINMUX_IPSR_MSEL(IP3_3_0,       MSIOF2_SCK_A,           SEL_MSIOF2_0),
 761         PINMUX_IPSR_MSEL(IP3_3_0,       CTS4_N_B,               SEL_SCIF4_1),
 762         PINMUX_IPSR_GPSR(IP3_3_0,       VI5_VSYNC_N),
 763
 764         PINMUX_IPSR_GPSR(IP3_7_4,       A10),
 765         PINMUX_IPSR_MSEL(IP3_7_4,       MSIOF2_RXD_A,           SEL_MSIOF2_0),
 766         PINMUX_IPSR_MSEL(IP3_7_4,       RTS4_N_B,               SEL_SCIF4_1),
 767         PINMUX_IPSR_GPSR(IP3_7_4,       VI5_HSYNC_N),
 768
 769         PINMUX_IPSR_GPSR(IP3_11_8,      A11),
 770         PINMUX_IPSR_MSEL(IP3_11_8,      TX3_B,                  SEL_SCIF3_1),
 771         PINMUX_IPSR_MSEL(IP3_11_8,      MSIOF2_TXD_A,           SEL_MSIOF2_0),
 772         PINMUX_IPSR_MSEL(IP3_11_8,      HTX4_B,                 SEL_HSCIF4_1),
 773         PINMUX_IPSR_GPSR(IP3_11_8,      HSCK4),
 774         PINMUX_IPSR_GPSR(IP3_11_8,      VI5_FIELD),
 775         PINMUX_IPSR_MSEL(IP3_11_8,      SCL6_A,                 SEL_I2C6_0),
 776         PINMUX_IPSR_MSEL(IP3_11_8,      AVB_AVTP_CAPTURE_B,     SEL_ETHERAVB_1),
 777         PINMUX_IPSR_MSEL(IP3_11_8,      PWM2_B,                 SEL_PWM2_1),
 778
 779         PINMUX_IPSR_GPSR(IP3_15_12,     A12),
 780         PINMUX_IPSR_GPSR(IP3_15_12,     LCDOUT12),
 781         PINMUX_IPSR_MSEL(IP3_15_12,     MSIOF3_SCK_C,           SEL_MSIOF3_2),
 782         PINMUX_IPSR_MSEL(IP3_15_12,     HRX4_A,                 SEL_HSCIF4_0),
 783         PINMUX_IPSR_GPSR(IP3_15_12,     VI5_DATA8),
 784         PINMUX_IPSR_GPSR(IP3_15_12,     DU_DG4),
 785
 786         PINMUX_IPSR_GPSR(IP3_19_16,     A13),
 787         PINMUX_IPSR_GPSR(IP3_19_16,     LCDOUT13),
 788         PINMUX_IPSR_MSEL(IP3_19_16,     MSIOF3_SYNC_C,          SEL_MSIOF3_2),
 789         PINMUX_IPSR_MSEL(IP3_19_16,     HTX4_A,                 SEL_HSCIF4_0),
 790         PINMUX_IPSR_GPSR(IP3_19_16,     VI5_DATA9),
 791         PINMUX_IPSR_GPSR(IP3_19_16,     DU_DG5),
 792
 793         PINMUX_IPSR_GPSR(IP3_23_20,     A14),
 794         PINMUX_IPSR_GPSR(IP3_23_20,     LCDOUT14),
 795         PINMUX_IPSR_MSEL(IP3_23_20,     MSIOF3_RXD_C,           SEL_MSIOF3_2),
 796         PINMUX_IPSR_GPSR(IP3_23_20,     HCTS4_N),
 797         PINMUX_IPSR_GPSR(IP3_23_20,     VI5_DATA10),
 798         PINMUX_IPSR_GPSR(IP3_23_20,     DU_DG6),
 799
 800         PINMUX_IPSR_GPSR(IP3_27_24,     A15),
 801         PINMUX_IPSR_GPSR(IP3_27_24,     LCDOUT15),
 802         PINMUX_IPSR_MSEL(IP3_27_24,     MSIOF3_TXD_C,           SEL_MSIOF3_2),
 803         PINMUX_IPSR_GPSR(IP3_27_24,     HRTS4_N),
 804         PINMUX_IPSR_GPSR(IP3_27_24,     VI5_DATA11),
 805         PINMUX_IPSR_GPSR(IP3_27_24,     DU_DG7),
 806
 807         PINMUX_IPSR_GPSR(IP3_31_28,     A16),
 808         PINMUX_IPSR_GPSR(IP3_31_28,     LCDOUT8),
 809         PINMUX_IPSR_GPSR(IP3_31_28,     VI4_FIELD),
 810         PINMUX_IPSR_GPSR(IP3_31_28,     DU_DG0),
 811
 812         /* IPSR4 */
 813         PINMUX_IPSR_GPSR(IP4_3_0,       A17),
 814         PINMUX_IPSR_GPSR(IP4_3_0,       LCDOUT9),
 815         PINMUX_IPSR_GPSR(IP4_3_0,       VI4_VSYNC_N),
 816         PINMUX_IPSR_GPSR(IP4_3_0,       DU_DG1),
 817
 818         PINMUX_IPSR_GPSR(IP4_7_4,       A18),
 819         PINMUX_IPSR_GPSR(IP4_7_4,       LCDOUT10),
 820         PINMUX_IPSR_GPSR(IP4_7_4,       VI4_HSYNC_N),
 821         PINMUX_IPSR_GPSR(IP4_7_4,       DU_DG2),
 822
 823         PINMUX_IPSR_GPSR(IP4_11_8,      A19),
 824         PINMUX_IPSR_GPSR(IP4_11_8,      LCDOUT11),
 825         PINMUX_IPSR_GPSR(IP4_11_8,      VI4_CLKENB),
 826         PINMUX_IPSR_GPSR(IP4_11_8,      DU_DG3),
 827
 828         PINMUX_IPSR_GPSR(IP4_15_12,     CS0_N),
 829         PINMUX_IPSR_GPSR(IP4_15_12,     VI5_CLKENB),
 830
 831         PINMUX_IPSR_GPSR(IP4_19_16,     CS1_N),
 832         PINMUX_IPSR_GPSR(IP4_19_16,     VI5_CLK),
 833         PINMUX_IPSR_MSEL(IP4_19_16,     EX_WAIT0_B,             SEL_LBSC_1),
 834
 835         PINMUX_IPSR_GPSR(IP4_23_20,     BS_N),
 836         PINMUX_IPSR_GPSR(IP4_23_20,     QSTVA_QVS),
 837         PINMUX_IPSR_MSEL(IP4_23_20,     MSIOF3_SCK_D,           SEL_MSIOF3_3),
 838         PINMUX_IPSR_GPSR(IP4_23_20,     SCK3),
 839         PINMUX_IPSR_GPSR(IP4_23_20,     HSCK3),
 840         PINMUX_IPSR_GPSR(IP4_23_20,     CAN1_TX),
 841         PINMUX_IPSR_GPSR(IP4_23_20,     CANFD1_TX),
 842         PINMUX_IPSR_MSEL(IP4_23_20,     IETX_A,                 SEL_IEBUS_0),
 843
 844         PINMUX_IPSR_GPSR(IP4_27_24,     RD_N),
 845         PINMUX_IPSR_MSEL(IP4_27_24,     MSIOF3_SYNC_D,          SEL_MSIOF3_3),
 846         PINMUX_IPSR_MSEL(IP4_27_24,     RX3_A,                  SEL_SCIF3_0),
 847         PINMUX_IPSR_MSEL(IP4_27_24,     HRX3_A,                 SEL_HSCIF3_0),
 848         PINMUX_IPSR_MSEL(IP4_27_24,     CAN0_TX_A,              SEL_RCAN0_0),
 849         PINMUX_IPSR_MSEL(IP4_27_24,     CANFD0_TX_A,            SEL_CANFD0_0),
 850
 851         PINMUX_IPSR_GPSR(IP4_31_28,     RD_WR_N),
 852         PINMUX_IPSR_MSEL(IP4_31_28,     MSIOF3_RXD_D,           SEL_MSIOF3_3),
 853         PINMUX_IPSR_MSEL(IP4_31_28,     TX3_A,                  SEL_SCIF3_0),
 854         PINMUX_IPSR_MSEL(IP4_31_28,     HTX3_A,                 SEL_HSCIF3_0),
 855         PINMUX_IPSR_MSEL(IP4_31_28,     CAN0_RX_A,              SEL_RCAN0_0),
 856         PINMUX_IPSR_MSEL(IP4_31_28,     CANFD0_RX_A,            SEL_CANFD0_0),
 857
 858         /* IPSR5 */
 859         PINMUX_IPSR_GPSR(IP5_3_0,       WE0_N),
 860         PINMUX_IPSR_MSEL(IP5_3_0,       MSIOF3_TXD_D,           SEL_MSIOF3_3),
 861         PINMUX_IPSR_GPSR(IP5_3_0,       CTS3_N),
 862         PINMUX_IPSR_GPSR(IP5_3_0,       HCTS3_N),
 863         PINMUX_IPSR_MSEL(IP5_3_0,       SCL6_B,                 SEL_I2C6_1),
 864         PINMUX_IPSR_GPSR(IP5_3_0,       CAN_CLK),
 865         PINMUX_IPSR_MSEL(IP5_3_0,       IECLK_A,                SEL_IEBUS_0),
 866
 867         PINMUX_IPSR_GPSR(IP5_7_4,       WE1_N),
 868         PINMUX_IPSR_MSEL(IP5_7_4,       MSIOF3_SS1_D,           SEL_MSIOF3_3),
 869         PINMUX_IPSR_GPSR(IP5_7_4,       RTS3_N),
 870         PINMUX_IPSR_GPSR(IP5_7_4,       HRTS3_N),
 871         PINMUX_IPSR_MSEL(IP5_7_4,       SDA6_B,                 SEL_I2C6_1),
 872         PINMUX_IPSR_GPSR(IP5_7_4,       CAN1_RX),
 873         PINMUX_IPSR_GPSR(IP5_7_4,       CANFD1_RX),
 874         PINMUX_IPSR_MSEL(IP5_7_4,       IERX_A,                 SEL_IEBUS_0),
 875
 876         PINMUX_IPSR_MSEL(IP5_11_8,      EX_WAIT0_A,             SEL_LBSC_0),
 877         PINMUX_IPSR_GPSR(IP5_11_8,      QCLK),
 878         PINMUX_IPSR_GPSR(IP5_11_8,      VI4_CLK),
 879         PINMUX_IPSR_GPSR(IP5_11_8,      DU_DOTCLKOUT0),
 880
 881         PINMUX_IPSR_GPSR(IP5_15_12,     D0),
 882         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF2_SS1_B,           SEL_MSIOF2_1),
 883         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF3_SCK_A,           SEL_MSIOF3_0),
 884         PINMUX_IPSR_GPSR(IP5_15_12,     VI4_DATA16),
 885         PINMUX_IPSR_GPSR(IP5_15_12,     VI5_DATA0),
 886
 887         PINMUX_IPSR_GPSR(IP5_19_16,     D1),
 888         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF2_SS2_B,           SEL_MSIOF2_1),
 889         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF3_SYNC_A,          SEL_MSIOF3_0),
 890         PINMUX_IPSR_GPSR(IP5_19_16,     VI4_DATA17),
 891         PINMUX_IPSR_GPSR(IP5_19_16,     VI5_DATA1),
 892
 893         PINMUX_IPSR_GPSR(IP5_23_20,     D2),
 894         PINMUX_IPSR_MSEL(IP5_23_20,     MSIOF3_RXD_A,           SEL_MSIOF3_0),
 895         PINMUX_IPSR_GPSR(IP5_23_20,     VI4_DATA18),
 896         PINMUX_IPSR_GPSR(IP5_23_20,     VI5_DATA2),
 897
 898         PINMUX_IPSR_GPSR(IP5_27_24,     D3),
 899         PINMUX_IPSR_MSEL(IP5_27_24,     MSIOF3_TXD_A,           SEL_MSIOF3_0),
 900         PINMUX_IPSR_GPSR(IP5_27_24,     VI4_DATA19),
 901         PINMUX_IPSR_GPSR(IP5_27_24,     VI5_DATA3),
 902
 903         PINMUX_IPSR_GPSR(IP5_31_28,     D4),
 904         PINMUX_IPSR_MSEL(IP5_31_28,     MSIOF2_SCK_B,           SEL_MSIOF2_1),
 905         PINMUX_IPSR_GPSR(IP5_31_28,     VI4_DATA20),
 906         PINMUX_IPSR_GPSR(IP5_31_28,     VI5_DATA4),
 907
 908         /* IPSR6 */
 909         PINMUX_IPSR_GPSR(IP6_3_0,       D5),
 910         PINMUX_IPSR_MSEL(IP6_3_0,       MSIOF2_SYNC_B,          SEL_MSIOF2_1),
 911         PINMUX_IPSR_GPSR(IP6_3_0,       VI4_DATA21),
 912         PINMUX_IPSR_GPSR(IP6_3_0,       VI5_DATA5),
 913
 914         PINMUX_IPSR_GPSR(IP6_7_4,       D6),
 915         PINMUX_IPSR_MSEL(IP6_7_4,       MSIOF2_RXD_B,           SEL_MSIOF2_1),
 916         PINMUX_IPSR_GPSR(IP6_7_4,       VI4_DATA22),
 917         PINMUX_IPSR_GPSR(IP6_7_4,       VI5_DATA6),
 918
 919         PINMUX_IPSR_GPSR(IP6_11_8,      D7),
 920         PINMUX_IPSR_MSEL(IP6_11_8,      MSIOF2_TXD_B,           SEL_MSIOF2_1),
 921         PINMUX_IPSR_GPSR(IP6_11_8,      VI4_DATA23),
 922         PINMUX_IPSR_GPSR(IP6_11_8,      VI5_DATA7),
 923
 924         PINMUX_IPSR_GPSR(IP6_15_12,     D8),
 925         PINMUX_IPSR_GPSR(IP6_15_12,     LCDOUT0),
 926         PINMUX_IPSR_MSEL(IP6_15_12,     MSIOF2_SCK_D,           SEL_MSIOF2_3),
 927         PINMUX_IPSR_MSEL(IP6_15_12,     SCK4_C,                 SEL_SCIF4_2),
 928         PINMUX_IPSR_MSEL(IP6_15_12,     VI4_DATA0_A,            SEL_VIN4_0),
 929         PINMUX_IPSR_GPSR(IP6_15_12,     DU_DR0),
 930
 931         PINMUX_IPSR_GPSR(IP6_19_16,     D9),
 932         PINMUX_IPSR_GPSR(IP6_19_16,     LCDOUT1),
 933         PINMUX_IPSR_MSEL(IP6_19_16,     MSIOF2_SYNC_D,          SEL_MSIOF2_3),
 934         PINMUX_IPSR_MSEL(IP6_19_16,     VI4_DATA1_A,            SEL_VIN4_0),
 935         PINMUX_IPSR_GPSR(IP6_19_16,     DU_DR1),
 936
 937         PINMUX_IPSR_GPSR(IP6_23_20,     D10),
 938         PINMUX_IPSR_GPSR(IP6_23_20,     LCDOUT2),
 939         PINMUX_IPSR_MSEL(IP6_23_20,     MSIOF2_RXD_D,           SEL_MSIOF2_3),
 940         PINMUX_IPSR_MSEL(IP6_23_20,     HRX3_B,                 SEL_HSCIF3_1),
 941         PINMUX_IPSR_MSEL(IP6_23_20,     VI4_DATA2_A,            SEL_VIN4_0),
 942         PINMUX_IPSR_MSEL(IP6_23_20,     CTS4_N_C,               SEL_SCIF4_2),
 943         PINMUX_IPSR_GPSR(IP6_23_20,     DU_DR2),
 944
 945         PINMUX_IPSR_GPSR(IP6_27_24,     D11),
 946         PINMUX_IPSR_GPSR(IP6_27_24,     LCDOUT3),
 947         PINMUX_IPSR_MSEL(IP6_27_24,     MSIOF2_TXD_D,           SEL_MSIOF2_3),
 948         PINMUX_IPSR_MSEL(IP6_27_24,     HTX3_B,                 SEL_HSCIF3_1),
 949         PINMUX_IPSR_MSEL(IP6_27_24,     VI4_DATA3_A,            SEL_VIN4_0),
 950         PINMUX_IPSR_MSEL(IP6_27_24,     RTS4_N_C,               SEL_SCIF4_2),
 951         PINMUX_IPSR_GPSR(IP6_27_24,     DU_DR3),
 952
 953         PINMUX_IPSR_GPSR(IP6_31_28,     D12),
 954         PINMUX_IPSR_GPSR(IP6_31_28,     LCDOUT4),
 955         PINMUX_IPSR_MSEL(IP6_31_28,     MSIOF2_SS1_D,           SEL_MSIOF2_3),
 956         PINMUX_IPSR_MSEL(IP6_31_28,     RX4_C,                  SEL_SCIF4_2),
 957         PINMUX_IPSR_MSEL(IP6_31_28,     VI4_DATA4_A,            SEL_VIN4_0),
 958         PINMUX_IPSR_GPSR(IP6_31_28,     DU_DR4),
 959
 960         /* IPSR7 */
 961         PINMUX_IPSR_GPSR(IP7_3_0,       D13),
 962         PINMUX_IPSR_GPSR(IP7_3_0,       LCDOUT5),
 963         PINMUX_IPSR_MSEL(IP7_3_0,       MSIOF2_SS2_D,           SEL_MSIOF2_3),
 964         PINMUX_IPSR_MSEL(IP7_3_0,       TX4_C,                  SEL_SCIF4_2),
 965         PINMUX_IPSR_MSEL(IP7_3_0,       VI4_DATA5_A,            SEL_VIN4_0),
 966         PINMUX_IPSR_GPSR(IP7_3_0,       DU_DR5),
 967
 968         PINMUX_IPSR_GPSR(IP7_7_4,       D14),
 969         PINMUX_IPSR_GPSR(IP7_7_4,       LCDOUT6),
 970         PINMUX_IPSR_MSEL(IP7_7_4,       MSIOF3_SS1_A,           SEL_MSIOF3_0),
 971         PINMUX_IPSR_MSEL(IP7_7_4,       HRX3_C,                 SEL_HSCIF3_2),
 972         PINMUX_IPSR_MSEL(IP7_7_4,       VI4_DATA6_A,            SEL_VIN4_0),
 973         PINMUX_IPSR_GPSR(IP7_7_4,       DU_DR6),
 974         PINMUX_IPSR_MSEL(IP7_7_4,       SCL6_C,                 SEL_I2C6_2),
 975
 976         PINMUX_IPSR_GPSR(IP7_11_8,      D15),
 977         PINMUX_IPSR_GPSR(IP7_11_8,      LCDOUT7),
 978         PINMUX_IPSR_MSEL(IP7_11_8,      MSIOF3_SS2_A,           SEL_MSIOF3_0),
 979         PINMUX_IPSR_MSEL(IP7_11_8,      HTX3_C,                 SEL_HSCIF3_2),
 980         PINMUX_IPSR_MSEL(IP7_11_8,      VI4_DATA7_A,            SEL_VIN4_0),
 981         PINMUX_IPSR_GPSR(IP7_11_8,      DU_DR7),
 982         PINMUX_IPSR_MSEL(IP7_11_8,      SDA6_C,                 SEL_I2C6_2),
 983
 984         PINMUX_IPSR_GPSR(IP7_19_16,     SD0_CLK),
 985         PINMUX_IPSR_MSEL(IP7_19_16,     MSIOF1_SCK_E,           SEL_MSIOF1_4),
 986         PINMUX_IPSR_MSEL(IP7_19_16,     STP_OPWM_0_B,           SEL_SSP1_0_1),
 987
 988         PINMUX_IPSR_GPSR(IP7_23_20,     SD0_CMD),
 989         PINMUX_IPSR_MSEL(IP7_23_20,     MSIOF1_SYNC_E,          SEL_MSIOF1_4),
 990         PINMUX_IPSR_MSEL(IP7_23_20,     STP_IVCXO27_0_B,        SEL_SSP1_0_1),
 991
 992         PINMUX_IPSR_GPSR(IP7_27_24,     SD0_DAT0),
 993         PINMUX_IPSR_MSEL(IP7_27_24,     MSIOF1_RXD_E,           SEL_MSIOF1_4),
 994         PINMUX_IPSR_MSEL(IP7_27_24,     TS_SCK0_B,              SEL_TSIF0_1),
 995         PINMUX_IPSR_MSEL(IP7_27_24,     STP_ISCLK_0_B,          SEL_SSP1_0_1),
 996
 997         PINMUX_IPSR_GPSR(IP7_31_28,     SD0_DAT1),
 998         PINMUX_IPSR_MSEL(IP7_31_28,     MSIOF1_TXD_E,           SEL_MSIOF1_4),
 999         PINMUX_IPSR_MSEL(IP7_31_28,     TS_SPSYNC0_B,           SEL_TSIF0_1),
1000         PINMUX_IPSR_MSEL(IP7_31_28,     STP_ISSYNC_0_B,         SEL_SSP1_0_1),
1001
1002         /* IPSR8 */
1003         PINMUX_IPSR_GPSR(IP8_3_0,       SD0_DAT2),
1004         PINMUX_IPSR_MSEL(IP8_3_0,       MSIOF1_SS1_E,           SEL_MSIOF1_4),
1005         PINMUX_IPSR_MSEL(IP8_3_0,       TS_SDAT0_B,             SEL_TSIF0_1),
1006         PINMUX_IPSR_MSEL(IP8_3_0,       STP_ISD_0_B,            SEL_SSP1_0_1),
1007
1008         PINMUX_IPSR_GPSR(IP8_7_4,       SD0_DAT3),
1009         PINMUX_IPSR_MSEL(IP8_7_4,       MSIOF1_SS2_E,           SEL_MSIOF1_4),
1010         PINMUX_IPSR_MSEL(IP8_7_4,       TS_SDEN0_B,             SEL_TSIF0_1),
1011         PINMUX_IPSR_MSEL(IP8_7_4,       STP_ISEN_0_B,           SEL_SSP1_0_1),
1012
1013         PINMUX_IPSR_GPSR(IP8_11_8,      SD1_CLK),
1014         PINMUX_IPSR_MSEL(IP8_11_8,      MSIOF1_SCK_G,           SEL_MSIOF1_6),
1015         PINMUX_IPSR_MSEL(IP8_11_8,      SIM0_CLK_A,             SEL_SIMCARD_0),
1016
1017         PINMUX_IPSR_GPSR(IP8_15_12,     SD1_CMD),
1018         PINMUX_IPSR_MSEL(IP8_15_12,     MSIOF1_SYNC_G,          SEL_MSIOF1_6),
1019         PINMUX_IPSR_MSEL(IP8_15_12,     NFCE_N_B,               SEL_NDFC_1),
1020         PINMUX_IPSR_MSEL(IP8_15_12,     SIM0_D_A,               SEL_SIMCARD_0),
1021         PINMUX_IPSR_MSEL(IP8_15_12,     STP_IVCXO27_1_B,        SEL_SSP1_1_1),
1022
1023         PINMUX_IPSR_GPSR(IP8_19_16,     SD1_DAT0),
1024         PINMUX_IPSR_GPSR(IP8_19_16,     SD2_DAT4),
1025         PINMUX_IPSR_MSEL(IP8_19_16,     MSIOF1_RXD_G,           SEL_MSIOF1_6),
1026         PINMUX_IPSR_MSEL(IP8_19_16,     NFWP_N_B,               SEL_NDFC_1),
1027         PINMUX_IPSR_MSEL(IP8_19_16,     TS_SCK1_B,              SEL_TSIF1_1),
1028         PINMUX_IPSR_MSEL(IP8_19_16,     STP_ISCLK_1_B,          SEL_SSP1_1_1),
1029
1030         PINMUX_IPSR_GPSR(IP8_23_20,     SD1_DAT1),
1031         PINMUX_IPSR_GPSR(IP8_23_20,     SD2_DAT5),
1032         PINMUX_IPSR_MSEL(IP8_23_20,     MSIOF1_TXD_G,           SEL_MSIOF1_6),
1033         PINMUX_IPSR_MSEL(IP8_23_20,     NFDATA14_B,             SEL_NDFC_1),
1034         PINMUX_IPSR_MSEL(IP8_23_20,     TS_SPSYNC1_B,           SEL_TSIF1_1),
1035         PINMUX_IPSR_MSEL(IP8_23_20,     STP_ISSYNC_1_B,         SEL_SSP1_1_1),
1036
1037         PINMUX_IPSR_GPSR(IP8_27_24,     SD1_DAT2),
1038         PINMUX_IPSR_GPSR(IP8_27_24,     SD2_DAT6),
1039         PINMUX_IPSR_MSEL(IP8_27_24,     MSIOF1_SS1_G,           SEL_MSIOF1_6),
1040         PINMUX_IPSR_MSEL(IP8_27_24,     NFDATA15_B,             SEL_NDFC_1),
1041         PINMUX_IPSR_MSEL(IP8_27_24,     TS_SDAT1_B,             SEL_TSIF1_1),
1042         PINMUX_IPSR_MSEL(IP8_27_24,     STP_ISD_1_B,            SEL_SSP1_1_1),
1043
1044         PINMUX_IPSR_GPSR(IP8_31_28,     SD1_DAT3),
1045         PINMUX_IPSR_GPSR(IP8_31_28,     SD2_DAT7),
1046         PINMUX_IPSR_MSEL(IP8_31_28,     MSIOF1_SS2_G,           SEL_MSIOF1_6),
1047         PINMUX_IPSR_MSEL(IP8_31_28,     NFRB_N_B,               SEL_NDFC_1),
1048         PINMUX_IPSR_MSEL(IP8_31_28,     TS_SDEN1_B,             SEL_TSIF1_1),
1049         PINMUX_IPSR_MSEL(IP8_31_28,     STP_ISEN_1_B,           SEL_SSP1_1_1),
1050
1051         /* IPSR9 */
1052         PINMUX_IPSR_GPSR(IP9_3_0,       SD2_CLK),
1053         PINMUX_IPSR_GPSR(IP9_3_0,       NFDATA8),
1054
1055         PINMUX_IPSR_GPSR(IP9_7_4,       SD2_CMD),
1056         PINMUX_IPSR_GPSR(IP9_7_4,       NFDATA9),
1057
1058         PINMUX_IPSR_GPSR(IP9_11_8,      SD2_DAT0),
1059         PINMUX_IPSR_GPSR(IP9_11_8,      NFDATA10),
1060
1061         PINMUX_IPSR_GPSR(IP9_15_12,     SD2_DAT1),
1062         PINMUX_IPSR_GPSR(IP9_15_12,     NFDATA11),
1063
1064         PINMUX_IPSR_GPSR(IP9_19_16,     SD2_DAT2),
1065         PINMUX_IPSR_GPSR(IP9_19_16,     NFDATA12),
1066
1067         PINMUX_IPSR_GPSR(IP9_23_20,     SD2_DAT3),
1068         PINMUX_IPSR_GPSR(IP9_23_20,     NFDATA13),
1069
1070         PINMUX_IPSR_GPSR(IP9_27_24,     SD2_DS),
1071         PINMUX_IPSR_GPSR(IP9_27_24,     NFALE),
1072         PINMUX_IPSR_GPSR(IP9_27_24,     SATA_DEVSLP_B),
1073
1074         PINMUX_IPSR_GPSR(IP9_31_28,     SD3_CLK),
1075         PINMUX_IPSR_GPSR(IP9_31_28,     NFWE_N),
1076
1077         /* IPSR10 */
1078         PINMUX_IPSR_GPSR(IP10_3_0,      SD3_CMD),
1079         PINMUX_IPSR_GPSR(IP10_3_0,      NFRE_N),
1080
1081         PINMUX_IPSR_GPSR(IP10_7_4,      SD3_DAT0),
1082         PINMUX_IPSR_GPSR(IP10_7_4,      NFDATA0),
1083
1084         PINMUX_IPSR_GPSR(IP10_11_8,     SD3_DAT1),
1085         PINMUX_IPSR_GPSR(IP10_11_8,     NFDATA1),
1086
1087         PINMUX_IPSR_GPSR(IP10_15_12,    SD3_DAT2),
1088         PINMUX_IPSR_GPSR(IP10_15_12,    NFDATA2),
1089
1090         PINMUX_IPSR_GPSR(IP10_19_16,    SD3_DAT3),
1091         PINMUX_IPSR_GPSR(IP10_19_16,    NFDATA3),
1092
1093         PINMUX_IPSR_GPSR(IP10_23_20,    SD3_DAT4),
1094         PINMUX_IPSR_MSEL(IP10_23_20,    SD2_CD_A,               SEL_SDHI2_0),
1095         PINMUX_IPSR_GPSR(IP10_23_20,    NFDATA4),
1096
1097         PINMUX_IPSR_GPSR(IP10_27_24,    SD3_DAT5),
1098         PINMUX_IPSR_MSEL(IP10_27_24,    SD2_WP_A,               SEL_SDHI2_0),
1099         PINMUX_IPSR_GPSR(IP10_27_24,    NFDATA5),
1100
1101         PINMUX_IPSR_GPSR(IP10_31_28,    SD3_DAT6),
1102         PINMUX_IPSR_GPSR(IP10_31_28,    SD3_CD),
1103         PINMUX_IPSR_GPSR(IP10_31_28,    NFDATA6),
1104
1105         /* IPSR11 */
1106         PINMUX_IPSR_GPSR(IP11_3_0,      SD3_DAT7),
1107         PINMUX_IPSR_GPSR(IP11_3_0,      SD3_WP),
1108         PINMUX_IPSR_GPSR(IP11_3_0,      NFDATA7),
1109
1110         PINMUX_IPSR_GPSR(IP11_7_4,      SD3_DS),
1111         PINMUX_IPSR_GPSR(IP11_7_4,      NFCLE),
1112
1113         PINMUX_IPSR_GPSR(IP11_11_8,     SD0_CD),
1114         PINMUX_IPSR_MSEL(IP11_11_8,     NFDATA14_A,             SEL_NDFC_0),
1115         PINMUX_IPSR_MSEL(IP11_11_8,     SCL2_B,                 SEL_I2C2_1),
1116         PINMUX_IPSR_MSEL(IP11_11_8,     SIM0_RST_A,             SEL_SIMCARD_0),
1117
1118         PINMUX_IPSR_GPSR(IP11_15_12,    SD0_WP),
1119         PINMUX_IPSR_MSEL(IP11_15_12,    NFDATA15_A,             SEL_NDFC_0),
1120         PINMUX_IPSR_MSEL(IP11_15_12,    SDA2_B,                 SEL_I2C2_1),
1121
1122         PINMUX_IPSR_GPSR(IP11_19_16,    SD1_CD),
1123         PINMUX_IPSR_MSEL(IP11_19_16,    NFRB_N_A,               SEL_NDFC_0),
1124         PINMUX_IPSR_MSEL(IP11_19_16,    SIM0_CLK_B,             SEL_SIMCARD_1),
1125
1126         PINMUX_IPSR_GPSR(IP11_23_20,    SD1_WP),
1127         PINMUX_IPSR_MSEL(IP11_23_20,    NFCE_N_A,               SEL_NDFC_0),
1128         PINMUX_IPSR_MSEL(IP11_23_20,    SIM0_D_B,               SEL_SIMCARD_1),
1129
1130         PINMUX_IPSR_GPSR(IP11_27_24,    SCK0),
1131         PINMUX_IPSR_MSEL(IP11_27_24,    HSCK1_B,                SEL_HSCIF1_1),
1132         PINMUX_IPSR_MSEL(IP11_27_24,    MSIOF1_SS2_B,           SEL_MSIOF1_1),
1133         PINMUX_IPSR_MSEL(IP11_27_24,    AUDIO_CLKC_B,           SEL_ADG_C_1),
1134         PINMUX_IPSR_MSEL(IP11_27_24,    SDA2_A,                 SEL_I2C2_0),
1135         PINMUX_IPSR_MSEL(IP11_27_24,    SIM0_RST_B,             SEL_SIMCARD_1),
1136         PINMUX_IPSR_MSEL(IP11_27_24,    STP_OPWM_0_C,           SEL_SSP1_0_2),
1137         PINMUX_IPSR_MSEL(IP11_27_24,    RIF0_CLK_B,             SEL_DRIF0_1),
1138         PINMUX_IPSR_GPSR(IP11_27_24,    ADICHS2),
1139         PINMUX_IPSR_MSEL(IP11_27_24,    SCK5_B,                 SEL_SCIF5_1),
1140
1141         PINMUX_IPSR_GPSR(IP11_31_28,    RX0),
1142         PINMUX_IPSR_MSEL(IP11_31_28,    HRX1_B,                 SEL_HSCIF1_1),
1143         PINMUX_IPSR_MSEL(IP11_31_28,    TS_SCK0_C,              SEL_TSIF0_2),
1144         PINMUX_IPSR_MSEL(IP11_31_28,    STP_ISCLK_0_C,          SEL_SSP1_0_2),
1145         PINMUX_IPSR_MSEL(IP11_31_28,    RIF0_D0_B,              SEL_DRIF0_1),
1146
1147         /* IPSR12 */
1148         PINMUX_IPSR_GPSR(IP12_3_0,      TX0),
1149         PINMUX_IPSR_MSEL(IP12_3_0,      HTX1_B,                 SEL_HSCIF1_1),
1150         PINMUX_IPSR_MSEL(IP12_3_0,      TS_SPSYNC0_C,           SEL_TSIF0_2),
1151         PINMUX_IPSR_MSEL(IP12_3_0,      STP_ISSYNC_0_C,         SEL_SSP1_0_2),
1152         PINMUX_IPSR_MSEL(IP12_3_0,      RIF0_D1_B,              SEL_DRIF0_1),
1153
1154         PINMUX_IPSR_GPSR(IP12_7_4,      CTS0_N),
1155         PINMUX_IPSR_MSEL(IP12_7_4,      HCTS1_N_B,              SEL_HSCIF1_1),
1156         PINMUX_IPSR_MSEL(IP12_7_4,      MSIOF1_SYNC_B,          SEL_MSIOF1_1),
1157         PINMUX_IPSR_MSEL(IP12_7_4,      TS_SPSYNC1_C,           SEL_TSIF1_2),
1158         PINMUX_IPSR_MSEL(IP12_7_4,      STP_ISSYNC_1_C,         SEL_SSP1_1_2),
1159         PINMUX_IPSR_MSEL(IP12_7_4,      RIF1_SYNC_B,            SEL_DRIF1_1),
1160         PINMUX_IPSR_GPSR(IP12_7_4,      AUDIO_CLKOUT_C),
1161         PINMUX_IPSR_GPSR(IP12_7_4,      ADICS_SAMP),
1162
1163         PINMUX_IPSR_GPSR(IP12_11_8,     RTS0_N),
1164         PINMUX_IPSR_MSEL(IP12_11_8,     HRTS1_N_B,              SEL_HSCIF1_1),
1165         PINMUX_IPSR_MSEL(IP12_11_8,     MSIOF1_SS1_B,           SEL_MSIOF1_1),
1166         PINMUX_IPSR_MSEL(IP12_11_8,     AUDIO_CLKA_B,           SEL_ADG_A_1),
1167         PINMUX_IPSR_MSEL(IP12_11_8,     SCL2_A,                 SEL_I2C2_0),
1168         PINMUX_IPSR_MSEL(IP12_11_8,     STP_IVCXO27_1_C,        SEL_SSP1_1_2),
1169         PINMUX_IPSR_MSEL(IP12_11_8,     RIF0_SYNC_B,            SEL_DRIF0_1),
1170         PINMUX_IPSR_GPSR(IP12_11_8,     ADICHS1),
1171
1172         PINMUX_IPSR_MSEL(IP12_15_12,    RX1_A,                  SEL_SCIF1_0),
1173         PINMUX_IPSR_MSEL(IP12_15_12,    HRX1_A,                 SEL_HSCIF1_0),
1174         PINMUX_IPSR_MSEL(IP12_15_12,    TS_SDAT0_C,             SEL_TSIF0_2),
1175         PINMUX_IPSR_MSEL(IP12_15_12,    STP_ISD_0_C,            SEL_SSP1_0_2),
1176         PINMUX_IPSR_MSEL(IP12_15_12,    RIF1_CLK_C,             SEL_DRIF1_2),
1177
1178         PINMUX_IPSR_MSEL(IP12_19_16,    TX1_A,                  SEL_SCIF1_0),
1179         PINMUX_IPSR_MSEL(IP12_19_16,    HTX1_A,                 SEL_HSCIF1_0),
1180         PINMUX_IPSR_MSEL(IP12_19_16,    TS_SDEN0_C,             SEL_TSIF0_2),
1181         PINMUX_IPSR_MSEL(IP12_19_16,    STP_ISEN_0_C,           SEL_SSP1_0_2),
1182         PINMUX_IPSR_MSEL(IP12_19_16,    RIF1_D0_C,              SEL_DRIF1_2),
1183
1184         PINMUX_IPSR_GPSR(IP12_23_20,    CTS1_N),
1185         PINMUX_IPSR_MSEL(IP12_23_20,    HCTS1_N_A,              SEL_HSCIF1_0),
1186         PINMUX_IPSR_MSEL(IP12_23_20,    MSIOF1_RXD_B,           SEL_MSIOF1_1),
1187         PINMUX_IPSR_MSEL(IP12_23_20,    TS_SDEN1_C,             SEL_TSIF1_2),
1188         PINMUX_IPSR_MSEL(IP12_23_20,    STP_ISEN_1_C,           SEL_SSP1_1_2),
1189         PINMUX_IPSR_MSEL(IP12_23_20,    RIF1_D0_B,              SEL_DRIF1_1),
1190         PINMUX_IPSR_GPSR(IP12_23_20,    ADIDATA),
1191
1192         PINMUX_IPSR_GPSR(IP12_27_24,    RTS1_N),
1193         PINMUX_IPSR_MSEL(IP12_27_24,    HRTS1_N_A,              SEL_HSCIF1_0),
1194         PINMUX_IPSR_MSEL(IP12_27_24,    MSIOF1_TXD_B,           SEL_MSIOF1_1),
1195         PINMUX_IPSR_MSEL(IP12_27_24,    TS_SDAT1_C,             SEL_TSIF1_2),
1196         PINMUX_IPSR_MSEL(IP12_27_24,    STP_ISD_1_C,            SEL_SSP1_1_2),
1197         PINMUX_IPSR_MSEL(IP12_27_24,    RIF1_D1_B,              SEL_DRIF1_1),
1198         PINMUX_IPSR_GPSR(IP12_27_24,    ADICHS0),
1199
1200         PINMUX_IPSR_GPSR(IP12_31_28,    SCK2),
1201         PINMUX_IPSR_MSEL(IP12_31_28,    SCIF_CLK_B,             SEL_SCIF_1),
1202         PINMUX_IPSR_MSEL(IP12_31_28,    MSIOF1_SCK_B,           SEL_MSIOF1_1),
1203         PINMUX_IPSR_MSEL(IP12_31_28,    TS_SCK1_C,              SEL_TSIF1_2),
1204         PINMUX_IPSR_MSEL(IP12_31_28,    STP_ISCLK_1_C,          SEL_SSP1_1_2),
1205         PINMUX_IPSR_MSEL(IP12_31_28,    RIF1_CLK_B,             SEL_DRIF1_1),
1206         PINMUX_IPSR_GPSR(IP12_31_28,    ADICLK),
1207
1208         /* IPSR13 */
1209         PINMUX_IPSR_MSEL(IP13_3_0,      TX2_A,                  SEL_SCIF2_0),
1210         PINMUX_IPSR_MSEL(IP13_3_0,      SD2_CD_B,               SEL_SDHI2_1),
1211         PINMUX_IPSR_MSEL(IP13_3_0,      SCL1_A,                 SEL_I2C1_0),
1212         PINMUX_IPSR_MSEL(IP13_3_0,      FMCLK_A,                SEL_FM_0),
1213         PINMUX_IPSR_MSEL(IP13_3_0,      RIF1_D1_C,              SEL_DRIF1_2),
1214         PINMUX_IPSR_GPSR(IP13_3_0,      FSO_CFE_0_N),
1215
1216         PINMUX_IPSR_MSEL(IP13_7_4,      RX2_A,                  SEL_SCIF2_0),
1217         PINMUX_IPSR_MSEL(IP13_7_4,      SD2_WP_B,               SEL_SDHI2_1),
1218         PINMUX_IPSR_MSEL(IP13_7_4,      SDA1_A,                 SEL_I2C1_0),
1219         PINMUX_IPSR_MSEL(IP13_7_4,      FMIN_A,                 SEL_FM_0),
1220         PINMUX_IPSR_MSEL(IP13_7_4,      RIF1_SYNC_C,            SEL_DRIF1_2),
1221         PINMUX_IPSR_GPSR(IP13_7_4,      FSO_CFE_1_N),
1222
1223         PINMUX_IPSR_GPSR(IP13_11_8,     HSCK0),
1224         PINMUX_IPSR_MSEL(IP13_11_8,     MSIOF1_SCK_D,           SEL_MSIOF1_3),
1225         PINMUX_IPSR_MSEL(IP13_11_8,     AUDIO_CLKB_A,           SEL_ADG_B_0),
1226         PINMUX_IPSR_MSEL(IP13_11_8,     SSI_SDATA1_B,           SEL_SSI1_1),
1227         PINMUX_IPSR_MSEL(IP13_11_8,     TS_SCK0_D,              SEL_TSIF0_3),
1228         PINMUX_IPSR_MSEL(IP13_11_8,     STP_ISCLK_0_D,          SEL_SSP1_0_3),
1229         PINMUX_IPSR_MSEL(IP13_11_8,     RIF0_CLK_C,             SEL_DRIF0_2),
1230         PINMUX_IPSR_MSEL(IP13_11_8,     RX5_B,                  SEL_SCIF5_1),
1231
1232         PINMUX_IPSR_GPSR(IP13_15_12,    HRX0),
1233         PINMUX_IPSR_MSEL(IP13_15_12,    MSIOF1_RXD_D,           SEL_MSIOF1_3),
1234         PINMUX_IPSR_MSEL(IP13_15_12,    SSI_SDATA2_B,           SEL_SSI2_1),
1235         PINMUX_IPSR_MSEL(IP13_15_12,    TS_SDEN0_D,             SEL_TSIF0_3),
1236         PINMUX_IPSR_MSEL(IP13_15_12,    STP_ISEN_0_D,           SEL_SSP1_0_3),
1237         PINMUX_IPSR_MSEL(IP13_15_12,    RIF0_D0_C,              SEL_DRIF0_2),
1238
1239         PINMUX_IPSR_GPSR(IP13_19_16,    HTX0),
1240         PINMUX_IPSR_MSEL(IP13_19_16,    MSIOF1_TXD_D,           SEL_MSIOF1_3),
1241         PINMUX_IPSR_MSEL(IP13_19_16,    SSI_SDATA9_B,           SEL_SSI9_1),
1242         PINMUX_IPSR_MSEL(IP13_19_16,    TS_SDAT0_D,             SEL_TSIF0_3),
1243         PINMUX_IPSR_MSEL(IP13_19_16,    STP_ISD_0_D,            SEL_SSP1_0_3),
1244         PINMUX_IPSR_MSEL(IP13_19_16,    RIF0_D1_C,              SEL_DRIF0_2),
1245
1246         PINMUX_IPSR_GPSR(IP13_23_20,    HCTS0_N),
1247         PINMUX_IPSR_MSEL(IP13_23_20,    RX2_B,                  SEL_SCIF2_1),
1248         PINMUX_IPSR_MSEL(IP13_23_20,    MSIOF1_SYNC_D,          SEL_MSIOF1_3),
1249         PINMUX_IPSR_MSEL(IP13_23_20,    SSI_SCK9_A,             SEL_SSI9_0),
1250         PINMUX_IPSR_MSEL(IP13_23_20,    TS_SPSYNC0_D,           SEL_TSIF0_3),
1251         PINMUX_IPSR_MSEL(IP13_23_20,    STP_ISSYNC_0_D,         SEL_SSP1_0_3),
1252         PINMUX_IPSR_MSEL(IP13_23_20,    RIF0_SYNC_C,            SEL_DRIF0_2),
1253         PINMUX_IPSR_GPSR(IP13_23_20,    AUDIO_CLKOUT1_A),
1254
1255         PINMUX_IPSR_GPSR(IP13_27_24,    HRTS0_N),
1256         PINMUX_IPSR_MSEL(IP13_27_24,    TX2_B,                  SEL_SCIF2_1),
1257         PINMUX_IPSR_MSEL(IP13_27_24,    MSIOF1_SS1_D,           SEL_MSIOF1_3),
1258         PINMUX_IPSR_MSEL(IP13_27_24,    SSI_WS9_A,              SEL_SSI9_0),
1259         PINMUX_IPSR_MSEL(IP13_27_24,    STP_IVCXO27_0_D,        SEL_SSP1_0_3),
1260         PINMUX_IPSR_MSEL(IP13_27_24,    BPFCLK_A,               SEL_FM_0),
1261         PINMUX_IPSR_GPSR(IP13_27_24,    AUDIO_CLKOUT2_A),
1262
1263         PINMUX_IPSR_GPSR(IP13_31_28,    MSIOF0_SYNC),
1264         PINMUX_IPSR_GPSR(IP13_31_28,    AUDIO_CLKOUT_A),
1265         PINMUX_IPSR_MSEL(IP13_31_28,    TX5_B,                  SEL_SCIF5_1),
1266         PINMUX_IPSR_MSEL(IP13_31_28,    BPFCLK_D,               SEL_FM_3),
1267
1268         /* IPSR14 */
1269         PINMUX_IPSR_GPSR(IP14_3_0,      MSIOF0_SS1),
1270         PINMUX_IPSR_MSEL(IP14_3_0,      RX5_A,                  SEL_SCIF5_0),
1271         PINMUX_IPSR_MSEL(IP14_3_0,      NFWP_N_A,               SEL_NDFC_0),
1272         PINMUX_IPSR_MSEL(IP14_3_0,      AUDIO_CLKA_C,           SEL_ADG_A_2),
1273         PINMUX_IPSR_MSEL(IP14_3_0,      SSI_SCK2_A,             SEL_SSI2_0),
1274         PINMUX_IPSR_MSEL(IP14_3_0,      STP_IVCXO27_0_C,        SEL_SSP1_0_2),
1275         PINMUX_IPSR_GPSR(IP14_3_0,      AUDIO_CLKOUT3_A),
1276         PINMUX_IPSR_MSEL(IP14_3_0,      TCLK1_B,                SEL_TIMER_TMU_1),
1277
1278         PINMUX_IPSR_GPSR(IP14_7_4,      MSIOF0_SS2),
1279         PINMUX_IPSR_MSEL(IP14_7_4,      TX5_A,                  SEL_SCIF5_0),
1280         PINMUX_IPSR_MSEL(IP14_7_4,      MSIOF1_SS2_D,           SEL_MSIOF1_3),
1281         PINMUX_IPSR_MSEL(IP14_7_4,      AUDIO_CLKC_A,           SEL_ADG_C_0),
1282         PINMUX_IPSR_MSEL(IP14_7_4,      SSI_WS2_A,              SEL_SSI2_0),
1283         PINMUX_IPSR_MSEL(IP14_7_4,      STP_OPWM_0_D,           SEL_SSP1_0_3),
1284         PINMUX_IPSR_GPSR(IP14_7_4,      AUDIO_CLKOUT_D),
1285         PINMUX_IPSR_MSEL(IP14_7_4,      SPEEDIN_B,              SEL_SPEED_PULSE_1),
1286
1287         PINMUX_IPSR_GPSR(IP14_11_8,     MLB_CLK),
1288         PINMUX_IPSR_MSEL(IP14_11_8,     MSIOF1_SCK_F,           SEL_MSIOF1_5),
1289         PINMUX_IPSR_MSEL(IP14_11_8,     SCL1_B,                 SEL_I2C1_1),
1290
1291         PINMUX_IPSR_GPSR(IP14_15_12,    MLB_SIG),
1292         PINMUX_IPSR_MSEL(IP14_15_12,    RX1_B,                  SEL_SCIF1_1),
1293         PINMUX_IPSR_MSEL(IP14_15_12,    MSIOF1_SYNC_F,          SEL_MSIOF1_5),
1294         PINMUX_IPSR_MSEL(IP14_15_12,    SDA1_B,                 SEL_I2C1_1),
1295
1296         PINMUX_IPSR_GPSR(IP14_19_16,    MLB_DAT),
1297         PINMUX_IPSR_MSEL(IP14_19_16,    TX1_B,                  SEL_SCIF1_1),
1298         PINMUX_IPSR_MSEL(IP14_19_16,    MSIOF1_RXD_F,           SEL_MSIOF1_5),
1299
1300         PINMUX_IPSR_GPSR(IP14_23_20,    SSI_SCK01239),
1301         PINMUX_IPSR_MSEL(IP14_23_20,    MSIOF1_TXD_F,           SEL_MSIOF1_5),
1302
1303         PINMUX_IPSR_GPSR(IP14_27_24,    SSI_WS01239),
1304         PINMUX_IPSR_MSEL(IP14_27_24,    MSIOF1_SS1_F,           SEL_MSIOF1_5),
1305
1306         PINMUX_IPSR_GPSR(IP14_31_28,    SSI_SDATA0),
1307         PINMUX_IPSR_MSEL(IP14_31_28,    MSIOF1_SS2_F,           SEL_MSIOF1_5),
1308
1309         /* IPSR15 */
1310         PINMUX_IPSR_MSEL(IP15_3_0,      SSI_SDATA1_A,           SEL_SSI1_0),
1311
1312         PINMUX_IPSR_MSEL(IP15_7_4,      SSI_SDATA2_A,           SEL_SSI2_0),
1313         PINMUX_IPSR_MSEL(IP15_7_4,      SSI_SCK1_B,             SEL_SSI1_1),
1314
1315         PINMUX_IPSR_GPSR(IP15_11_8,     SSI_SCK349),
1316         PINMUX_IPSR_MSEL(IP15_11_8,     MSIOF1_SS1_A,           SEL_MSIOF1_0),
1317         PINMUX_IPSR_MSEL(IP15_11_8,     STP_OPWM_0_A,           SEL_SSP1_0_0),
1318
1319         PINMUX_IPSR_GPSR(IP15_15_12,    SSI_WS349),
1320         PINMUX_IPSR_MSEL(IP15_15_12,    HCTS2_N_A,              SEL_HSCIF2_0),
1321         PINMUX_IPSR_MSEL(IP15_15_12,    MSIOF1_SS2_A,           SEL_MSIOF1_0),
1322         PINMUX_IPSR_MSEL(IP15_15_12,    STP_IVCXO27_0_A,        SEL_SSP1_0_0),
1323
1324         PINMUX_IPSR_GPSR(IP15_19_16,    SSI_SDATA3),
1325         PINMUX_IPSR_MSEL(IP15_19_16,    HRTS2_N_A,              SEL_HSCIF2_0),
1326         PINMUX_IPSR_MSEL(IP15_19_16,    MSIOF1_TXD_A,           SEL_MSIOF1_0),
1327         PINMUX_IPSR_MSEL(IP15_19_16,    TS_SCK0_A,              SEL_TSIF0_0),
1328         PINMUX_IPSR_MSEL(IP15_19_16,    STP_ISCLK_0_A,          SEL_SSP1_0_0),
1329         PINMUX_IPSR_MSEL(IP15_19_16,    RIF0_D1_A,              SEL_DRIF0_0),
1330         PINMUX_IPSR_MSEL(IP15_19_16,    RIF2_D0_A,              SEL_DRIF2_0),
1331
1332         PINMUX_IPSR_GPSR(IP15_23_20,    SSI_SCK4),
1333         PINMUX_IPSR_MSEL(IP15_23_20,    HRX2_A,                 SEL_HSCIF2_0),
1334         PINMUX_IPSR_MSEL(IP15_23_20,    MSIOF1_SCK_A,           SEL_MSIOF1_0),
1335         PINMUX_IPSR_MSEL(IP15_23_20,    TS_SDAT0_A,             SEL_TSIF0_0),
1336         PINMUX_IPSR_MSEL(IP15_23_20,    STP_ISD_0_A,            SEL_SSP1_0_0),
1337         PINMUX_IPSR_MSEL(IP15_23_20,    RIF0_CLK_A,             SEL_DRIF0_0),
1338         PINMUX_IPSR_MSEL(IP15_23_20,    RIF2_CLK_A,             SEL_DRIF2_0),
1339
1340         PINMUX_IPSR_GPSR(IP15_27_24,    SSI_WS4),
1341         PINMUX_IPSR_MSEL(IP15_27_24,    HTX2_A,                 SEL_HSCIF2_0),
1342         PINMUX_IPSR_MSEL(IP15_27_24,    MSIOF1_SYNC_A,          SEL_MSIOF1_0),
1343         PINMUX_IPSR_MSEL(IP15_27_24,    TS_SDEN0_A,             SEL_TSIF0_0),
1344         PINMUX_IPSR_MSEL(IP15_27_24,    STP_ISEN_0_A,           SEL_SSP1_0_0),
1345         PINMUX_IPSR_MSEL(IP15_27_24,    RIF0_SYNC_A,            SEL_DRIF0_0),
1346         PINMUX_IPSR_MSEL(IP15_27_24,    RIF2_SYNC_A,            SEL_DRIF2_0),
1347
1348         PINMUX_IPSR_GPSR(IP15_31_28,    SSI_SDATA4),
1349         PINMUX_IPSR_MSEL(IP15_31_28,    HSCK2_A,                SEL_HSCIF2_0),
1350         PINMUX_IPSR_MSEL(IP15_31_28,    MSIOF1_RXD_A,           SEL_MSIOF1_0),
1351         PINMUX_IPSR_MSEL(IP15_31_28,    TS_SPSYNC0_A,           SEL_TSIF0_0),
1352         PINMUX_IPSR_MSEL(IP15_31_28,    STP_ISSYNC_0_A,         SEL_SSP1_0_0),
1353         PINMUX_IPSR_MSEL(IP15_31_28,    RIF0_D0_A,              SEL_DRIF0_0),
1354         PINMUX_IPSR_MSEL(IP15_31_28,    RIF2_D1_A,              SEL_DRIF2_0),
1355
1356         /* IPSR16 */
1357         PINMUX_IPSR_GPSR(IP16_3_0,      SSI_SCK6),
1358         PINMUX_IPSR_MSEL(IP16_3_0,      SIM0_RST_D,             SEL_SIMCARD_3),
1359
1360         PINMUX_IPSR_GPSR(IP16_7_4,      SSI_WS6),
1361         PINMUX_IPSR_MSEL(IP16_7_4,      SIM0_D_D,               SEL_SIMCARD_3),
1362
1363         PINMUX_IPSR_GPSR(IP16_11_8,     SSI_SDATA6),
1364         PINMUX_IPSR_MSEL(IP16_11_8,     SIM0_CLK_D,             SEL_SIMCARD_3),
1365         PINMUX_IPSR_GPSR(IP16_11_8,     SATA_DEVSLP_A),
1366
1367         PINMUX_IPSR_GPSR(IP16_15_12,    SSI_SCK78),
1368         PINMUX_IPSR_MSEL(IP16_15_12,    HRX2_B,                 SEL_HSCIF2_1),
1369         PINMUX_IPSR_MSEL(IP16_15_12,    MSIOF1_SCK_C,           SEL_MSIOF1_2),
1370         PINMUX_IPSR_MSEL(IP16_15_12,    TS_SCK1_A,              SEL_TSIF1_0),
1371         PINMUX_IPSR_MSEL(IP16_15_12,    STP_ISCLK_1_A,          SEL_SSP1_1_0),
1372         PINMUX_IPSR_MSEL(IP16_15_12,    RIF1_CLK_A,             SEL_DRIF1_0),
1373         PINMUX_IPSR_MSEL(IP16_15_12,    RIF3_CLK_A,             SEL_DRIF3_0),
1374
1375         PINMUX_IPSR_GPSR(IP16_19_16,    SSI_WS78),
1376         PINMUX_IPSR_MSEL(IP16_19_16,    HTX2_B,                 SEL_HSCIF2_1),
1377         PINMUX_IPSR_MSEL(IP16_19_16,    MSIOF1_SYNC_C,          SEL_MSIOF1_2),
1378         PINMUX_IPSR_MSEL(IP16_19_16,    TS_SDAT1_A,             SEL_TSIF1_0),
1379         PINMUX_IPSR_MSEL(IP16_19_16,    STP_ISD_1_A,            SEL_SSP1_1_0),
1380         PINMUX_IPSR_MSEL(IP16_19_16,    RIF1_SYNC_A,            SEL_DRIF1_0),
1381         PINMUX_IPSR_MSEL(IP16_19_16,    RIF3_SYNC_A,            SEL_DRIF3_0),
1382
1383         PINMUX_IPSR_GPSR(IP16_23_20,    SSI_SDATA7),
1384         PINMUX_IPSR_MSEL(IP16_23_20,    HCTS2_N_B,              SEL_HSCIF2_1),
1385         PINMUX_IPSR_MSEL(IP16_23_20,    MSIOF1_RXD_C,           SEL_MSIOF1_2),
1386         PINMUX_IPSR_MSEL(IP16_23_20,    TS_SDEN1_A,             SEL_TSIF1_0),
1387         PINMUX_IPSR_MSEL(IP16_23_20,    STP_ISEN_1_A,           SEL_SSP1_1_0),
1388         PINMUX_IPSR_MSEL(IP16_23_20,    RIF1_D0_A,              SEL_DRIF1_0),
1389         PINMUX_IPSR_MSEL(IP16_23_20,    RIF3_D0_A,              SEL_DRIF3_0),
1390         PINMUX_IPSR_MSEL(IP16_23_20,    TCLK2_A,                SEL_TIMER_TMU2_0),
1391
1392         PINMUX_IPSR_GPSR(IP16_27_24,    SSI_SDATA8),
1393         PINMUX_IPSR_MSEL(IP16_27_24,    HRTS2_N_B,              SEL_HSCIF2_1),
1394         PINMUX_IPSR_MSEL(IP16_27_24,    MSIOF1_TXD_C,           SEL_MSIOF1_2),
1395         PINMUX_IPSR_MSEL(IP16_27_24,    TS_SPSYNC1_A,           SEL_TSIF1_0),
1396         PINMUX_IPSR_MSEL(IP16_27_24,    STP_ISSYNC_1_A,         SEL_SSP1_1_0),
1397         PINMUX_IPSR_MSEL(IP16_27_24,    RIF1_D1_A,              SEL_DRIF1_0),
1398         PINMUX_IPSR_MSEL(IP16_27_24,    RIF3_D1_A,              SEL_DRIF3_0),
1399
1400         PINMUX_IPSR_MSEL(IP16_31_28,    SSI_SDATA9_A,           SEL_SSI9_0),
1401         PINMUX_IPSR_MSEL(IP16_31_28,    HSCK2_B,                SEL_HSCIF2_1),
1402         PINMUX_IPSR_MSEL(IP16_31_28,    MSIOF1_SS1_C,           SEL_MSIOF1_2),
1403         PINMUX_IPSR_MSEL(IP16_31_28,    HSCK1_A,                SEL_HSCIF1_0),
1404         PINMUX_IPSR_MSEL(IP16_31_28,    SSI_WS1_B,              SEL_SSI1_1),
1405         PINMUX_IPSR_GPSR(IP16_31_28,    SCK1),
1406         PINMUX_IPSR_MSEL(IP16_31_28,    STP_IVCXO27_1_A,        SEL_SSP1_1_0),
1407         PINMUX_IPSR_MSEL(IP16_31_28,    SCK5_A,                 SEL_SCIF5_0),
1408
1409         /* IPSR17 */
1410         PINMUX_IPSR_MSEL(IP17_3_0,      AUDIO_CLKA_A,           SEL_ADG_A_0),
1411         PINMUX_IPSR_GPSR(IP17_3_0,      CC5_OSCOUT),
1412
1413         PINMUX_IPSR_MSEL(IP17_7_4,      AUDIO_CLKB_B,           SEL_ADG_B_1),
1414         PINMUX_IPSR_MSEL(IP17_7_4,      SCIF_CLK_A,             SEL_SCIF_0),
1415         PINMUX_IPSR_MSEL(IP17_7_4,      STP_IVCXO27_1_D,        SEL_SSP1_1_3),
1416         PINMUX_IPSR_MSEL(IP17_7_4,      REMOCON_A,              SEL_REMOCON_0),
1417         PINMUX_IPSR_MSEL(IP17_7_4,      TCLK1_A,                SEL_TIMER_TMU_0),
1418
1419         PINMUX_IPSR_GPSR(IP17_11_8,     USB0_PWEN),
1420         PINMUX_IPSR_MSEL(IP17_11_8,     SIM0_RST_C,             SEL_SIMCARD_2),
1421         PINMUX_IPSR_MSEL(IP17_11_8,     TS_SCK1_D,              SEL_TSIF1_3),
1422         PINMUX_IPSR_MSEL(IP17_11_8,     STP_ISCLK_1_D,          SEL_SSP1_1_3),
1423         PINMUX_IPSR_MSEL(IP17_11_8,     BPFCLK_B,               SEL_FM_1),
1424         PINMUX_IPSR_MSEL(IP17_11_8,     RIF3_CLK_B,             SEL_DRIF3_1),
1425         PINMUX_IPSR_MSEL(IP17_11_8,     HSCK2_C,                SEL_HSCIF2_2),
1426
1427         PINMUX_IPSR_GPSR(IP17_15_12,    USB0_OVC),
1428         PINMUX_IPSR_MSEL(IP17_15_12,    SIM0_D_C,               SEL_SIMCARD_2),
1429         PINMUX_IPSR_MSEL(IP17_15_12,    TS_SDAT1_D,             SEL_TSIF1_3),
1430         PINMUX_IPSR_MSEL(IP17_15_12,    STP_ISD_1_D,            SEL_SSP1_1_3),
1431         PINMUX_IPSR_MSEL(IP17_15_12,    RIF3_SYNC_B,            SEL_DRIF3_1),
1432         PINMUX_IPSR_MSEL(IP17_15_12,    HRX2_C,                 SEL_HSCIF2_2),
1433
1434         PINMUX_IPSR_GPSR(IP17_19_16,    USB1_PWEN),
1435         PINMUX_IPSR_MSEL(IP17_19_16,    SIM0_CLK_C,             SEL_SIMCARD_2),
1436         PINMUX_IPSR_MSEL(IP17_19_16,    SSI_SCK1_A,             SEL_SSI1_0),
1437         PINMUX_IPSR_MSEL(IP17_19_16,    TS_SCK0_E,              SEL_TSIF0_4),
1438         PINMUX_IPSR_MSEL(IP17_19_16,    STP_ISCLK_0_E,          SEL_SSP1_0_4),
1439         PINMUX_IPSR_MSEL(IP17_19_16,    FMCLK_B,                SEL_FM_1),
1440         PINMUX_IPSR_MSEL(IP17_19_16,    RIF2_CLK_B,             SEL_DRIF2_1),
1441         PINMUX_IPSR_MSEL(IP17_19_16,    SPEEDIN_A,              SEL_SPEED_PULSE_0),
1442         PINMUX_IPSR_MSEL(IP17_19_16,    HTX2_C,                 SEL_HSCIF2_2),
1443
1444         PINMUX_IPSR_GPSR(IP17_23_20,    USB1_OVC),
1445         PINMUX_IPSR_MSEL(IP17_23_20,    MSIOF1_SS2_C,           SEL_MSIOF1_2),
1446         PINMUX_IPSR_MSEL(IP17_23_20,    SSI_WS1_A,              SEL_SSI1_0),
1447         PINMUX_IPSR_MSEL(IP17_23_20,    TS_SDAT0_E,             SEL_TSIF0_4),
1448         PINMUX_IPSR_MSEL(IP17_23_20,    STP_ISD_0_E,            SEL_SSP1_0_4),
1449         PINMUX_IPSR_MSEL(IP17_23_20,    FMIN_B,                 SEL_FM_1),
1450         PINMUX_IPSR_MSEL(IP17_23_20,    RIF2_SYNC_B,            SEL_DRIF2_1),
1451         PINMUX_IPSR_MSEL(IP17_23_20,    REMOCON_B,              SEL_REMOCON_1),
1452         PINMUX_IPSR_MSEL(IP17_23_20,    HCTS2_N_C,              SEL_HSCIF2_2),
1453
1454         PINMUX_IPSR_GPSR(IP17_27_24,    USB30_PWEN),
1455         PINMUX_IPSR_GPSR(IP17_27_24,    AUDIO_CLKOUT_B),
1456         PINMUX_IPSR_MSEL(IP17_27_24,    SSI_SCK2_B,             SEL_SSI2_1),
1457         PINMUX_IPSR_MSEL(IP17_27_24,    TS_SDEN1_D,             SEL_TSIF1_3),
1458         PINMUX_IPSR_MSEL(IP17_27_24,    STP_ISEN_1_D,           SEL_SSP1_1_3),
1459         PINMUX_IPSR_MSEL(IP17_27_24,    STP_OPWM_0_E,           SEL_SSP1_0_4),
1460         PINMUX_IPSR_MSEL(IP17_27_24,    RIF3_D0_B,              SEL_DRIF3_1),
1461         PINMUX_IPSR_MSEL(IP17_27_24,    TCLK2_B,                SEL_TIMER_TMU2_1),
1462         PINMUX_IPSR_GPSR(IP17_27_24,    TPU0TO0),
1463         PINMUX_IPSR_MSEL(IP17_27_24,    BPFCLK_C,               SEL_FM_2),
1464         PINMUX_IPSR_MSEL(IP17_27_24,    HRTS2_N_C,              SEL_HSCIF2_2),
1465
1466         PINMUX_IPSR_GPSR(IP17_31_28,    USB30_OVC),
1467         PINMUX_IPSR_GPSR(IP17_31_28,    AUDIO_CLKOUT1_B),
1468         PINMUX_IPSR_MSEL(IP17_31_28,    SSI_WS2_B,              SEL_SSI2_1),
1469         PINMUX_IPSR_MSEL(IP17_31_28,    TS_SPSYNC1_D,           SEL_TSIF1_3),
1470         PINMUX_IPSR_MSEL(IP17_31_28,    STP_ISSYNC_1_D,         SEL_SSP1_1_3),
1471         PINMUX_IPSR_MSEL(IP17_31_28,    STP_IVCXO27_0_E,        SEL_SSP1_0_4),
1472         PINMUX_IPSR_MSEL(IP17_31_28,    RIF3_D1_B,              SEL_DRIF3_1),
1473         PINMUX_IPSR_GPSR(IP17_31_28,    FSO_TOE_N),
1474         PINMUX_IPSR_GPSR(IP17_31_28,    TPU0TO1),
1475
1476         /* IPSR18 */
1477         PINMUX_IPSR_GPSR(IP18_3_0,      GP6_30),
1478         PINMUX_IPSR_GPSR(IP18_3_0,      AUDIO_CLKOUT2_B),
1479         PINMUX_IPSR_MSEL(IP18_3_0,      SSI_SCK9_B,             SEL_SSI9_1),
1480         PINMUX_IPSR_MSEL(IP18_3_0,      TS_SDEN0_E,             SEL_TSIF0_4),
1481         PINMUX_IPSR_MSEL(IP18_3_0,      STP_ISEN_0_E,           SEL_SSP1_0_4),
1482         PINMUX_IPSR_MSEL(IP18_3_0,      RIF2_D0_B,              SEL_DRIF2_1),
1483         PINMUX_IPSR_GPSR(IP18_3_0,      TPU0TO2),
1484         PINMUX_IPSR_MSEL(IP18_3_0,      FMCLK_C,                SEL_FM_2),
1485         PINMUX_IPSR_MSEL(IP18_3_0,      FMCLK_D,                SEL_FM_3),
1486
1487         PINMUX_IPSR_GPSR(IP18_7_4,      GP6_31),
1488         PINMUX_IPSR_GPSR(IP18_7_4,      AUDIO_CLKOUT3_B),
1489         PINMUX_IPSR_MSEL(IP18_7_4,      SSI_WS9_B,              SEL_SSI9_1),
1490         PINMUX_IPSR_MSEL(IP18_7_4,      TS_SPSYNC0_E,           SEL_TSIF0_4),
1491         PINMUX_IPSR_MSEL(IP18_7_4,      STP_ISSYNC_0_E,         SEL_SSP1_0_4),
1492         PINMUX_IPSR_MSEL(IP18_7_4,      RIF2_D1_B,              SEL_DRIF2_1),
1493         PINMUX_IPSR_GPSR(IP18_7_4,      TPU0TO3),
1494         PINMUX_IPSR_MSEL(IP18_7_4,      FMIN_C,                 SEL_FM_2),
1495         PINMUX_IPSR_MSEL(IP18_7_4,      FMIN_D,                 SEL_FM_3),
1496
1497         /* I2C */
1498         PINMUX_IPSR_NOGP(0,             I2C_SEL_0_1),
1499         PINMUX_IPSR_NOGP(0,             I2C_SEL_3_1),
1500         PINMUX_IPSR_NOGP(0,             I2C_SEL_5_1),
1501
1502 /*
1503  * Static pins can not be muxed between different functions but
1504  * still need mark entries in the pinmux list. Add each static
1505  * pin to the list without an associated function. The sh-pfc
1506  * core will do the right thing and skip trying to mux the pin
1507  * while still applying configuration to it.
1508  */
1509 #define FM(x)   PINMUX_DATA(x##_MARK, 0),
1510         PINMUX_STATIC
1511 #undef FM
1512 };
1513
1514 /*
1515  * R8A77965 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1516  * Physical layout rows: A - AW, cols: 1 - 39.
1517  */
1518 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1519 #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1520 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1521 #define PIN_NONE U16_MAX
1522
1523 static const struct sh_pfc_pin pinmux_pins[] = {
1524         PINMUX_GPIO_GP_ALL(),
1525
1526         /*
1527          * Pins not associated with a GPIO port.
1528          *
1529          * The pin positions are different between different r8a77965
1530          * packages, all that is needed for the pfc driver is a unique
1531          * number for each pin. To this end use the pin layout from
1532          * R-Car M3SiP to calculate a unique number for each pin.
1533          */
1534         SH_PFC_PIN_NAMED_CFG('A',  8, AVB_TX_CTL, CFG_FLAGS),
1535         SH_PFC_PIN_NAMED_CFG('A',  9, AVB_MDIO, CFG_FLAGS),
1536         SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1537         SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1538         SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1539         SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1540         SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1541         SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1542         SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1543         SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1544         SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1545         SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1546         SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1547         SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1548         SH_PFC_PIN_NAMED_CFG('C',  1, PRESETOUT#, CFG_FLAGS),
1549         SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1550         SH_PFC_PIN_NAMED_CFG('V',  3, QSPI1_SPCLK, CFG_FLAGS),
1551         SH_PFC_PIN_NAMED_CFG('V',  5, QSPI1_SSL, CFG_FLAGS),
1552         SH_PFC_PIN_NAMED_CFG('V',  6, RPC_WP#, CFG_FLAGS),
1553         SH_PFC_PIN_NAMED_CFG('V',  7, RPC_RESET#, CFG_FLAGS),
1554         SH_PFC_PIN_NAMED_CFG('W',  3, QSPI0_SPCLK, CFG_FLAGS),
1555         SH_PFC_PIN_NAMED_CFG('Y',  3, QSPI0_SSL, CFG_FLAGS),
1556         SH_PFC_PIN_NAMED_CFG('Y',  6, QSPI0_IO2, CFG_FLAGS),
1557         SH_PFC_PIN_NAMED_CFG('Y',  7, RPC_INT#, CFG_FLAGS),
1558         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  4, QSPI0_MISO_IO1, CFG_FLAGS),
1559         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  6, QSPI0_IO3, CFG_FLAGS),
1560         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  3, QSPI1_IO3, CFG_FLAGS),
1561         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  5, QSPI0_MOSI_IO0, CFG_FLAGS),
1562         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  7, QSPI1_MOSI_IO0, CFG_FLAGS),
1563         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
1564         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1565         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  4, QSPI1_IO2, CFG_FLAGS),
1566         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  5, QSPI1_MISO_IO1, CFG_FLAGS),
1567         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  7, DU_DOTCLKIN0, CFG_FLAGS),
1568         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  8, DU_DOTCLKIN1, CFG_FLAGS),
1569         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  8, DU_DOTCLKIN2, CFG_FLAGS),
1570         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1571         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1572         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1573         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1574         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1575         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1576 };
1577
1578 /* - AUDIO CLOCK ------------------------------------------------------------ */
1579 static const unsigned int audio_clk_a_a_pins[] = {
1580         /* CLK A */
1581         RCAR_GP_PIN(6, 22),
1582 };
1583 static const unsigned int audio_clk_a_a_mux[] = {
1584         AUDIO_CLKA_A_MARK,
1585 };
1586 static const unsigned int audio_clk_a_b_pins[] = {
1587         /* CLK A */
1588         RCAR_GP_PIN(5, 4),
1589 };
1590 static const unsigned int audio_clk_a_b_mux[] = {
1591         AUDIO_CLKA_B_MARK,
1592 };
1593 static const unsigned int audio_clk_a_c_pins[] = {
1594         /* CLK A */
1595         RCAR_GP_PIN(5, 19),
1596 };
1597 static const unsigned int audio_clk_a_c_mux[] = {
1598         AUDIO_CLKA_C_MARK,
1599 };
1600 static const unsigned int audio_clk_b_a_pins[] = {
1601         /* CLK B */
1602         RCAR_GP_PIN(5, 12),
1603 };
1604 static const unsigned int audio_clk_b_a_mux[] = {
1605         AUDIO_CLKB_A_MARK,
1606 };
1607 static const unsigned int audio_clk_b_b_pins[] = {
1608         /* CLK B */
1609         RCAR_GP_PIN(6, 23),
1610 };
1611 static const unsigned int audio_clk_b_b_mux[] = {
1612         AUDIO_CLKB_B_MARK,
1613 };
1614 static const unsigned int audio_clk_c_a_pins[] = {
1615         /* CLK C */
1616         RCAR_GP_PIN(5, 21),
1617 };
1618 static const unsigned int audio_clk_c_a_mux[] = {
1619         AUDIO_CLKC_A_MARK,
1620 };
1621 static const unsigned int audio_clk_c_b_pins[] = {
1622         /* CLK C */
1623         RCAR_GP_PIN(5, 0),
1624 };
1625 static const unsigned int audio_clk_c_b_mux[] = {
1626         AUDIO_CLKC_B_MARK,
1627 };
1628 static const unsigned int audio_clkout_a_pins[] = {
1629         /* CLKOUT */
1630         RCAR_GP_PIN(5, 18),
1631 };
1632 static const unsigned int audio_clkout_a_mux[] = {
1633         AUDIO_CLKOUT_A_MARK,
1634 };
1635 static const unsigned int audio_clkout_b_pins[] = {
1636         /* CLKOUT */
1637         RCAR_GP_PIN(6, 28),
1638 };
1639 static const unsigned int audio_clkout_b_mux[] = {
1640         AUDIO_CLKOUT_B_MARK,
1641 };
1642 static const unsigned int audio_clkout_c_pins[] = {
1643         /* CLKOUT */
1644         RCAR_GP_PIN(5, 3),
1645 };
1646 static const unsigned int audio_clkout_c_mux[] = {
1647         AUDIO_CLKOUT_C_MARK,
1648 };
1649 static const unsigned int audio_clkout_d_pins[] = {
1650         /* CLKOUT */
1651         RCAR_GP_PIN(5, 21),
1652 };
1653 static const unsigned int audio_clkout_d_mux[] = {
1654         AUDIO_CLKOUT_D_MARK,
1655 };
1656 static const unsigned int audio_clkout1_a_pins[] = {
1657         /* CLKOUT1 */
1658         RCAR_GP_PIN(5, 15),
1659 };
1660 static const unsigned int audio_clkout1_a_mux[] = {
1661         AUDIO_CLKOUT1_A_MARK,
1662 };
1663 static const unsigned int audio_clkout1_b_pins[] = {
1664         /* CLKOUT1 */
1665         RCAR_GP_PIN(6, 29),
1666 };
1667 static const unsigned int audio_clkout1_b_mux[] = {
1668         AUDIO_CLKOUT1_B_MARK,
1669 };
1670 static const unsigned int audio_clkout2_a_pins[] = {
1671         /* CLKOUT2 */
1672         RCAR_GP_PIN(5, 16),
1673 };
1674 static const unsigned int audio_clkout2_a_mux[] = {
1675         AUDIO_CLKOUT2_A_MARK,
1676 };
1677 static const unsigned int audio_clkout2_b_pins[] = {
1678         /* CLKOUT2 */
1679         RCAR_GP_PIN(6, 30),
1680 };
1681 static const unsigned int audio_clkout2_b_mux[] = {
1682         AUDIO_CLKOUT2_B_MARK,
1683 };
1684
1685 static const unsigned int audio_clkout3_a_pins[] = {
1686         /* CLKOUT3 */
1687         RCAR_GP_PIN(5, 19),
1688 };
1689 static const unsigned int audio_clkout3_a_mux[] = {
1690         AUDIO_CLKOUT3_A_MARK,
1691 };
1692 static const unsigned int audio_clkout3_b_pins[] = {
1693         /* CLKOUT3 */
1694         RCAR_GP_PIN(6, 31),
1695 };
1696 static const unsigned int audio_clkout3_b_mux[] = {
1697         AUDIO_CLKOUT3_B_MARK,
1698 };
1699
1700 /* - EtherAVB --------------------------------------------------------------- */
1701 static const unsigned int avb_link_pins[] = {
1702         /* AVB_LINK */
1703         RCAR_GP_PIN(2, 12),
1704 };
1705 static const unsigned int avb_link_mux[] = {
1706         AVB_LINK_MARK,
1707 };
1708 static const unsigned int avb_magic_pins[] = {
1709         /* AVB_MAGIC_ */
1710         RCAR_GP_PIN(2, 10),
1711 };
1712 static const unsigned int avb_magic_mux[] = {
1713         AVB_MAGIC_MARK,
1714 };
1715 static const unsigned int avb_phy_int_pins[] = {
1716         /* AVB_PHY_INT */
1717         RCAR_GP_PIN(2, 11),
1718 };
1719 static const unsigned int avb_phy_int_mux[] = {
1720         AVB_PHY_INT_MARK,
1721 };
1722 static const unsigned int avb_mdio_pins[] = {
1723         /* AVB_MDC, AVB_MDIO */
1724         RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1725 };
1726 static const unsigned int avb_mdio_mux[] = {
1727         AVB_MDC_MARK, AVB_MDIO_MARK,
1728 };
1729 static const unsigned int avb_mii_pins[] = {
1730         /*
1731          * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1732          * AVB_TD1, AVB_TD2, AVB_TD3,
1733          * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1734          * AVB_RD1, AVB_RD2, AVB_RD3,
1735          * AVB_TXCREFCLK
1736          */
1737         PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1738         PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1739         PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1740         PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1741         PIN_NUMBER('A', 12),
1742
1743 };
1744 static const unsigned int avb_mii_mux[] = {
1745         AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1746         AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1747         AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1748         AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1749         AVB_TXCREFCLK_MARK,
1750 };
1751 static const unsigned int avb_avtp_pps_pins[] = {
1752         /* AVB_AVTP_PPS */
1753         RCAR_GP_PIN(2, 6),
1754 };
1755 static const unsigned int avb_avtp_pps_mux[] = {
1756         AVB_AVTP_PPS_MARK,
1757 };
1758 static const unsigned int avb_avtp_match_a_pins[] = {
1759         /* AVB_AVTP_MATCH_A */
1760         RCAR_GP_PIN(2, 13),
1761 };
1762 static const unsigned int avb_avtp_match_a_mux[] = {
1763         AVB_AVTP_MATCH_A_MARK,
1764 };
1765 static const unsigned int avb_avtp_capture_a_pins[] = {
1766         /* AVB_AVTP_CAPTURE_A */
1767         RCAR_GP_PIN(2, 14),
1768 };
1769 static const unsigned int avb_avtp_capture_a_mux[] = {
1770         AVB_AVTP_CAPTURE_A_MARK,
1771 };
1772 static const unsigned int avb_avtp_match_b_pins[] = {
1773         /*  AVB_AVTP_MATCH_B */
1774         RCAR_GP_PIN(1, 8),
1775 };
1776 static const unsigned int avb_avtp_match_b_mux[] = {
1777         AVB_AVTP_MATCH_B_MARK,
1778 };
1779 static const unsigned int avb_avtp_capture_b_pins[] = {
1780         /* AVB_AVTP_CAPTURE_B */
1781         RCAR_GP_PIN(1, 11),
1782 };
1783 static const unsigned int avb_avtp_capture_b_mux[] = {
1784         AVB_AVTP_CAPTURE_B_MARK,
1785 };
1786
1787 /* - DU --------------------------------------------------------------------- */
1788 static const unsigned int du_rgb666_pins[] = {
1789         /* R[7:2], G[7:2], B[7:2] */
1790         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1791         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1792         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1793         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1794         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
1795         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
1796 };
1797
1798 static const unsigned int du_rgb666_mux[] = {
1799         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1800         DU_DR3_MARK, DU_DR2_MARK,
1801         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1802         DU_DG3_MARK, DU_DG2_MARK,
1803         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1804         DU_DB3_MARK, DU_DB2_MARK,
1805 };
1806
1807 static const unsigned int du_rgb888_pins[] = {
1808         /* R[7:0], G[7:0], B[7:0] */
1809         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1810         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1811         RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),
1812         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1813         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1814         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1815         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
1816         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
1817         RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
1818 };
1819
1820 static const unsigned int du_rgb888_mux[] = {
1821         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1822         DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
1823         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1824         DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
1825         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1826         DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
1827 };
1828
1829 static const unsigned int du_clk_out_0_pins[] = {
1830         /* CLKOUT */
1831         RCAR_GP_PIN(1, 27),
1832 };
1833
1834 static const unsigned int du_clk_out_0_mux[] = {
1835         DU_DOTCLKOUT0_MARK
1836 };
1837
1838 static const unsigned int du_clk_out_1_pins[] = {
1839         /* CLKOUT */
1840         RCAR_GP_PIN(2, 3),
1841 };
1842
1843 static const unsigned int du_clk_out_1_mux[] = {
1844         DU_DOTCLKOUT1_MARK
1845 };
1846
1847 static const unsigned int du_sync_pins[] = {
1848         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1849         RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
1850 };
1851
1852 static const unsigned int du_sync_mux[] = {
1853         DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
1854 };
1855
1856 static const unsigned int du_oddf_pins[] = {
1857         /* EXDISP/EXODDF/EXCDE */
1858         RCAR_GP_PIN(2, 2),
1859 };
1860
1861 static const unsigned int du_oddf_mux[] = {
1862         DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
1863 };
1864
1865 static const unsigned int du_cde_pins[] = {
1866         /* CDE */
1867         RCAR_GP_PIN(2, 0),
1868 };
1869
1870 static const unsigned int du_cde_mux[] = {
1871         DU_CDE_MARK,
1872 };
1873
1874 static const unsigned int du_disp_pins[] = {
1875         /* DISP */
1876         RCAR_GP_PIN(2, 1),
1877 };
1878
1879 static const unsigned int du_disp_mux[] = {
1880         DU_DISP_MARK,
1881 };
1882
1883 /* - HSCIF0 ----------------------------------------------------------------- */
1884 static const unsigned int hscif0_data_pins[] = {
1885         /* RX, TX */
1886         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1887 };
1888
1889 static const unsigned int hscif0_data_mux[] = {
1890         HRX0_MARK, HTX0_MARK,
1891 };
1892
1893 static const unsigned int hscif0_clk_pins[] = {
1894         /* SCK */
1895         RCAR_GP_PIN(5, 12),
1896 };
1897
1898 static const unsigned int hscif0_clk_mux[] = {
1899         HSCK0_MARK,
1900 };
1901
1902 static const unsigned int hscif0_ctrl_pins[] = {
1903         /* RTS, CTS */
1904         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
1905 };
1906
1907 static const unsigned int hscif0_ctrl_mux[] = {
1908         HRTS0_N_MARK, HCTS0_N_MARK,
1909 };
1910
1911 /* - HSCIF1 ----------------------------------------------------------------- */
1912 static const unsigned int hscif1_data_a_pins[] = {
1913         /* RX, TX */
1914         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
1915 };
1916
1917 static const unsigned int hscif1_data_a_mux[] = {
1918         HRX1_A_MARK, HTX1_A_MARK,
1919 };
1920
1921 static const unsigned int hscif1_clk_a_pins[] = {
1922         /* SCK */
1923         RCAR_GP_PIN(6, 21),
1924 };
1925
1926 static const unsigned int hscif1_clk_a_mux[] = {
1927         HSCK1_A_MARK,
1928 };
1929
1930 static const unsigned int hscif1_ctrl_a_pins[] = {
1931         /* RTS, CTS */
1932         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
1933 };
1934
1935 static const unsigned int hscif1_ctrl_a_mux[] = {
1936         HRTS1_N_A_MARK, HCTS1_N_A_MARK,
1937 };
1938
1939 static const unsigned int hscif1_data_b_pins[] = {
1940         /* RX, TX */
1941         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1942 };
1943
1944 static const unsigned int hscif1_data_b_mux[] = {
1945         HRX1_B_MARK, HTX1_B_MARK,
1946 };
1947
1948 static const unsigned int hscif1_clk_b_pins[] = {
1949         /* SCK */
1950         RCAR_GP_PIN(5, 0),
1951 };
1952
1953 static const unsigned int hscif1_clk_b_mux[] = {
1954         HSCK1_B_MARK,
1955 };
1956
1957 static const unsigned int hscif1_ctrl_b_pins[] = {
1958         /* RTS, CTS */
1959         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
1960 };
1961
1962 static const unsigned int hscif1_ctrl_b_mux[] = {
1963         HRTS1_N_B_MARK, HCTS1_N_B_MARK,
1964 };
1965
1966 /* - HSCIF2 ----------------------------------------------------------------- */
1967 static const unsigned int hscif2_data_a_pins[] = {
1968         /* RX, TX */
1969         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1970 };
1971
1972 static const unsigned int hscif2_data_a_mux[] = {
1973         HRX2_A_MARK, HTX2_A_MARK,
1974 };
1975
1976 static const unsigned int hscif2_clk_a_pins[] = {
1977         /* SCK */
1978         RCAR_GP_PIN(6, 10),
1979 };
1980
1981 static const unsigned int hscif2_clk_a_mux[] = {
1982         HSCK2_A_MARK,
1983 };
1984
1985 static const unsigned int hscif2_ctrl_a_pins[] = {
1986         /* RTS, CTS */
1987         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1988 };
1989
1990 static const unsigned int hscif2_ctrl_a_mux[] = {
1991         HRTS2_N_A_MARK, HCTS2_N_A_MARK,
1992 };
1993
1994 static const unsigned int hscif2_data_b_pins[] = {
1995         /* RX, TX */
1996         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1997 };
1998
1999 static const unsigned int hscif2_data_b_mux[] = {
2000         HRX2_B_MARK, HTX2_B_MARK,
2001 };
2002
2003 static const unsigned int hscif2_clk_b_pins[] = {
2004         /* SCK */
2005         RCAR_GP_PIN(6, 21),
2006 };
2007
2008 static const unsigned int hscif2_clk_b_mux[] = {
2009         HSCK2_B_MARK,
2010 };
2011
2012 static const unsigned int hscif2_ctrl_b_pins[] = {
2013         /* RTS, CTS */
2014         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2015 };
2016
2017 static const unsigned int hscif2_ctrl_b_mux[] = {
2018         HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2019 };
2020
2021 static const unsigned int hscif2_data_c_pins[] = {
2022         /* RX, TX */
2023         RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2024 };
2025
2026 static const unsigned int hscif2_data_c_mux[] = {
2027         HRX2_C_MARK, HTX2_C_MARK,
2028 };
2029
2030 static const unsigned int hscif2_clk_c_pins[] = {
2031         /* SCK */
2032         RCAR_GP_PIN(6, 24),
2033 };
2034
2035 static const unsigned int hscif2_clk_c_mux[] = {
2036         HSCK2_C_MARK,
2037 };
2038
2039 static const unsigned int hscif2_ctrl_c_pins[] = {
2040         /* RTS, CTS */
2041         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2042 };
2043
2044 static const unsigned int hscif2_ctrl_c_mux[] = {
2045         HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2046 };
2047
2048 /* - HSCIF3 ----------------------------------------------------------------- */
2049 static const unsigned int hscif3_data_a_pins[] = {
2050         /* RX, TX */
2051         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2052 };
2053
2054 static const unsigned int hscif3_data_a_mux[] = {
2055         HRX3_A_MARK, HTX3_A_MARK,
2056 };
2057
2058 static const unsigned int hscif3_clk_pins[] = {
2059         /* SCK */
2060         RCAR_GP_PIN(1, 22),
2061 };
2062
2063 static const unsigned int hscif3_clk_mux[] = {
2064         HSCK3_MARK,
2065 };
2066
2067 static const unsigned int hscif3_ctrl_pins[] = {
2068         /* RTS, CTS */
2069         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2070 };
2071
2072 static const unsigned int hscif3_ctrl_mux[] = {
2073         HRTS3_N_MARK, HCTS3_N_MARK,
2074 };
2075
2076 static const unsigned int hscif3_data_b_pins[] = {
2077         /* RX, TX */
2078         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2079 };
2080
2081 static const unsigned int hscif3_data_b_mux[] = {
2082         HRX3_B_MARK, HTX3_B_MARK,
2083 };
2084
2085 static const unsigned int hscif3_data_c_pins[] = {
2086         /* RX, TX */
2087         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2088 };
2089
2090 static const unsigned int hscif3_data_c_mux[] = {
2091         HRX3_C_MARK, HTX3_C_MARK,
2092 };
2093
2094 static const unsigned int hscif3_data_d_pins[] = {
2095         /* RX, TX */
2096         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2097 };
2098
2099 static const unsigned int hscif3_data_d_mux[] = {
2100         HRX3_D_MARK, HTX3_D_MARK,
2101 };
2102
2103 /* - HSCIF4 ----------------------------------------------------------------- */
2104 static const unsigned int hscif4_data_a_pins[] = {
2105         /* RX, TX */
2106         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2107 };
2108
2109 static const unsigned int hscif4_data_a_mux[] = {
2110         HRX4_A_MARK, HTX4_A_MARK,
2111 };
2112
2113 static const unsigned int hscif4_clk_pins[] = {
2114         /* SCK */
2115         RCAR_GP_PIN(1, 11),
2116 };
2117
2118 static const unsigned int hscif4_clk_mux[] = {
2119         HSCK4_MARK,
2120 };
2121
2122 static const unsigned int hscif4_ctrl_pins[] = {
2123         /* RTS, CTS */
2124         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2125 };
2126
2127 static const unsigned int hscif4_ctrl_mux[] = {
2128         HRTS4_N_MARK, HCTS4_N_MARK,
2129 };
2130
2131 static const unsigned int hscif4_data_b_pins[] = {
2132         /* RX, TX */
2133         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2134 };
2135
2136 static const unsigned int hscif4_data_b_mux[] = {
2137         HRX4_B_MARK, HTX4_B_MARK,
2138 };
2139
2140 /* - I2C -------------------------------------------------------------------- */
2141 static const unsigned int i2c1_a_pins[] = {
2142         /* SDA, SCL */
2143         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2144 };
2145 static const unsigned int i2c1_a_mux[] = {
2146         SDA1_A_MARK, SCL1_A_MARK,
2147 };
2148 static const unsigned int i2c1_b_pins[] = {
2149         /* SDA, SCL */
2150         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2151 };
2152 static const unsigned int i2c1_b_mux[] = {
2153         SDA1_B_MARK, SCL1_B_MARK,
2154 };
2155 static const unsigned int i2c2_a_pins[] = {
2156         /* SDA, SCL */
2157         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2158 };
2159 static const unsigned int i2c2_a_mux[] = {
2160         SDA2_A_MARK, SCL2_A_MARK,
2161 };
2162 static const unsigned int i2c2_b_pins[] = {
2163         /* SDA, SCL */
2164         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2165 };
2166 static const unsigned int i2c2_b_mux[] = {
2167         SDA2_B_MARK, SCL2_B_MARK,
2168 };
2169 static const unsigned int i2c6_a_pins[] = {
2170         /* SDA, SCL */
2171         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2172 };
2173 static const unsigned int i2c6_a_mux[] = {
2174         SDA6_A_MARK, SCL6_A_MARK,
2175 };
2176 static const unsigned int i2c6_b_pins[] = {
2177         /* SDA, SCL */
2178         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2179 };
2180 static const unsigned int i2c6_b_mux[] = {
2181         SDA6_B_MARK, SCL6_B_MARK,
2182 };
2183 static const unsigned int i2c6_c_pins[] = {
2184         /* SDA, SCL */
2185         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2186 };
2187 static const unsigned int i2c6_c_mux[] = {
2188         SDA6_C_MARK, SCL6_C_MARK,
2189 };
2190
2191 /* - INTC-EX ---------------------------------------------------------------- */
2192 static const unsigned int intc_ex_irq0_pins[] = {
2193         /* IRQ0 */
2194         RCAR_GP_PIN(2, 0),
2195 };
2196 static const unsigned int intc_ex_irq0_mux[] = {
2197         IRQ0_MARK,
2198 };
2199 static const unsigned int intc_ex_irq1_pins[] = {
2200         /* IRQ1 */
2201         RCAR_GP_PIN(2, 1),
2202 };
2203 static const unsigned int intc_ex_irq1_mux[] = {
2204         IRQ1_MARK,
2205 };
2206 static const unsigned int intc_ex_irq2_pins[] = {
2207         /* IRQ2 */
2208         RCAR_GP_PIN(2, 2),
2209 };
2210 static const unsigned int intc_ex_irq2_mux[] = {
2211         IRQ2_MARK,
2212 };
2213 static const unsigned int intc_ex_irq3_pins[] = {
2214         /* IRQ3 */
2215         RCAR_GP_PIN(2, 3),
2216 };
2217 static const unsigned int intc_ex_irq3_mux[] = {
2218         IRQ3_MARK,
2219 };
2220 static const unsigned int intc_ex_irq4_pins[] = {
2221         /* IRQ4 */
2222         RCAR_GP_PIN(2, 4),
2223 };
2224 static const unsigned int intc_ex_irq4_mux[] = {
2225         IRQ4_MARK,
2226 };
2227 static const unsigned int intc_ex_irq5_pins[] = {
2228         /* IRQ5 */
2229         RCAR_GP_PIN(2, 5),
2230 };
2231 static const unsigned int intc_ex_irq5_mux[] = {
2232         IRQ5_MARK,
2233 };
2234
2235 /* - MSIOF0 ----------------------------------------------------------------- */
2236 static const unsigned int msiof0_clk_pins[] = {
2237         /* SCK */
2238         RCAR_GP_PIN(5, 17),
2239 };
2240 static const unsigned int msiof0_clk_mux[] = {
2241         MSIOF0_SCK_MARK,
2242 };
2243 static const unsigned int msiof0_sync_pins[] = {
2244         /* SYNC */
2245         RCAR_GP_PIN(5, 18),
2246 };
2247 static const unsigned int msiof0_sync_mux[] = {
2248         MSIOF0_SYNC_MARK,
2249 };
2250 static const unsigned int msiof0_ss1_pins[] = {
2251         /* SS1 */
2252         RCAR_GP_PIN(5, 19),
2253 };
2254 static const unsigned int msiof0_ss1_mux[] = {
2255         MSIOF0_SS1_MARK,
2256 };
2257 static const unsigned int msiof0_ss2_pins[] = {
2258         /* SS2 */
2259         RCAR_GP_PIN(5, 21),
2260 };
2261 static const unsigned int msiof0_ss2_mux[] = {
2262         MSIOF0_SS2_MARK,
2263 };
2264 static const unsigned int msiof0_txd_pins[] = {
2265         /* TXD */
2266         RCAR_GP_PIN(5, 20),
2267 };
2268 static const unsigned int msiof0_txd_mux[] = {
2269         MSIOF0_TXD_MARK,
2270 };
2271 static const unsigned int msiof0_rxd_pins[] = {
2272         /* RXD */
2273         RCAR_GP_PIN(5, 22),
2274 };
2275 static const unsigned int msiof0_rxd_mux[] = {
2276         MSIOF0_RXD_MARK,
2277 };
2278 /* - MSIOF1 ----------------------------------------------------------------- */
2279 static const unsigned int msiof1_clk_a_pins[] = {
2280         /* SCK */
2281         RCAR_GP_PIN(6, 8),
2282 };
2283 static const unsigned int msiof1_clk_a_mux[] = {
2284         MSIOF1_SCK_A_MARK,
2285 };
2286 static const unsigned int msiof1_sync_a_pins[] = {
2287         /* SYNC */
2288         RCAR_GP_PIN(6, 9),
2289 };
2290 static const unsigned int msiof1_sync_a_mux[] = {
2291         MSIOF1_SYNC_A_MARK,
2292 };
2293 static const unsigned int msiof1_ss1_a_pins[] = {
2294         /* SS1 */
2295         RCAR_GP_PIN(6, 5),
2296 };
2297 static const unsigned int msiof1_ss1_a_mux[] = {
2298         MSIOF1_SS1_A_MARK,
2299 };
2300 static const unsigned int msiof1_ss2_a_pins[] = {
2301         /* SS2 */
2302         RCAR_GP_PIN(6, 6),
2303 };
2304 static const unsigned int msiof1_ss2_a_mux[] = {
2305         MSIOF1_SS2_A_MARK,
2306 };
2307 static const unsigned int msiof1_txd_a_pins[] = {
2308         /* TXD */
2309         RCAR_GP_PIN(6, 7),
2310 };
2311 static const unsigned int msiof1_txd_a_mux[] = {
2312         MSIOF1_TXD_A_MARK,
2313 };
2314 static const unsigned int msiof1_rxd_a_pins[] = {
2315         /* RXD */
2316         RCAR_GP_PIN(6, 10),
2317 };
2318 static const unsigned int msiof1_rxd_a_mux[] = {
2319         MSIOF1_RXD_A_MARK,
2320 };
2321 static const unsigned int msiof1_clk_b_pins[] = {
2322         /* SCK */
2323         RCAR_GP_PIN(5, 9),
2324 };
2325 static const unsigned int msiof1_clk_b_mux[] = {
2326         MSIOF1_SCK_B_MARK,
2327 };
2328 static const unsigned int msiof1_sync_b_pins[] = {
2329         /* SYNC */
2330         RCAR_GP_PIN(5, 3),
2331 };
2332 static const unsigned int msiof1_sync_b_mux[] = {
2333         MSIOF1_SYNC_B_MARK,
2334 };
2335 static const unsigned int msiof1_ss1_b_pins[] = {
2336         /* SS1 */
2337         RCAR_GP_PIN(5, 4),
2338 };
2339 static const unsigned int msiof1_ss1_b_mux[] = {
2340         MSIOF1_SS1_B_MARK,
2341 };
2342 static const unsigned int msiof1_ss2_b_pins[] = {
2343         /* SS2 */
2344         RCAR_GP_PIN(5, 0),
2345 };
2346 static const unsigned int msiof1_ss2_b_mux[] = {
2347         MSIOF1_SS2_B_MARK,
2348 };
2349 static const unsigned int msiof1_txd_b_pins[] = {
2350         /* TXD */
2351         RCAR_GP_PIN(5, 8),
2352 };
2353 static const unsigned int msiof1_txd_b_mux[] = {
2354         MSIOF1_TXD_B_MARK,
2355 };
2356 static const unsigned int msiof1_rxd_b_pins[] = {
2357         /* RXD */
2358         RCAR_GP_PIN(5, 7),
2359 };
2360 static const unsigned int msiof1_rxd_b_mux[] = {
2361         MSIOF1_RXD_B_MARK,
2362 };
2363 static const unsigned int msiof1_clk_c_pins[] = {
2364         /* SCK */
2365         RCAR_GP_PIN(6, 17),
2366 };
2367 static const unsigned int msiof1_clk_c_mux[] = {
2368         MSIOF1_SCK_C_MARK,
2369 };
2370 static const unsigned int msiof1_sync_c_pins[] = {
2371         /* SYNC */
2372         RCAR_GP_PIN(6, 18),
2373 };
2374 static const unsigned int msiof1_sync_c_mux[] = {
2375         MSIOF1_SYNC_C_MARK,
2376 };
2377 static const unsigned int msiof1_ss1_c_pins[] = {
2378         /* SS1 */
2379         RCAR_GP_PIN(6, 21),
2380 };
2381 static const unsigned int msiof1_ss1_c_mux[] = {
2382         MSIOF1_SS1_C_MARK,
2383 };
2384 static const unsigned int msiof1_ss2_c_pins[] = {
2385         /* SS2 */
2386         RCAR_GP_PIN(6, 27),
2387 };
2388 static const unsigned int msiof1_ss2_c_mux[] = {
2389         MSIOF1_SS2_C_MARK,
2390 };
2391 static const unsigned int msiof1_txd_c_pins[] = {
2392         /* TXD */
2393         RCAR_GP_PIN(6, 20),
2394 };
2395 static const unsigned int msiof1_txd_c_mux[] = {
2396         MSIOF1_TXD_C_MARK,
2397 };
2398 static const unsigned int msiof1_rxd_c_pins[] = {
2399         /* RXD */
2400         RCAR_GP_PIN(6, 19),
2401 };
2402 static const unsigned int msiof1_rxd_c_mux[] = {
2403         MSIOF1_RXD_C_MARK,
2404 };
2405 static const unsigned int msiof1_clk_d_pins[] = {
2406         /* SCK */
2407         RCAR_GP_PIN(5, 12),
2408 };
2409 static const unsigned int msiof1_clk_d_mux[] = {
2410         MSIOF1_SCK_D_MARK,
2411 };
2412 static const unsigned int msiof1_sync_d_pins[] = {
2413         /* SYNC */
2414         RCAR_GP_PIN(5, 15),
2415 };
2416 static const unsigned int msiof1_sync_d_mux[] = {
2417         MSIOF1_SYNC_D_MARK,
2418 };
2419 static const unsigned int msiof1_ss1_d_pins[] = {
2420         /* SS1 */
2421         RCAR_GP_PIN(5, 16),
2422 };
2423 static const unsigned int msiof1_ss1_d_mux[] = {
2424         MSIOF1_SS1_D_MARK,
2425 };
2426 static const unsigned int msiof1_ss2_d_pins[] = {
2427         /* SS2 */
2428         RCAR_GP_PIN(5, 21),
2429 };
2430 static const unsigned int msiof1_ss2_d_mux[] = {
2431         MSIOF1_SS2_D_MARK,
2432 };
2433 static const unsigned int msiof1_txd_d_pins[] = {
2434         /* TXD */
2435         RCAR_GP_PIN(5, 14),
2436 };
2437 static const unsigned int msiof1_txd_d_mux[] = {
2438         MSIOF1_TXD_D_MARK,
2439 };
2440 static const unsigned int msiof1_rxd_d_pins[] = {
2441         /* RXD */
2442         RCAR_GP_PIN(5, 13),
2443 };
2444 static const unsigned int msiof1_rxd_d_mux[] = {
2445         MSIOF1_RXD_D_MARK,
2446 };
2447 static const unsigned int msiof1_clk_e_pins[] = {
2448         /* SCK */
2449         RCAR_GP_PIN(3, 0),
2450 };
2451 static const unsigned int msiof1_clk_e_mux[] = {
2452         MSIOF1_SCK_E_MARK,
2453 };
2454 static const unsigned int msiof1_sync_e_pins[] = {
2455         /* SYNC */
2456         RCAR_GP_PIN(3, 1),
2457 };
2458 static const unsigned int msiof1_sync_e_mux[] = {
2459         MSIOF1_SYNC_E_MARK,
2460 };
2461 static const unsigned int msiof1_ss1_e_pins[] = {
2462         /* SS1 */
2463         RCAR_GP_PIN(3, 4),
2464 };
2465 static const unsigned int msiof1_ss1_e_mux[] = {
2466         MSIOF1_SS1_E_MARK,
2467 };
2468 static const unsigned int msiof1_ss2_e_pins[] = {
2469         /* SS2 */
2470         RCAR_GP_PIN(3, 5),
2471 };
2472 static const unsigned int msiof1_ss2_e_mux[] = {
2473         MSIOF1_SS2_E_MARK,
2474 };
2475 static const unsigned int msiof1_txd_e_pins[] = {
2476         /* TXD */
2477         RCAR_GP_PIN(3, 3),
2478 };
2479 static const unsigned int msiof1_txd_e_mux[] = {
2480         MSIOF1_TXD_E_MARK,
2481 };
2482 static const unsigned int msiof1_rxd_e_pins[] = {
2483         /* RXD */
2484         RCAR_GP_PIN(3, 2),
2485 };
2486 static const unsigned int msiof1_rxd_e_mux[] = {
2487         MSIOF1_RXD_E_MARK,
2488 };
2489 static const unsigned int msiof1_clk_f_pins[] = {
2490         /* SCK */
2491         RCAR_GP_PIN(5, 23),
2492 };
2493 static const unsigned int msiof1_clk_f_mux[] = {
2494         MSIOF1_SCK_F_MARK,
2495 };
2496 static const unsigned int msiof1_sync_f_pins[] = {
2497         /* SYNC */
2498         RCAR_GP_PIN(5, 24),
2499 };
2500 static const unsigned int msiof1_sync_f_mux[] = {
2501         MSIOF1_SYNC_F_MARK,
2502 };
2503 static const unsigned int msiof1_ss1_f_pins[] = {
2504         /* SS1 */
2505         RCAR_GP_PIN(6, 1),
2506 };
2507 static const unsigned int msiof1_ss1_f_mux[] = {
2508         MSIOF1_SS1_F_MARK,
2509 };
2510 static const unsigned int msiof1_ss2_f_pins[] = {
2511         /* SS2 */
2512         RCAR_GP_PIN(6, 2),
2513 };
2514 static const unsigned int msiof1_ss2_f_mux[] = {
2515         MSIOF1_SS2_F_MARK,
2516 };
2517 static const unsigned int msiof1_txd_f_pins[] = {
2518         /* TXD */
2519         RCAR_GP_PIN(6, 0),
2520 };
2521 static const unsigned int msiof1_txd_f_mux[] = {
2522         MSIOF1_TXD_F_MARK,
2523 };
2524 static const unsigned int msiof1_rxd_f_pins[] = {
2525         /* RXD */
2526         RCAR_GP_PIN(5, 25),
2527 };
2528 static const unsigned int msiof1_rxd_f_mux[] = {
2529         MSIOF1_RXD_F_MARK,
2530 };
2531 static const unsigned int msiof1_clk_g_pins[] = {
2532         /* SCK */
2533         RCAR_GP_PIN(3, 6),
2534 };
2535 static const unsigned int msiof1_clk_g_mux[] = {
2536         MSIOF1_SCK_G_MARK,
2537 };
2538 static const unsigned int msiof1_sync_g_pins[] = {
2539         /* SYNC */
2540         RCAR_GP_PIN(3, 7),
2541 };
2542 static const unsigned int msiof1_sync_g_mux[] = {
2543         MSIOF1_SYNC_G_MARK,
2544 };
2545 static const unsigned int msiof1_ss1_g_pins[] = {
2546         /* SS1 */
2547         RCAR_GP_PIN(3, 10),
2548 };
2549 static const unsigned int msiof1_ss1_g_mux[] = {
2550         MSIOF1_SS1_G_MARK,
2551 };
2552 static const unsigned int msiof1_ss2_g_pins[] = {
2553         /* SS2 */
2554         RCAR_GP_PIN(3, 11),
2555 };
2556 static const unsigned int msiof1_ss2_g_mux[] = {
2557         MSIOF1_SS2_G_MARK,
2558 };
2559 static const unsigned int msiof1_txd_g_pins[] = {
2560         /* TXD */
2561         RCAR_GP_PIN(3, 9),
2562 };
2563 static const unsigned int msiof1_txd_g_mux[] = {
2564         MSIOF1_TXD_G_MARK,
2565 };
2566 static const unsigned int msiof1_rxd_g_pins[] = {
2567         /* RXD */
2568         RCAR_GP_PIN(3, 8),
2569 };
2570 static const unsigned int msiof1_rxd_g_mux[] = {
2571         MSIOF1_RXD_G_MARK,
2572 };
2573 /* - MSIOF2 ----------------------------------------------------------------- */
2574 static const unsigned int msiof2_clk_a_pins[] = {
2575         /* SCK */
2576         RCAR_GP_PIN(1, 9),
2577 };
2578 static const unsigned int msiof2_clk_a_mux[] = {
2579         MSIOF2_SCK_A_MARK,
2580 };
2581 static const unsigned int msiof2_sync_a_pins[] = {
2582         /* SYNC */
2583         RCAR_GP_PIN(1, 8),
2584 };
2585 static const unsigned int msiof2_sync_a_mux[] = {
2586         MSIOF2_SYNC_A_MARK,
2587 };
2588 static const unsigned int msiof2_ss1_a_pins[] = {
2589         /* SS1 */
2590         RCAR_GP_PIN(1, 6),
2591 };
2592 static const unsigned int msiof2_ss1_a_mux[] = {
2593         MSIOF2_SS1_A_MARK,
2594 };
2595 static const unsigned int msiof2_ss2_a_pins[] = {
2596         /* SS2 */
2597         RCAR_GP_PIN(1, 7),
2598 };
2599 static const unsigned int msiof2_ss2_a_mux[] = {
2600         MSIOF2_SS2_A_MARK,
2601 };
2602 static const unsigned int msiof2_txd_a_pins[] = {
2603         /* TXD */
2604         RCAR_GP_PIN(1, 11),
2605 };
2606 static const unsigned int msiof2_txd_a_mux[] = {
2607         MSIOF2_TXD_A_MARK,
2608 };
2609 static const unsigned int msiof2_rxd_a_pins[] = {
2610         /* RXD */
2611         RCAR_GP_PIN(1, 10),
2612 };
2613 static const unsigned int msiof2_rxd_a_mux[] = {
2614         MSIOF2_RXD_A_MARK,
2615 };
2616 static const unsigned int msiof2_clk_b_pins[] = {
2617         /* SCK */
2618         RCAR_GP_PIN(0, 4),
2619 };
2620 static const unsigned int msiof2_clk_b_mux[] = {
2621         MSIOF2_SCK_B_MARK,
2622 };
2623 static const unsigned int msiof2_sync_b_pins[] = {
2624         /* SYNC */
2625         RCAR_GP_PIN(0, 5),
2626 };
2627 static const unsigned int msiof2_sync_b_mux[] = {
2628         MSIOF2_SYNC_B_MARK,
2629 };
2630 static const unsigned int msiof2_ss1_b_pins[] = {
2631         /* SS1 */
2632         RCAR_GP_PIN(0, 0),
2633 };
2634 static const unsigned int msiof2_ss1_b_mux[] = {
2635         MSIOF2_SS1_B_MARK,
2636 };
2637 static const unsigned int msiof2_ss2_b_pins[] = {
2638         /* SS2 */
2639         RCAR_GP_PIN(0, 1),
2640 };
2641 static const unsigned int msiof2_ss2_b_mux[] = {
2642         MSIOF2_SS2_B_MARK,
2643 };
2644 static const unsigned int msiof2_txd_b_pins[] = {
2645         /* TXD */
2646         RCAR_GP_PIN(0, 7),
2647 };
2648 static const unsigned int msiof2_txd_b_mux[] = {
2649         MSIOF2_TXD_B_MARK,
2650 };
2651 static const unsigned int msiof2_rxd_b_pins[] = {
2652         /* RXD */
2653         RCAR_GP_PIN(0, 6),
2654 };
2655 static const unsigned int msiof2_rxd_b_mux[] = {
2656         MSIOF2_RXD_B_MARK,
2657 };
2658 static const unsigned int msiof2_clk_c_pins[] = {
2659         /* SCK */
2660         RCAR_GP_PIN(2, 12),
2661 };
2662 static const unsigned int msiof2_clk_c_mux[] = {
2663         MSIOF2_SCK_C_MARK,
2664 };
2665 static const unsigned int msiof2_sync_c_pins[] = {
2666         /* SYNC */
2667         RCAR_GP_PIN(2, 11),
2668 };
2669 static const unsigned int msiof2_sync_c_mux[] = {
2670         MSIOF2_SYNC_C_MARK,
2671 };
2672 static const unsigned int msiof2_ss1_c_pins[] = {
2673         /* SS1 */
2674         RCAR_GP_PIN(2, 10),
2675 };
2676 static const unsigned int msiof2_ss1_c_mux[] = {
2677         MSIOF2_SS1_C_MARK,
2678 };
2679 static const unsigned int msiof2_ss2_c_pins[] = {
2680         /* SS2 */
2681         RCAR_GP_PIN(2, 9),
2682 };
2683 static const unsigned int msiof2_ss2_c_mux[] = {
2684         MSIOF2_SS2_C_MARK,
2685 };
2686 static const unsigned int msiof2_txd_c_pins[] = {
2687         /* TXD */
2688         RCAR_GP_PIN(2, 14),
2689 };
2690 static const unsigned int msiof2_txd_c_mux[] = {
2691         MSIOF2_TXD_C_MARK,
2692 };
2693 static const unsigned int msiof2_rxd_c_pins[] = {
2694         /* RXD */
2695         RCAR_GP_PIN(2, 13),
2696 };
2697 static const unsigned int msiof2_rxd_c_mux[] = {
2698         MSIOF2_RXD_C_MARK,
2699 };
2700 static const unsigned int msiof2_clk_d_pins[] = {
2701         /* SCK */
2702         RCAR_GP_PIN(0, 8),
2703 };
2704 static const unsigned int msiof2_clk_d_mux[] = {
2705         MSIOF2_SCK_D_MARK,
2706 };
2707 static const unsigned int msiof2_sync_d_pins[] = {
2708         /* SYNC */
2709         RCAR_GP_PIN(0, 9),
2710 };
2711 static const unsigned int msiof2_sync_d_mux[] = {
2712         MSIOF2_SYNC_D_MARK,
2713 };
2714 static const unsigned int msiof2_ss1_d_pins[] = {
2715         /* SS1 */
2716         RCAR_GP_PIN(0, 12),
2717 };
2718 static const unsigned int msiof2_ss1_d_mux[] = {
2719         MSIOF2_SS1_D_MARK,
2720 };
2721 static const unsigned int msiof2_ss2_d_pins[] = {
2722         /* SS2 */
2723         RCAR_GP_PIN(0, 13),
2724 };
2725 static const unsigned int msiof2_ss2_d_mux[] = {
2726         MSIOF2_SS2_D_MARK,
2727 };
2728 static const unsigned int msiof2_txd_d_pins[] = {
2729         /* TXD */
2730         RCAR_GP_PIN(0, 11),
2731 };
2732 static const unsigned int msiof2_txd_d_mux[] = {
2733         MSIOF2_TXD_D_MARK,
2734 };
2735 static const unsigned int msiof2_rxd_d_pins[] = {
2736         /* RXD */
2737         RCAR_GP_PIN(0, 10),
2738 };
2739 static const unsigned int msiof2_rxd_d_mux[] = {
2740         MSIOF2_RXD_D_MARK,
2741 };
2742 /* - MSIOF3 ----------------------------------------------------------------- */
2743 static const unsigned int msiof3_clk_a_pins[] = {
2744         /* SCK */
2745         RCAR_GP_PIN(0, 0),
2746 };
2747 static const unsigned int msiof3_clk_a_mux[] = {
2748         MSIOF3_SCK_A_MARK,
2749 };
2750 static const unsigned int msiof3_sync_a_pins[] = {
2751         /* SYNC */
2752         RCAR_GP_PIN(0, 1),
2753 };
2754 static const unsigned int msiof3_sync_a_mux[] = {
2755         MSIOF3_SYNC_A_MARK,
2756 };
2757 static const unsigned int msiof3_ss1_a_pins[] = {
2758         /* SS1 */
2759         RCAR_GP_PIN(0, 14),
2760 };
2761 static const unsigned int msiof3_ss1_a_mux[] = {
2762         MSIOF3_SS1_A_MARK,
2763 };
2764 static const unsigned int msiof3_ss2_a_pins[] = {
2765         /* SS2 */
2766         RCAR_GP_PIN(0, 15),
2767 };
2768 static const unsigned int msiof3_ss2_a_mux[] = {
2769         MSIOF3_SS2_A_MARK,
2770 };
2771 static const unsigned int msiof3_txd_a_pins[] = {
2772         /* TXD */
2773         RCAR_GP_PIN(0, 3),
2774 };
2775 static const unsigned int msiof3_txd_a_mux[] = {
2776         MSIOF3_TXD_A_MARK,
2777 };
2778 static const unsigned int msiof3_rxd_a_pins[] = {
2779         /* RXD */
2780         RCAR_GP_PIN(0, 2),
2781 };
2782 static const unsigned int msiof3_rxd_a_mux[] = {
2783         MSIOF3_RXD_A_MARK,
2784 };
2785 static const unsigned int msiof3_clk_b_pins[] = {
2786         /* SCK */
2787         RCAR_GP_PIN(1, 2),
2788 };
2789 static const unsigned int msiof3_clk_b_mux[] = {
2790         MSIOF3_SCK_B_MARK,
2791 };
2792 static const unsigned int msiof3_sync_b_pins[] = {
2793         /* SYNC */
2794         RCAR_GP_PIN(1, 0),
2795 };
2796 static const unsigned int msiof3_sync_b_mux[] = {
2797         MSIOF3_SYNC_B_MARK,
2798 };
2799 static const unsigned int msiof3_ss1_b_pins[] = {
2800         /* SS1 */
2801         RCAR_GP_PIN(1, 4),
2802 };
2803 static const unsigned int msiof3_ss1_b_mux[] = {
2804         MSIOF3_SS1_B_MARK,
2805 };
2806 static const unsigned int msiof3_ss2_b_pins[] = {
2807         /* SS2 */
2808         RCAR_GP_PIN(1, 5),
2809 };
2810 static const unsigned int msiof3_ss2_b_mux[] = {
2811         MSIOF3_SS2_B_MARK,
2812 };
2813 static const unsigned int msiof3_txd_b_pins[] = {
2814         /* TXD */
2815         RCAR_GP_PIN(1, 1),
2816 };
2817 static const unsigned int msiof3_txd_b_mux[] = {
2818         MSIOF3_TXD_B_MARK,
2819 };
2820 static const unsigned int msiof3_rxd_b_pins[] = {
2821         /* RXD */
2822         RCAR_GP_PIN(1, 3),
2823 };
2824 static const unsigned int msiof3_rxd_b_mux[] = {
2825         MSIOF3_RXD_B_MARK,
2826 };
2827 static const unsigned int msiof3_clk_c_pins[] = {
2828         /* SCK */
2829         RCAR_GP_PIN(1, 12),
2830 };
2831 static const unsigned int msiof3_clk_c_mux[] = {
2832         MSIOF3_SCK_C_MARK,
2833 };
2834 static const unsigned int msiof3_sync_c_pins[] = {
2835         /* SYNC */
2836         RCAR_GP_PIN(1, 13),
2837 };
2838 static const unsigned int msiof3_sync_c_mux[] = {
2839         MSIOF3_SYNC_C_MARK,
2840 };
2841 static const unsigned int msiof3_txd_c_pins[] = {
2842         /* TXD */
2843         RCAR_GP_PIN(1, 15),
2844 };
2845 static const unsigned int msiof3_txd_c_mux[] = {
2846         MSIOF3_TXD_C_MARK,
2847 };
2848 static const unsigned int msiof3_rxd_c_pins[] = {
2849         /* RXD */
2850         RCAR_GP_PIN(1, 14),
2851 };
2852 static const unsigned int msiof3_rxd_c_mux[] = {
2853         MSIOF3_RXD_C_MARK,
2854 };
2855 static const unsigned int msiof3_clk_d_pins[] = {
2856         /* SCK */
2857         RCAR_GP_PIN(1, 22),
2858 };
2859 static const unsigned int msiof3_clk_d_mux[] = {
2860         MSIOF3_SCK_D_MARK,
2861 };
2862 static const unsigned int msiof3_sync_d_pins[] = {
2863         /* SYNC */
2864         RCAR_GP_PIN(1, 23),
2865 };
2866 static const unsigned int msiof3_sync_d_mux[] = {
2867         MSIOF3_SYNC_D_MARK,
2868 };
2869 static const unsigned int msiof3_ss1_d_pins[] = {
2870         /* SS1 */
2871         RCAR_GP_PIN(1, 26),
2872 };
2873 static const unsigned int msiof3_ss1_d_mux[] = {
2874         MSIOF3_SS1_D_MARK,
2875 };
2876 static const unsigned int msiof3_txd_d_pins[] = {
2877         /* TXD */
2878         RCAR_GP_PIN(1, 25),
2879 };
2880 static const unsigned int msiof3_txd_d_mux[] = {
2881         MSIOF3_TXD_D_MARK,
2882 };
2883 static const unsigned int msiof3_rxd_d_pins[] = {
2884         /* RXD */
2885         RCAR_GP_PIN(1, 24),
2886 };
2887 static const unsigned int msiof3_rxd_d_mux[] = {
2888         MSIOF3_RXD_D_MARK,
2889 };
2890 static const unsigned int msiof3_clk_e_pins[] = {
2891         /* SCK */
2892         RCAR_GP_PIN(2, 3),
2893 };
2894 static const unsigned int msiof3_clk_e_mux[] = {
2895         MSIOF3_SCK_E_MARK,
2896 };
2897 static const unsigned int msiof3_sync_e_pins[] = {
2898         /* SYNC */
2899         RCAR_GP_PIN(2, 2),
2900 };
2901 static const unsigned int msiof3_sync_e_mux[] = {
2902         MSIOF3_SYNC_E_MARK,
2903 };
2904 static const unsigned int msiof3_ss1_e_pins[] = {
2905         /* SS1 */
2906         RCAR_GP_PIN(2, 1),
2907 };
2908 static const unsigned int msiof3_ss1_e_mux[] = {
2909         MSIOF3_SS1_E_MARK,
2910 };
2911 static const unsigned int msiof3_ss2_e_pins[] = {
2912         /* SS2 */
2913         RCAR_GP_PIN(2, 0),
2914 };
2915 static const unsigned int msiof3_ss2_e_mux[] = {
2916         MSIOF3_SS2_E_MARK,
2917 };
2918 static const unsigned int msiof3_txd_e_pins[] = {
2919         /* TXD */
2920         RCAR_GP_PIN(2, 5),
2921 };
2922 static const unsigned int msiof3_txd_e_mux[] = {
2923         MSIOF3_TXD_E_MARK,
2924 };
2925 static const unsigned int msiof3_rxd_e_pins[] = {
2926         /* RXD */
2927         RCAR_GP_PIN(2, 4),
2928 };
2929 static const unsigned int msiof3_rxd_e_mux[] = {
2930         MSIOF3_RXD_E_MARK,
2931 };
2932
2933 /* - PWM0 --------------------------------------------------------------------*/
2934 static const unsigned int pwm0_pins[] = {
2935         /* PWM */
2936         RCAR_GP_PIN(2, 6),
2937 };
2938 static const unsigned int pwm0_mux[] = {
2939         PWM0_MARK,
2940 };
2941 /* - PWM1 --------------------------------------------------------------------*/
2942 static const unsigned int pwm1_a_pins[] = {
2943         /* PWM */
2944         RCAR_GP_PIN(2, 7),
2945 };
2946 static const unsigned int pwm1_a_mux[] = {
2947         PWM1_A_MARK,
2948 };
2949 static const unsigned int pwm1_b_pins[] = {
2950         /* PWM */
2951         RCAR_GP_PIN(1, 8),
2952 };
2953 static const unsigned int pwm1_b_mux[] = {
2954         PWM1_B_MARK,
2955 };
2956 /* - PWM2 --------------------------------------------------------------------*/
2957 static const unsigned int pwm2_a_pins[] = {
2958         /* PWM */
2959         RCAR_GP_PIN(2, 8),
2960 };
2961 static const unsigned int pwm2_a_mux[] = {
2962         PWM2_A_MARK,
2963 };
2964 static const unsigned int pwm2_b_pins[] = {
2965         /* PWM */
2966         RCAR_GP_PIN(1, 11),
2967 };
2968 static const unsigned int pwm2_b_mux[] = {
2969         PWM2_B_MARK,
2970 };
2971 /* - PWM3 --------------------------------------------------------------------*/
2972 static const unsigned int pwm3_a_pins[] = {
2973         /* PWM */
2974         RCAR_GP_PIN(1, 0),
2975 };
2976 static const unsigned int pwm3_a_mux[] = {
2977         PWM3_A_MARK,
2978 };
2979 static const unsigned int pwm3_b_pins[] = {
2980         /* PWM */
2981         RCAR_GP_PIN(2, 2),
2982 };
2983 static const unsigned int pwm3_b_mux[] = {
2984         PWM3_B_MARK,
2985 };
2986 /* - PWM4 --------------------------------------------------------------------*/
2987 static const unsigned int pwm4_a_pins[] = {
2988         /* PWM */
2989         RCAR_GP_PIN(1, 1),
2990 };
2991 static const unsigned int pwm4_a_mux[] = {
2992         PWM4_A_MARK,
2993 };
2994 static const unsigned int pwm4_b_pins[] = {
2995         /* PWM */
2996         RCAR_GP_PIN(2, 3),
2997 };
2998 static const unsigned int pwm4_b_mux[] = {
2999         PWM4_B_MARK,
3000 };
3001 /* - PWM5 --------------------------------------------------------------------*/
3002 static const unsigned int pwm5_a_pins[] = {
3003         /* PWM */
3004         RCAR_GP_PIN(1, 2),
3005 };
3006 static const unsigned int pwm5_a_mux[] = {
3007         PWM5_A_MARK,
3008 };
3009 static const unsigned int pwm5_b_pins[] = {
3010         /* PWM */
3011         RCAR_GP_PIN(2, 4),
3012 };
3013 static const unsigned int pwm5_b_mux[] = {
3014         PWM5_B_MARK,
3015 };
3016 /* - PWM6 --------------------------------------------------------------------*/
3017 static const unsigned int pwm6_a_pins[] = {
3018         /* PWM */
3019         RCAR_GP_PIN(1, 3),
3020 };
3021 static const unsigned int pwm6_a_mux[] = {
3022         PWM6_A_MARK,
3023 };
3024 static const unsigned int pwm6_b_pins[] = {
3025         /* PWM */
3026         RCAR_GP_PIN(2, 5),
3027 };
3028 static const unsigned int pwm6_b_mux[] = {
3029         PWM6_B_MARK,
3030 };
3031
3032 /* - SATA --------------------------------------------------------------------*/
3033 static const unsigned int sata0_devslp_a_pins[] = {
3034         /* DEVSLP */
3035         RCAR_GP_PIN(6, 16),
3036 };
3037
3038 static const unsigned int sata0_devslp_a_mux[] = {
3039         SATA_DEVSLP_A_MARK,
3040 };
3041
3042 static const unsigned int sata0_devslp_b_pins[] = {
3043         /* DEVSLP */
3044         RCAR_GP_PIN(4, 6),
3045 };
3046
3047 static const unsigned int sata0_devslp_b_mux[] = {
3048         SATA_DEVSLP_B_MARK,
3049 };
3050
3051 /* - SCIF0 ------------------------------------------------------------------ */
3052 static const unsigned int scif0_data_pins[] = {
3053         /* RX, TX */
3054         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3055 };
3056 static const unsigned int scif0_data_mux[] = {
3057         RX0_MARK, TX0_MARK,
3058 };
3059 static const unsigned int scif0_clk_pins[] = {
3060         /* SCK */
3061         RCAR_GP_PIN(5, 0),
3062 };
3063 static const unsigned int scif0_clk_mux[] = {
3064         SCK0_MARK,
3065 };
3066 static const unsigned int scif0_ctrl_pins[] = {
3067         /* RTS, CTS */
3068         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3069 };
3070 static const unsigned int scif0_ctrl_mux[] = {
3071         RTS0_N_MARK, CTS0_N_MARK,
3072 };
3073 /* - SCIF1 ------------------------------------------------------------------ */
3074 static const unsigned int scif1_data_a_pins[] = {
3075         /* RX, TX */
3076         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3077 };
3078 static const unsigned int scif1_data_a_mux[] = {
3079         RX1_A_MARK, TX1_A_MARK,
3080 };
3081 static const unsigned int scif1_clk_pins[] = {
3082         /* SCK */
3083         RCAR_GP_PIN(6, 21),
3084 };
3085 static const unsigned int scif1_clk_mux[] = {
3086         SCK1_MARK,
3087 };
3088 static const unsigned int scif1_ctrl_pins[] = {
3089         /* RTS, CTS */
3090         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3091 };
3092 static const unsigned int scif1_ctrl_mux[] = {
3093         RTS1_N_MARK, CTS1_N_MARK,
3094 };
3095 static const unsigned int scif1_data_b_pins[] = {
3096         /* RX, TX */
3097         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3098 };
3099 static const unsigned int scif1_data_b_mux[] = {
3100         RX1_B_MARK, TX1_B_MARK,
3101 };
3102 /* - SCIF2 ------------------------------------------------------------------ */
3103 static const unsigned int scif2_data_a_pins[] = {
3104         /* RX, TX */
3105         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3106 };
3107 static const unsigned int scif2_data_a_mux[] = {
3108         RX2_A_MARK, TX2_A_MARK,
3109 };
3110 static const unsigned int scif2_clk_pins[] = {
3111         /* SCK */
3112         RCAR_GP_PIN(5, 9),
3113 };
3114 static const unsigned int scif2_clk_mux[] = {
3115         SCK2_MARK,
3116 };
3117 static const unsigned int scif2_data_b_pins[] = {
3118         /* RX, TX */
3119         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3120 };
3121 static const unsigned int scif2_data_b_mux[] = {
3122         RX2_B_MARK, TX2_B_MARK,
3123 };
3124 /* - SCIF3 ------------------------------------------------------------------ */
3125 static const unsigned int scif3_data_a_pins[] = {
3126         /* RX, TX */
3127         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3128 };
3129 static const unsigned int scif3_data_a_mux[] = {
3130         RX3_A_MARK, TX3_A_MARK,
3131 };
3132 static const unsigned int scif3_clk_pins[] = {
3133         /* SCK */
3134         RCAR_GP_PIN(1, 22),
3135 };
3136 static const unsigned int scif3_clk_mux[] = {
3137         SCK3_MARK,
3138 };
3139 static const unsigned int scif3_ctrl_pins[] = {
3140         /* RTS, CTS */
3141         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3142 };
3143 static const unsigned int scif3_ctrl_mux[] = {
3144         RTS3_N_MARK, CTS3_N_MARK,
3145 };
3146 static const unsigned int scif3_data_b_pins[] = {
3147         /* RX, TX */
3148         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3149 };
3150 static const unsigned int scif3_data_b_mux[] = {
3151         RX3_B_MARK, TX3_B_MARK,
3152 };
3153 /* - SCIF4 ------------------------------------------------------------------ */
3154 static const unsigned int scif4_data_a_pins[] = {
3155         /* RX, TX */
3156         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3157 };
3158 static const unsigned int scif4_data_a_mux[] = {
3159         RX4_A_MARK, TX4_A_MARK,
3160 };
3161 static const unsigned int scif4_clk_a_pins[] = {
3162         /* SCK */
3163         RCAR_GP_PIN(2, 10),
3164 };
3165 static const unsigned int scif4_clk_a_mux[] = {
3166         SCK4_A_MARK,
3167 };
3168 static const unsigned int scif4_ctrl_a_pins[] = {
3169         /* RTS, CTS */
3170         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3171 };
3172 static const unsigned int scif4_ctrl_a_mux[] = {
3173         RTS4_N_A_MARK, CTS4_N_A_MARK,
3174 };
3175 static const unsigned int scif4_data_b_pins[] = {
3176         /* RX, TX */
3177         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3178 };
3179 static const unsigned int scif4_data_b_mux[] = {
3180         RX4_B_MARK, TX4_B_MARK,
3181 };
3182 static const unsigned int scif4_clk_b_pins[] = {
3183         /* SCK */
3184         RCAR_GP_PIN(1, 5),
3185 };
3186 static const unsigned int scif4_clk_b_mux[] = {
3187         SCK4_B_MARK,
3188 };
3189 static const unsigned int scif4_ctrl_b_pins[] = {
3190         /* RTS, CTS */
3191         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3192 };
3193 static const unsigned int scif4_ctrl_b_mux[] = {
3194         RTS4_N_B_MARK, CTS4_N_B_MARK,
3195 };
3196 static const unsigned int scif4_data_c_pins[] = {
3197         /* RX, TX */
3198         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3199 };
3200 static const unsigned int scif4_data_c_mux[] = {
3201         RX4_C_MARK, TX4_C_MARK,
3202 };
3203 static const unsigned int scif4_clk_c_pins[] = {
3204         /* SCK */
3205         RCAR_GP_PIN(0, 8),
3206 };
3207 static const unsigned int scif4_clk_c_mux[] = {
3208         SCK4_C_MARK,
3209 };
3210 static const unsigned int scif4_ctrl_c_pins[] = {
3211         /* RTS, CTS */
3212         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3213 };
3214 static const unsigned int scif4_ctrl_c_mux[] = {
3215         RTS4_N_C_MARK, CTS4_N_C_MARK,
3216 };
3217 /* - SCIF5 ------------------------------------------------------------------ */
3218 static const unsigned int scif5_data_a_pins[] = {
3219         /* RX, TX */
3220         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3221 };
3222 static const unsigned int scif5_data_a_mux[] = {
3223         RX5_A_MARK, TX5_A_MARK,
3224 };
3225 static const unsigned int scif5_clk_a_pins[] = {
3226         /* SCK */
3227         RCAR_GP_PIN(6, 21),
3228 };
3229 static const unsigned int scif5_clk_a_mux[] = {
3230         SCK5_A_MARK,
3231 };
3232 static const unsigned int scif5_data_b_pins[] = {
3233         /* RX, TX */
3234         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3235 };
3236 static const unsigned int scif5_data_b_mux[] = {
3237         RX5_B_MARK, TX5_B_MARK,
3238 };
3239 static const unsigned int scif5_clk_b_pins[] = {
3240         /* SCK */
3241         RCAR_GP_PIN(5, 0),
3242 };
3243 static const unsigned int scif5_clk_b_mux[] = {
3244         SCK5_B_MARK,
3245 };
3246 /* - SCIF Clock ------------------------------------------------------------- */
3247 static const unsigned int scif_clk_a_pins[] = {
3248         /* SCIF_CLK */
3249         RCAR_GP_PIN(6, 23),
3250 };
3251 static const unsigned int scif_clk_a_mux[] = {
3252         SCIF_CLK_A_MARK,
3253 };
3254 static const unsigned int scif_clk_b_pins[] = {
3255         /* SCIF_CLK */
3256         RCAR_GP_PIN(5, 9),
3257 };
3258 static const unsigned int scif_clk_b_mux[] = {
3259         SCIF_CLK_B_MARK,
3260 };
3261
3262 /* - SDHI0 ------------------------------------------------------------------ */
3263 static const unsigned int sdhi0_data1_pins[] = {
3264         /* D0 */
3265         RCAR_GP_PIN(3, 2),
3266 };
3267
3268 static const unsigned int sdhi0_data1_mux[] = {
3269         SD0_DAT0_MARK,
3270 };
3271
3272 static const unsigned int sdhi0_data4_pins[] = {
3273         /* D[0:3] */
3274         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3275         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3276 };
3277
3278 static const unsigned int sdhi0_data4_mux[] = {
3279         SD0_DAT0_MARK, SD0_DAT1_MARK,
3280         SD0_DAT2_MARK, SD0_DAT3_MARK,
3281 };
3282
3283 static const unsigned int sdhi0_ctrl_pins[] = {
3284         /* CLK, CMD */
3285         RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3286 };
3287
3288 static const unsigned int sdhi0_ctrl_mux[] = {
3289         SD0_CLK_MARK, SD0_CMD_MARK,
3290 };
3291
3292 static const unsigned int sdhi0_cd_pins[] = {
3293         /* CD */
3294         RCAR_GP_PIN(3, 12),
3295 };
3296
3297 static const unsigned int sdhi0_cd_mux[] = {
3298         SD0_CD_MARK,
3299 };
3300
3301 static const unsigned int sdhi0_wp_pins[] = {
3302         /* WP */
3303         RCAR_GP_PIN(3, 13),
3304 };
3305
3306 static const unsigned int sdhi0_wp_mux[] = {
3307         SD0_WP_MARK,
3308 };
3309
3310 /* - SDHI1 ------------------------------------------------------------------ */
3311 static const unsigned int sdhi1_data1_pins[] = {
3312         /* D0 */
3313         RCAR_GP_PIN(3, 8),
3314 };
3315
3316 static const unsigned int sdhi1_data1_mux[] = {
3317         SD1_DAT0_MARK,
3318 };
3319
3320 static const unsigned int sdhi1_data4_pins[] = {
3321         /* D[0:3] */
3322         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3323         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3324 };
3325
3326 static const unsigned int sdhi1_data4_mux[] = {
3327         SD1_DAT0_MARK, SD1_DAT1_MARK,
3328         SD1_DAT2_MARK, SD1_DAT3_MARK,
3329 };
3330
3331 static const unsigned int sdhi1_ctrl_pins[] = {
3332         /* CLK, CMD */
3333         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3334 };
3335
3336 static const unsigned int sdhi1_ctrl_mux[] = {
3337         SD1_CLK_MARK, SD1_CMD_MARK,
3338 };
3339
3340 static const unsigned int sdhi1_cd_pins[] = {
3341         /* CD */
3342         RCAR_GP_PIN(3, 14),
3343 };
3344
3345 static const unsigned int sdhi1_cd_mux[] = {
3346         SD1_CD_MARK,
3347 };
3348
3349 static const unsigned int sdhi1_wp_pins[] = {
3350         /* WP */
3351         RCAR_GP_PIN(3, 15),
3352 };
3353
3354 static const unsigned int sdhi1_wp_mux[] = {
3355         SD1_WP_MARK,
3356 };
3357
3358 /* - SDHI2 ------------------------------------------------------------------ */
3359 static const unsigned int sdhi2_data1_pins[] = {
3360         /* D0 */
3361         RCAR_GP_PIN(4, 2),
3362 };
3363
3364 static const unsigned int sdhi2_data1_mux[] = {
3365         SD2_DAT0_MARK,
3366 };
3367
3368 static const unsigned int sdhi2_data4_pins[] = {
3369         /* D[0:3] */
3370         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3371         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3372 };
3373
3374 static const unsigned int sdhi2_data4_mux[] = {
3375         SD2_DAT0_MARK, SD2_DAT1_MARK,
3376         SD2_DAT2_MARK, SD2_DAT3_MARK,
3377 };
3378
3379 static const unsigned int sdhi2_data8_pins[] = {
3380         /* D[0:7] */
3381         RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
3382         RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
3383         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3384         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3385 };
3386
3387 static const unsigned int sdhi2_data8_mux[] = {
3388         SD2_DAT0_MARK, SD2_DAT1_MARK,
3389         SD2_DAT2_MARK, SD2_DAT3_MARK,
3390         SD2_DAT4_MARK, SD2_DAT5_MARK,
3391         SD2_DAT6_MARK, SD2_DAT7_MARK,
3392 };
3393
3394 static const unsigned int sdhi2_ctrl_pins[] = {
3395         /* CLK, CMD */
3396         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3397 };
3398
3399 static const unsigned int sdhi2_ctrl_mux[] = {
3400         SD2_CLK_MARK, SD2_CMD_MARK,
3401 };
3402
3403 static const unsigned int sdhi2_cd_a_pins[] = {
3404         /* CD */
3405         RCAR_GP_PIN(4, 13),
3406 };
3407
3408 static const unsigned int sdhi2_cd_a_mux[] = {
3409         SD2_CD_A_MARK,
3410 };
3411
3412 static const unsigned int sdhi2_cd_b_pins[] = {
3413         /* CD */
3414         RCAR_GP_PIN(5, 10),
3415 };
3416
3417 static const unsigned int sdhi2_cd_b_mux[] = {
3418         SD2_CD_B_MARK,
3419 };
3420
3421 static const unsigned int sdhi2_wp_a_pins[] = {
3422         /* WP */
3423         RCAR_GP_PIN(4, 14),
3424 };
3425
3426 static const unsigned int sdhi2_wp_a_mux[] = {
3427         SD2_WP_A_MARK,
3428 };
3429
3430 static const unsigned int sdhi2_wp_b_pins[] = {
3431         /* WP */
3432         RCAR_GP_PIN(5, 11),
3433 };
3434
3435 static const unsigned int sdhi2_wp_b_mux[] = {
3436         SD2_WP_B_MARK,
3437 };
3438
3439 static const unsigned int sdhi2_ds_pins[] = {
3440         /* DS */
3441         RCAR_GP_PIN(4, 6),
3442 };
3443
3444 static const unsigned int sdhi2_ds_mux[] = {
3445         SD2_DS_MARK,
3446 };
3447
3448 /* - SDHI3 ------------------------------------------------------------------ */
3449 static const unsigned int sdhi3_data1_pins[] = {
3450         /* D0 */
3451         RCAR_GP_PIN(4, 9),
3452 };
3453
3454 static const unsigned int sdhi3_data1_mux[] = {
3455         SD3_DAT0_MARK,
3456 };
3457
3458 static const unsigned int sdhi3_data4_pins[] = {
3459         /* D[0:3] */
3460         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3461         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3462 };
3463
3464 static const unsigned int sdhi3_data4_mux[] = {
3465         SD3_DAT0_MARK, SD3_DAT1_MARK,
3466         SD3_DAT2_MARK, SD3_DAT3_MARK,
3467 };
3468
3469 static const unsigned int sdhi3_data8_pins[] = {
3470         /* D[0:7] */
3471         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3472         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3473         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3474         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3475 };
3476
3477 static const unsigned int sdhi3_data8_mux[] = {
3478         SD3_DAT0_MARK, SD3_DAT1_MARK,
3479         SD3_DAT2_MARK, SD3_DAT3_MARK,
3480         SD3_DAT4_MARK, SD3_DAT5_MARK,
3481         SD3_DAT6_MARK, SD3_DAT7_MARK,
3482 };
3483
3484 static const unsigned int sdhi3_ctrl_pins[] = {
3485         /* CLK, CMD */
3486         RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3487 };
3488
3489 static const unsigned int sdhi3_ctrl_mux[] = {
3490         SD3_CLK_MARK, SD3_CMD_MARK,
3491 };
3492
3493 static const unsigned int sdhi3_cd_pins[] = {
3494         /* CD */
3495         RCAR_GP_PIN(4, 15),
3496 };
3497
3498 static const unsigned int sdhi3_cd_mux[] = {
3499         SD3_CD_MARK,
3500 };
3501
3502 static const unsigned int sdhi3_wp_pins[] = {
3503         /* WP */
3504         RCAR_GP_PIN(4, 16),
3505 };
3506
3507 static const unsigned int sdhi3_wp_mux[] = {
3508         SD3_WP_MARK,
3509 };
3510
3511 static const unsigned int sdhi3_ds_pins[] = {
3512         /* DS */
3513         RCAR_GP_PIN(4, 17),
3514 };
3515
3516 static const unsigned int sdhi3_ds_mux[] = {
3517         SD3_DS_MARK,
3518 };
3519
3520 /* - SSI -------------------------------------------------------------------- */
3521 static const unsigned int ssi0_data_pins[] = {
3522         /* SDATA */
3523         RCAR_GP_PIN(6, 2),
3524 };
3525 static const unsigned int ssi0_data_mux[] = {
3526         SSI_SDATA0_MARK,
3527 };
3528 static const unsigned int ssi01239_ctrl_pins[] = {
3529         /* SCK, WS */
3530         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3531 };
3532 static const unsigned int ssi01239_ctrl_mux[] = {
3533         SSI_SCK01239_MARK, SSI_WS01239_MARK,
3534 };
3535 static const unsigned int ssi1_data_a_pins[] = {
3536         /* SDATA */
3537         RCAR_GP_PIN(6, 3),
3538 };
3539 static const unsigned int ssi1_data_a_mux[] = {
3540         SSI_SDATA1_A_MARK,
3541 };
3542 static const unsigned int ssi1_data_b_pins[] = {
3543         /* SDATA */
3544         RCAR_GP_PIN(5, 12),
3545 };
3546 static const unsigned int ssi1_data_b_mux[] = {
3547         SSI_SDATA1_B_MARK,
3548 };
3549 static const unsigned int ssi1_ctrl_a_pins[] = {
3550         /* SCK, WS */
3551         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3552 };
3553 static const unsigned int ssi1_ctrl_a_mux[] = {
3554         SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3555 };
3556 static const unsigned int ssi1_ctrl_b_pins[] = {
3557         /* SCK, WS */
3558         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3559 };
3560 static const unsigned int ssi1_ctrl_b_mux[] = {
3561         SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3562 };
3563 static const unsigned int ssi2_data_a_pins[] = {
3564         /* SDATA */
3565         RCAR_GP_PIN(6, 4),
3566 };
3567 static const unsigned int ssi2_data_a_mux[] = {
3568         SSI_SDATA2_A_MARK,
3569 };
3570 static const unsigned int ssi2_data_b_pins[] = {
3571         /* SDATA */
3572         RCAR_GP_PIN(5, 13),
3573 };
3574 static const unsigned int ssi2_data_b_mux[] = {
3575         SSI_SDATA2_B_MARK,
3576 };
3577 static const unsigned int ssi2_ctrl_a_pins[] = {
3578         /* SCK, WS */
3579         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3580 };
3581 static const unsigned int ssi2_ctrl_a_mux[] = {
3582         SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3583 };
3584 static const unsigned int ssi2_ctrl_b_pins[] = {
3585         /* SCK, WS */
3586         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3587 };
3588 static const unsigned int ssi2_ctrl_b_mux[] = {
3589         SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3590 };
3591 static const unsigned int ssi3_data_pins[] = {
3592         /* SDATA */
3593         RCAR_GP_PIN(6, 7),
3594 };
3595 static const unsigned int ssi3_data_mux[] = {
3596         SSI_SDATA3_MARK,
3597 };
3598 static const unsigned int ssi349_ctrl_pins[] = {
3599         /* SCK, WS */
3600         RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3601 };
3602 static const unsigned int ssi349_ctrl_mux[] = {
3603         SSI_SCK349_MARK, SSI_WS349_MARK,
3604 };
3605 static const unsigned int ssi4_data_pins[] = {
3606         /* SDATA */
3607         RCAR_GP_PIN(6, 10),
3608 };
3609 static const unsigned int ssi4_data_mux[] = {
3610         SSI_SDATA4_MARK,
3611 };
3612 static const unsigned int ssi4_ctrl_pins[] = {
3613         /* SCK, WS */
3614         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3615 };
3616 static const unsigned int ssi4_ctrl_mux[] = {
3617         SSI_SCK4_MARK, SSI_WS4_MARK,
3618 };
3619 static const unsigned int ssi5_data_pins[] = {
3620         /* SDATA */
3621         RCAR_GP_PIN(6, 13),
3622 };
3623 static const unsigned int ssi5_data_mux[] = {
3624         SSI_SDATA5_MARK,
3625 };
3626 static const unsigned int ssi5_ctrl_pins[] = {
3627         /* SCK, WS */
3628         RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3629 };
3630 static const unsigned int ssi5_ctrl_mux[] = {
3631         SSI_SCK5_MARK, SSI_WS5_MARK,
3632 };
3633 static const unsigned int ssi6_data_pins[] = {
3634         /* SDATA */
3635         RCAR_GP_PIN(6, 16),
3636 };
3637 static const unsigned int ssi6_data_mux[] = {
3638         SSI_SDATA6_MARK,
3639 };
3640 static const unsigned int ssi6_ctrl_pins[] = {
3641         /* SCK, WS */
3642         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3643 };
3644 static const unsigned int ssi6_ctrl_mux[] = {
3645         SSI_SCK6_MARK, SSI_WS6_MARK,
3646 };
3647 static const unsigned int ssi7_data_pins[] = {
3648         /* SDATA */
3649         RCAR_GP_PIN(6, 19),
3650 };
3651 static const unsigned int ssi7_data_mux[] = {
3652         SSI_SDATA7_MARK,
3653 };
3654 static const unsigned int ssi78_ctrl_pins[] = {
3655         /* SCK, WS */
3656         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3657 };
3658 static const unsigned int ssi78_ctrl_mux[] = {
3659         SSI_SCK78_MARK, SSI_WS78_MARK,
3660 };
3661 static const unsigned int ssi8_data_pins[] = {
3662         /* SDATA */
3663         RCAR_GP_PIN(6, 20),
3664 };
3665 static const unsigned int ssi8_data_mux[] = {
3666         SSI_SDATA8_MARK,
3667 };
3668 static const unsigned int ssi9_data_a_pins[] = {
3669         /* SDATA */
3670         RCAR_GP_PIN(6, 21),
3671 };
3672 static const unsigned int ssi9_data_a_mux[] = {
3673         SSI_SDATA9_A_MARK,
3674 };
3675 static const unsigned int ssi9_data_b_pins[] = {
3676         /* SDATA */
3677         RCAR_GP_PIN(5, 14),
3678 };
3679 static const unsigned int ssi9_data_b_mux[] = {
3680         SSI_SDATA9_B_MARK,
3681 };
3682 static const unsigned int ssi9_ctrl_a_pins[] = {
3683         /* SCK, WS */
3684         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3685 };
3686 static const unsigned int ssi9_ctrl_a_mux[] = {
3687         SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3688 };
3689 static const unsigned int ssi9_ctrl_b_pins[] = {
3690         /* SCK, WS */
3691         RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3692 };
3693 static const unsigned int ssi9_ctrl_b_mux[] = {
3694         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3695 };
3696
3697
3698 /* - USB0 ------------------------------------------------------------------- */
3699 static const unsigned int usb0_pins[] = {
3700         /* PWEN, OVC */
3701         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3702 };
3703
3704 static const unsigned int usb0_mux[] = {
3705         USB0_PWEN_MARK, USB0_OVC_MARK,
3706 };
3707
3708 /* - USB1 ------------------------------------------------------------------- */
3709 static const unsigned int usb1_pins[] = {
3710         /* PWEN, OVC */
3711         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3712 };
3713
3714 static const unsigned int usb1_mux[] = {
3715         USB1_PWEN_MARK, USB1_OVC_MARK,
3716 };
3717
3718 /* - USB30 ------------------------------------------------------------------ */
3719 static const unsigned int usb30_pins[] = {
3720         /* PWEN, OVC */
3721         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3722 };
3723
3724 static const unsigned int usb30_mux[] = {
3725         USB30_PWEN_MARK, USB30_OVC_MARK,
3726 };
3727
3728 static const struct sh_pfc_pin_group pinmux_groups[] = {
3729         SH_PFC_PIN_GROUP(audio_clk_a_a),
3730         SH_PFC_PIN_GROUP(audio_clk_a_b),
3731         SH_PFC_PIN_GROUP(audio_clk_a_c),
3732         SH_PFC_PIN_GROUP(audio_clk_b_a),
3733         SH_PFC_PIN_GROUP(audio_clk_b_b),
3734         SH_PFC_PIN_GROUP(audio_clk_c_a),
3735         SH_PFC_PIN_GROUP(audio_clk_c_b),
3736         SH_PFC_PIN_GROUP(audio_clkout_a),
3737         SH_PFC_PIN_GROUP(audio_clkout_b),
3738         SH_PFC_PIN_GROUP(audio_clkout_c),
3739         SH_PFC_PIN_GROUP(audio_clkout_d),
3740         SH_PFC_PIN_GROUP(audio_clkout1_a),
3741         SH_PFC_PIN_GROUP(audio_clkout1_b),
3742         SH_PFC_PIN_GROUP(audio_clkout2_a),
3743         SH_PFC_PIN_GROUP(audio_clkout2_b),
3744         SH_PFC_PIN_GROUP(audio_clkout3_a),
3745         SH_PFC_PIN_GROUP(audio_clkout3_b),
3746         SH_PFC_PIN_GROUP(avb_link),
3747         SH_PFC_PIN_GROUP(avb_magic),
3748         SH_PFC_PIN_GROUP(avb_phy_int),
3749         SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio),      /* Deprecated */
3750         SH_PFC_PIN_GROUP(avb_mdio),
3751         SH_PFC_PIN_GROUP(avb_mii),
3752         SH_PFC_PIN_GROUP(avb_avtp_pps),
3753         SH_PFC_PIN_GROUP(avb_avtp_match_a),
3754         SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3755         SH_PFC_PIN_GROUP(avb_avtp_match_b),
3756         SH_PFC_PIN_GROUP(avb_avtp_capture_b),
3757         SH_PFC_PIN_GROUP(du_rgb666),
3758         SH_PFC_PIN_GROUP(du_rgb888),
3759         SH_PFC_PIN_GROUP(du_clk_out_0),
3760         SH_PFC_PIN_GROUP(du_clk_out_1),
3761         SH_PFC_PIN_GROUP(du_sync),
3762         SH_PFC_PIN_GROUP(du_oddf),
3763         SH_PFC_PIN_GROUP(du_cde),
3764         SH_PFC_PIN_GROUP(du_disp),
3765         SH_PFC_PIN_GROUP(hscif0_data),
3766         SH_PFC_PIN_GROUP(hscif0_clk),
3767         SH_PFC_PIN_GROUP(hscif0_ctrl),
3768         SH_PFC_PIN_GROUP(hscif1_data_a),
3769         SH_PFC_PIN_GROUP(hscif1_clk_a),
3770         SH_PFC_PIN_GROUP(hscif1_ctrl_a),
3771         SH_PFC_PIN_GROUP(hscif1_data_b),
3772         SH_PFC_PIN_GROUP(hscif1_clk_b),
3773         SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3774         SH_PFC_PIN_GROUP(hscif2_data_a),
3775         SH_PFC_PIN_GROUP(hscif2_clk_a),
3776         SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3777         SH_PFC_PIN_GROUP(hscif2_data_b),
3778         SH_PFC_PIN_GROUP(hscif2_clk_b),
3779         SH_PFC_PIN_GROUP(hscif2_ctrl_b),
3780         SH_PFC_PIN_GROUP(hscif2_data_c),
3781         SH_PFC_PIN_GROUP(hscif2_clk_c),
3782         SH_PFC_PIN_GROUP(hscif2_ctrl_c),
3783         SH_PFC_PIN_GROUP(hscif3_data_a),
3784         SH_PFC_PIN_GROUP(hscif3_clk),
3785         SH_PFC_PIN_GROUP(hscif3_ctrl),
3786         SH_PFC_PIN_GROUP(hscif3_data_b),
3787         SH_PFC_PIN_GROUP(hscif3_data_c),
3788         SH_PFC_PIN_GROUP(hscif3_data_d),
3789         SH_PFC_PIN_GROUP(hscif4_data_a),
3790         SH_PFC_PIN_GROUP(hscif4_clk),
3791         SH_PFC_PIN_GROUP(hscif4_ctrl),
3792         SH_PFC_PIN_GROUP(hscif4_data_b),
3793         SH_PFC_PIN_GROUP(i2c1_a),
3794         SH_PFC_PIN_GROUP(i2c1_b),
3795         SH_PFC_PIN_GROUP(i2c2_a),
3796         SH_PFC_PIN_GROUP(i2c2_b),
3797         SH_PFC_PIN_GROUP(i2c6_a),
3798         SH_PFC_PIN_GROUP(i2c6_b),
3799         SH_PFC_PIN_GROUP(i2c6_c),
3800         SH_PFC_PIN_GROUP(intc_ex_irq0),
3801         SH_PFC_PIN_GROUP(intc_ex_irq1),
3802         SH_PFC_PIN_GROUP(intc_ex_irq2),
3803         SH_PFC_PIN_GROUP(intc_ex_irq3),
3804         SH_PFC_PIN_GROUP(intc_ex_irq4),
3805         SH_PFC_PIN_GROUP(intc_ex_irq5),
3806         SH_PFC_PIN_GROUP(msiof0_clk),
3807         SH_PFC_PIN_GROUP(msiof0_sync),
3808         SH_PFC_PIN_GROUP(msiof0_ss1),
3809         SH_PFC_PIN_GROUP(msiof0_ss2),
3810         SH_PFC_PIN_GROUP(msiof0_txd),
3811         SH_PFC_PIN_GROUP(msiof0_rxd),
3812         SH_PFC_PIN_GROUP(msiof1_clk_a),
3813         SH_PFC_PIN_GROUP(msiof1_sync_a),
3814         SH_PFC_PIN_GROUP(msiof1_ss1_a),
3815         SH_PFC_PIN_GROUP(msiof1_ss2_a),
3816         SH_PFC_PIN_GROUP(msiof1_txd_a),
3817         SH_PFC_PIN_GROUP(msiof1_rxd_a),
3818         SH_PFC_PIN_GROUP(msiof1_clk_b),
3819         SH_PFC_PIN_GROUP(msiof1_sync_b),
3820         SH_PFC_PIN_GROUP(msiof1_ss1_b),
3821         SH_PFC_PIN_GROUP(msiof1_ss2_b),
3822         SH_PFC_PIN_GROUP(msiof1_txd_b),
3823         SH_PFC_PIN_GROUP(msiof1_rxd_b),
3824         SH_PFC_PIN_GROUP(msiof1_clk_c),
3825         SH_PFC_PIN_GROUP(msiof1_sync_c),
3826         SH_PFC_PIN_GROUP(msiof1_ss1_c),
3827         SH_PFC_PIN_GROUP(msiof1_ss2_c),
3828         SH_PFC_PIN_GROUP(msiof1_txd_c),
3829         SH_PFC_PIN_GROUP(msiof1_rxd_c),
3830         SH_PFC_PIN_GROUP(msiof1_clk_d),
3831         SH_PFC_PIN_GROUP(msiof1_sync_d),
3832         SH_PFC_PIN_GROUP(msiof1_ss1_d),
3833         SH_PFC_PIN_GROUP(msiof1_ss2_d),
3834         SH_PFC_PIN_GROUP(msiof1_txd_d),
3835         SH_PFC_PIN_GROUP(msiof1_rxd_d),
3836         SH_PFC_PIN_GROUP(msiof1_clk_e),
3837         SH_PFC_PIN_GROUP(msiof1_sync_e),
3838         SH_PFC_PIN_GROUP(msiof1_ss1_e),
3839         SH_PFC_PIN_GROUP(msiof1_ss2_e),
3840         SH_PFC_PIN_GROUP(msiof1_txd_e),
3841         SH_PFC_PIN_GROUP(msiof1_rxd_e),
3842         SH_PFC_PIN_GROUP(msiof1_clk_f),
3843         SH_PFC_PIN_GROUP(msiof1_sync_f),
3844         SH_PFC_PIN_GROUP(msiof1_ss1_f),
3845         SH_PFC_PIN_GROUP(msiof1_ss2_f),
3846         SH_PFC_PIN_GROUP(msiof1_txd_f),
3847         SH_PFC_PIN_GROUP(msiof1_rxd_f),
3848         SH_PFC_PIN_GROUP(msiof1_clk_g),
3849         SH_PFC_PIN_GROUP(msiof1_sync_g),
3850         SH_PFC_PIN_GROUP(msiof1_ss1_g),
3851         SH_PFC_PIN_GROUP(msiof1_ss2_g),
3852         SH_PFC_PIN_GROUP(msiof1_txd_g),
3853         SH_PFC_PIN_GROUP(msiof1_rxd_g),
3854         SH_PFC_PIN_GROUP(msiof2_clk_a),
3855         SH_PFC_PIN_GROUP(msiof2_sync_a),
3856         SH_PFC_PIN_GROUP(msiof2_ss1_a),
3857         SH_PFC_PIN_GROUP(msiof2_ss2_a),
3858         SH_PFC_PIN_GROUP(msiof2_txd_a),
3859         SH_PFC_PIN_GROUP(msiof2_rxd_a),
3860         SH_PFC_PIN_GROUP(msiof2_clk_b),
3861         SH_PFC_PIN_GROUP(msiof2_sync_b),
3862         SH_PFC_PIN_GROUP(msiof2_ss1_b),
3863         SH_PFC_PIN_GROUP(msiof2_ss2_b),
3864         SH_PFC_PIN_GROUP(msiof2_txd_b),
3865         SH_PFC_PIN_GROUP(msiof2_rxd_b),
3866         SH_PFC_PIN_GROUP(msiof2_clk_c),
3867         SH_PFC_PIN_GROUP(msiof2_sync_c),
3868         SH_PFC_PIN_GROUP(msiof2_ss1_c),
3869         SH_PFC_PIN_GROUP(msiof2_ss2_c),
3870         SH_PFC_PIN_GROUP(msiof2_txd_c),
3871         SH_PFC_PIN_GROUP(msiof2_rxd_c),
3872         SH_PFC_PIN_GROUP(msiof2_clk_d),
3873         SH_PFC_PIN_GROUP(msiof2_sync_d),
3874         SH_PFC_PIN_GROUP(msiof2_ss1_d),
3875         SH_PFC_PIN_GROUP(msiof2_ss2_d),
3876         SH_PFC_PIN_GROUP(msiof2_txd_d),
3877         SH_PFC_PIN_GROUP(msiof2_rxd_d),
3878         SH_PFC_PIN_GROUP(msiof3_clk_a),
3879         SH_PFC_PIN_GROUP(msiof3_sync_a),
3880         SH_PFC_PIN_GROUP(msiof3_ss1_a),
3881         SH_PFC_PIN_GROUP(msiof3_ss2_a),
3882         SH_PFC_PIN_GROUP(msiof3_txd_a),
3883         SH_PFC_PIN_GROUP(msiof3_rxd_a),
3884         SH_PFC_PIN_GROUP(msiof3_clk_b),
3885         SH_PFC_PIN_GROUP(msiof3_sync_b),
3886         SH_PFC_PIN_GROUP(msiof3_ss1_b),
3887         SH_PFC_PIN_GROUP(msiof3_ss2_b),
3888         SH_PFC_PIN_GROUP(msiof3_txd_b),
3889         SH_PFC_PIN_GROUP(msiof3_rxd_b),
3890         SH_PFC_PIN_GROUP(msiof3_clk_c),
3891         SH_PFC_PIN_GROUP(msiof3_sync_c),
3892         SH_PFC_PIN_GROUP(msiof3_txd_c),
3893         SH_PFC_PIN_GROUP(msiof3_rxd_c),
3894         SH_PFC_PIN_GROUP(msiof3_clk_d),
3895         SH_PFC_PIN_GROUP(msiof3_sync_d),
3896         SH_PFC_PIN_GROUP(msiof3_ss1_d),
3897         SH_PFC_PIN_GROUP(msiof3_txd_d),
3898         SH_PFC_PIN_GROUP(msiof3_rxd_d),
3899         SH_PFC_PIN_GROUP(msiof3_clk_e),
3900         SH_PFC_PIN_GROUP(msiof3_sync_e),
3901         SH_PFC_PIN_GROUP(msiof3_ss1_e),
3902         SH_PFC_PIN_GROUP(msiof3_ss2_e),
3903         SH_PFC_PIN_GROUP(msiof3_txd_e),
3904         SH_PFC_PIN_GROUP(msiof3_rxd_e),
3905         SH_PFC_PIN_GROUP(pwm0),
3906         SH_PFC_PIN_GROUP(pwm1_a),
3907         SH_PFC_PIN_GROUP(pwm1_b),
3908         SH_PFC_PIN_GROUP(pwm2_a),
3909         SH_PFC_PIN_GROUP(pwm2_b),
3910         SH_PFC_PIN_GROUP(pwm3_a),
3911         SH_PFC_PIN_GROUP(pwm3_b),
3912         SH_PFC_PIN_GROUP(pwm4_a),
3913         SH_PFC_PIN_GROUP(pwm4_b),
3914         SH_PFC_PIN_GROUP(pwm5_a),
3915         SH_PFC_PIN_GROUP(pwm5_b),
3916         SH_PFC_PIN_GROUP(pwm6_a),
3917         SH_PFC_PIN_GROUP(pwm6_b),
3918         SH_PFC_PIN_GROUP(sata0_devslp_a),
3919         SH_PFC_PIN_GROUP(sata0_devslp_b),
3920         SH_PFC_PIN_GROUP(scif0_data),
3921         SH_PFC_PIN_GROUP(scif0_clk),
3922         SH_PFC_PIN_GROUP(scif0_ctrl),
3923         SH_PFC_PIN_GROUP(scif1_data_a),
3924         SH_PFC_PIN_GROUP(scif1_clk),
3925         SH_PFC_PIN_GROUP(scif1_ctrl),
3926         SH_PFC_PIN_GROUP(scif1_data_b),
3927         SH_PFC_PIN_GROUP(scif2_data_a),
3928         SH_PFC_PIN_GROUP(scif2_clk),
3929         SH_PFC_PIN_GROUP(scif2_data_b),
3930         SH_PFC_PIN_GROUP(scif3_data_a),
3931         SH_PFC_PIN_GROUP(scif3_clk),
3932         SH_PFC_PIN_GROUP(scif3_ctrl),
3933         SH_PFC_PIN_GROUP(scif3_data_b),
3934         SH_PFC_PIN_GROUP(scif4_data_a),
3935         SH_PFC_PIN_GROUP(scif4_clk_a),
3936         SH_PFC_PIN_GROUP(scif4_ctrl_a),
3937         SH_PFC_PIN_GROUP(scif4_data_b),
3938         SH_PFC_PIN_GROUP(scif4_clk_b),
3939         SH_PFC_PIN_GROUP(scif4_ctrl_b),
3940         SH_PFC_PIN_GROUP(scif4_data_c),
3941         SH_PFC_PIN_GROUP(scif4_clk_c),
3942         SH_PFC_PIN_GROUP(scif4_ctrl_c),
3943         SH_PFC_PIN_GROUP(scif5_data_a),
3944         SH_PFC_PIN_GROUP(scif5_clk_a),
3945         SH_PFC_PIN_GROUP(scif5_data_b),
3946         SH_PFC_PIN_GROUP(scif5_clk_b),
3947         SH_PFC_PIN_GROUP(scif_clk_a),
3948         SH_PFC_PIN_GROUP(scif_clk_b),
3949         SH_PFC_PIN_GROUP(sdhi0_data1),
3950         SH_PFC_PIN_GROUP(sdhi0_data4),
3951         SH_PFC_PIN_GROUP(sdhi0_ctrl),
3952         SH_PFC_PIN_GROUP(sdhi0_cd),
3953         SH_PFC_PIN_GROUP(sdhi0_wp),
3954         SH_PFC_PIN_GROUP(sdhi1_data1),
3955         SH_PFC_PIN_GROUP(sdhi1_data4),
3956         SH_PFC_PIN_GROUP(sdhi1_ctrl),
3957         SH_PFC_PIN_GROUP(sdhi1_cd),
3958         SH_PFC_PIN_GROUP(sdhi1_wp),
3959         SH_PFC_PIN_GROUP(sdhi2_data1),
3960         SH_PFC_PIN_GROUP(sdhi2_data4),
3961         SH_PFC_PIN_GROUP(sdhi2_data8),
3962         SH_PFC_PIN_GROUP(sdhi2_ctrl),
3963         SH_PFC_PIN_GROUP(sdhi2_cd_a),
3964         SH_PFC_PIN_GROUP(sdhi2_wp_a),
3965         SH_PFC_PIN_GROUP(sdhi2_cd_b),
3966         SH_PFC_PIN_GROUP(sdhi2_wp_b),
3967         SH_PFC_PIN_GROUP(sdhi2_ds),
3968         SH_PFC_PIN_GROUP(sdhi3_data1),
3969         SH_PFC_PIN_GROUP(sdhi3_data4),
3970         SH_PFC_PIN_GROUP(sdhi3_data8),
3971         SH_PFC_PIN_GROUP(sdhi3_ctrl),
3972         SH_PFC_PIN_GROUP(sdhi3_cd),
3973         SH_PFC_PIN_GROUP(sdhi3_wp),
3974         SH_PFC_PIN_GROUP(sdhi3_ds),
3975         SH_PFC_PIN_GROUP(ssi0_data),
3976         SH_PFC_PIN_GROUP(ssi01239_ctrl),
3977         SH_PFC_PIN_GROUP(ssi1_data_a),
3978         SH_PFC_PIN_GROUP(ssi1_data_b),
3979         SH_PFC_PIN_GROUP(ssi1_ctrl_a),
3980         SH_PFC_PIN_GROUP(ssi1_ctrl_b),
3981         SH_PFC_PIN_GROUP(ssi2_data_a),
3982         SH_PFC_PIN_GROUP(ssi2_data_b),
3983         SH_PFC_PIN_GROUP(ssi2_ctrl_a),
3984         SH_PFC_PIN_GROUP(ssi2_ctrl_b),
3985         SH_PFC_PIN_GROUP(ssi3_data),
3986         SH_PFC_PIN_GROUP(ssi349_ctrl),
3987         SH_PFC_PIN_GROUP(ssi4_data),
3988         SH_PFC_PIN_GROUP(ssi4_ctrl),
3989         SH_PFC_PIN_GROUP(ssi5_data),
3990         SH_PFC_PIN_GROUP(ssi5_ctrl),
3991         SH_PFC_PIN_GROUP(ssi6_data),
3992         SH_PFC_PIN_GROUP(ssi6_ctrl),
3993         SH_PFC_PIN_GROUP(ssi7_data),
3994         SH_PFC_PIN_GROUP(ssi78_ctrl),
3995         SH_PFC_PIN_GROUP(ssi8_data),
3996         SH_PFC_PIN_GROUP(ssi9_data_a),
3997         SH_PFC_PIN_GROUP(ssi9_data_b),
3998         SH_PFC_PIN_GROUP(ssi9_ctrl_a),
3999         SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4000         SH_PFC_PIN_GROUP(usb0),
4001         SH_PFC_PIN_GROUP(usb1),
4002         SH_PFC_PIN_GROUP(usb30),
4003 };
4004
4005 static const char * const audio_clk_groups[] = {
4006         "audio_clk_a_a",
4007         "audio_clk_a_b",
4008         "audio_clk_a_c",
4009         "audio_clk_b_a",
4010         "audio_clk_b_b",
4011         "audio_clk_c_a",
4012         "audio_clk_c_b",
4013         "audio_clkout_a",
4014         "audio_clkout_b",
4015         "audio_clkout_c",
4016         "audio_clkout_d",
4017         "audio_clkout1_a",
4018         "audio_clkout1_b",
4019         "audio_clkout2_a",
4020         "audio_clkout2_b",
4021         "audio_clkout3_a",
4022         "audio_clkout3_b",
4023 };
4024
4025 static const char * const avb_groups[] = {
4026         "avb_link",
4027         "avb_magic",
4028         "avb_phy_int",
4029         "avb_mdc",      /* Deprecated, please use "avb_mdio" instead */
4030         "avb_mdio",
4031         "avb_mii",
4032         "avb_avtp_pps",
4033         "avb_avtp_match_a",
4034         "avb_avtp_capture_a",
4035         "avb_avtp_match_b",
4036         "avb_avtp_capture_b",
4037 };
4038
4039 static const char * const du_groups[] = {
4040         "du_rgb666",
4041         "du_rgb888",
4042         "du_clk_out_0",
4043         "du_clk_out_1",
4044         "du_sync",
4045         "du_oddf",
4046         "du_cde",
4047         "du_disp",
4048 };
4049
4050 static const char * const hscif0_groups[] = {
4051         "hscif0_data",
4052         "hscif0_clk",
4053         "hscif0_ctrl",
4054 };
4055
4056 static const char * const hscif1_groups[] = {
4057         "hscif1_data_a",
4058         "hscif1_clk_a",
4059         "hscif1_ctrl_a",
4060         "hscif1_data_b",
4061         "hscif1_clk_b",
4062         "hscif1_ctrl_b",
4063 };
4064
4065 static const char * const hscif2_groups[] = {
4066         "hscif2_data_a",
4067         "hscif2_clk_a",
4068         "hscif2_ctrl_a",
4069         "hscif2_data_b",
4070         "hscif2_clk_b",
4071         "hscif2_ctrl_b",
4072         "hscif2_data_c",
4073         "hscif2_clk_c",
4074         "hscif2_ctrl_c",
4075 };
4076
4077 static const char * const hscif3_groups[] = {
4078         "hscif3_data_a",
4079         "hscif3_clk",
4080         "hscif3_ctrl",
4081         "hscif3_data_b",
4082         "hscif3_data_c",
4083         "hscif3_data_d",
4084 };
4085
4086 static const char * const hscif4_groups[] = {
4087         "hscif4_data_a",
4088         "hscif4_clk",
4089         "hscif4_ctrl",
4090         "hscif4_data_b",
4091 };
4092
4093 static const char * const i2c1_groups[] = {
4094         "i2c1_a",
4095         "i2c1_b",
4096 };
4097
4098 static const char * const i2c2_groups[] = {
4099         "i2c2_a",
4100         "i2c2_b",
4101 };
4102
4103 static const char * const i2c6_groups[] = {
4104         "i2c6_a",
4105         "i2c6_b",
4106         "i2c6_c",
4107 };
4108
4109 static const char * const intc_ex_groups[] = {
4110         "intc_ex_irq0",
4111         "intc_ex_irq1",
4112         "intc_ex_irq2",
4113         "intc_ex_irq3",
4114         "intc_ex_irq4",
4115         "intc_ex_irq5",
4116 };
4117
4118 static const char * const msiof0_groups[] = {
4119         "msiof0_clk",
4120         "msiof0_sync",
4121         "msiof0_ss1",
4122         "msiof0_ss2",
4123         "msiof0_txd",
4124         "msiof0_rxd",
4125 };
4126
4127 static const char * const msiof1_groups[] = {
4128         "msiof1_clk_a",
4129         "msiof1_sync_a",
4130         "msiof1_ss1_a",
4131         "msiof1_ss2_a",
4132         "msiof1_txd_a",
4133         "msiof1_rxd_a",
4134         "msiof1_clk_b",
4135         "msiof1_sync_b",
4136         "msiof1_ss1_b",
4137         "msiof1_ss2_b",
4138         "msiof1_txd_b",
4139         "msiof1_rxd_b",
4140         "msiof1_clk_c",
4141         "msiof1_sync_c",
4142         "msiof1_ss1_c",
4143         "msiof1_ss2_c",
4144         "msiof1_txd_c",
4145         "msiof1_rxd_c",
4146         "msiof1_clk_d",
4147         "msiof1_sync_d",
4148         "msiof1_ss1_d",
4149         "msiof1_ss2_d",
4150         "msiof1_txd_d",
4151         "msiof1_rxd_d",
4152         "msiof1_clk_e",
4153         "msiof1_sync_e",
4154         "msiof1_ss1_e",
4155         "msiof1_ss2_e",
4156         "msiof1_txd_e",
4157         "msiof1_rxd_e",
4158         "msiof1_clk_f",
4159         "msiof1_sync_f",
4160         "msiof1_ss1_f",
4161         "msiof1_ss2_f",
4162         "msiof1_txd_f",
4163         "msiof1_rxd_f",
4164         "msiof1_clk_g",
4165         "msiof1_sync_g",
4166         "msiof1_ss1_g",
4167         "msiof1_ss2_g",
4168         "msiof1_txd_g",
4169         "msiof1_rxd_g",
4170 };
4171
4172 static const char * const msiof2_groups[] = {
4173         "msiof2_clk_a",
4174         "msiof2_sync_a",
4175         "msiof2_ss1_a",
4176         "msiof2_ss2_a",
4177         "msiof2_txd_a",
4178         "msiof2_rxd_a",
4179         "msiof2_clk_b",
4180         "msiof2_sync_b",
4181         "msiof2_ss1_b",
4182         "msiof2_ss2_b",
4183         "msiof2_txd_b",
4184         "msiof2_rxd_b",
4185         "msiof2_clk_c",
4186         "msiof2_sync_c",
4187         "msiof2_ss1_c",
4188         "msiof2_ss2_c",
4189         "msiof2_txd_c",
4190         "msiof2_rxd_c",
4191         "msiof2_clk_d",
4192         "msiof2_sync_d",
4193         "msiof2_ss1_d",
4194         "msiof2_ss2_d",
4195         "msiof2_txd_d",
4196         "msiof2_rxd_d",
4197 };
4198
4199 static const char * const msiof3_groups[] = {
4200         "msiof3_clk_a",
4201         "msiof3_sync_a",
4202         "msiof3_ss1_a",
4203         "msiof3_ss2_a",
4204         "msiof3_txd_a",
4205         "msiof3_rxd_a",
4206         "msiof3_clk_b",
4207         "msiof3_sync_b",
4208         "msiof3_ss1_b",
4209         "msiof3_ss2_b",
4210         "msiof3_txd_b",
4211         "msiof3_rxd_b",
4212         "msiof3_clk_c",
4213         "msiof3_sync_c",
4214         "msiof3_txd_c",
4215         "msiof3_rxd_c",
4216         "msiof3_clk_d",
4217         "msiof3_sync_d",
4218         "msiof3_ss1_d",
4219         "msiof3_txd_d",
4220         "msiof3_rxd_d",
4221         "msiof3_clk_e",
4222         "msiof3_sync_e",
4223         "msiof3_ss1_e",
4224         "msiof3_ss2_e",
4225         "msiof3_txd_e",
4226         "msiof3_rxd_e",
4227 };
4228
4229 static const char * const pwm0_groups[] = {
4230         "pwm0",
4231 };
4232
4233 static const char * const pwm1_groups[] = {
4234         "pwm1_a",
4235         "pwm1_b",
4236 };
4237
4238 static const char * const pwm2_groups[] = {
4239         "pwm2_a",
4240         "pwm2_b",
4241 };
4242
4243 static const char * const pwm3_groups[] = {
4244         "pwm3_a",
4245         "pwm3_b",
4246 };
4247
4248 static const char * const pwm4_groups[] = {
4249         "pwm4_a",
4250         "pwm4_b",
4251 };
4252
4253 static const char * const pwm5_groups[] = {
4254         "pwm5_a",
4255         "pwm5_b",
4256 };
4257
4258 static const char * const pwm6_groups[] = {
4259         "pwm6_a",
4260         "pwm6_b",
4261 };
4262
4263 static const char * const sata0_groups[] = {
4264         "sata0_devslp_a",
4265         "sata0_devslp_b",
4266 };
4267
4268 static const char * const scif0_groups[] = {
4269         "scif0_data",
4270         "scif0_clk",
4271         "scif0_ctrl",
4272 };
4273
4274 static const char * const scif1_groups[] = {
4275         "scif1_data_a",
4276         "scif1_clk",
4277         "scif1_ctrl",
4278         "scif1_data_b",
4279 };
4280 static const char * const scif2_groups[] = {
4281         "scif2_data_a",
4282         "scif2_clk",
4283         "scif2_data_b",
4284 };
4285
4286 static const char * const scif3_groups[] = {
4287         "scif3_data_a",
4288         "scif3_clk",
4289         "scif3_ctrl",
4290         "scif3_data_b",
4291 };
4292
4293 static const char * const scif4_groups[] = {
4294         "scif4_data_a",
4295         "scif4_clk_a",
4296         "scif4_ctrl_a",
4297         "scif4_data_b",
4298         "scif4_clk_b",
4299         "scif4_ctrl_b",
4300         "scif4_data_c",
4301         "scif4_clk_c",
4302         "scif4_ctrl_c",
4303 };
4304
4305 static const char * const scif5_groups[] = {
4306         "scif5_data_a",
4307         "scif5_clk_a",
4308         "scif5_data_b",
4309         "scif5_clk_b",
4310 };
4311
4312 static const char * const scif_clk_groups[] = {
4313         "scif_clk_a",
4314         "scif_clk_b",
4315 };
4316
4317 static const char * const sdhi0_groups[] = {
4318         "sdhi0_data1",
4319         "sdhi0_data4",
4320         "sdhi0_ctrl",
4321         "sdhi0_cd",
4322         "sdhi0_wp",
4323 };
4324
4325 static const char * const sdhi1_groups[] = {
4326         "sdhi1_data1",
4327         "sdhi1_data4",
4328         "sdhi1_ctrl",
4329         "sdhi1_cd",
4330         "sdhi1_wp",
4331 };
4332
4333 static const char * const sdhi2_groups[] = {
4334         "sdhi2_data1",
4335         "sdhi2_data4",
4336         "sdhi2_data8",
4337         "sdhi2_ctrl",
4338         "sdhi2_cd_a",
4339         "sdhi2_wp_a",
4340         "sdhi2_cd_b",
4341         "sdhi2_wp_b",
4342         "sdhi2_ds",
4343 };
4344
4345 static const char * const sdhi3_groups[] = {
4346         "sdhi3_data1",
4347         "sdhi3_data4",
4348         "sdhi3_data8",
4349         "sdhi3_ctrl",
4350         "sdhi3_cd",
4351         "sdhi3_wp",
4352         "sdhi3_ds",
4353 };
4354
4355 static const char * const ssi_groups[] = {
4356         "ssi0_data",
4357         "ssi01239_ctrl",
4358         "ssi1_data_a",
4359         "ssi1_data_b",
4360         "ssi1_ctrl_a",
4361         "ssi1_ctrl_b",
4362         "ssi2_data_a",
4363         "ssi2_data_b",
4364         "ssi2_ctrl_a",
4365         "ssi2_ctrl_b",
4366         "ssi3_data",
4367         "ssi349_ctrl",
4368         "ssi4_data",
4369         "ssi4_ctrl",
4370         "ssi5_data",
4371         "ssi5_ctrl",
4372         "ssi6_data",
4373         "ssi6_ctrl",
4374         "ssi7_data",
4375         "ssi78_ctrl",
4376         "ssi8_data",
4377         "ssi9_data_a",
4378         "ssi9_data_b",
4379         "ssi9_ctrl_a",
4380         "ssi9_ctrl_b",
4381 };
4382
4383 static const char * const usb0_groups[] = {
4384         "usb0",
4385 };
4386
4387 static const char * const usb1_groups[] = {
4388         "usb1",
4389 };
4390
4391 static const char * const usb30_groups[] = {
4392         "usb30",
4393 };
4394
4395 static const struct sh_pfc_function pinmux_functions[] = {
4396         SH_PFC_FUNCTION(audio_clk),
4397         SH_PFC_FUNCTION(avb),
4398         SH_PFC_FUNCTION(du),
4399         SH_PFC_FUNCTION(hscif0),
4400         SH_PFC_FUNCTION(hscif1),
4401         SH_PFC_FUNCTION(hscif2),
4402         SH_PFC_FUNCTION(hscif3),
4403         SH_PFC_FUNCTION(hscif4),
4404         SH_PFC_FUNCTION(i2c1),
4405         SH_PFC_FUNCTION(i2c2),
4406         SH_PFC_FUNCTION(i2c6),
4407         SH_PFC_FUNCTION(intc_ex),
4408         SH_PFC_FUNCTION(msiof0),
4409         SH_PFC_FUNCTION(msiof1),
4410         SH_PFC_FUNCTION(msiof2),
4411         SH_PFC_FUNCTION(msiof3),
4412         SH_PFC_FUNCTION(pwm0),
4413         SH_PFC_FUNCTION(pwm1),
4414         SH_PFC_FUNCTION(pwm2),
4415         SH_PFC_FUNCTION(pwm3),
4416         SH_PFC_FUNCTION(pwm4),
4417         SH_PFC_FUNCTION(pwm5),
4418         SH_PFC_FUNCTION(pwm6),
4419         SH_PFC_FUNCTION(sata0),
4420         SH_PFC_FUNCTION(scif0),
4421         SH_PFC_FUNCTION(scif1),
4422         SH_PFC_FUNCTION(scif2),
4423         SH_PFC_FUNCTION(scif3),
4424         SH_PFC_FUNCTION(scif4),
4425         SH_PFC_FUNCTION(scif5),
4426         SH_PFC_FUNCTION(scif_clk),
4427         SH_PFC_FUNCTION(sdhi0),
4428         SH_PFC_FUNCTION(sdhi1),
4429         SH_PFC_FUNCTION(sdhi2),
4430         SH_PFC_FUNCTION(sdhi3),
4431         SH_PFC_FUNCTION(ssi),
4432         SH_PFC_FUNCTION(usb0),
4433         SH_PFC_FUNCTION(usb1),
4434         SH_PFC_FUNCTION(usb30),
4435 };
4436
4437 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4438 #define F_(x, y)        FN_##y
4439 #define FM(x)           FN_##x
4440         { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
4441                 0, 0,
4442                 0, 0,
4443                 0, 0,
4444                 0, 0,
4445                 0, 0,
4446                 0, 0,
4447                 0, 0,
4448                 0, 0,
4449                 0, 0,
4450                 0, 0,
4451                 0, 0,
4452                 0, 0,
4453                 0, 0,
4454                 0, 0,
4455                 0, 0,
4456                 0, 0,
4457                 GP_0_15_FN,     GPSR0_15,
4458                 GP_0_14_FN,     GPSR0_14,
4459                 GP_0_13_FN,     GPSR0_13,
4460                 GP_0_12_FN,     GPSR0_12,
4461                 GP_0_11_FN,     GPSR0_11,
4462                 GP_0_10_FN,     GPSR0_10,
4463                 GP_0_9_FN,      GPSR0_9,
4464                 GP_0_8_FN,      GPSR0_8,
4465                 GP_0_7_FN,      GPSR0_7,
4466                 GP_0_6_FN,      GPSR0_6,
4467                 GP_0_5_FN,      GPSR0_5,
4468                 GP_0_4_FN,      GPSR0_4,
4469                 GP_0_3_FN,      GPSR0_3,
4470                 GP_0_2_FN,      GPSR0_2,
4471                 GP_0_1_FN,      GPSR0_1,
4472                 GP_0_0_FN,      GPSR0_0, }
4473         },
4474         { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
4475                 0, 0,
4476                 0, 0,
4477                 0, 0,
4478                 GP_1_28_FN,     GPSR1_28,
4479                 GP_1_27_FN,     GPSR1_27,
4480                 GP_1_26_FN,     GPSR1_26,
4481                 GP_1_25_FN,     GPSR1_25,
4482                 GP_1_24_FN,     GPSR1_24,
4483                 GP_1_23_FN,     GPSR1_23,
4484                 GP_1_22_FN,     GPSR1_22,
4485                 GP_1_21_FN,     GPSR1_21,
4486                 GP_1_20_FN,     GPSR1_20,
4487                 GP_1_19_FN,     GPSR1_19,
4488                 GP_1_18_FN,     GPSR1_18,
4489                 GP_1_17_FN,     GPSR1_17,
4490                 GP_1_16_FN,     GPSR1_16,
4491                 GP_1_15_FN,     GPSR1_15,
4492                 GP_1_14_FN,     GPSR1_14,
4493                 GP_1_13_FN,     GPSR1_13,
4494                 GP_1_12_FN,     GPSR1_12,
4495                 GP_1_11_FN,     GPSR1_11,
4496                 GP_1_10_FN,     GPSR1_10,
4497                 GP_1_9_FN,      GPSR1_9,
4498                 GP_1_8_FN,      GPSR1_8,
4499                 GP_1_7_FN,      GPSR1_7,
4500                 GP_1_6_FN,      GPSR1_6,
4501                 GP_1_5_FN,      GPSR1_5,
4502                 GP_1_4_FN,      GPSR1_4,
4503                 GP_1_3_FN,      GPSR1_3,
4504                 GP_1_2_FN,      GPSR1_2,
4505                 GP_1_1_FN,      GPSR1_1,
4506                 GP_1_0_FN,      GPSR1_0, }
4507         },
4508         { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
4509                 0, 0,
4510                 0, 0,
4511                 0, 0,
4512                 0, 0,
4513                 0, 0,
4514                 0, 0,
4515                 0, 0,
4516                 0, 0,
4517                 0, 0,
4518                 0, 0,
4519                 0, 0,
4520                 0, 0,
4521                 0, 0,
4522                 0, 0,
4523                 0, 0,
4524                 0, 0,
4525                 0, 0,
4526                 GP_2_14_FN,     GPSR2_14,
4527                 GP_2_13_FN,     GPSR2_13,
4528                 GP_2_12_FN,     GPSR2_12,
4529                 GP_2_11_FN,     GPSR2_11,
4530                 GP_2_10_FN,     GPSR2_10,
4531                 GP_2_9_FN,      GPSR2_9,
4532                 GP_2_8_FN,      GPSR2_8,
4533                 GP_2_7_FN,      GPSR2_7,
4534                 GP_2_6_FN,      GPSR2_6,
4535                 GP_2_5_FN,      GPSR2_5,
4536                 GP_2_4_FN,      GPSR2_4,
4537                 GP_2_3_FN,      GPSR2_3,
4538                 GP_2_2_FN,      GPSR2_2,
4539                 GP_2_1_FN,      GPSR2_1,
4540                 GP_2_0_FN,      GPSR2_0, }
4541         },
4542         { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
4543                 0, 0,
4544                 0, 0,
4545                 0, 0,
4546                 0, 0,
4547                 0, 0,
4548                 0, 0,
4549                 0, 0,
4550                 0, 0,
4551                 0, 0,
4552                 0, 0,
4553                 0, 0,
4554                 0, 0,
4555                 0, 0,
4556                 0, 0,
4557                 0, 0,
4558                 0, 0,
4559                 GP_3_15_FN,     GPSR3_15,
4560                 GP_3_14_FN,     GPSR3_14,
4561                 GP_3_13_FN,     GPSR3_13,
4562                 GP_3_12_FN,     GPSR3_12,
4563                 GP_3_11_FN,     GPSR3_11,
4564                 GP_3_10_FN,     GPSR3_10,
4565                 GP_3_9_FN,      GPSR3_9,
4566                 GP_3_8_FN,      GPSR3_8,
4567                 GP_3_7_FN,      GPSR3_7,
4568                 GP_3_6_FN,      GPSR3_6,
4569                 GP_3_5_FN,      GPSR3_5,
4570                 GP_3_4_FN,      GPSR3_4,
4571                 GP_3_3_FN,      GPSR3_3,
4572                 GP_3_2_FN,      GPSR3_2,
4573                 GP_3_1_FN,      GPSR3_1,
4574                 GP_3_0_FN,      GPSR3_0, }
4575         },
4576         { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
4577                 0, 0,
4578                 0, 0,
4579                 0, 0,
4580                 0, 0,
4581                 0, 0,
4582                 0, 0,
4583                 0, 0,
4584                 0, 0,
4585                 0, 0,
4586                 0, 0,
4587                 0, 0,
4588                 0, 0,
4589                 0, 0,
4590                 0, 0,
4591                 GP_4_17_FN,     GPSR4_17,
4592                 GP_4_16_FN,     GPSR4_16,
4593                 GP_4_15_FN,     GPSR4_15,
4594                 GP_4_14_FN,     GPSR4_14,
4595                 GP_4_13_FN,     GPSR4_13,
4596                 GP_4_12_FN,     GPSR4_12,
4597                 GP_4_11_FN,     GPSR4_11,
4598                 GP_4_10_FN,     GPSR4_10,
4599                 GP_4_9_FN,      GPSR4_9,
4600                 GP_4_8_FN,      GPSR4_8,
4601                 GP_4_7_FN,      GPSR4_7,
4602                 GP_4_6_FN,      GPSR4_6,
4603                 GP_4_5_FN,      GPSR4_5,
4604                 GP_4_4_FN,      GPSR4_4,
4605                 GP_4_3_FN,      GPSR4_3,
4606                 GP_4_2_FN,      GPSR4_2,
4607                 GP_4_1_FN,      GPSR4_1,
4608                 GP_4_0_FN,      GPSR4_0, }
4609         },
4610         { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
4611                 0, 0,
4612                 0, 0,
4613                 0, 0,
4614                 0, 0,
4615                 0, 0,
4616                 0, 0,
4617                 GP_5_25_FN,     GPSR5_25,
4618                 GP_5_24_FN,     GPSR5_24,
4619                 GP_5_23_FN,     GPSR5_23,
4620                 GP_5_22_FN,     GPSR5_22,
4621                 GP_5_21_FN,     GPSR5_21,
4622                 GP_5_20_FN,     GPSR5_20,
4623                 GP_5_19_FN,     GPSR5_19,
4624                 GP_5_18_FN,     GPSR5_18,
4625                 GP_5_17_FN,     GPSR5_17,
4626                 GP_5_16_FN,     GPSR5_16,
4627                 GP_5_15_FN,     GPSR5_15,
4628                 GP_5_14_FN,     GPSR5_14,
4629                 GP_5_13_FN,     GPSR5_13,
4630                 GP_5_12_FN,     GPSR5_12,
4631                 GP_5_11_FN,     GPSR5_11,
4632                 GP_5_10_FN,     GPSR5_10,
4633                 GP_5_9_FN,      GPSR5_9,
4634                 GP_5_8_FN,      GPSR5_8,
4635                 GP_5_7_FN,      GPSR5_7,
4636                 GP_5_6_FN,      GPSR5_6,
4637                 GP_5_5_FN,      GPSR5_5,
4638                 GP_5_4_FN,      GPSR5_4,
4639                 GP_5_3_FN,      GPSR5_3,
4640                 GP_5_2_FN,      GPSR5_2,
4641                 GP_5_1_FN,      GPSR5_1,
4642                 GP_5_0_FN,      GPSR5_0, }
4643         },
4644         { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
4645                 GP_6_31_FN,     GPSR6_31,
4646                 GP_6_30_FN,     GPSR6_30,
4647                 GP_6_29_FN,     GPSR6_29,
4648                 GP_6_28_FN,     GPSR6_28,
4649                 GP_6_27_FN,     GPSR6_27,
4650                 GP_6_26_FN,     GPSR6_26,
4651                 GP_6_25_FN,     GPSR6_25,
4652                 GP_6_24_FN,     GPSR6_24,
4653                 GP_6_23_FN,     GPSR6_23,
4654                 GP_6_22_FN,     GPSR6_22,
4655                 GP_6_21_FN,     GPSR6_21,
4656                 GP_6_20_FN,     GPSR6_20,
4657                 GP_6_19_FN,     GPSR6_19,
4658                 GP_6_18_FN,     GPSR6_18,
4659                 GP_6_17_FN,     GPSR6_17,
4660                 GP_6_16_FN,     GPSR6_16,
4661                 GP_6_15_FN,     GPSR6_15,
4662                 GP_6_14_FN,     GPSR6_14,
4663                 GP_6_13_FN,     GPSR6_13,
4664                 GP_6_12_FN,     GPSR6_12,
4665                 GP_6_11_FN,     GPSR6_11,
4666                 GP_6_10_FN,     GPSR6_10,
4667                 GP_6_9_FN,      GPSR6_9,
4668                 GP_6_8_FN,      GPSR6_8,
4669                 GP_6_7_FN,      GPSR6_7,
4670                 GP_6_6_FN,      GPSR6_6,
4671                 GP_6_5_FN,      GPSR6_5,
4672                 GP_6_4_FN,      GPSR6_4,
4673                 GP_6_3_FN,      GPSR6_3,
4674                 GP_6_2_FN,      GPSR6_2,
4675                 GP_6_1_FN,      GPSR6_1,
4676                 GP_6_0_FN,      GPSR6_0, }
4677         },
4678         { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
4679                 0, 0,
4680                 0, 0,
4681                 0, 0,
4682                 0, 0,
4683                 0, 0,
4684                 0, 0,
4685                 0, 0,
4686                 0, 0,
4687                 0, 0,
4688                 0, 0,
4689                 0, 0,
4690                 0, 0,
4691                 0, 0,
4692                 0, 0,
4693                 0, 0,
4694                 0, 0,
4695                 0, 0,
4696                 0, 0,
4697                 0, 0,
4698                 0, 0,
4699                 0, 0,
4700                 0, 0,
4701                 0, 0,
4702                 0, 0,
4703                 0, 0,
4704                 0, 0,
4705                 0, 0,
4706                 0, 0,
4707                 GP_7_3_FN, GPSR7_3,
4708                 GP_7_2_FN, GPSR7_2,
4709                 GP_7_1_FN, GPSR7_1,
4710                 GP_7_0_FN, GPSR7_0, }
4711         },
4712 #undef F_
4713 #undef FM
4714
4715 #define F_(x, y)        x,
4716 #define FM(x)           FN_##x,
4717         { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
4718                 IP0_31_28
4719                 IP0_27_24
4720                 IP0_23_20
4721                 IP0_19_16
4722                 IP0_15_12
4723                 IP0_11_8
4724                 IP0_7_4
4725                 IP0_3_0 }
4726         },
4727         { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
4728                 IP1_31_28
4729                 IP1_27_24
4730                 IP1_23_20
4731                 IP1_19_16
4732                 IP1_15_12
4733                 IP1_11_8
4734                 IP1_7_4
4735                 IP1_3_0 }
4736         },
4737         { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
4738                 IP2_31_28
4739                 IP2_27_24
4740                 IP2_23_20
4741                 IP2_19_16
4742                 IP2_15_12
4743                 IP2_11_8
4744                 IP2_7_4
4745                 IP2_3_0 }
4746         },
4747         { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
4748                 IP3_31_28
4749                 IP3_27_24
4750                 IP3_23_20
4751                 IP3_19_16
4752                 IP3_15_12
4753                 IP3_11_8
4754                 IP3_7_4
4755                 IP3_3_0 }
4756         },
4757         { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
4758                 IP4_31_28
4759                 IP4_27_24
4760                 IP4_23_20
4761                 IP4_19_16
4762                 IP4_15_12
4763                 IP4_11_8
4764                 IP4_7_4
4765                 IP4_3_0 }
4766         },
4767         { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
4768                 IP5_31_28
4769                 IP5_27_24
4770                 IP5_23_20
4771                 IP5_19_16
4772                 IP5_15_12
4773                 IP5_11_8
4774                 IP5_7_4
4775                 IP5_3_0 }
4776         },
4777         { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
4778                 IP6_31_28
4779                 IP6_27_24
4780                 IP6_23_20
4781                 IP6_19_16
4782                 IP6_15_12
4783                 IP6_11_8
4784                 IP6_7_4
4785                 IP6_3_0 }
4786         },
4787         { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
4788                 IP7_31_28
4789                 IP7_27_24
4790                 IP7_23_20
4791                 IP7_19_16
4792                 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4793                 IP7_11_8
4794                 IP7_7_4
4795                 IP7_3_0 }
4796         },
4797         { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
4798                 IP8_31_28
4799                 IP8_27_24
4800                 IP8_23_20
4801                 IP8_19_16
4802                 IP8_15_12
4803                 IP8_11_8
4804                 IP8_7_4
4805                 IP8_3_0 }
4806         },
4807         { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
4808                 IP9_31_28
4809                 IP9_27_24
4810                 IP9_23_20
4811                 IP9_19_16
4812                 IP9_15_12
4813                 IP9_11_8
4814                 IP9_7_4
4815                 IP9_3_0 }
4816         },
4817         { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
4818                 IP10_31_28
4819                 IP10_27_24
4820                 IP10_23_20
4821                 IP10_19_16
4822                 IP10_15_12
4823                 IP10_11_8
4824                 IP10_7_4
4825                 IP10_3_0 }
4826         },
4827         { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
4828                 IP11_31_28
4829                 IP11_27_24
4830                 IP11_23_20
4831                 IP11_19_16
4832                 IP11_15_12
4833                 IP11_11_8
4834                 IP11_7_4
4835                 IP11_3_0 }
4836         },
4837         { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
4838                 IP12_31_28
4839                 IP12_27_24
4840                 IP12_23_20
4841                 IP12_19_16
4842                 IP12_15_12
4843                 IP12_11_8
4844                 IP12_7_4
4845                 IP12_3_0 }
4846         },
4847         { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
4848                 IP13_31_28
4849                 IP13_27_24
4850                 IP13_23_20
4851                 IP13_19_16
4852                 IP13_15_12
4853                 IP13_11_8
4854                 IP13_7_4
4855                 IP13_3_0 }
4856         },
4857         { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
4858                 IP14_31_28
4859                 IP14_27_24
4860                 IP14_23_20
4861                 IP14_19_16
4862                 IP14_15_12
4863                 IP14_11_8
4864                 IP14_7_4
4865                 IP14_3_0 }
4866         },
4867         { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
4868                 IP15_31_28
4869                 IP15_27_24
4870                 IP15_23_20
4871                 IP15_19_16
4872                 IP15_15_12
4873                 IP15_11_8
4874                 IP15_7_4
4875                 IP15_3_0 }
4876         },
4877         { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
4878                 IP16_31_28
4879                 IP16_27_24
4880                 IP16_23_20
4881                 IP16_19_16
4882                 IP16_15_12
4883                 IP16_11_8
4884                 IP16_7_4
4885                 IP16_3_0 }
4886         },
4887         { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
4888                 IP17_31_28
4889                 IP17_27_24
4890                 IP17_23_20
4891                 IP17_19_16
4892                 IP17_15_12
4893                 IP17_11_8
4894                 IP17_7_4
4895                 IP17_3_0 }
4896         },
4897         { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
4898                 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4899                 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4900                 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4901                 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4902                 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4903                 /* IP18_11_8  */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4904                 IP18_7_4
4905                 IP18_3_0 }
4906         },
4907 #undef F_
4908 #undef FM
4909
4910 #define F_(x, y)        x,
4911 #define FM(x)           FN_##x,
4912         { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
4913                              3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
4914                              1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
4915                 MOD_SEL0_31_30_29
4916                 MOD_SEL0_28_27
4917                 MOD_SEL0_26_25_24
4918                 MOD_SEL0_23
4919                 MOD_SEL0_22
4920                 MOD_SEL0_21
4921                 MOD_SEL0_20
4922                 MOD_SEL0_19
4923                 MOD_SEL0_18_17
4924                 MOD_SEL0_16
4925                 0, 0, /* RESERVED 15 */
4926                 MOD_SEL0_14_13
4927                 MOD_SEL0_12
4928                 MOD_SEL0_11
4929                 MOD_SEL0_10
4930                 MOD_SEL0_9_8
4931                 MOD_SEL0_7_6
4932                 MOD_SEL0_5
4933                 MOD_SEL0_4_3
4934                 /* RESERVED 2, 1, 0 */
4935                 0, 0, 0, 0, 0, 0, 0, 0 }
4936         },
4937         { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
4938                              2, 3, 1, 2, 3, 1, 1, 2, 1,
4939                              2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
4940                 MOD_SEL1_31_30
4941                 MOD_SEL1_29_28_27
4942                 MOD_SEL1_26
4943                 MOD_SEL1_25_24
4944                 MOD_SEL1_23_22_21
4945                 MOD_SEL1_20
4946                 MOD_SEL1_19
4947                 MOD_SEL1_18_17
4948                 MOD_SEL1_16
4949                 MOD_SEL1_15_14
4950                 MOD_SEL1_13
4951                 MOD_SEL1_12
4952                 MOD_SEL1_11
4953                 MOD_SEL1_10
4954                 MOD_SEL1_9
4955                 0, 0, 0, 0, /* RESERVED 8, 7 */
4956                 MOD_SEL1_6
4957                 MOD_SEL1_5
4958                 MOD_SEL1_4
4959                 MOD_SEL1_3
4960                 MOD_SEL1_2
4961                 MOD_SEL1_1
4962                 MOD_SEL1_0 }
4963         },
4964         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
4965                              1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
4966                              4, 4, 4, 3, 1) {
4967                 MOD_SEL2_31
4968                 MOD_SEL2_30
4969                 MOD_SEL2_29
4970                 MOD_SEL2_28_27
4971                 MOD_SEL2_26
4972                 MOD_SEL2_25_24_23
4973                 MOD_SEL2_22
4974                 MOD_SEL2_21
4975                 MOD_SEL2_20
4976                 MOD_SEL2_19
4977                 MOD_SEL2_18
4978                 MOD_SEL2_17
4979                 /* RESERVED 16 */
4980                 0, 0,
4981                 /* RESERVED 15, 14, 13, 12 */
4982                 0, 0, 0, 0, 0, 0, 0, 0,
4983                 0, 0, 0, 0, 0, 0, 0, 0,
4984                 /* RESERVED 11, 10, 9, 8 */
4985                 0, 0, 0, 0, 0, 0, 0, 0,
4986                 0, 0, 0, 0, 0, 0, 0, 0,
4987                 /* RESERVED 7, 6, 5, 4 */
4988                 0, 0, 0, 0, 0, 0, 0, 0,
4989                 0, 0, 0, 0, 0, 0, 0, 0,
4990                 /* RESERVED 3, 2, 1 */
4991                 0, 0, 0, 0, 0, 0, 0, 0,
4992                 MOD_SEL2_0 }
4993         },
4994         { },
4995 };
4996
4997 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
4998         { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
4999                 { PIN_NUMBER('W', 3),   28, 2 },        /* QSPI0_SPCLK */
5000                 { PIN_A_NUMBER('C', 5), 24, 2 },        /* QSPI0_MOSI_IO0 */
5001                 { PIN_A_NUMBER('B', 4), 20, 2 },        /* QSPI0_MISO_IO1 */
5002                 { PIN_NUMBER('Y', 6),   16, 2 },        /* QSPI0_IO2 */
5003                 { PIN_A_NUMBER('B', 6), 12, 2 },        /* QSPI0_IO3 */
5004                 { PIN_NUMBER('Y', 3),    8, 2 },        /* QSPI0_SSL */
5005                 { PIN_NUMBER('V', 3),    4, 2 },        /* QSPI1_SPCLK */
5006                 { PIN_A_NUMBER('C', 7),  0, 2 },        /* QSPI1_MOSI_IO0 */
5007         } },
5008         { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5009                 { PIN_A_NUMBER('E', 5), 28, 2 },        /* QSPI1_MISO_IO1 */
5010                 { PIN_A_NUMBER('E', 4), 24, 2 },        /* QSPI1_IO2 */
5011                 { PIN_A_NUMBER('C', 3), 20, 2 },        /* QSPI1_IO3 */
5012                 { PIN_NUMBER('V', 5),   16, 2 },        /* QSPI1_SSL */
5013                 { PIN_NUMBER('Y', 7),   12, 2 },        /* RPC_INT# */
5014                 { PIN_NUMBER('V', 6),    8, 2 },        /* RPC_WP# */
5015                 { PIN_NUMBER('V', 7),    4, 2 },        /* RPC_RESET# */
5016                 { PIN_NUMBER('A', 16),   0, 3 },        /* AVB_RX_CTL */
5017         } },
5018         { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5019                 { PIN_NUMBER('B', 19),  28, 3 },        /* AVB_RXC */
5020                 { PIN_NUMBER('A', 13),  24, 3 },        /* AVB_RD0 */
5021                 { PIN_NUMBER('B', 13),  20, 3 },        /* AVB_RD1 */
5022                 { PIN_NUMBER('A', 14),  16, 3 },        /* AVB_RD2 */
5023                 { PIN_NUMBER('B', 14),  12, 3 },        /* AVB_RD3 */
5024                 { PIN_NUMBER('A', 8),    8, 3 },        /* AVB_TX_CTL */
5025                 { PIN_NUMBER('A', 19),   4, 3 },        /* AVB_TXC */
5026                 { PIN_NUMBER('A', 18),   0, 3 },        /* AVB_TD0 */
5027         } },
5028         { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5029                 { PIN_NUMBER('B', 18),  28, 3 },        /* AVB_TD1 */
5030                 { PIN_NUMBER('A', 17),  24, 3 },        /* AVB_TD2 */
5031                 { PIN_NUMBER('B', 17),  20, 3 },        /* AVB_TD3 */
5032                 { PIN_NUMBER('A', 12),  16, 3 },        /* AVB_TXCREFCLK */
5033                 { PIN_NUMBER('A', 9),   12, 3 },        /* AVB_MDIO */
5034                 { RCAR_GP_PIN(2,  9),    8, 3 },        /* AVB_MDC */
5035                 { RCAR_GP_PIN(2, 10),    4, 3 },        /* AVB_MAGIC */
5036                 { RCAR_GP_PIN(2, 11),    0, 3 },        /* AVB_PHY_INT */
5037         } },
5038         { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5039                 { RCAR_GP_PIN(2, 12), 28, 3 },  /* AVB_LINK */
5040                 { RCAR_GP_PIN(2, 13), 24, 3 },  /* AVB_AVTP_MATCH */
5041                 { RCAR_GP_PIN(2, 14), 20, 3 },  /* AVB_AVTP_CAPTURE */
5042                 { RCAR_GP_PIN(2,  0), 16, 3 },  /* IRQ0 */
5043                 { RCAR_GP_PIN(2,  1), 12, 3 },  /* IRQ1 */
5044                 { RCAR_GP_PIN(2,  2),  8, 3 },  /* IRQ2 */
5045                 { RCAR_GP_PIN(2,  3),  4, 3 },  /* IRQ3 */
5046                 { RCAR_GP_PIN(2,  4),  0, 3 },  /* IRQ4 */
5047         } },
5048         { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5049                 { RCAR_GP_PIN(2,  5), 28, 3 },  /* IRQ5 */
5050                 { RCAR_GP_PIN(2,  6), 24, 3 },  /* PWM0 */
5051                 { RCAR_GP_PIN(2,  7), 20, 3 },  /* PWM1 */
5052                 { RCAR_GP_PIN(2,  8), 16, 3 },  /* PWM2 */
5053                 { RCAR_GP_PIN(1,  0), 12, 3 },  /* A0 */
5054                 { RCAR_GP_PIN(1,  1),  8, 3 },  /* A1 */
5055                 { RCAR_GP_PIN(1,  2),  4, 3 },  /* A2 */
5056                 { RCAR_GP_PIN(1,  3),  0, 3 },  /* A3 */
5057         } },
5058         { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5059                 { RCAR_GP_PIN(1,  4), 28, 3 },  /* A4 */
5060                 { RCAR_GP_PIN(1,  5), 24, 3 },  /* A5 */
5061                 { RCAR_GP_PIN(1,  6), 20, 3 },  /* A6 */
5062                 { RCAR_GP_PIN(1,  7), 16, 3 },  /* A7 */
5063                 { RCAR_GP_PIN(1,  8), 12, 3 },  /* A8 */
5064                 { RCAR_GP_PIN(1,  9),  8, 3 },  /* A9 */
5065                 { RCAR_GP_PIN(1, 10),  4, 3 },  /* A10 */
5066                 { RCAR_GP_PIN(1, 11),  0, 3 },  /* A11 */
5067         } },
5068         { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5069                 { RCAR_GP_PIN(1, 12), 28, 3 },  /* A12 */
5070                 { RCAR_GP_PIN(1, 13), 24, 3 },  /* A13 */
5071                 { RCAR_GP_PIN(1, 14), 20, 3 },  /* A14 */
5072                 { RCAR_GP_PIN(1, 15), 16, 3 },  /* A15 */
5073                 { RCAR_GP_PIN(1, 16), 12, 3 },  /* A16 */
5074                 { RCAR_GP_PIN(1, 17),  8, 3 },  /* A17 */
5075                 { RCAR_GP_PIN(1, 18),  4, 3 },  /* A18 */
5076                 { RCAR_GP_PIN(1, 19),  0, 3 },  /* A19 */
5077         } },
5078         { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5079                 { RCAR_GP_PIN(1, 28), 28, 3 },  /* CLKOUT */
5080                 { RCAR_GP_PIN(1, 20), 24, 3 },  /* CS0 */
5081                 { RCAR_GP_PIN(1, 21), 20, 3 },  /* CS1_A26 */
5082                 { RCAR_GP_PIN(1, 22), 16, 3 },  /* BS */
5083                 { RCAR_GP_PIN(1, 23), 12, 3 },  /* RD */
5084                 { RCAR_GP_PIN(1, 24),  8, 3 },  /* RD_WR */
5085                 { RCAR_GP_PIN(1, 25),  4, 3 },  /* WE0 */
5086                 { RCAR_GP_PIN(1, 26),  0, 3 },  /* WE1 */
5087         } },
5088         { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5089                 { RCAR_GP_PIN(1, 27), 28, 3 },  /* EX_WAIT0 */
5090                 { PIN_NUMBER('C', 1), 24, 3 },  /* PRESETOUT# */
5091                 { RCAR_GP_PIN(0,  0), 20, 3 },  /* D0 */
5092                 { RCAR_GP_PIN(0,  1), 16, 3 },  /* D1 */
5093                 { RCAR_GP_PIN(0,  2), 12, 3 },  /* D2 */
5094                 { RCAR_GP_PIN(0,  3),  8, 3 },  /* D3 */
5095                 { RCAR_GP_PIN(0,  4),  4, 3 },  /* D4 */
5096                 { RCAR_GP_PIN(0,  5),  0, 3 },  /* D5 */
5097         } },
5098         { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5099                 { RCAR_GP_PIN(0,  6), 28, 3 },  /* D6 */
5100                 { RCAR_GP_PIN(0,  7), 24, 3 },  /* D7 */
5101                 { RCAR_GP_PIN(0,  8), 20, 3 },  /* D8 */
5102                 { RCAR_GP_PIN(0,  9), 16, 3 },  /* D9 */
5103                 { RCAR_GP_PIN(0, 10), 12, 3 },  /* D10 */
5104                 { RCAR_GP_PIN(0, 11),  8, 3 },  /* D11 */
5105                 { RCAR_GP_PIN(0, 12),  4, 3 },  /* D12 */
5106                 { RCAR_GP_PIN(0, 13),  0, 3 },  /* D13 */
5107         } },
5108         { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5109                 { RCAR_GP_PIN(0, 14),   28, 3 },        /* D14 */
5110                 { RCAR_GP_PIN(0, 15),   24, 3 },        /* D15 */
5111                 { RCAR_GP_PIN(7,  0),   20, 3 },        /* AVS1 */
5112                 { RCAR_GP_PIN(7,  1),   16, 3 },        /* AVS2 */
5113                 { RCAR_GP_PIN(7,  2),   12, 3 },        /* HDMI0_CEC */
5114                 { RCAR_GP_PIN(7,  3),    8, 3 },        /* GP7_03 */
5115                 { PIN_A_NUMBER('P', 7),  4, 2 },        /* DU_DOTCLKIN0 */
5116                 { PIN_A_NUMBER('P', 8),  0, 2 },        /* DU_DOTCLKIN1 */
5117         } },
5118         { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5119                 { PIN_A_NUMBER('R', 8),  28, 2 },       /* DU_DOTCLKIN3 */
5120                 { PIN_A_NUMBER('D', 38), 20, 2 },       /* FSCLKST */
5121                 { PIN_A_NUMBER('R', 30),  4, 2 },       /* TMS */
5122         } },
5123         { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5124                 { PIN_A_NUMBER('T', 28), 28, 2 },       /* TDO */
5125                 { PIN_A_NUMBER('T', 30), 24, 2 },       /* ASEBRK */
5126                 { RCAR_GP_PIN(3,  0),    20, 3 },       /* SD0_CLK */
5127                 { RCAR_GP_PIN(3,  1),    16, 3 },       /* SD0_CMD */
5128                 { RCAR_GP_PIN(3,  2),    12, 3 },       /* SD0_DAT0 */
5129                 { RCAR_GP_PIN(3,  3),     8, 3 },       /* SD0_DAT1 */
5130                 { RCAR_GP_PIN(3,  4),     4, 3 },       /* SD0_DAT2 */
5131                 { RCAR_GP_PIN(3,  5),     0, 3 },       /* SD0_DAT3 */
5132         } },
5133         { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5134                 { RCAR_GP_PIN(3,  6), 28, 3 },  /* SD1_CLK */
5135                 { RCAR_GP_PIN(3,  7), 24, 3 },  /* SD1_CMD */
5136                 { RCAR_GP_PIN(3,  8), 20, 3 },  /* SD1_DAT0 */
5137                 { RCAR_GP_PIN(3,  9), 16, 3 },  /* SD1_DAT1 */
5138                 { RCAR_GP_PIN(3, 10), 12, 3 },  /* SD1_DAT2 */
5139                 { RCAR_GP_PIN(3, 11),  8, 3 },  /* SD1_DAT3 */
5140                 { RCAR_GP_PIN(4,  0),  4, 3 },  /* SD2_CLK */
5141                 { RCAR_GP_PIN(4,  1),  0, 3 },  /* SD2_CMD */
5142         } },
5143         { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5144                 { RCAR_GP_PIN(4,  2), 28, 3 },  /* SD2_DAT0 */
5145                 { RCAR_GP_PIN(4,  3), 24, 3 },  /* SD2_DAT1 */
5146                 { RCAR_GP_PIN(4,  4), 20, 3 },  /* SD2_DAT2 */
5147                 { RCAR_GP_PIN(4,  5), 16, 3 },  /* SD2_DAT3 */
5148                 { RCAR_GP_PIN(4,  6), 12, 3 },  /* SD2_DS */
5149                 { RCAR_GP_PIN(4,  7),  8, 3 },  /* SD3_CLK */
5150                 { RCAR_GP_PIN(4,  8),  4, 3 },  /* SD3_CMD */
5151                 { RCAR_GP_PIN(4,  9),  0, 3 },  /* SD3_DAT0 */
5152         } },
5153         { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5154                 { RCAR_GP_PIN(4, 10), 28, 3 },  /* SD3_DAT1 */
5155                 { RCAR_GP_PIN(4, 11), 24, 3 },  /* SD3_DAT2 */
5156                 { RCAR_GP_PIN(4, 12), 20, 3 },  /* SD3_DAT3 */
5157                 { RCAR_GP_PIN(4, 13), 16, 3 },  /* SD3_DAT4 */
5158                 { RCAR_GP_PIN(4, 14), 12, 3 },  /* SD3_DAT5 */
5159                 { RCAR_GP_PIN(4, 15),  8, 3 },  /* SD3_DAT6 */
5160                 { RCAR_GP_PIN(4, 16),  4, 3 },  /* SD3_DAT7 */
5161                 { RCAR_GP_PIN(4, 17),  0, 3 },  /* SD3_DS */
5162         } },
5163         { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5164                 { RCAR_GP_PIN(3, 12), 28, 3 },  /* SD0_CD */
5165                 { RCAR_GP_PIN(3, 13), 24, 3 },  /* SD0_WP */
5166                 { RCAR_GP_PIN(3, 14), 20, 3 },  /* SD1_CD */
5167                 { RCAR_GP_PIN(3, 15), 16, 3 },  /* SD1_WP */
5168                 { RCAR_GP_PIN(5,  0), 12, 3 },  /* SCK0 */
5169                 { RCAR_GP_PIN(5,  1),  8, 3 },  /* RX0 */
5170                 { RCAR_GP_PIN(5,  2),  4, 3 },  /* TX0 */
5171                 { RCAR_GP_PIN(5,  3),  0, 3 },  /* CTS0 */
5172         } },
5173         { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5174                 { RCAR_GP_PIN(5,  4), 28, 3 },  /* RTS0 */
5175                 { RCAR_GP_PIN(5,  5), 24, 3 },  /* RX1 */
5176                 { RCAR_GP_PIN(5,  6), 20, 3 },  /* TX1 */
5177                 { RCAR_GP_PIN(5,  7), 16, 3 },  /* CTS1 */
5178                 { RCAR_GP_PIN(5,  8), 12, 3 },  /* RTS1 */
5179                 { RCAR_GP_PIN(5,  9),  8, 3 },  /* SCK2 */
5180                 { RCAR_GP_PIN(5, 10),  4, 3 },  /* TX2 */
5181                 { RCAR_GP_PIN(5, 11),  0, 3 },  /* RX2 */
5182         } },
5183         { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5184                 { RCAR_GP_PIN(5, 12), 28, 3 },  /* HSCK0 */
5185                 { RCAR_GP_PIN(5, 13), 24, 3 },  /* HRX0 */
5186                 { RCAR_GP_PIN(5, 14), 20, 3 },  /* HTX0 */
5187                 { RCAR_GP_PIN(5, 15), 16, 3 },  /* HCTS0 */
5188                 { RCAR_GP_PIN(5, 16), 12, 3 },  /* HRTS0 */
5189                 { RCAR_GP_PIN(5, 17),  8, 3 },  /* MSIOF0_SCK */
5190                 { RCAR_GP_PIN(5, 18),  4, 3 },  /* MSIOF0_SYNC */
5191                 { RCAR_GP_PIN(5, 19),  0, 3 },  /* MSIOF0_SS1 */
5192         } },
5193         { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5194                 { RCAR_GP_PIN(5, 20), 28, 3 },  /* MSIOF0_TXD */
5195                 { RCAR_GP_PIN(5, 21), 24, 3 },  /* MSIOF0_SS2 */
5196                 { RCAR_GP_PIN(5, 22), 20, 3 },  /* MSIOF0_RXD */
5197                 { RCAR_GP_PIN(5, 23), 16, 3 },  /* MLB_CLK */
5198                 { RCAR_GP_PIN(5, 24), 12, 3 },  /* MLB_SIG */
5199                 { RCAR_GP_PIN(5, 25),  8, 3 },  /* MLB_DAT */
5200                 { PIN_NUMBER('H', 37),  4, 3 }, /* MLB_REF */
5201                 { RCAR_GP_PIN(6,  0),  0, 3 },  /* SSI_SCK01239 */
5202         } },
5203         { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5204                 { RCAR_GP_PIN(6,  1), 28, 3 },  /* SSI_WS01239 */
5205                 { RCAR_GP_PIN(6,  2), 24, 3 },  /* SSI_SDATA0 */
5206                 { RCAR_GP_PIN(6,  3), 20, 3 },  /* SSI_SDATA1 */
5207                 { RCAR_GP_PIN(6,  4), 16, 3 },  /* SSI_SDATA2 */
5208                 { RCAR_GP_PIN(6,  5), 12, 3 },  /* SSI_SCK349 */
5209                 { RCAR_GP_PIN(6,  6),  8, 3 },  /* SSI_WS349 */
5210                 { RCAR_GP_PIN(6,  7),  4, 3 },  /* SSI_SDATA3 */
5211                 { RCAR_GP_PIN(6,  8),  0, 3 },  /* SSI_SCK4 */
5212         } },
5213         { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5214                 { RCAR_GP_PIN(6,  9), 28, 3 },  /* SSI_WS4 */
5215                 { RCAR_GP_PIN(6, 10), 24, 3 },  /* SSI_SDATA4 */
5216                 { RCAR_GP_PIN(6, 11), 20, 3 },  /* SSI_SCK5 */
5217                 { RCAR_GP_PIN(6, 12), 16, 3 },  /* SSI_WS5 */
5218                 { RCAR_GP_PIN(6, 13), 12, 3 },  /* SSI_SDATA5 */
5219                 { RCAR_GP_PIN(6, 14),  8, 3 },  /* SSI_SCK6 */
5220                 { RCAR_GP_PIN(6, 15),  4, 3 },  /* SSI_WS6 */
5221                 { RCAR_GP_PIN(6, 16),  0, 3 },  /* SSI_SDATA6 */
5222         } },
5223         { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5224                 { RCAR_GP_PIN(6, 17), 28, 3 },  /* SSI_SCK78 */
5225                 { RCAR_GP_PIN(6, 18), 24, 3 },  /* SSI_WS78 */
5226                 { RCAR_GP_PIN(6, 19), 20, 3 },  /* SSI_SDATA7 */
5227                 { RCAR_GP_PIN(6, 20), 16, 3 },  /* SSI_SDATA8 */
5228                 { RCAR_GP_PIN(6, 21), 12, 3 },  /* SSI_SDATA9 */
5229                 { RCAR_GP_PIN(6, 22),  8, 3 },  /* AUDIO_CLKA */
5230                 { RCAR_GP_PIN(6, 23),  4, 3 },  /* AUDIO_CLKB */
5231                 { RCAR_GP_PIN(6, 24),  0, 3 },  /* USB0_PWEN */
5232         } },
5233         { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5234                 { RCAR_GP_PIN(6, 25), 28, 3 },  /* USB0_OVC */
5235                 { RCAR_GP_PIN(6, 26), 24, 3 },  /* USB1_PWEN */
5236                 { RCAR_GP_PIN(6, 27), 20, 3 },  /* USB1_OVC */
5237                 { RCAR_GP_PIN(6, 28), 16, 3 },  /* USB30_PWEN */
5238                 { RCAR_GP_PIN(6, 29), 12, 3 },  /* USB30_OVC */
5239                 { RCAR_GP_PIN(6, 30),  8, 3 },  /* GP6_30 */
5240                 { RCAR_GP_PIN(6, 31),  4, 3 },  /* GP6_31 */
5241         } },
5242         { },
5243 };
5244
5245 enum ioctrl_regs {
5246         POCCTRL,
5247 };
5248
5249 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5250         [POCCTRL] = { 0xe6060380, },
5251         { /* sentinel */ },
5252 };
5253
5254 static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5255 {
5256         int bit = -EINVAL;
5257
5258         *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5259
5260         if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5261                 bit = pin & 0x1f;
5262
5263         if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5264                 bit = (pin & 0x1f) + 12;
5265
5266         return bit;
5267 }
5268
5269 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5270         { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5271                 [ 0] = PIN_NUMBER('W', 3),      /* QSPI0_SPCLK */
5272                 [ 1] = PIN_A_NUMBER('C', 5),    /* QSPI0_MOSI_IO0 */
5273                 [ 2] = PIN_A_NUMBER('B', 4),    /* QSPI0_MISO_IO1 */
5274                 [ 3] = PIN_NUMBER('Y', 6),      /* QSPI0_IO2 */
5275                 [ 4] = PIN_A_NUMBER('B', 6),    /* QSPI0_IO3 */
5276                 [ 5] = PIN_NUMBER('Y', 3),      /* QSPI0_SSL */
5277                 [ 6] = PIN_NUMBER('V', 3),      /* QSPI1_SPCLK */
5278                 [ 7] = PIN_A_NUMBER('C', 7),    /* QSPI1_MOSI_IO0 */
5279                 [ 8] = PIN_A_NUMBER('E', 5),    /* QSPI1_MISO_IO1 */
5280                 [ 9] = PIN_A_NUMBER('E', 4),    /* QSPI1_IO2 */
5281                 [10] = PIN_A_NUMBER('C', 3),    /* QSPI1_IO3 */
5282                 [11] = PIN_NUMBER('V', 5),      /* QSPI1_SSL */
5283                 [12] = PIN_NUMBER('Y', 7),      /* RPC_INT# */
5284                 [13] = PIN_NUMBER('V', 6),      /* RPC_WP# */
5285                 [14] = PIN_NUMBER('V', 7),      /* RPC_RESET# */
5286                 [15] = PIN_NUMBER('A', 16),     /* AVB_RX_CTL */
5287                 [16] = PIN_NUMBER('B', 19),     /* AVB_RXC */
5288                 [17] = PIN_NUMBER('A', 13),     /* AVB_RD0 */
5289                 [18] = PIN_NUMBER('B', 13),     /* AVB_RD1 */
5290                 [19] = PIN_NUMBER('A', 14),     /* AVB_RD2 */
5291                 [20] = PIN_NUMBER('B', 14),     /* AVB_RD3 */
5292                 [21] = PIN_NUMBER('A', 8),      /* AVB_TX_CTL */
5293                 [22] = PIN_NUMBER('A', 19),     /* AVB_TXC */
5294                 [23] = PIN_NUMBER('A', 18),     /* AVB_TD0 */
5295                 [24] = PIN_NUMBER('B', 18),     /* AVB_TD1 */
5296                 [25] = PIN_NUMBER('A', 17),     /* AVB_TD2 */
5297                 [26] = PIN_NUMBER('B', 17),     /* AVB_TD3 */
5298                 [27] = PIN_NUMBER('A', 12),     /* AVB_TXCREFCLK */
5299                 [28] = PIN_NUMBER('A', 9),      /* AVB_MDIO */
5300                 [29] = RCAR_GP_PIN(2,  9),      /* AVB_MDC */
5301                 [30] = RCAR_GP_PIN(2, 10),      /* AVB_MAGIC */
5302                 [31] = RCAR_GP_PIN(2, 11),      /* AVB_PHY_INT */
5303         } },
5304         { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5305                 [ 0] = RCAR_GP_PIN(2, 12),      /* AVB_LINK */
5306                 [ 1] = RCAR_GP_PIN(2, 13),      /* AVB_AVTP_MATCH_A */
5307                 [ 2] = RCAR_GP_PIN(2, 14),      /* AVB_AVTP_CAPTURE_A */
5308                 [ 3] = RCAR_GP_PIN(2,  0),      /* IRQ0 */
5309                 [ 4] = RCAR_GP_PIN(2,  1),      /* IRQ1 */
5310                 [ 5] = RCAR_GP_PIN(2,  2),      /* IRQ2 */
5311                 [ 6] = RCAR_GP_PIN(2,  3),      /* IRQ3 */
5312                 [ 7] = RCAR_GP_PIN(2,  4),      /* IRQ4 */
5313                 [ 8] = RCAR_GP_PIN(2,  5),      /* IRQ5 */
5314                 [ 9] = RCAR_GP_PIN(2,  6),      /* PWM0 */
5315                 [10] = RCAR_GP_PIN(2,  7),      /* PWM1_A */
5316                 [11] = RCAR_GP_PIN(2,  8),      /* PWM2_A */
5317                 [12] = RCAR_GP_PIN(1,  0),      /* A0 */
5318                 [13] = RCAR_GP_PIN(1,  1),      /* A1 */
5319                 [14] = RCAR_GP_PIN(1,  2),      /* A2 */
5320                 [15] = RCAR_GP_PIN(1,  3),      /* A3 */
5321                 [16] = RCAR_GP_PIN(1,  4),      /* A4 */
5322                 [17] = RCAR_GP_PIN(1,  5),      /* A5 */
5323                 [18] = RCAR_GP_PIN(1,  6),      /* A6 */
5324                 [19] = RCAR_GP_PIN(1,  7),      /* A7 */
5325                 [20] = RCAR_GP_PIN(1,  8),      /* A8 */
5326                 [21] = RCAR_GP_PIN(1,  9),      /* A9 */
5327                 [22] = RCAR_GP_PIN(1, 10),      /* A10 */
5328                 [23] = RCAR_GP_PIN(1, 11),      /* A11 */
5329                 [24] = RCAR_GP_PIN(1, 12),      /* A12 */
5330                 [25] = RCAR_GP_PIN(1, 13),      /* A13 */
5331                 [26] = RCAR_GP_PIN(1, 14),      /* A14 */
5332                 [27] = RCAR_GP_PIN(1, 15),      /* A15 */
5333                 [28] = RCAR_GP_PIN(1, 16),      /* A16 */
5334                 [29] = RCAR_GP_PIN(1, 17),      /* A17 */
5335                 [30] = RCAR_GP_PIN(1, 18),      /* A18 */
5336                 [31] = RCAR_GP_PIN(1, 19),      /* A19 */
5337         } },
5338         { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5339                 [ 0] = RCAR_GP_PIN(1, 28),      /* CLKOUT */
5340                 [ 1] = RCAR_GP_PIN(1, 20),      /* CS0_N */
5341                 [ 2] = RCAR_GP_PIN(1, 21),      /* CS1_N */
5342                 [ 3] = RCAR_GP_PIN(1, 22),      /* BS_N */
5343                 [ 4] = RCAR_GP_PIN(1, 23),      /* RD_N */
5344                 [ 5] = RCAR_GP_PIN(1, 24),      /* RD_WR_N */
5345                 [ 6] = RCAR_GP_PIN(1, 25),      /* WE0_N */
5346                 [ 7] = RCAR_GP_PIN(1, 26),      /* WE1_N */
5347                 [ 8] = RCAR_GP_PIN(1, 27),      /* EX_WAIT0_A */
5348                 [ 9] = PIN_NUMBER('C', 1),      /* PRESETOUT# */
5349                 [10] = RCAR_GP_PIN(0,  0),      /* D0 */
5350                 [11] = RCAR_GP_PIN(0,  1),      /* D1 */
5351                 [12] = RCAR_GP_PIN(0,  2),      /* D2 */
5352                 [13] = RCAR_GP_PIN(0,  3),      /* D3 */
5353                 [14] = RCAR_GP_PIN(0,  4),      /* D4 */
5354                 [15] = RCAR_GP_PIN(0,  5),      /* D5 */
5355                 [16] = RCAR_GP_PIN(0,  6),      /* D6 */
5356                 [17] = RCAR_GP_PIN(0,  7),      /* D7 */
5357                 [18] = RCAR_GP_PIN(0,  8),      /* D8 */
5358                 [19] = RCAR_GP_PIN(0,  9),      /* D9 */
5359                 [20] = RCAR_GP_PIN(0, 10),      /* D10 */
5360                 [21] = RCAR_GP_PIN(0, 11),      /* D11 */
5361                 [22] = RCAR_GP_PIN(0, 12),      /* D12 */
5362                 [23] = RCAR_GP_PIN(0, 13),      /* D13 */
5363                 [24] = RCAR_GP_PIN(0, 14),      /* D14 */
5364                 [25] = RCAR_GP_PIN(0, 15),      /* D15 */
5365                 [26] = RCAR_GP_PIN(7,  0),      /* AVS1 */
5366                 [27] = RCAR_GP_PIN(7,  1),      /* AVS2 */
5367                 [28] = RCAR_GP_PIN(7,  2),      /* HDMI0_CEC */
5368                 [29] = RCAR_GP_PIN(7,  3),      /* GP7_03 */
5369                 [30] = PIN_A_NUMBER('P', 7),    /* DU_DOTCLKIN0 */
5370                 [31] = PIN_A_NUMBER('P', 8),    /* DU_DOTCLKIN1 */
5371         } },
5372         { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5373                 [ 0] = PIN_A_NUMBER('R', 8),    /* DU_DOTCLKIN2 */
5374                 [ 1] = PIN_NONE,
5375                 [ 2] = PIN_A_NUMBER('D', 38),   /* FSCLKST */
5376                 [ 3] = PIN_A_NUMBER('D', 39),   /* EXTALR*/
5377                 [ 4] = PIN_A_NUMBER('R', 26),   /* TRST# */
5378                 [ 5] = PIN_A_NUMBER('T', 27),   /* TCK */
5379                 [ 6] = PIN_A_NUMBER('R', 30),   /* TMS */
5380                 [ 7] = PIN_A_NUMBER('R', 29),   /* TDI */
5381                 [ 8] = PIN_NONE,
5382                 [ 9] = PIN_A_NUMBER('T', 30),   /* ASEBRK */
5383                 [10] = RCAR_GP_PIN(3,  0),      /* SD0_CLK */
5384                 [11] = RCAR_GP_PIN(3,  1),      /* SD0_CMD */
5385                 [12] = RCAR_GP_PIN(3,  2),      /* SD0_DAT0 */
5386                 [13] = RCAR_GP_PIN(3,  3),      /* SD0_DAT1 */
5387                 [14] = RCAR_GP_PIN(3,  4),      /* SD0_DAT2 */
5388                 [15] = RCAR_GP_PIN(3,  5),      /* SD0_DAT3 */
5389                 [16] = RCAR_GP_PIN(3,  6),      /* SD1_CLK */
5390                 [17] = RCAR_GP_PIN(3,  7),      /* SD1_CMD */
5391                 [18] = RCAR_GP_PIN(3,  8),      /* SD1_DAT0 */
5392                 [19] = RCAR_GP_PIN(3,  9),      /* SD1_DAT1 */
5393                 [20] = RCAR_GP_PIN(3, 10),      /* SD1_DAT2 */
5394                 [21] = RCAR_GP_PIN(3, 11),      /* SD1_DAT3 */
5395                 [22] = RCAR_GP_PIN(4,  0),      /* SD2_CLK */
5396                 [23] = RCAR_GP_PIN(4,  1),      /* SD2_CMD */
5397                 [24] = RCAR_GP_PIN(4,  2),      /* SD2_DAT0 */
5398                 [25] = RCAR_GP_PIN(4,  3),      /* SD2_DAT1 */
5399                 [26] = RCAR_GP_PIN(4,  4),      /* SD2_DAT2 */
5400                 [27] = RCAR_GP_PIN(4,  5),      /* SD2_DAT3 */
5401                 [28] = RCAR_GP_PIN(4,  6),      /* SD2_DS */
5402                 [29] = RCAR_GP_PIN(4,  7),      /* SD3_CLK */
5403                 [30] = RCAR_GP_PIN(4,  8),      /* SD3_CMD */
5404                 [31] = RCAR_GP_PIN(4,  9),      /* SD3_DAT0 */
5405         } },
5406         { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5407                 [ 0] = RCAR_GP_PIN(4, 10),      /* SD3_DAT1 */
5408                 [ 1] = RCAR_GP_PIN(4, 11),      /* SD3_DAT2 */
5409                 [ 2] = RCAR_GP_PIN(4, 12),      /* SD3_DAT3 */
5410                 [ 3] = RCAR_GP_PIN(4, 13),      /* SD3_DAT4 */
5411                 [ 4] = RCAR_GP_PIN(4, 14),      /* SD3_DAT5 */
5412                 [ 5] = RCAR_GP_PIN(4, 15),      /* SD3_DAT6 */
5413                 [ 6] = RCAR_GP_PIN(4, 16),      /* SD3_DAT7 */
5414                 [ 7] = RCAR_GP_PIN(4, 17),      /* SD3_DS */
5415                 [ 8] = RCAR_GP_PIN(3, 12),      /* SD0_CD */
5416                 [ 9] = RCAR_GP_PIN(3, 13),      /* SD0_WP */
5417                 [10] = RCAR_GP_PIN(3, 14),      /* SD1_CD */
5418                 [11] = RCAR_GP_PIN(3, 15),      /* SD1_WP */
5419                 [12] = RCAR_GP_PIN(5,  0),      /* SCK0 */
5420                 [13] = RCAR_GP_PIN(5,  1),      /* RX0 */
5421                 [14] = RCAR_GP_PIN(5,  2),      /* TX0 */
5422                 [15] = RCAR_GP_PIN(5,  3),      /* CTS0_N */
5423                 [16] = RCAR_GP_PIN(5,  4),      /* RTS0_N */
5424                 [17] = RCAR_GP_PIN(5,  5),      /* RX1_A */
5425                 [18] = RCAR_GP_PIN(5,  6),      /* TX1_A */
5426                 [19] = RCAR_GP_PIN(5,  7),      /* CTS1_N */
5427                 [20] = RCAR_GP_PIN(5,  8),      /* RTS1_N */
5428                 [21] = RCAR_GP_PIN(5,  9),      /* SCK2 */
5429                 [22] = RCAR_GP_PIN(5, 10),      /* TX2_A */
5430                 [23] = RCAR_GP_PIN(5, 11),      /* RX2_A */
5431                 [24] = RCAR_GP_PIN(5, 12),      /* HSCK0 */
5432                 [25] = RCAR_GP_PIN(5, 13),      /* HRX0 */
5433                 [26] = RCAR_GP_PIN(5, 14),      /* HTX0 */
5434                 [27] = RCAR_GP_PIN(5, 15),      /* HCTS0_N */
5435                 [28] = RCAR_GP_PIN(5, 16),      /* HRTS0_N */
5436                 [29] = RCAR_GP_PIN(5, 17),      /* MSIOF0_SCK */
5437                 [30] = RCAR_GP_PIN(5, 18),      /* MSIOF0_SYNC */
5438                 [31] = RCAR_GP_PIN(5, 19),      /* MSIOF0_SS1 */
5439         } },
5440         { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
5441                 [ 0] = RCAR_GP_PIN(5, 20),      /* MSIOF0_TXD */
5442                 [ 1] = RCAR_GP_PIN(5, 21),      /* MSIOF0_SS2 */
5443                 [ 2] = RCAR_GP_PIN(5, 22),      /* MSIOF0_RXD */
5444                 [ 3] = RCAR_GP_PIN(5, 23),      /* MLB_CLK */
5445                 [ 4] = RCAR_GP_PIN(5, 24),      /* MLB_SIG */
5446                 [ 5] = RCAR_GP_PIN(5, 25),      /* MLB_DAT */
5447                 [ 6] = PIN_NUMBER('H', 37),     /* MLB_REF */
5448                 [ 7] = RCAR_GP_PIN(6,  0),      /* SSI_SCK01239 */
5449                 [ 8] = RCAR_GP_PIN(6,  1),      /* SSI_WS01239 */
5450                 [ 9] = RCAR_GP_PIN(6,  2),      /* SSI_SDATA0 */
5451                 [10] = RCAR_GP_PIN(6,  3),      /* SSI_SDATA1_A */
5452                 [11] = RCAR_GP_PIN(6,  4),      /* SSI_SDATA2_A */
5453                 [12] = RCAR_GP_PIN(6,  5),      /* SSI_SCK349 */
5454                 [13] = RCAR_GP_PIN(6,  6),      /* SSI_WS349 */
5455                 [14] = RCAR_GP_PIN(6,  7),      /* SSI_SDATA3 */
5456                 [15] = RCAR_GP_PIN(6,  8),      /* SSI_SCK4 */
5457                 [16] = RCAR_GP_PIN(6,  9),      /* SSI_WS4 */
5458                 [17] = RCAR_GP_PIN(6, 10),      /* SSI_SDATA4 */
5459                 [18] = RCAR_GP_PIN(6, 11),      /* SSI_SCK5 */
5460                 [19] = RCAR_GP_PIN(6, 12),      /* SSI_WS5 */
5461                 [20] = RCAR_GP_PIN(6, 13),      /* SSI_SDATA5 */
5462                 [21] = RCAR_GP_PIN(6, 14),      /* SSI_SCK6 */
5463                 [22] = RCAR_GP_PIN(6, 15),      /* SSI_WS6 */
5464                 [23] = RCAR_GP_PIN(6, 16),      /* SSI_SDATA6 */
5465                 [24] = RCAR_GP_PIN(6, 17),      /* SSI_SCK78 */
5466                 [25] = RCAR_GP_PIN(6, 18),      /* SSI_WS78 */
5467                 [26] = RCAR_GP_PIN(6, 19),      /* SSI_SDATA7 */
5468                 [27] = RCAR_GP_PIN(6, 20),      /* SSI_SDATA8 */
5469                 [28] = RCAR_GP_PIN(6, 21),      /* SSI_SDATA9_A */
5470                 [29] = RCAR_GP_PIN(6, 22),      /* AUDIO_CLKA_A */
5471                 [30] = RCAR_GP_PIN(6, 23),      /* AUDIO_CLKB_B */
5472                 [31] = RCAR_GP_PIN(6, 24),      /* USB0_PWEN */
5473         } },
5474         { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
5475                 [ 0] = RCAR_GP_PIN(6, 25),      /* USB0_OVC */
5476                 [ 1] = RCAR_GP_PIN(6, 26),      /* USB1_PWEN */
5477                 [ 2] = RCAR_GP_PIN(6, 27),      /* USB1_OVC */
5478                 [ 3] = RCAR_GP_PIN(6, 28),      /* USB30_PWEN */
5479                 [ 4] = RCAR_GP_PIN(6, 29),      /* USB30_OVC */
5480                 [ 5] = RCAR_GP_PIN(6, 30),      /* GP6_30 */
5481                 [ 6] = RCAR_GP_PIN(6, 31),      /* GP6_31 */
5482                 [ 7] = PIN_NONE,
5483                 [ 8] = PIN_NONE,
5484                 [ 9] = PIN_NONE,
5485                 [10] = PIN_NONE,
5486                 [11] = PIN_NONE,
5487                 [12] = PIN_NONE,
5488                 [13] = PIN_NONE,
5489                 [14] = PIN_NONE,
5490                 [15] = PIN_NONE,
5491                 [16] = PIN_NONE,
5492                 [17] = PIN_NONE,
5493                 [18] = PIN_NONE,
5494                 [19] = PIN_NONE,
5495                 [20] = PIN_NONE,
5496                 [21] = PIN_NONE,
5497                 [22] = PIN_NONE,
5498                 [23] = PIN_NONE,
5499                 [24] = PIN_NONE,
5500                 [25] = PIN_NONE,
5501                 [26] = PIN_NONE,
5502                 [27] = PIN_NONE,
5503                 [28] = PIN_NONE,
5504                 [29] = PIN_NONE,
5505                 [30] = PIN_NONE,
5506                 [31] = PIN_NONE,
5507         } },
5508         { /* sentinel */ },
5509 };
5510
5511 static unsigned int r8a77965_pinmux_get_bias(struct sh_pfc *pfc,
5512                                             unsigned int pin)
5513 {
5514         const struct pinmux_bias_reg *reg;
5515         unsigned int bit;
5516
5517         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5518         if (!reg)
5519                 return PIN_CONFIG_BIAS_DISABLE;
5520
5521         if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
5522                 return PIN_CONFIG_BIAS_DISABLE;
5523         else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
5524                 return PIN_CONFIG_BIAS_PULL_UP;
5525         else
5526                 return PIN_CONFIG_BIAS_PULL_DOWN;
5527 }
5528
5529 static void r8a77965_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5530                                    unsigned int bias)
5531 {
5532         const struct pinmux_bias_reg *reg;
5533         u32 enable, updown;
5534         unsigned int bit;
5535
5536         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5537         if (!reg)
5538                 return;
5539
5540         enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
5541         if (bias != PIN_CONFIG_BIAS_DISABLE)
5542                 enable |= BIT(bit);
5543
5544         updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
5545         if (bias == PIN_CONFIG_BIAS_PULL_UP)
5546                 updown |= BIT(bit);
5547
5548         sh_pfc_write(pfc, reg->pud, updown);
5549         sh_pfc_write(pfc, reg->puen, enable);
5550 }
5551
5552 static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = {
5553         .pin_to_pocctrl = r8a77965_pin_to_pocctrl,
5554         .get_bias = r8a77965_pinmux_get_bias,
5555         .set_bias = r8a77965_pinmux_set_bias,
5556 };
5557
5558 const struct sh_pfc_soc_info r8a77965_pinmux_info = {
5559         .name = "r8a77965_pfc",
5560         .ops = &r8a77965_pinmux_ops,
5561         .unlock_reg = 0xe6060000, /* PMMR */
5562
5563         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5564
5565         .pins = pinmux_pins,
5566         .nr_pins = ARRAY_SIZE(pinmux_pins),
5567         .groups = pinmux_groups,
5568         .nr_groups = ARRAY_SIZE(pinmux_groups),
5569         .functions = pinmux_functions,
5570         .nr_functions = ARRAY_SIZE(pinmux_functions),
5571
5572         .cfg_regs = pinmux_config_regs,
5573         .drive_regs = pinmux_drive_regs,
5574         .bias_regs = pinmux_bias_regs,
5575         .ioctrl_regs = pinmux_ioctrl_regs,
5576
5577         .pinmux_data = pinmux_data,
5578         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5579 };