drivers/pinctrl/sunxi/pinctrl-sunxi.c

   1 /*
   2  * Allwinner A1X SoCs pinctrl driver.
   3  *
   4  * Copyright (C) 2012 Maxime Ripard
   5  *
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #include <linux/io.h>
  14 #include <linux/clk.h>
  15 #include <linux/gpio/driver.h>
  16 #include <linux/irqdomain.h>
  17 #include <linux/irqchip/chained_irq.h>
  18 #include <linux/export.h>
  19 #include <linux/of.h>
  20 #include <linux/of_clk.h>
  21 #include <linux/of_address.h>
  22 #include <linux/of_device.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/pinctrl/consumer.h>
  25 #include <linux/pinctrl/machine.h>
  26 #include <linux/pinctrl/pinctrl.h>
  27 #include <linux/pinctrl/pinconf-generic.h>
  28 #include <linux/pinctrl/pinmux.h>
  29 #include <linux/regulator/consumer.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/slab.h>
  32
  33 #include <dt-bindings/pinctrl/sun4i-a10.h>
  34
  35 #include "../core.h"
  36 #include "pinctrl-sunxi.h"
  37
  38 static struct irq_chip sunxi_pinctrl_edge_irq_chip;
  39 static struct irq_chip sunxi_pinctrl_level_irq_chip;
  40
  41 static struct sunxi_pinctrl_group *
  42 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
  43 {
  44         int i;
  45
  46         for (i = 0; i < pctl->ngroups; i++) {
  47                 struct sunxi_pinctrl_group *grp = pctl->groups + i;
  48
  49                 if (!strcmp(grp->name, group))
  50                         return grp;
  51         }
  52
  53         return NULL;
  54 }
  55
  56 static struct sunxi_pinctrl_function *
  57 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
  58                                     const char *name)
  59 {
  60         struct sunxi_pinctrl_function *func = pctl->functions;
  61         int i;
  62
  63         for (i = 0; i < pctl->nfunctions; i++) {
  64                 if (!func[i].name)
  65                         break;
  66
  67                 if (!strcmp(func[i].name, name))
  68                         return func + i;
  69         }
  70
  71         return NULL;
  72 }
  73
  74 static struct sunxi_desc_function *
  75 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
  76                                          const char *pin_name,
  77                                          const char *func_name)
  78 {
  79         int i;
  80
  81         for (i = 0; i < pctl->desc->npins; i++) {
  82                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
  83
  84                 if (!strcmp(pin->pin.name, pin_name)) {
  85                         struct sunxi_desc_function *func = pin->functions;
  86
  87                         while (func->name) {
  88                                 if (!strcmp(func->name, func_name) &&
  89                                         (!func->variant ||
  90                                         func->variant & pctl->variant))
  91                                         return func;
  92
  93                                 func++;
  94                         }
  95                 }
  96         }
  97
  98         return NULL;
  99 }
 100
 101 static struct sunxi_desc_function *
 102 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
 103                                         const u16 pin_num,
 104                                         const char *func_name)
 105 {
 106         int i;
 107
 108         for (i = 0; i < pctl->desc->npins; i++) {
 109                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
 110
 111                 if (pin->pin.number == pin_num) {
 112                         struct sunxi_desc_function *func = pin->functions;
 113
 114                         while (func->name) {
 115                                 if (!strcmp(func->name, func_name))
 116                                         return func;
 117
 118                                 func++;
 119                         }
 120                 }
 121         }
 122
 123         return NULL;
 124 }
 125
 126 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
 127 {
 128         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 129
 130         return pctl->ngroups;
 131 }
 132
 133 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
 134                                               unsigned group)
 135 {
 136         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 137
 138         return pctl->groups[group].name;
 139 }
 140
 141 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
 142                                       unsigned group,
 143                                       const unsigned **pins,
 144                                       unsigned *num_pins)
 145 {
 146         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 147
 148         *pins = (unsigned *)&pctl->groups[group].pin;
 149         *num_pins = 1;
 150
 151         return 0;
 152 }
 153
 154 static bool sunxi_pctrl_has_bias_prop(struct device_node *node)
 155 {
 156         return of_find_property(node, "bias-pull-up", NULL) ||
 157                 of_find_property(node, "bias-pull-down", NULL) ||
 158                 of_find_property(node, "bias-disable", NULL) ||
 159                 of_find_property(node, "allwinner,pull", NULL);
 160 }
 161
 162 static bool sunxi_pctrl_has_drive_prop(struct device_node *node)
 163 {
 164         return of_find_property(node, "drive-strength", NULL) ||
 165                 of_find_property(node, "allwinner,drive", NULL);
 166 }
 167
 168 static int sunxi_pctrl_parse_bias_prop(struct device_node *node)
 169 {
 170         u32 val;
 171
 172         /* Try the new style binding */
 173         if (of_find_property(node, "bias-pull-up", NULL))
 174                 return PIN_CONFIG_BIAS_PULL_UP;
 175
 176         if (of_find_property(node, "bias-pull-down", NULL))
 177                 return PIN_CONFIG_BIAS_PULL_DOWN;
 178
 179         if (of_find_property(node, "bias-disable", NULL))
 180                 return PIN_CONFIG_BIAS_DISABLE;
 181
 182         /* And fall back to the old binding */
 183         if (of_property_read_u32(node, "allwinner,pull", &val))
 184                 return -EINVAL;
 185
 186         switch (val) {
 187         case SUN4I_PINCTRL_NO_PULL:
 188                 return PIN_CONFIG_BIAS_DISABLE;
 189         case SUN4I_PINCTRL_PULL_UP:
 190                 return PIN_CONFIG_BIAS_PULL_UP;
 191         case SUN4I_PINCTRL_PULL_DOWN:
 192                 return PIN_CONFIG_BIAS_PULL_DOWN;
 193         }
 194
 195         return -EINVAL;
 196 }
 197
 198 static int sunxi_pctrl_parse_drive_prop(struct device_node *node)
 199 {
 200         u32 val;
 201
 202         /* Try the new style binding */
 203         if (!of_property_read_u32(node, "drive-strength", &val)) {
 204                 /* We can't go below 10mA ... */
 205                 if (val < 10)
 206                         return -EINVAL;
 207
 208                 /* ... and only up to 40 mA ... */
 209                 if (val > 40)
 210                         val = 40;
 211
 212                 /* by steps of 10 mA */
 213                 return rounddown(val, 10);
 214         }
 215
 216         /* And then fall back to the old binding */
 217         if (of_property_read_u32(node, "allwinner,drive", &val))
 218                 return -EINVAL;
 219
 220         return (val + 1) * 10;
 221 }
 222
 223 static const char *sunxi_pctrl_parse_function_prop(struct device_node *node)
 224 {
 225         const char *function;
 226         int ret;
 227
 228         /* Try the generic binding */
 229         ret = of_property_read_string(node, "function", &function);
 230         if (!ret)
 231                 return function;
 232
 233         /* And fall back to our legacy one */
 234         ret = of_property_read_string(node, "allwinner,function", &function);
 235         if (!ret)
 236                 return function;
 237
 238         return NULL;
 239 }
 240
 241 static const char *sunxi_pctrl_find_pins_prop(struct device_node *node,
 242                                               int *npins)
 243 {
 244         int count;
 245
 246         /* Try the generic binding */
 247         count = of_property_count_strings(node, "pins");
 248         if (count > 0) {
 249                 *npins = count;
 250                 return "pins";
 251         }
 252
 253         /* And fall back to our legacy one */
 254         count = of_property_count_strings(node, "allwinner,pins");
 255         if (count > 0) {
 256                 *npins = count;
 257                 return "allwinner,pins";
 258         }
 259
 260         return NULL;
 261 }
 262
 263 static unsigned long *sunxi_pctrl_build_pin_config(struct device_node *node,
 264                                                    unsigned int *len)
 265 {
 266         unsigned long *pinconfig;
 267         unsigned int configlen = 0, idx = 0;
 268         int ret;
 269
 270         if (sunxi_pctrl_has_drive_prop(node))
 271                 configlen++;
 272         if (sunxi_pctrl_has_bias_prop(node))
 273                 configlen++;
 274
 275         /*
 276          * If we don't have any configuration, bail out
 277          */
 278         if (!configlen)
 279                 return NULL;
 280
 281         pinconfig = kcalloc(configlen, sizeof(*pinconfig), GFP_KERNEL);
 282         if (!pinconfig)
 283                 return ERR_PTR(-ENOMEM);
 284
 285         if (sunxi_pctrl_has_drive_prop(node)) {
 286                 int drive = sunxi_pctrl_parse_drive_prop(node);
 287                 if (drive < 0) {
 288                         ret = drive;
 289                         goto err_free;
 290                 }
 291
 292                 pinconfig[idx++] = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
 293                                                           drive);
 294         }
 295
 296         if (sunxi_pctrl_has_bias_prop(node)) {
 297                 int pull = sunxi_pctrl_parse_bias_prop(node);
 298                 int arg = 0;
 299                 if (pull < 0) {
 300                         ret = pull;
 301                         goto err_free;
 302                 }
 303
 304                 if (pull != PIN_CONFIG_BIAS_DISABLE)
 305                         arg = 1; /* hardware uses weak pull resistors */
 306
 307                 pinconfig[idx++] = pinconf_to_config_packed(pull, arg);
 308         }
 309
 310
 311         *len = configlen;
 312         return pinconfig;
 313
 314 err_free:
 315         kfree(pinconfig);
 316         return ERR_PTR(ret);
 317 }
 318
 319 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
 320                                       struct device_node *node,
 321                                       struct pinctrl_map **map,
 322                                       unsigned *num_maps)
 323 {
 324         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 325         unsigned long *pinconfig;
 326         struct property *prop;
 327         const char *function, *pin_prop;
 328         const char *group;
 329         int ret, npins, nmaps, configlen = 0, i = 0;
 330
 331         *map = NULL;
 332         *num_maps = 0;
 333
 334         function = sunxi_pctrl_parse_function_prop(node);
 335         if (!function) {
 336                 dev_err(pctl->dev, "missing function property in node %pOFn\n",
 337                         node);
 338                 return -EINVAL;
 339         }
 340
 341         pin_prop = sunxi_pctrl_find_pins_prop(node, &npins);
 342         if (!pin_prop) {
 343                 dev_err(pctl->dev, "missing pins property in node %pOFn\n",
 344                         node);
 345                 return -EINVAL;
 346         }
 347
 348         /*
 349          * We have two maps for each pin: one for the function, one
 350          * for the configuration (bias, strength, etc).
 351          *
 352          * We might be slightly overshooting, since we might not have
 353          * any configuration.
 354          */
 355         nmaps = npins * 2;
 356         *map = kmalloc_array(nmaps, sizeof(struct pinctrl_map), GFP_KERNEL);
 357         if (!*map)
 358                 return -ENOMEM;
 359
 360         pinconfig = sunxi_pctrl_build_pin_config(node, &configlen);
 361         if (IS_ERR(pinconfig)) {
 362                 ret = PTR_ERR(pinconfig);
 363                 goto err_free_map;
 364         }
 365
 366         of_property_for_each_string(node, pin_prop, prop, group) {
 367                 struct sunxi_pinctrl_group *grp =
 368                         sunxi_pinctrl_find_group_by_name(pctl, group);
 369
 370                 if (!grp) {
 371                         dev_err(pctl->dev, "unknown pin %s", group);
 372                         continue;
 373                 }
 374
 375                 if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
 376                                                               grp->name,
 377                                                               function)) {
 378                         dev_err(pctl->dev, "unsupported function %s on pin %s",
 379                                 function, group);
 380                         continue;
 381                 }
 382
 383                 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
 384                 (*map)[i].data.mux.group = group;
 385                 (*map)[i].data.mux.function = function;
 386
 387                 i++;
 388
 389                 if (pinconfig) {
 390                         (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
 391                         (*map)[i].data.configs.group_or_pin = group;
 392                         (*map)[i].data.configs.configs = pinconfig;
 393                         (*map)[i].data.configs.num_configs = configlen;
 394                         i++;
 395                 }
 396         }
 397
 398         *num_maps = i;
 399
 400         /*
 401          * We know have the number of maps we need, we can resize our
 402          * map array
 403          */
 404         *map = krealloc(*map, i * sizeof(struct pinctrl_map), GFP_KERNEL);
 405         if (!*map)
 406                 return -ENOMEM;
 407
 408         return 0;
 409
 410 err_free_map:
 411         kfree(*map);
 412         *map = NULL;
 413         return ret;
 414 }
 415
 416 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
 417                                     struct pinctrl_map *map,
 418                                     unsigned num_maps)
 419 {
 420         int i;
 421
 422         /* pin config is never in the first map */
 423         for (i = 1; i < num_maps; i++) {
 424                 if (map[i].type != PIN_MAP_TYPE_CONFIGS_GROUP)
 425                         continue;
 426
 427                 /*
 428                  * All the maps share the same pin config,
 429                  * free only the first one we find.
 430                  */
 431                 kfree(map[i].data.configs.configs);
 432                 break;
 433         }
 434
 435         kfree(map);
 436 }
 437
 438 static const struct pinctrl_ops sunxi_pctrl_ops = {
 439         .dt_node_to_map         = sunxi_pctrl_dt_node_to_map,
 440         .dt_free_map            = sunxi_pctrl_dt_free_map,
 441         .get_groups_count       = sunxi_pctrl_get_groups_count,
 442         .get_group_name         = sunxi_pctrl_get_group_name,
 443         .get_group_pins         = sunxi_pctrl_get_group_pins,
 444 };
 445
 446 static int sunxi_pconf_reg(unsigned pin, enum pin_config_param param,
 447                            u32 *offset, u32 *shift, u32 *mask)
 448 {
 449         switch (param) {
 450         case PIN_CONFIG_DRIVE_STRENGTH:
 451                 *offset = sunxi_dlevel_reg(pin);
 452                 *shift = sunxi_dlevel_offset(pin);
 453                 *mask = DLEVEL_PINS_MASK;
 454                 break;
 455
 456         case PIN_CONFIG_BIAS_PULL_UP:
 457         case PIN_CONFIG_BIAS_PULL_DOWN:
 458         case PIN_CONFIG_BIAS_DISABLE:
 459                 *offset = sunxi_pull_reg(pin);
 460                 *shift = sunxi_pull_offset(pin);
 461                 *mask = PULL_PINS_MASK;
 462                 break;
 463
 464         default:
 465                 return -ENOTSUPP;
 466         }
 467
 468         return 0;
 469 }
 470
 471 static int sunxi_pconf_get(struct pinctrl_dev *pctldev, unsigned pin,
 472                            unsigned long *config)
 473 {
 474         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 475         enum pin_config_param param = pinconf_to_config_param(*config);
 476         u32 offset, shift, mask, val;
 477         u16 arg;
 478         int ret;
 479
 480         pin -= pctl->desc->pin_base;
 481
 482         ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask);
 483         if (ret < 0)
 484                 return ret;
 485
 486         val = (readl(pctl->membase + offset) >> shift) & mask;
 487
 488         switch (pinconf_to_config_param(*config)) {
 489         case PIN_CONFIG_DRIVE_STRENGTH:
 490                 arg = (val + 1) * 10;
 491                 break;
 492
 493         case PIN_CONFIG_BIAS_PULL_UP:
 494                 if (val != SUN4I_PINCTRL_PULL_UP)
 495                         return -EINVAL;
 496                 arg = 1; /* hardware is weak pull-up */
 497                 break;
 498
 499         case PIN_CONFIG_BIAS_PULL_DOWN:
 500                 if (val != SUN4I_PINCTRL_PULL_DOWN)
 501                         return -EINVAL;
 502                 arg = 1; /* hardware is weak pull-down */
 503                 break;
 504
 505         case PIN_CONFIG_BIAS_DISABLE:
 506                 if (val != SUN4I_PINCTRL_NO_PULL)
 507                         return -EINVAL;
 508                 arg = 0;
 509                 break;
 510
 511         default:
 512                 /* sunxi_pconf_reg should catch anything unsupported */
 513                 WARN_ON(1);
 514                 return -ENOTSUPP;
 515         }
 516
 517         *config = pinconf_to_config_packed(param, arg);
 518
 519         return 0;
 520 }
 521
 522 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
 523                                  unsigned group,
 524                                  unsigned long *config)
 525 {
 526         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 527         struct sunxi_pinctrl_group *g = &pctl->groups[group];
 528
 529         /* We only support 1 pin per group. Chain it to the pin callback */
 530         return sunxi_pconf_get(pctldev, g->pin, config);
 531 }
 532
 533 static int sunxi_pconf_set(struct pinctrl_dev *pctldev, unsigned pin,
 534                            unsigned long *configs, unsigned num_configs)
 535 {
 536         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 537         int i;
 538
 539         for (i = 0; i < num_configs; i++) {
 540                 enum pin_config_param param;
 541                 unsigned long flags;
 542                 u32 offset, shift, mask, reg;
 543                 u32 arg, val;
 544                 int ret;
 545
 546                 param = pinconf_to_config_param(configs[i]);
 547                 arg = pinconf_to_config_argument(configs[i]);
 548
 549                 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask);
 550                 if (ret < 0)
 551                         return ret;
 552
 553                 switch (param) {
 554                 case PIN_CONFIG_DRIVE_STRENGTH:
 555                         if (arg < 10 || arg > 40)
 556                                 return -EINVAL;
 557                         /*
 558                          * We convert from mA to what the register expects:
 559                          *   0: 10mA
 560                          *   1: 20mA
 561                          *   2: 30mA
 562                          *   3: 40mA
 563                          */
 564                         val = arg / 10 - 1;
 565                         break;
 566                 case PIN_CONFIG_BIAS_DISABLE:
 567                         val = 0;
 568                         break;
 569                 case PIN_CONFIG_BIAS_PULL_UP:
 570                         if (arg == 0)
 571                                 return -EINVAL;
 572                         val = 1;
 573                         break;
 574                 case PIN_CONFIG_BIAS_PULL_DOWN:
 575                         if (arg == 0)
 576                                 return -EINVAL;
 577                         val = 2;
 578                         break;
 579                 default:
 580                         /* sunxi_pconf_reg should catch anything unsupported */
 581                         WARN_ON(1);
 582                         return -ENOTSUPP;
 583                 }
 584
 585                 raw_spin_lock_irqsave(&pctl->lock, flags);
 586                 reg = readl(pctl->membase + offset);
 587                 reg &= ~(mask << shift);
 588                 writel(reg | val << shift, pctl->membase + offset);
 589                 raw_spin_unlock_irqrestore(&pctl->lock, flags);
 590         } /* for each config */
 591
 592         return 0;
 593 }
 594
 595 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
 596                                  unsigned long *configs, unsigned num_configs)
 597 {
 598         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 599         struct sunxi_pinctrl_group *g = &pctl->groups[group];
 600
 601         /* We only support 1 pin per group. Chain it to the pin callback */
 602         return sunxi_pconf_set(pctldev, g->pin, configs, num_configs);
 603 }
 604
 605 static const struct pinconf_ops sunxi_pconf_ops = {
 606         .is_generic             = true,
 607         .pin_config_get         = sunxi_pconf_get,
 608         .pin_config_set         = sunxi_pconf_set,
 609         .pin_config_group_get   = sunxi_pconf_group_get,
 610         .pin_config_group_set   = sunxi_pconf_group_set,
 611 };
 612
 613 static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
 614                                          unsigned pin,
 615                                          struct regulator *supply)
 616 {
 617         unsigned short bank = pin / PINS_PER_BANK;
 618         unsigned long flags;
 619         u32 val, reg;
 620         int uV;
 621
 622         if (!pctl->desc->io_bias_cfg_variant)
 623                 return 0;
 624
 625         uV = regulator_get_voltage(supply);
 626         if (uV < 0)
 627                 return uV;
 628
 629         /* Might be dummy regulator with no voltage set */
 630         if (uV == 0)
 631                 return 0;
 632
 633         switch (pctl->desc->io_bias_cfg_variant) {
 634         case BIAS_VOLTAGE_GRP_CONFIG:
 635                 /*
 636                  * Configured value must be equal or greater to actual
 637                  * voltage.
 638                  */
 639                 if (uV <= 1800000)
 640                         val = 0x0; /* 1.8V */
 641                 else if (uV <= 2500000)
 642                         val = 0x6; /* 2.5V */
 643                 else if (uV <= 2800000)
 644                         val = 0x9; /* 2.8V */
 645                 else if (uV <= 3000000)
 646                         val = 0xA; /* 3.0V */
 647                 else
 648                         val = 0xD; /* 3.3V */
 649
 650                 pin -= pctl->desc->pin_base;
 651
 652                 reg = readl(pctl->membase + sunxi_grp_config_reg(pin));
 653                 reg &= ~IO_BIAS_MASK;
 654                 writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));
 655                 return 0;
 656         case BIAS_VOLTAGE_PIO_POW_MODE_SEL:
 657                 val = uV <= 1800000 ? 1 : 0;
 658
 659                 raw_spin_lock_irqsave(&pctl->lock, flags);
 660                 reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG);
 661                 reg &= ~(1 << bank);
 662                 writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG);
 663                 raw_spin_unlock_irqrestore(&pctl->lock, flags);
 664                 return 0;
 665         default:
 666                 return -EINVAL;
 667         }
 668 }
 669
 670 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
 671 {
 672         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 673
 674         return pctl->nfunctions;
 675 }
 676
 677 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
 678                                            unsigned function)
 679 {
 680         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 681
 682         return pctl->functions[function].name;
 683 }
 684
 685 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
 686                                      unsigned function,
 687                                      const char * const **groups,
 688                                      unsigned * const num_groups)
 689 {
 690         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 691
 692         *groups = pctl->functions[function].groups;
 693         *num_groups = pctl->functions[function].ngroups;
 694
 695         return 0;
 696 }
 697
 698 static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
 699                                  unsigned pin,
 700                                  u8 config)
 701 {
 702         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 703         unsigned long flags;
 704         u32 val, mask;
 705
 706         raw_spin_lock_irqsave(&pctl->lock, flags);
 707
 708         pin -= pctl->desc->pin_base;
 709         val = readl(pctl->membase + sunxi_mux_reg(pin));
 710         mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
 711         writel((val & ~mask) | config << sunxi_mux_offset(pin),
 712                 pctl->membase + sunxi_mux_reg(pin));
 713
 714         raw_spin_unlock_irqrestore(&pctl->lock, flags);
 715 }
 716
 717 static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev,
 718                              unsigned function,
 719                              unsigned group)
 720 {
 721         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 722         struct sunxi_pinctrl_group *g = pctl->groups + group;
 723         struct sunxi_pinctrl_function *func = pctl->functions + function;
 724         struct sunxi_desc_function *desc =
 725                 sunxi_pinctrl_desc_find_function_by_name(pctl,
 726                                                          g->name,
 727                                                          func->name);
 728
 729         if (!desc)
 730                 return -EINVAL;
 731
 732         sunxi_pmx_set(pctldev, g->pin, desc->muxval);
 733
 734         return 0;
 735 }
 736
 737 static int
 738 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 739                         struct pinctrl_gpio_range *range,
 740                         unsigned offset,
 741                         bool input)
 742 {
 743         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 744         struct sunxi_desc_function *desc;
 745         const char *func;
 746
 747         if (input)
 748                 func = "gpio_in";
 749         else
 750                 func = "gpio_out";
 751
 752         desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
 753         if (!desc)
 754                 return -EINVAL;
 755
 756         sunxi_pmx_set(pctldev, offset, desc->muxval);
 757
 758         return 0;
 759 }
 760
 761 static int sunxi_pmx_request(struct pinctrl_dev *pctldev, unsigned offset)
 762 {
 763         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 764         unsigned short bank = offset / PINS_PER_BANK;
 765         unsigned short bank_offset = bank - pctl->desc->pin_base /
 766                                             PINS_PER_BANK;
 767         struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];
 768         struct regulator *reg = s_reg->regulator;
 769         char supply[16];
 770         int ret;
 771
 772         if (reg) {
 773                 refcount_inc(&s_reg->refcount);
 774                 return 0;
 775         }
 776
 777         snprintf(supply, sizeof(supply), "vcc-p%c", 'a' + bank);
 778         reg = regulator_get(pctl->dev, supply);
 779         if (IS_ERR(reg)) {
 780                 dev_err(pctl->dev, "Couldn't get bank P%c regulator\n",
 781                         'A' + bank);
 782                 return PTR_ERR(reg);
 783         }
 784
 785         ret = regulator_enable(reg);
 786         if (ret) {
 787                 dev_err(pctl->dev,
 788                         "Couldn't enable bank P%c regulator\n", 'A' + bank);
 789                 goto out;
 790         }
 791
 792         sunxi_pinctrl_set_io_bias_cfg(pctl, offset, reg);
 793
 794         s_reg->regulator = reg;
 795         refcount_set(&s_reg->refcount, 1);
 796
 797         return 0;
 798
 799 out:
 800         regulator_put(s_reg->regulator);
 801
 802         return ret;
 803 }
 804
 805 static int sunxi_pmx_free(struct pinctrl_dev *pctldev, unsigned offset)
 806 {
 807         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 808         unsigned short bank = offset / PINS_PER_BANK;
 809         unsigned short bank_offset = bank - pctl->desc->pin_base /
 810                                             PINS_PER_BANK;
 811         struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];
 812
 813         if (!refcount_dec_and_test(&s_reg->refcount))
 814                 return 0;
 815
 816         regulator_disable(s_reg->regulator);
 817         regulator_put(s_reg->regulator);
 818         s_reg->regulator = NULL;
 819
 820         return 0;
 821 }
 822
 823 static const struct pinmux_ops sunxi_pmx_ops = {
 824         .get_functions_count    = sunxi_pmx_get_funcs_cnt,
 825         .get_function_name      = sunxi_pmx_get_func_name,
 826         .get_function_groups    = sunxi_pmx_get_func_groups,
 827         .set_mux                = sunxi_pmx_set_mux,
 828         .gpio_set_direction     = sunxi_pmx_gpio_set_direction,
 829         .request                = sunxi_pmx_request,
 830         .free                   = sunxi_pmx_free,
 831         .strict                 = true,
 832 };
 833
 834 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
 835                                         unsigned offset)
 836 {
 837         return pinctrl_gpio_direction_input(chip->base + offset);
 838 }
 839
 840 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
 841 {
 842         struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
 843         u32 reg = sunxi_data_reg(offset);
 844         u8 index = sunxi_data_offset(offset);
 845         bool set_mux = pctl->desc->irq_read_needs_mux &&
 846                 gpiochip_line_is_irq(chip, offset);
 847         u32 pin = offset + chip->base;
 848         u32 val;
 849
 850         if (set_mux)
 851                 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
 852
 853         val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
 854
 855         if (set_mux)
 856                 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
 857
 858         return !!val;
 859 }
 860
 861 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
 862                                 unsigned offset, int value)
 863 {
 864         struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
 865         u32 reg = sunxi_data_reg(offset);
 866         u8 index = sunxi_data_offset(offset);
 867         unsigned long flags;
 868         u32 regval;
 869
 870         raw_spin_lock_irqsave(&pctl->lock, flags);
 871
 872         regval = readl(pctl->membase + reg);
 873
 874         if (value)
 875                 regval |= BIT(index);
 876         else
 877                 regval &= ~(BIT(index));
 878
 879         writel(regval, pctl->membase + reg);
 880
 881         raw_spin_unlock_irqrestore(&pctl->lock, flags);
 882 }
 883
 884 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
 885                                         unsigned offset, int value)
 886 {
 887         sunxi_pinctrl_gpio_set(chip, offset, value);
 888         return pinctrl_gpio_direction_output(chip->base + offset);
 889 }
 890
 891 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
 892                                 const struct of_phandle_args *gpiospec,
 893                                 u32 *flags)
 894 {
 895         int pin, base;
 896
 897         base = PINS_PER_BANK * gpiospec->args[0];
 898         pin = base + gpiospec->args[1];
 899
 900         if (pin > gc->ngpio)
 901                 return -EINVAL;
 902
 903         if (flags)
 904                 *flags = gpiospec->args[2];
 905
 906         return pin;
 907 }
 908
 909 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 910 {
 911         struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
 912         struct sunxi_desc_function *desc;
 913         unsigned pinnum = pctl->desc->pin_base + offset;
 914         unsigned irqnum;
 915
 916         if (offset >= chip->ngpio)
 917                 return -ENXIO;
 918
 919         desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq");
 920         if (!desc)
 921                 return -EINVAL;
 922
 923         irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum;
 924
 925         dev_dbg(chip->parent, "%s: request IRQ for GPIO %d, return %d\n",
 926                 chip->label, offset + chip->base, irqnum);
 927
 928         return irq_find_mapping(pctl->domain, irqnum);
 929 }
 930
 931 static int sunxi_pinctrl_irq_request_resources(struct irq_data *d)
 932 {
 933         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 934         struct sunxi_desc_function *func;
 935         int ret;
 936
 937         func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
 938                                         pctl->irq_array[d->hwirq], "irq");
 939         if (!func)
 940                 return -EINVAL;
 941
 942         ret = gpiochip_lock_as_irq(pctl->chip,
 943                         pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
 944         if (ret) {
 945                 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
 946                         irqd_to_hwirq(d));
 947                 return ret;
 948         }
 949
 950         /* Change muxing to INT mode */
 951         sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
 952
 953         return 0;
 954 }
 955
 956 static void sunxi_pinctrl_irq_release_resources(struct irq_data *d)
 957 {
 958         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 959
 960         gpiochip_unlock_as_irq(pctl->chip,
 961                               pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
 962 }
 963
 964 static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
 965 {
 966         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 967         u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq);
 968         u8 index = sunxi_irq_cfg_offset(d->hwirq);
 969         unsigned long flags;
 970         u32 regval;
 971         u8 mode;
 972
 973         switch (type) {
 974         case IRQ_TYPE_EDGE_RISING:
 975                 mode = IRQ_EDGE_RISING;
 976                 break;
 977         case IRQ_TYPE_EDGE_FALLING:
 978                 mode = IRQ_EDGE_FALLING;
 979                 break;
 980         case IRQ_TYPE_EDGE_BOTH:
 981                 mode = IRQ_EDGE_BOTH;
 982                 break;
 983         case IRQ_TYPE_LEVEL_HIGH:
 984                 mode = IRQ_LEVEL_HIGH;
 985                 break;
 986         case IRQ_TYPE_LEVEL_LOW:
 987                 mode = IRQ_LEVEL_LOW;
 988                 break;
 989         default:
 990                 return -EINVAL;
 991         }
 992
 993         raw_spin_lock_irqsave(&pctl->lock, flags);
 994
 995         if (type & IRQ_TYPE_LEVEL_MASK)
 996                 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip,
 997                                                  handle_fasteoi_irq, NULL);
 998         else
 999                 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip,
1000                                                  handle_edge_irq, NULL);
1001
1002         regval = readl(pctl->membase + reg);
1003         regval &= ~(IRQ_CFG_IRQ_MASK << index);
1004         writel(regval | (mode << index), pctl->membase + reg);
1005
1006         raw_spin_unlock_irqrestore(&pctl->lock, flags);
1007
1008         return 0;
1009 }
1010
1011 static void sunxi_pinctrl_irq_ack(struct irq_data *d)
1012 {
1013         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1014         u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq);
1015         u8 status_idx = sunxi_irq_status_offset(d->hwirq);
1016
1017         /* Clear the IRQ */
1018         writel(1 << status_idx, pctl->membase + status_reg);
1019 }
1020
1021 static void sunxi_pinctrl_irq_mask(struct irq_data *d)
1022 {
1023         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1024         u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
1025         u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
1026         unsigned long flags;
1027         u32 val;
1028
1029         raw_spin_lock_irqsave(&pctl->lock, flags);
1030
1031         /* Mask the IRQ */
1032         val = readl(pctl->membase + reg);
1033         writel(val & ~(1 << idx), pctl->membase + reg);
1034
1035         raw_spin_unlock_irqrestore(&pctl->lock, flags);
1036 }
1037
1038 static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
1039 {
1040         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1041         u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
1042         u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
1043         unsigned long flags;
1044         u32 val;
1045
1046         raw_spin_lock_irqsave(&pctl->lock, flags);
1047
1048         /* Unmask the IRQ */
1049         val = readl(pctl->membase + reg);
1050         writel(val | (1 << idx), pctl->membase + reg);
1051
1052         raw_spin_unlock_irqrestore(&pctl->lock, flags);
1053 }
1054
1055 static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d)
1056 {
1057         sunxi_pinctrl_irq_ack(d);
1058         sunxi_pinctrl_irq_unmask(d);
1059 }
1060
1061 static struct irq_chip sunxi_pinctrl_edge_irq_chip = {
1062         .name           = "sunxi_pio_edge",
1063         .irq_ack        = sunxi_pinctrl_irq_ack,
1064         .irq_mask       = sunxi_pinctrl_irq_mask,
1065         .irq_unmask     = sunxi_pinctrl_irq_unmask,
1066         .irq_request_resources = sunxi_pinctrl_irq_request_resources,
1067         .irq_release_resources = sunxi_pinctrl_irq_release_resources,
1068         .irq_set_type   = sunxi_pinctrl_irq_set_type,
1069         .flags          = IRQCHIP_SKIP_SET_WAKE,
1070 };
1071
1072 static struct irq_chip sunxi_pinctrl_level_irq_chip = {
1073         .name           = "sunxi_pio_level",
1074         .irq_eoi        = sunxi_pinctrl_irq_ack,
1075         .irq_mask       = sunxi_pinctrl_irq_mask,
1076         .irq_unmask     = sunxi_pinctrl_irq_unmask,
1077         /* Define irq_enable / disable to avoid spurious irqs for drivers
1078          * using these to suppress irqs while they clear the irq source */
1079         .irq_enable     = sunxi_pinctrl_irq_ack_unmask,
1080         .irq_disable    = sunxi_pinctrl_irq_mask,
1081         .irq_request_resources = sunxi_pinctrl_irq_request_resources,
1082         .irq_release_resources = sunxi_pinctrl_irq_release_resources,
1083         .irq_set_type   = sunxi_pinctrl_irq_set_type,
1084         .flags          = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_EOI_THREADED |
1085                           IRQCHIP_EOI_IF_HANDLED,
1086 };
1087
1088 static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d,
1089                                       struct device_node *node,
1090                                       const u32 *intspec,
1091                                       unsigned int intsize,
1092                                       unsigned long *out_hwirq,
1093                                       unsigned int *out_type)
1094 {
1095         struct sunxi_pinctrl *pctl = d->host_data;
1096         struct sunxi_desc_function *desc;
1097         int pin, base;
1098
1099         if (intsize < 3)
1100                 return -EINVAL;
1101
1102         base = PINS_PER_BANK * intspec[0];
1103         pin = pctl->desc->pin_base + base + intspec[1];
1104
1105         desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq");
1106         if (!desc)
1107                 return -EINVAL;
1108
1109         *out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum;
1110         *out_type = intspec[2];
1111
1112         return 0;
1113 }
1114
1115 static const struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = {
1116         .xlate          = sunxi_pinctrl_irq_of_xlate,
1117 };
1118
1119 static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
1120 {
1121         unsigned int irq = irq_desc_get_irq(desc);
1122         struct irq_chip *chip = irq_desc_get_chip(desc);
1123         struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc);
1124         unsigned long bank, reg, val;
1125
1126         for (bank = 0; bank < pctl->desc->irq_banks; bank++)
1127                 if (irq == pctl->irq[bank])
1128                         break;
1129
1130         if (bank == pctl->desc->irq_banks)
1131                 return;
1132
1133         reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank);
1134         val = readl(pctl->membase + reg);
1135
1136         if (val) {
1137                 int irqoffset;
1138
1139                 chained_irq_enter(chip, desc);
1140                 for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) {
1141                         int pin_irq = irq_find_mapping(pctl->domain,
1142                                                        bank * IRQ_PER_BANK + irqoffset);
1143                         generic_handle_irq(pin_irq);
1144                 }
1145                 chained_irq_exit(chip, desc);
1146         }
1147 }
1148
1149 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
1150                                         const char *name)
1151 {
1152         struct sunxi_pinctrl_function *func = pctl->functions;
1153
1154         while (func->name) {
1155                 /* function already there */
1156                 if (strcmp(func->name, name) == 0) {
1157                         func->ngroups++;
1158                         return -EEXIST;
1159                 }
1160                 func++;
1161         }
1162
1163         func->name = name;
1164         func->ngroups = 1;
1165
1166         pctl->nfunctions++;
1167
1168         return 0;
1169 }
1170
1171 static int sunxi_pinctrl_build_state(struct platform_device *pdev)
1172 {
1173         struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
1174         void *ptr;
1175         int i;
1176
1177         /*
1178          * Allocate groups
1179          *
1180          * We assume that the number of groups is the number of pins
1181          * given in the data array.
1182
1183          * This will not always be true, since some pins might not be
1184          * available in the current variant, but fortunately for us,
1185          * this means that the number of pins is the maximum group
1186          * number we will ever see.
1187          */
1188         pctl->groups = devm_kcalloc(&pdev->dev,
1189                                     pctl->desc->npins, sizeof(*pctl->groups),
1190                                     GFP_KERNEL);
1191         if (!pctl->groups)
1192                 return -ENOMEM;
1193
1194         for (i = 0; i < pctl->desc->npins; i++) {
1195                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1196                 struct sunxi_pinctrl_group *group = pctl->groups + pctl->ngroups;
1197
1198                 if (pin->variant && !(pctl->variant & pin->variant))
1199                         continue;
1200
1201                 group->name = pin->pin.name;
1202                 group->pin = pin->pin.number;
1203
1204                 /* And now we count the actual number of pins / groups */
1205                 pctl->ngroups++;
1206         }
1207
1208         /*
1209          * We suppose that we won't have any more functions than pins,
1210          * we'll reallocate that later anyway
1211          */
1212         pctl->functions = kcalloc(pctl->ngroups,
1213                                   sizeof(*pctl->functions),
1214                                   GFP_KERNEL);
1215         if (!pctl->functions)
1216                 return -ENOMEM;
1217
1218         /* Count functions and their associated groups */
1219         for (i = 0; i < pctl->desc->npins; i++) {
1220                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1221                 struct sunxi_desc_function *func;
1222
1223                 if (pin->variant && !(pctl->variant & pin->variant))
1224                         continue;
1225
1226                 for (func = pin->functions; func->name; func++) {
1227                         if (func->variant && !(pctl->variant & func->variant))
1228                                 continue;
1229
1230                         /* Create interrupt mapping while we're at it */
1231                         if (!strcmp(func->name, "irq")) {
1232                                 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK;
1233                                 pctl->irq_array[irqnum] = pin->pin.number;
1234                         }
1235
1236                         sunxi_pinctrl_add_function(pctl, func->name);
1237                 }
1238         }
1239
1240         /* And now allocated and fill the array for real */
1241         ptr = krealloc(pctl->functions,
1242                        pctl->nfunctions * sizeof(*pctl->functions),
1243                        GFP_KERNEL);
1244         if (!ptr) {
1245                 kfree(pctl->functions);
1246                 pctl->functions = NULL;
1247                 return -ENOMEM;
1248         }
1249         pctl->functions = ptr;
1250
1251         for (i = 0; i < pctl->desc->npins; i++) {
1252                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1253                 struct sunxi_desc_function *func;
1254
1255                 if (pin->variant && !(pctl->variant & pin->variant))
1256                         continue;
1257
1258                 for (func = pin->functions; func->name; func++) {
1259                         struct sunxi_pinctrl_function *func_item;
1260                         const char **func_grp;
1261
1262                         if (func->variant && !(pctl->variant & func->variant))
1263                                 continue;
1264
1265                         func_item = sunxi_pinctrl_find_function_by_name(pctl,
1266                                                                         func->name);
1267                         if (!func_item) {
1268                                 kfree(pctl->functions);
1269                                 return -EINVAL;
1270                         }
1271
1272                         if (!func_item->groups) {
1273                                 func_item->groups =
1274                                         devm_kcalloc(&pdev->dev,
1275                                                      func_item->ngroups,
1276                                                      sizeof(*func_item->groups),
1277                                                      GFP_KERNEL);
1278                                 if (!func_item->groups) {
1279                                         kfree(pctl->functions);
1280                                         return -ENOMEM;
1281                                 }
1282                         }
1283
1284                         func_grp = func_item->groups;
1285                         while (*func_grp)
1286                                 func_grp++;
1287
1288                         *func_grp = pin->pin.name;
1289                 }
1290         }
1291
1292         return 0;
1293 }
1294
1295 static int sunxi_pinctrl_get_debounce_div(struct clk *clk, int freq, int *diff)
1296 {
1297         unsigned long clock = clk_get_rate(clk);
1298         unsigned int best_diff, best_div;
1299         int i;
1300
1301         best_diff = abs(freq - clock);
1302         best_div = 0;
1303
1304         for (i = 1; i < 8; i++) {
1305                 int cur_diff = abs(freq - (clock >> i));
1306
1307                 if (cur_diff < best_diff) {
1308                         best_diff = cur_diff;
1309                         best_div = i;
1310                 }
1311         }
1312
1313         *diff = best_diff;
1314         return best_div;
1315 }
1316
1317 static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,
1318                                         struct device_node *node)
1319 {
1320         unsigned int hosc_diff, losc_diff;
1321         unsigned int hosc_div, losc_div;
1322         struct clk *hosc, *losc;
1323         u8 div, src;
1324         int i, ret;
1325
1326         /* Deal with old DTs that didn't have the oscillators */
1327         if (of_clk_get_parent_count(node) != 3)
1328                 return 0;
1329
1330         /* If we don't have any setup, bail out */
1331         if (!of_find_property(node, "input-debounce", NULL))
1332                 return 0;
1333
1334         losc = devm_clk_get(pctl->dev, "losc");
1335         if (IS_ERR(losc))
1336                 return PTR_ERR(losc);
1337
1338         hosc = devm_clk_get(pctl->dev, "hosc");
1339         if (IS_ERR(hosc))
1340                 return PTR_ERR(hosc);
1341
1342         for (i = 0; i < pctl->desc->irq_banks; i++) {
1343                 unsigned long debounce_freq;
1344                 u32 debounce;
1345
1346                 ret = of_property_read_u32_index(node, "input-debounce",
1347                                                  i, &debounce);
1348                 if (ret)
1349                         return ret;
1350
1351                 if (!debounce)
1352                         continue;
1353
1354                 debounce_freq = DIV_ROUND_CLOSEST(USEC_PER_SEC, debounce);
1355                 losc_div = sunxi_pinctrl_get_debounce_div(losc,
1356                                                           debounce_freq,
1357                                                           &losc_diff);
1358
1359                 hosc_div = sunxi_pinctrl_get_debounce_div(hosc,
1360                                                           debounce_freq,
1361                                                           &hosc_diff);
1362
1363                 if (hosc_diff < losc_diff) {
1364                         div = hosc_div;
1365                         src = 1;
1366                 } else {
1367                         div = losc_div;
1368                         src = 0;
1369                 }
1370
1371                 writel(src | div << 4,
1372                        pctl->membase +
1373                        sunxi_irq_debounce_reg_from_bank(pctl->desc, i));
1374         }
1375
1376         return 0;
1377 }
1378
1379 int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
1380                                     const struct sunxi_pinctrl_desc *desc,
1381                                     unsigned long variant)
1382 {
1383         struct device_node *node = pdev->dev.of_node;
1384         struct pinctrl_desc *pctrl_desc;
1385         struct pinctrl_pin_desc *pins;
1386         struct sunxi_pinctrl *pctl;
1387         struct pinmux_ops *pmxops;
1388         int i, ret, last_pin, pin_idx;
1389         struct clk *clk;
1390
1391         pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1392         if (!pctl)
1393                 return -ENOMEM;
1394         platform_set_drvdata(pdev, pctl);
1395
1396         raw_spin_lock_init(&pctl->lock);
1397
1398         pctl->membase = devm_platform_ioremap_resource(pdev, 0);
1399         if (IS_ERR(pctl->membase))
1400                 return PTR_ERR(pctl->membase);
1401
1402         pctl->dev = &pdev->dev;
1403         pctl->desc = desc;
1404         pctl->variant = variant;
1405
1406         pctl->irq_array = devm_kcalloc(&pdev->dev,
1407                                        IRQ_PER_BANK * pctl->desc->irq_banks,
1408                                        sizeof(*pctl->irq_array),
1409                                        GFP_KERNEL);
1410         if (!pctl->irq_array)
1411                 return -ENOMEM;
1412
1413         ret = sunxi_pinctrl_build_state(pdev);
1414         if (ret) {
1415                 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
1416                 return ret;
1417         }
1418
1419         pins = devm_kcalloc(&pdev->dev,
1420                             pctl->desc->npins, sizeof(*pins),
1421                             GFP_KERNEL);
1422         if (!pins)
1423                 return -ENOMEM;
1424
1425         for (i = 0, pin_idx = 0; i < pctl->desc->npins; i++) {
1426                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1427
1428                 if (pin->variant && !(pctl->variant & pin->variant))
1429                         continue;
1430
1431                 pins[pin_idx++] = pin->pin;
1432         }
1433
1434         pctrl_desc = devm_kzalloc(&pdev->dev,
1435                                   sizeof(*pctrl_desc),
1436                                   GFP_KERNEL);
1437         if (!pctrl_desc)
1438                 return -ENOMEM;
1439
1440         pctrl_desc->name = dev_name(&pdev->dev);
1441         pctrl_desc->owner = THIS_MODULE;
1442         pctrl_desc->pins = pins;
1443         pctrl_desc->npins = pctl->ngroups;
1444         pctrl_desc->confops = &sunxi_pconf_ops;
1445         pctrl_desc->pctlops = &sunxi_pctrl_ops;
1446
1447         pmxops = devm_kmemdup(&pdev->dev, &sunxi_pmx_ops, sizeof(sunxi_pmx_ops),
1448                               GFP_KERNEL);
1449         if (!pmxops)
1450                 return -ENOMEM;
1451
1452         if (desc->disable_strict_mode)
1453                 pmxops->strict = false;
1454
1455         pctrl_desc->pmxops = pmxops;
1456
1457         pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
1458         if (IS_ERR(pctl->pctl_dev)) {
1459                 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
1460                 return PTR_ERR(pctl->pctl_dev);
1461         }
1462
1463         pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1464         if (!pctl->chip)
1465                 return -ENOMEM;
1466
1467         last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
1468         pctl->chip->owner = THIS_MODULE;
1469         pctl->chip->request = gpiochip_generic_request;
1470         pctl->chip->free = gpiochip_generic_free;
1471         pctl->chip->set_config = gpiochip_generic_config;
1472         pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input;
1473         pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output;
1474         pctl->chip->get = sunxi_pinctrl_gpio_get;
1475         pctl->chip->set = sunxi_pinctrl_gpio_set;
1476         pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate;
1477         pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq;
1478         pctl->chip->of_gpio_n_cells = 3;
1479         pctl->chip->can_sleep = false;
1480         pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -
1481                             pctl->desc->pin_base;
1482         pctl->chip->label = dev_name(&pdev->dev);
1483         pctl->chip->parent = &pdev->dev;
1484         pctl->chip->base = pctl->desc->pin_base;
1485
1486         ret = gpiochip_add_data(pctl->chip, pctl);
1487         if (ret)
1488                 return ret;
1489
1490         for (i = 0; i < pctl->desc->npins; i++) {
1491                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1492
1493                 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1494                                              pin->pin.number - pctl->desc->pin_base,
1495                                              pin->pin.number, 1);
1496                 if (ret)
1497                         goto gpiochip_error;
1498         }
1499
1500         ret = of_clk_get_parent_count(node);
1501         clk = devm_clk_get(&pdev->dev, ret == 1 ? NULL : "apb");
1502         if (IS_ERR(clk)) {
1503                 ret = PTR_ERR(clk);
1504                 goto gpiochip_error;
1505         }
1506
1507         ret = clk_prepare_enable(clk);
1508         if (ret)
1509                 goto gpiochip_error;
1510
1511         pctl->irq = devm_kcalloc(&pdev->dev,
1512                                  pctl->desc->irq_banks,
1513                                  sizeof(*pctl->irq),
1514                                  GFP_KERNEL);
1515         if (!pctl->irq) {
1516                 ret = -ENOMEM;
1517                 goto clk_error;
1518         }
1519
1520         for (i = 0; i < pctl->desc->irq_banks; i++) {
1521                 pctl->irq[i] = platform_get_irq(pdev, i);
1522                 if (pctl->irq[i] < 0) {
1523                         ret = pctl->irq[i];
1524                         goto clk_error;
1525                 }
1526         }
1527
1528         pctl->domain = irq_domain_add_linear(node,
1529                                              pctl->desc->irq_banks * IRQ_PER_BANK,
1530                                              &sunxi_pinctrl_irq_domain_ops,
1531                                              pctl);
1532         if (!pctl->domain) {
1533                 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
1534                 ret = -ENOMEM;
1535                 goto clk_error;
1536         }
1537
1538         for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
1539                 int irqno = irq_create_mapping(pctl->domain, i);
1540
1541                 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip,
1542                                          handle_edge_irq);
1543                 irq_set_chip_data(irqno, pctl);
1544         }
1545
1546         for (i = 0; i < pctl->desc->irq_banks; i++) {
1547                 /* Mask and clear all IRQs before registering a handler */
1548                 writel(0, pctl->membase +
1549                           sunxi_irq_ctrl_reg_from_bank(pctl->desc, i));
1550                 writel(0xffffffff,
1551                        pctl->membase +
1552                        sunxi_irq_status_reg_from_bank(pctl->desc, i));
1553
1554                 irq_set_chained_handler_and_data(pctl->irq[i],
1555                                                  sunxi_pinctrl_irq_handler,
1556                                                  pctl);
1557         }
1558
1559         sunxi_pinctrl_setup_debounce(pctl, node);
1560
1561         dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
1562
1563         return 0;
1564
1565 clk_error:
1566         clk_disable_unprepare(clk);
1567 gpiochip_error:
1568         gpiochip_remove(pctl->chip);
1569         return ret;
1570 }