1 // SPDX-License-Identifier: GPL-2.0
3 * simple driver for PWM (Pulse Width Modulator) controller
5 * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
8 #include <linux/bitfield.h>
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/err.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/platform_device.h>
19 #include <linux/pwm.h>
20 #include <linux/slab.h>
22 /* i.MX1 and i.MX21 share the same PWM function block: */
24 #define MX1_PWMC 0x00 /* PWM Control Register */
25 #define MX1_PWMS 0x04 /* PWM Sample Register */
26 #define MX1_PWMP 0x08 /* PWM Period Register */
28 #define MX1_PWMC_EN BIT(4)
30 /* i.MX27, i.MX31, i.MX35 share the same PWM function block: */
32 #define MX3_PWMCR 0x00 /* PWM Control Register */
33 #define MX3_PWMSR 0x04 /* PWM Status Register */
34 #define MX3_PWMSAR 0x0C /* PWM Sample Register */
35 #define MX3_PWMPR 0x10 /* PWM Period Register */
37 #define MX3_PWMCR_FWM GENMASK(27, 26)
38 #define MX3_PWMCR_STOPEN BIT(25)
39 #define MX3_PWMCR_DOZEN BIT(24)
40 #define MX3_PWMCR_WAITEN BIT(23)
41 #define MX3_PWMCR_DBGEN BIT(22)
42 #define MX3_PWMCR_BCTR BIT(21)
43 #define MX3_PWMCR_HCTR BIT(20)
45 #define MX3_PWMCR_POUTC GENMASK(19, 18)
46 #define MX3_PWMCR_POUTC_NORMAL 0
47 #define MX3_PWMCR_POUTC_INVERTED 1
48 #define MX3_PWMCR_POUTC_OFF 2
50 #define MX3_PWMCR_CLKSRC GENMASK(17, 16)
51 #define MX3_PWMCR_CLKSRC_OFF 0
52 #define MX3_PWMCR_CLKSRC_IPG 1
53 #define MX3_PWMCR_CLKSRC_IPG_HIGH 2
54 #define MX3_PWMCR_CLKSRC_IPG_32K 3
56 #define MX3_PWMCR_PRESCALER GENMASK(15, 4)
58 #define MX3_PWMCR_SWR BIT(3)
60 #define MX3_PWMCR_REPEAT GENMASK(2, 1)
61 #define MX3_PWMCR_REPEAT_1X 0
62 #define MX3_PWMCR_REPEAT_2X 1
63 #define MX3_PWMCR_REPEAT_4X 2
64 #define MX3_PWMCR_REPEAT_8X 3
66 #define MX3_PWMCR_EN BIT(0)
68 #define MX3_PWMSR_FWE BIT(6)
69 #define MX3_PWMSR_CMP BIT(5)
70 #define MX3_PWMSR_ROV BIT(4)
71 #define MX3_PWMSR_FE BIT(3)
73 #define MX3_PWMSR_FIFOAV GENMASK(2, 0)
74 #define MX3_PWMSR_FIFOAV_EMPTY 0
75 #define MX3_PWMSR_FIFOAV_1WORD 1
76 #define MX3_PWMSR_FIFOAV_2WORDS 2
77 #define MX3_PWMSR_FIFOAV_3WORDS 3
78 #define MX3_PWMSR_FIFOAV_4WORDS 4
80 #define MX3_PWMCR_PRESCALER_SET(x) FIELD_PREP(MX3_PWMCR_PRESCALER, (x) - 1)
81 #define MX3_PWMCR_PRESCALER_GET(x) (FIELD_GET(MX3_PWMCR_PRESCALER, \
84 #define MX3_PWM_SWR_LOOP 5
86 /* PWMPR register value of 0xffff has the same effect as 0xfffe */
87 #define MX3_PWMPR_MAX 0xfffe
94 void __iomem *mmio_base;
99 #define to_imx_chip(chip) container_of(chip, struct imx_chip, chip)
101 static int imx_pwm_clk_prepare_enable(struct pwm_chip *chip)
103 struct imx_chip *imx = to_imx_chip(chip);
106 ret = clk_prepare_enable(imx->clk_ipg);
110 ret = clk_prepare_enable(imx->clk_per);
112 clk_disable_unprepare(imx->clk_ipg);
119 static void imx_pwm_clk_disable_unprepare(struct pwm_chip *chip)
121 struct imx_chip *imx = to_imx_chip(chip);
123 clk_disable_unprepare(imx->clk_per);
124 clk_disable_unprepare(imx->clk_ipg);
127 static void imx_pwm_get_state(struct pwm_chip *chip,
128 struct pwm_device *pwm, struct pwm_state *state)
130 struct imx_chip *imx = to_imx_chip(chip);
131 u32 period, prescaler, pwm_clk, ret, val;
134 ret = imx_pwm_clk_prepare_enable(chip);
138 val = readl(imx->mmio_base + MX3_PWMCR);
140 if (val & MX3_PWMCR_EN) {
141 state->enabled = true;
142 ret = imx_pwm_clk_prepare_enable(chip);
146 state->enabled = false;
149 switch (FIELD_GET(MX3_PWMCR_POUTC, val)) {
150 case MX3_PWMCR_POUTC_NORMAL:
151 state->polarity = PWM_POLARITY_NORMAL;
153 case MX3_PWMCR_POUTC_INVERTED:
154 state->polarity = PWM_POLARITY_INVERSED;
157 dev_warn(chip->dev, "can't set polarity, output disconnected");
160 prescaler = MX3_PWMCR_PRESCALER_GET(val);
161 pwm_clk = clk_get_rate(imx->clk_per);
162 pwm_clk = DIV_ROUND_CLOSEST_ULL(pwm_clk, prescaler);
163 val = readl(imx->mmio_base + MX3_PWMPR);
164 period = val >= MX3_PWMPR_MAX ? MX3_PWMPR_MAX : val;
166 /* PWMOUT (Hz) = PWMCLK / (PWMPR + 2) */
167 tmp = NSEC_PER_SEC * (u64)(period + 2);
168 state->period = DIV_ROUND_CLOSEST_ULL(tmp, pwm_clk);
170 /* PWMSAR can be read only if PWM is enabled */
171 if (state->enabled) {
172 val = readl(imx->mmio_base + MX3_PWMSAR);
173 tmp = NSEC_PER_SEC * (u64)(val);
174 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, pwm_clk);
176 state->duty_cycle = 0;
179 imx_pwm_clk_disable_unprepare(chip);
182 static int imx_pwm_config_v1(struct pwm_chip *chip,
183 struct pwm_device *pwm, int duty_ns, int period_ns)
185 struct imx_chip *imx = to_imx_chip(chip);
188 * The PWM subsystem allows for exact frequencies. However,
189 * I cannot connect a scope on my device to the PWM line and
190 * thus cannot provide the program the PWM controller
191 * exactly. Instead, I'm relying on the fact that the
192 * Bootloader (u-boot or WinCE+haret) has programmed the PWM
193 * function group already. So I'll just modify the PWM sample
194 * register to follow the ratio of duty_ns vs. period_ns
197 * This is good enough for programming the brightness of
200 * The real implementation would divide PERCLK[0] first by
201 * both the prescaler (/1 .. /128) and then by CLKSEL
204 u32 max = readl(imx->mmio_base + MX1_PWMP);
205 u32 p = max * duty_ns / period_ns;
206 writel(max - p, imx->mmio_base + MX1_PWMS);
211 static int imx_pwm_enable_v1(struct pwm_chip *chip, struct pwm_device *pwm)
213 struct imx_chip *imx = to_imx_chip(chip);
217 ret = imx_pwm_clk_prepare_enable(chip);
221 val = readl(imx->mmio_base + MX1_PWMC);
223 writel(val, imx->mmio_base + MX1_PWMC);
228 static void imx_pwm_disable_v1(struct pwm_chip *chip, struct pwm_device *pwm)
230 struct imx_chip *imx = to_imx_chip(chip);
233 val = readl(imx->mmio_base + MX1_PWMC);
235 writel(val, imx->mmio_base + MX1_PWMC);
237 imx_pwm_clk_disable_unprepare(chip);
240 static void imx_pwm_sw_reset(struct pwm_chip *chip)
242 struct imx_chip *imx = to_imx_chip(chip);
243 struct device *dev = chip->dev;
247 writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
249 usleep_range(200, 1000);
250 cr = readl(imx->mmio_base + MX3_PWMCR);
251 } while ((cr & MX3_PWMCR_SWR) &&
252 (wait_count++ < MX3_PWM_SWR_LOOP));
254 if (cr & MX3_PWMCR_SWR)
255 dev_warn(dev, "software reset timeout\n");
258 static void imx_pwm_wait_fifo_slot(struct pwm_chip *chip,
259 struct pwm_device *pwm)
261 struct imx_chip *imx = to_imx_chip(chip);
262 struct device *dev = chip->dev;
263 unsigned int period_ms;
267 sr = readl(imx->mmio_base + MX3_PWMSR);
268 fifoav = FIELD_GET(MX3_PWMSR_FIFOAV, sr);
269 if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
270 period_ms = DIV_ROUND_UP(pwm_get_period(pwm),
274 sr = readl(imx->mmio_base + MX3_PWMSR);
275 if (fifoav == FIELD_GET(MX3_PWMSR_FIFOAV, sr))
276 dev_warn(dev, "there is no free FIFO slot\n");
280 static int imx_pwm_apply_v2(struct pwm_chip *chip, struct pwm_device *pwm,
281 struct pwm_state *state)
283 unsigned long period_cycles, duty_cycles, prescale;
284 struct imx_chip *imx = to_imx_chip(chip);
285 struct pwm_state cstate;
286 unsigned long long c;
290 pwm_get_state(pwm, &cstate);
292 if (state->enabled) {
293 c = clk_get_rate(imx->clk_per);
296 do_div(c, 1000000000);
299 prescale = period_cycles / 0x10000 + 1;
301 period_cycles /= prescale;
302 c = (unsigned long long)period_cycles * state->duty_cycle;
303 do_div(c, state->period);
307 * according to imx pwm RM, the real period value should be
308 * PERIOD value in PWMPR plus 2.
310 if (period_cycles > 2)
316 * Wait for a free FIFO slot if the PWM is already enabled, and
317 * flush the FIFO if the PWM was disabled and is about to be
320 if (cstate.enabled) {
321 imx_pwm_wait_fifo_slot(chip, pwm);
323 ret = imx_pwm_clk_prepare_enable(chip);
327 imx_pwm_sw_reset(chip);
330 writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
331 writel(period_cycles, imx->mmio_base + MX3_PWMPR);
333 cr = MX3_PWMCR_PRESCALER_SET(prescale) |
334 MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEN | MX3_PWMCR_WAITEN |
335 FIELD_PREP(MX3_PWMCR_CLKSRC, MX3_PWMCR_CLKSRC_IPG_HIGH) |
336 MX3_PWMCR_DBGEN | MX3_PWMCR_EN;
338 if (state->polarity == PWM_POLARITY_INVERSED)
339 cr |= FIELD_PREP(MX3_PWMCR_POUTC,
340 MX3_PWMCR_POUTC_INVERTED);
342 writel(cr, imx->mmio_base + MX3_PWMCR);
343 } else if (cstate.enabled) {
344 writel(0, imx->mmio_base + MX3_PWMCR);
346 imx_pwm_clk_disable_unprepare(chip);
352 static const struct pwm_ops imx_pwm_ops_v1 = {
353 .enable = imx_pwm_enable_v1,
354 .disable = imx_pwm_disable_v1,
355 .config = imx_pwm_config_v1,
356 .owner = THIS_MODULE,
359 static const struct pwm_ops imx_pwm_ops_v2 = {
360 .apply = imx_pwm_apply_v2,
361 .get_state = imx_pwm_get_state,
362 .owner = THIS_MODULE,
365 struct imx_pwm_data {
366 bool polarity_supported;
367 const struct pwm_ops *ops;
370 static struct imx_pwm_data imx_pwm_data_v1 = {
371 .ops = &imx_pwm_ops_v1,
374 static struct imx_pwm_data imx_pwm_data_v2 = {
375 .polarity_supported = true,
376 .ops = &imx_pwm_ops_v2,
379 static const struct of_device_id imx_pwm_dt_ids[] = {
380 { .compatible = "fsl,imx1-pwm", .data = &imx_pwm_data_v1, },
381 { .compatible = "fsl,imx27-pwm", .data = &imx_pwm_data_v2, },
384 MODULE_DEVICE_TABLE(of, imx_pwm_dt_ids);
386 static int imx_pwm_probe(struct platform_device *pdev)
388 const struct of_device_id *of_id =
389 of_match_device(imx_pwm_dt_ids, &pdev->dev);
390 const struct imx_pwm_data *data;
391 struct imx_chip *imx;
400 imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
404 imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
405 if (IS_ERR(imx->clk_ipg)) {
406 dev_err(&pdev->dev, "getting ipg clock failed with %ld\n",
407 PTR_ERR(imx->clk_ipg));
408 return PTR_ERR(imx->clk_ipg);
411 imx->clk_per = devm_clk_get(&pdev->dev, "per");
412 if (IS_ERR(imx->clk_per)) {
413 dev_err(&pdev->dev, "getting per clock failed with %ld\n",
414 PTR_ERR(imx->clk_per));
415 return PTR_ERR(imx->clk_per);
418 imx->chip.ops = data->ops;
419 imx->chip.dev = &pdev->dev;
423 if (data->polarity_supported) {
424 dev_dbg(&pdev->dev, "PWM supports output inversion\n");
425 imx->chip.of_xlate = of_pwm_xlate_with_flags;
426 imx->chip.of_pwm_n_cells = 3;
429 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
430 imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
431 if (IS_ERR(imx->mmio_base))
432 return PTR_ERR(imx->mmio_base);
434 ret = pwmchip_add(&imx->chip);
438 platform_set_drvdata(pdev, imx);
442 static int imx_pwm_remove(struct platform_device *pdev)
444 struct imx_chip *imx;
446 imx = platform_get_drvdata(pdev);
450 imx_pwm_clk_disable_unprepare(&imx->chip);
452 return pwmchip_remove(&imx->chip);
455 static struct platform_driver imx_pwm_driver = {
458 .of_match_table = imx_pwm_dt_ids,
460 .probe = imx_pwm_probe,
461 .remove = imx_pwm_remove,
464 module_platform_driver(imx_pwm_driver);
466 MODULE_LICENSE("GPL v2");
467 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");