drivers/pwm/pwm-sun4i.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Driver for Allwinner sun4i Pulse Width Modulation Controller
   4  *
   5  * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
   6  */
   7
   8 #include <linux/bitops.h>
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/err.h>
  12 #include <linux/io.h>
  13 #include <linux/jiffies.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/of_device.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pwm.h>
  19 #include <linux/slab.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/time.h>
  22
  23 #define PWM_CTRL_REG            0x0
  24
  25 #define PWM_CH_PRD_BASE         0x4
  26 #define PWM_CH_PRD_OFFSET       0x4
  27 #define PWM_CH_PRD(ch)          (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))
  28
  29 #define PWMCH_OFFSET            15
  30 #define PWM_PRESCAL_MASK        GENMASK(3, 0)
  31 #define PWM_PRESCAL_OFF         0
  32 #define PWM_EN                  BIT(4)
  33 #define PWM_ACT_STATE           BIT(5)
  34 #define PWM_CLK_GATING          BIT(6)
  35 #define PWM_MODE                BIT(7)
  36 #define PWM_PULSE               BIT(8)
  37 #define PWM_BYPASS              BIT(9)
  38
  39 #define PWM_RDY_BASE            28
  40 #define PWM_RDY_OFFSET          1
  41 #define PWM_RDY(ch)             BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
  42
  43 #define PWM_PRD(prd)            (((prd) - 1) << 16)
  44 #define PWM_PRD_MASK            GENMASK(15, 0)
  45
  46 #define PWM_DTY_MASK            GENMASK(15, 0)
  47
  48 #define PWM_REG_PRD(reg)        ((((reg) >> 16) & PWM_PRD_MASK) + 1)
  49 #define PWM_REG_DTY(reg)        ((reg) & PWM_DTY_MASK)
  50 #define PWM_REG_PRESCAL(reg, chan)      (((reg) >> ((chan) * PWMCH_OFFSET)) & PWM_PRESCAL_MASK)
  51
  52 #define BIT_CH(bit, chan)       ((bit) << ((chan) * PWMCH_OFFSET))
  53
  54 static const u32 prescaler_table[] = {
  55         120,
  56         180,
  57         240,
  58         360,
  59         480,
  60         0,
  61         0,
  62         0,
  63         12000,
  64         24000,
  65         36000,
  66         48000,
  67         72000,
  68         0,
  69         0,
  70         0, /* Actually 1 but tested separately */
  71 };
  72
  73 struct sun4i_pwm_data {
  74         bool has_prescaler_bypass;
  75         unsigned int npwm;
  76 };
  77
  78 struct sun4i_pwm_chip {
  79         struct pwm_chip chip;
  80         struct clk *clk;
  81         void __iomem *base;
  82         spinlock_t ctrl_lock;
  83         const struct sun4i_pwm_data *data;
  84         unsigned long next_period[2];
  85         bool needs_delay[2];
  86 };
  87
  88 static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip)
  89 {
  90         return container_of(chip, struct sun4i_pwm_chip, chip);
  91 }
  92
  93 static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip,
  94                                   unsigned long offset)
  95 {
  96         return readl(chip->base + offset);
  97 }
  98
  99 static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
 100                                     u32 val, unsigned long offset)
 101 {
 102         writel(val, chip->base + offset);
 103 }
 104
 105 static void sun4i_pwm_get_state(struct pwm_chip *chip,
 106                                 struct pwm_device *pwm,
 107                                 struct pwm_state *state)
 108 {
 109         struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
 110         u64 clk_rate, tmp;
 111         u32 val;
 112         unsigned int prescaler;
 113
 114         clk_rate = clk_get_rate(sun4i_pwm->clk);
 115
 116         val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
 117
 118         if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
 119             sun4i_pwm->data->has_prescaler_bypass)
 120                 prescaler = 1;
 121         else
 122                 prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];
 123
 124         if (prescaler == 0)
 125                 return;
 126
 127         if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm))
 128                 state->polarity = PWM_POLARITY_NORMAL;
 129         else
 130                 state->polarity = PWM_POLARITY_INVERSED;
 131
 132         if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) ==
 133             BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm))
 134                 state->enabled = true;
 135         else
 136                 state->enabled = false;
 137
 138         val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm));
 139
 140         tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_DTY(val);
 141         state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
 142
 143         tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);
 144         state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
 145 }
 146
 147 static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
 148                                const struct pwm_state *state,
 149                                u32 *dty, u32 *prd, unsigned int *prsclr)
 150 {
 151         u64 clk_rate, div = 0;
 152         unsigned int pval, prescaler = 0;
 153
 154         clk_rate = clk_get_rate(sun4i_pwm->clk);
 155
 156         if (sun4i_pwm->data->has_prescaler_bypass) {
 157                 /* First, test without any prescaler when available */
 158                 prescaler = PWM_PRESCAL_MASK;
 159                 /*
 160                  * When not using any prescaler, the clock period in nanoseconds
 161                  * is not an integer so round it half up instead of
 162                  * truncating to get less surprising values.
 163                  */
 164                 div = clk_rate * state->period + NSEC_PER_SEC / 2;
 165                 do_div(div, NSEC_PER_SEC);
 166                 if (div - 1 > PWM_PRD_MASK)
 167                         prescaler = 0;
 168         }
 169
 170         if (prescaler == 0) {
 171                 /* Go up from the first divider */
 172                 for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
 173                         if (!prescaler_table[prescaler])
 174                                 continue;
 175                         pval = prescaler_table[prescaler];
 176                         div = clk_rate;
 177                         do_div(div, pval);
 178                         div = div * state->period;
 179                         do_div(div, NSEC_PER_SEC);
 180                         if (div - 1 <= PWM_PRD_MASK)
 181                                 break;
 182                 }
 183
 184                 if (div - 1 > PWM_PRD_MASK)
 185                         return -EINVAL;
 186         }
 187
 188         *prd = div;
 189         div *= state->duty_cycle;
 190         do_div(div, state->period);
 191         *dty = div;
 192         *prsclr = prescaler;
 193
 194         return 0;
 195 }
 196
 197 static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 198                            const struct pwm_state *state)
 199 {
 200         struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
 201         struct pwm_state cstate;
 202         u32 ctrl;
 203         int ret;
 204         unsigned int delay_us;
 205         unsigned long now;
 206
 207         pwm_get_state(pwm, &cstate);
 208
 209         if (!cstate.enabled) {
 210                 ret = clk_prepare_enable(sun4i_pwm->clk);
 211                 if (ret) {
 212                         dev_err(chip->dev, "failed to enable PWM clock\n");
 213                         return ret;
 214                 }
 215         }
 216
 217         spin_lock(&sun4i_pwm->ctrl_lock);
 218         ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
 219
 220         if ((cstate.period != state->period) ||
 221             (cstate.duty_cycle != state->duty_cycle)) {
 222                 u32 period, duty, val;
 223                 unsigned int prescaler;
 224
 225                 ret = sun4i_pwm_calculate(sun4i_pwm, state,
 226                                           &duty, &period, &prescaler);
 227                 if (ret) {
 228                         dev_err(chip->dev, "period exceeds the maximum value\n");
 229                         spin_unlock(&sun4i_pwm->ctrl_lock);
 230                         if (!cstate.enabled)
 231                                 clk_disable_unprepare(sun4i_pwm->clk);
 232                         return ret;
 233                 }
 234
 235                 if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
 236                         /* Prescaler changed, the clock has to be gated */
 237                         ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
 238                         sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
 239
 240                         ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
 241                         ctrl |= BIT_CH(prescaler, pwm->hwpwm);
 242                 }
 243
 244                 val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
 245                 sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
 246                 sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
 247                         usecs_to_jiffies(cstate.period / 1000 + 1);
 248                 sun4i_pwm->needs_delay[pwm->hwpwm] = true;
 249         }
 250
 251         if (state->polarity != PWM_POLARITY_NORMAL)
 252                 ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
 253         else
 254                 ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
 255
 256         ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
 257         if (state->enabled) {
 258                 ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);
 259         } else if (!sun4i_pwm->needs_delay[pwm->hwpwm]) {
 260                 ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
 261                 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
 262         }
 263
 264         sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
 265
 266         spin_unlock(&sun4i_pwm->ctrl_lock);
 267
 268         if (state->enabled)
 269                 return 0;
 270
 271         if (!sun4i_pwm->needs_delay[pwm->hwpwm]) {
 272                 clk_disable_unprepare(sun4i_pwm->clk);
 273                 return 0;
 274         }
 275
 276         /* We need a full period to elapse before disabling the channel. */
 277         now = jiffies;
 278         if (sun4i_pwm->needs_delay[pwm->hwpwm] &&
 279             time_before(now, sun4i_pwm->next_period[pwm->hwpwm])) {
 280                 delay_us = jiffies_to_usecs(sun4i_pwm->next_period[pwm->hwpwm] -
 281                                            now);
 282                 if ((delay_us / 500) > MAX_UDELAY_MS)
 283                         msleep(delay_us / 1000 + 1);
 284                 else
 285                         usleep_range(delay_us, delay_us * 2);
 286         }
 287         sun4i_pwm->needs_delay[pwm->hwpwm] = false;
 288
 289         spin_lock(&sun4i_pwm->ctrl_lock);
 290         ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
 291         ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
 292         ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
 293         sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
 294         spin_unlock(&sun4i_pwm->ctrl_lock);
 295
 296         clk_disable_unprepare(sun4i_pwm->clk);
 297
 298         return 0;
 299 }
 300
 301 static const struct pwm_ops sun4i_pwm_ops = {
 302         .apply = sun4i_pwm_apply,
 303         .get_state = sun4i_pwm_get_state,
 304         .owner = THIS_MODULE,
 305 };
 306
 307 static const struct sun4i_pwm_data sun4i_pwm_dual_nobypass = {
 308         .has_prescaler_bypass = false,
 309         .npwm = 2,
 310 };
 311
 312 static const struct sun4i_pwm_data sun4i_pwm_dual_bypass = {
 313         .has_prescaler_bypass = true,
 314         .npwm = 2,
 315 };
 316
 317 static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
 318         .has_prescaler_bypass = true,
 319         .npwm = 1,
 320 };
 321
 322 static const struct of_device_id sun4i_pwm_dt_ids[] = {
 323         {
 324                 .compatible = "allwinner,sun4i-a10-pwm",
 325                 .data = &sun4i_pwm_dual_nobypass,
 326         }, {
 327                 .compatible = "allwinner,sun5i-a10s-pwm",
 328                 .data = &sun4i_pwm_dual_bypass,
 329         }, {
 330                 .compatible = "allwinner,sun5i-a13-pwm",
 331                 .data = &sun4i_pwm_single_bypass,
 332         }, {
 333                 .compatible = "allwinner,sun7i-a20-pwm",
 334                 .data = &sun4i_pwm_dual_bypass,
 335         }, {
 336                 .compatible = "allwinner,sun8i-h3-pwm",
 337                 .data = &sun4i_pwm_single_bypass,
 338         }, {
 339                 /* sentinel */
 340         },
 341 };
 342 MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);
 343
 344 static int sun4i_pwm_probe(struct platform_device *pdev)
 345 {
 346         struct sun4i_pwm_chip *pwm;
 347         struct resource *res;
 348         int ret;
 349
 350         pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
 351         if (!pwm)
 352                 return -ENOMEM;
 353
 354         pwm->data = of_device_get_match_data(&pdev->dev);
 355         if (!pwm->data)
 356                 return -ENODEV;
 357
 358         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 359         pwm->base = devm_ioremap_resource(&pdev->dev, res);
 360         if (IS_ERR(pwm->base))
 361                 return PTR_ERR(pwm->base);
 362
 363         pwm->clk = devm_clk_get(&pdev->dev, NULL);
 364         if (IS_ERR(pwm->clk))
 365                 return PTR_ERR(pwm->clk);
 366
 367         pwm->chip.dev = &pdev->dev;
 368         pwm->chip.ops = &sun4i_pwm_ops;
 369         pwm->chip.base = -1;
 370         pwm->chip.npwm = pwm->data->npwm;
 371         pwm->chip.of_xlate = of_pwm_xlate_with_flags;
 372         pwm->chip.of_pwm_n_cells = 3;
 373
 374         spin_lock_init(&pwm->ctrl_lock);
 375
 376         ret = pwmchip_add(&pwm->chip);
 377         if (ret < 0) {
 378                 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
 379                 return ret;
 380         }
 381
 382         platform_set_drvdata(pdev, pwm);
 383
 384         return 0;
 385 }
 386
 387 static int sun4i_pwm_remove(struct platform_device *pdev)
 388 {
 389         struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
 390
 391         return pwmchip_remove(&pwm->chip);
 392 }
 393
 394 static struct platform_driver sun4i_pwm_driver = {
 395         .driver = {
 396                 .name = "sun4i-pwm",
 397                 .of_match_table = sun4i_pwm_dt_ids,
 398         },
 399         .probe = sun4i_pwm_probe,
 400         .remove = sun4i_pwm_remove,
 401 };
 402 module_platform_driver(sun4i_pwm_driver);
 403
 404 MODULE_ALIAS("platform:sun4i-pwm");
 405 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
 406 MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
 407 MODULE_LICENSE("GPL v2");