1 // SPDX-License-Identifier: GPL-2.0-only
3 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
5 * Copyright (C) 2005 James Chapman (ds1337 core)
6 * Copyright (C) 2006 David Brownell
7 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
8 * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
11 #include <linux/acpi.h>
12 #include <linux/bcd.h>
13 #include <linux/i2c.h>
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/of_device.h>
17 #include <linux/rtc/ds1307.h>
18 #include <linux/rtc.h>
19 #include <linux/slab.h>
20 #include <linux/string.h>
21 #include <linux/hwmon.h>
22 #include <linux/hwmon-sysfs.h>
23 #include <linux/clk-provider.h>
24 #include <linux/regmap.h>
27 * We can't determine type by probing, but if we expect pre-Linux code
28 * to have set the chip up as a clock (turning on the oscillator and
29 * setting the date and time), Linux can ignore the non-clock features.
30 * That's a natural job for a factory or repair bench.
48 last_ds_type /* always last */
49 /* rs5c372 too? different address... */
52 /* RTC registers don't differ much, except for the century flag */
53 #define DS1307_REG_SECS 0x00 /* 00-59 */
54 # define DS1307_BIT_CH 0x80
55 # define DS1340_BIT_nEOSC 0x80
56 # define MCP794XX_BIT_ST 0x80
57 #define DS1307_REG_MIN 0x01 /* 00-59 */
58 # define M41T0_BIT_OF 0x80
59 #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
60 # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
61 # define DS1307_BIT_PM 0x20 /* in REG_HOUR */
62 # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
63 # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
64 #define DS1307_REG_WDAY 0x03 /* 01-07 */
65 # define MCP794XX_BIT_VBATEN 0x08
66 #define DS1307_REG_MDAY 0x04 /* 01-31 */
67 #define DS1307_REG_MONTH 0x05 /* 01-12 */
68 # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
69 #define DS1307_REG_YEAR 0x06 /* 00-99 */
72 * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
73 * start at 7, and they differ a LOT. Only control and status matter for
74 * basic RTC date and time functionality; be careful using them.
76 #define DS1307_REG_CONTROL 0x07 /* or ds1338 */
77 # define DS1307_BIT_OUT 0x80
78 # define DS1338_BIT_OSF 0x20
79 # define DS1307_BIT_SQWE 0x10
80 # define DS1307_BIT_RS1 0x02
81 # define DS1307_BIT_RS0 0x01
82 #define DS1337_REG_CONTROL 0x0e
83 # define DS1337_BIT_nEOSC 0x80
84 # define DS1339_BIT_BBSQI 0x20
85 # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
86 # define DS1337_BIT_RS2 0x10
87 # define DS1337_BIT_RS1 0x08
88 # define DS1337_BIT_INTCN 0x04
89 # define DS1337_BIT_A2IE 0x02
90 # define DS1337_BIT_A1IE 0x01
91 #define DS1340_REG_CONTROL 0x07
92 # define DS1340_BIT_OUT 0x80
93 # define DS1340_BIT_FT 0x40
94 # define DS1340_BIT_CALIB_SIGN 0x20
95 # define DS1340_M_CALIBRATION 0x1f
96 #define DS1340_REG_FLAG 0x09
97 # define DS1340_BIT_OSF 0x80
98 #define DS1337_REG_STATUS 0x0f
99 # define DS1337_BIT_OSF 0x80
100 # define DS3231_BIT_EN32KHZ 0x08
101 # define DS1337_BIT_A2I 0x02
102 # define DS1337_BIT_A1I 0x01
103 #define DS1339_REG_ALARM1_SECS 0x07
105 #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
107 #define RX8025_REG_CTRL1 0x0e
108 # define RX8025_BIT_2412 0x20
109 #define RX8025_REG_CTRL2 0x0f
110 # define RX8025_BIT_PON 0x10
111 # define RX8025_BIT_VDET 0x40
112 # define RX8025_BIT_XST 0x20
114 #define RX8130_REG_ALARM_MIN 0x17
115 #define RX8130_REG_ALARM_HOUR 0x18
116 #define RX8130_REG_ALARM_WEEK_OR_DAY 0x19
117 #define RX8130_REG_EXTENSION 0x1c
118 #define RX8130_REG_EXTENSION_WADA BIT(3)
119 #define RX8130_REG_FLAG 0x1d
120 #define RX8130_REG_FLAG_VLF BIT(1)
121 #define RX8130_REG_FLAG_AF BIT(3)
122 #define RX8130_REG_CONTROL0 0x1e
123 #define RX8130_REG_CONTROL0_AIE BIT(3)
125 #define MCP794XX_REG_CONTROL 0x07
126 # define MCP794XX_BIT_ALM0_EN 0x10
127 # define MCP794XX_BIT_ALM1_EN 0x20
128 #define MCP794XX_REG_ALARM0_BASE 0x0a
129 #define MCP794XX_REG_ALARM0_CTRL 0x0d
130 #define MCP794XX_REG_ALARM1_BASE 0x11
131 #define MCP794XX_REG_ALARM1_CTRL 0x14
132 # define MCP794XX_BIT_ALMX_IF BIT(3)
133 # define MCP794XX_BIT_ALMX_C0 BIT(4)
134 # define MCP794XX_BIT_ALMX_C1 BIT(5)
135 # define MCP794XX_BIT_ALMX_C2 BIT(6)
136 # define MCP794XX_BIT_ALMX_POL BIT(7)
137 # define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
138 MCP794XX_BIT_ALMX_C1 | \
139 MCP794XX_BIT_ALMX_C2)
141 #define M41TXX_REG_CONTROL 0x07
142 # define M41TXX_BIT_OUT BIT(7)
143 # define M41TXX_BIT_FT BIT(6)
144 # define M41TXX_BIT_CALIB_SIGN BIT(5)
145 # define M41TXX_M_CALIBRATION GENMASK(4, 0)
147 /* negative offset step is -2.034ppm */
148 #define M41TXX_NEG_OFFSET_STEP_PPB 2034
149 /* positive offset step is +4.068ppm */
150 #define M41TXX_POS_OFFSET_STEP_PPB 4068
151 /* Min and max values supported with 'offset' interface by M41TXX */
152 #define M41TXX_MIN_OFFSET ((-31) * M41TXX_NEG_OFFSET_STEP_PPB)
153 #define M41TXX_MAX_OFFSET ((31) * M41TXX_POS_OFFSET_STEP_PPB)
158 #define HAS_NVRAM 0 /* bit 0 == sysfs file active */
159 #define HAS_ALARM 1 /* bit 1 == irq claimed */
161 struct regmap *regmap;
163 struct rtc_device *rtc;
164 #ifdef CONFIG_COMMON_CLK
165 struct clk_hw clks[2];
173 u8 offset; /* register's offset */
175 u8 century_enable_bit;
178 irq_handler_t irq_handler;
179 const struct rtc_class_ops *rtc_ops;
180 u16 trickle_charger_reg;
181 u8 (*do_trickle_setup)(struct ds1307 *, u32,
185 static const struct chip_desc chips[last_ds_type];
187 static int ds1307_get_time(struct device *dev, struct rtc_time *t)
189 struct ds1307 *ds1307 = dev_get_drvdata(dev);
191 const struct chip_desc *chip = &chips[ds1307->type];
194 if (ds1307->type == rx_8130) {
195 unsigned int regflag;
196 ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, ®flag);
198 dev_err(dev, "%s error %d\n", "read", ret);
202 if (regflag & RX8130_REG_FLAG_VLF) {
203 dev_warn_once(dev, "oscillator failed, set time!\n");
208 /* read the RTC date and time registers all at once */
209 ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
212 dev_err(dev, "%s error %d\n", "read", ret);
216 dev_dbg(dev, "%s: %7ph\n", "read", regs);
218 /* if oscillator fail bit is set, no data can be trusted */
219 if (ds1307->type == m41t0 &&
220 regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
221 dev_warn_once(dev, "oscillator failed, set time!\n");
225 tmp = regs[DS1307_REG_SECS];
226 switch (ds1307->type) {
231 if (tmp & DS1307_BIT_CH)
236 if (tmp & DS1307_BIT_CH)
239 ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &tmp);
242 if (tmp & DS1338_BIT_OSF)
246 if (tmp & DS1340_BIT_nEOSC)
249 ret = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
252 if (tmp & DS1340_BIT_OSF)
256 if (!(tmp & MCP794XX_BIT_ST))
264 t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
265 t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
266 tmp = regs[DS1307_REG_HOUR] & 0x3f;
267 t->tm_hour = bcd2bin(tmp);
268 t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;
269 t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);
270 tmp = regs[DS1307_REG_MONTH] & 0x1f;
271 t->tm_mon = bcd2bin(tmp) - 1;
272 t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100;
274 if (regs[chip->century_reg] & chip->century_bit &&
275 IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
278 dev_dbg(dev, "%s secs=%d, mins=%d, "
279 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
280 "read", t->tm_sec, t->tm_min,
281 t->tm_hour, t->tm_mday,
282 t->tm_mon, t->tm_year, t->tm_wday);
287 static int ds1307_set_time(struct device *dev, struct rtc_time *t)
289 struct ds1307 *ds1307 = dev_get_drvdata(dev);
290 const struct chip_desc *chip = &chips[ds1307->type];
295 dev_dbg(dev, "%s secs=%d, mins=%d, "
296 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
297 "write", t->tm_sec, t->tm_min,
298 t->tm_hour, t->tm_mday,
299 t->tm_mon, t->tm_year, t->tm_wday);
301 if (t->tm_year < 100)
304 #ifdef CONFIG_RTC_DRV_DS1307_CENTURY
305 if (t->tm_year > (chip->century_bit ? 299 : 199))
308 if (t->tm_year > 199)
312 regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
313 regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);
314 regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
315 regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
316 regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
317 regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
319 /* assume 20YY not 19YY */
320 tmp = t->tm_year - 100;
321 regs[DS1307_REG_YEAR] = bin2bcd(tmp);
323 if (chip->century_enable_bit)
324 regs[chip->century_reg] |= chip->century_enable_bit;
325 if (t->tm_year > 199 && chip->century_bit)
326 regs[chip->century_reg] |= chip->century_bit;
328 switch (ds1307->type) {
331 regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL,
335 regmap_update_bits(ds1307->regmap, DS1340_REG_FLAG,
340 * these bits were cleared when preparing the date/time
341 * values and need to be set again before writing the
342 * regsfer out to the device.
344 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
345 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
351 dev_dbg(dev, "%s: %7ph\n", "write", regs);
353 result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,
356 dev_err(dev, "%s error %d\n", "write", result);
360 if (ds1307->type == rx_8130) {
361 /* clear Voltage Loss Flag as data is available now */
362 result = regmap_write(ds1307->regmap, RX8130_REG_FLAG,
363 ~(u8)RX8130_REG_FLAG_VLF);
365 dev_err(dev, "%s error %d\n", "write", result);
373 static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
375 struct ds1307 *ds1307 = dev_get_drvdata(dev);
379 if (!test_bit(HAS_ALARM, &ds1307->flags))
382 /* read all ALARM1, ALARM2, and status registers at once */
383 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
386 dev_err(dev, "%s error %d\n", "alarm read", ret);
390 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
391 ®s[0], ®s[4], ®s[7]);
394 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
395 * and that all four fields are checked matches
397 t->time.tm_sec = bcd2bin(regs[0] & 0x7f);
398 t->time.tm_min = bcd2bin(regs[1] & 0x7f);
399 t->time.tm_hour = bcd2bin(regs[2] & 0x3f);
400 t->time.tm_mday = bcd2bin(regs[3] & 0x3f);
403 t->enabled = !!(regs[7] & DS1337_BIT_A1IE);
404 t->pending = !!(regs[8] & DS1337_BIT_A1I);
406 dev_dbg(dev, "%s secs=%d, mins=%d, "
407 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
408 "alarm read", t->time.tm_sec, t->time.tm_min,
409 t->time.tm_hour, t->time.tm_mday,
410 t->enabled, t->pending);
415 static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
417 struct ds1307 *ds1307 = dev_get_drvdata(dev);
418 unsigned char regs[9];
422 if (!test_bit(HAS_ALARM, &ds1307->flags))
425 dev_dbg(dev, "%s secs=%d, mins=%d, "
426 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
427 "alarm set", t->time.tm_sec, t->time.tm_min,
428 t->time.tm_hour, t->time.tm_mday,
429 t->enabled, t->pending);
431 /* read current status of both alarms and the chip */
432 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
435 dev_err(dev, "%s error %d\n", "alarm write", ret);
441 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
442 ®s[0], ®s[4], control, status);
444 /* set ALARM1, using 24 hour and day-of-month modes */
445 regs[0] = bin2bcd(t->time.tm_sec);
446 regs[1] = bin2bcd(t->time.tm_min);
447 regs[2] = bin2bcd(t->time.tm_hour);
448 regs[3] = bin2bcd(t->time.tm_mday);
450 /* set ALARM2 to non-garbage */
456 regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
457 regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
459 ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
462 dev_err(dev, "can't set alarm time\n");
466 /* optionally enable ALARM1 */
468 dev_dbg(dev, "alarm IRQ armed\n");
469 regs[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
470 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]);
476 static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
478 struct ds1307 *ds1307 = dev_get_drvdata(dev);
480 if (!test_bit(HAS_ALARM, &ds1307->flags))
483 return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
485 enabled ? DS1337_BIT_A1IE : 0);
488 static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode)
490 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
491 DS1307_TRICKLE_CHARGER_NO_DIODE;
495 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
498 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
501 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
504 dev_warn(ds1307->dev,
505 "Unsupported ohm value %u in dt\n", ohms);
511 static irqreturn_t rx8130_irq(int irq, void *dev_id)
513 struct ds1307 *ds1307 = dev_id;
514 struct mutex *lock = &ds1307->rtc->ops_lock;
520 /* Read control registers. */
521 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
525 if (!(ctl[1] & RX8130_REG_FLAG_AF))
527 ctl[1] &= ~RX8130_REG_FLAG_AF;
528 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
530 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
535 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
543 static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
545 struct ds1307 *ds1307 = dev_get_drvdata(dev);
549 if (!test_bit(HAS_ALARM, &ds1307->flags))
552 /* Read alarm registers. */
553 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
558 /* Read control registers. */
559 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
564 t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
565 t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
567 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
569 t->time.tm_min = bcd2bin(ald[0] & 0x7f);
570 t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
571 t->time.tm_wday = -1;
572 t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
574 t->time.tm_year = -1;
575 t->time.tm_yday = -1;
576 t->time.tm_isdst = -1;
578 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
579 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
580 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
585 static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
587 struct ds1307 *ds1307 = dev_get_drvdata(dev);
591 if (!test_bit(HAS_ALARM, &ds1307->flags))
594 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
595 "enabled=%d pending=%d\n", __func__,
596 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
597 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
598 t->enabled, t->pending);
600 /* Read control registers. */
601 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
606 ctl[0] &= RX8130_REG_EXTENSION_WADA;
607 ctl[1] &= ~RX8130_REG_FLAG_AF;
608 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
610 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
615 /* Hardware alarm precision is 1 minute! */
616 ald[0] = bin2bcd(t->time.tm_min);
617 ald[1] = bin2bcd(t->time.tm_hour);
618 ald[2] = bin2bcd(t->time.tm_mday);
620 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
628 ctl[2] |= RX8130_REG_CONTROL0_AIE;
630 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]);
633 static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
635 struct ds1307 *ds1307 = dev_get_drvdata(dev);
638 if (!test_bit(HAS_ALARM, &ds1307->flags))
641 ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, ®);
646 reg |= RX8130_REG_CONTROL0_AIE;
648 reg &= ~RX8130_REG_CONTROL0_AIE;
650 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
653 static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
655 struct ds1307 *ds1307 = dev_id;
656 struct mutex *lock = &ds1307->rtc->ops_lock;
661 /* Check and clear alarm 0 interrupt flag. */
662 ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, ®);
665 if (!(reg & MCP794XX_BIT_ALMX_IF))
667 reg &= ~MCP794XX_BIT_ALMX_IF;
668 ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
672 /* Disable alarm 0. */
673 ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
674 MCP794XX_BIT_ALM0_EN, 0);
678 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
686 static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
688 struct ds1307 *ds1307 = dev_get_drvdata(dev);
692 if (!test_bit(HAS_ALARM, &ds1307->flags))
695 /* Read control and alarm 0 registers. */
696 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
701 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
703 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
704 t->time.tm_sec = bcd2bin(regs[3] & 0x7f);
705 t->time.tm_min = bcd2bin(regs[4] & 0x7f);
706 t->time.tm_hour = bcd2bin(regs[5] & 0x3f);
707 t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1;
708 t->time.tm_mday = bcd2bin(regs[7] & 0x3f);
709 t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1;
710 t->time.tm_year = -1;
711 t->time.tm_yday = -1;
712 t->time.tm_isdst = -1;
714 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
715 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__,
716 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
717 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
718 !!(regs[6] & MCP794XX_BIT_ALMX_POL),
719 !!(regs[6] & MCP794XX_BIT_ALMX_IF),
720 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
726 * We may have a random RTC weekday, therefore calculate alarm weekday based
727 * on current weekday we read from the RTC timekeeping regs
729 static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm)
731 struct rtc_time tm_now;
732 int days_now, days_alarm, ret;
734 ret = ds1307_get_time(dev, &tm_now);
738 days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60);
739 days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60);
741 return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1;
744 static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
746 struct ds1307 *ds1307 = dev_get_drvdata(dev);
747 unsigned char regs[10];
750 if (!test_bit(HAS_ALARM, &ds1307->flags))
753 wday = mcp794xx_alm_weekday(dev, &t->time);
757 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
758 "enabled=%d pending=%d\n", __func__,
759 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
760 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
761 t->enabled, t->pending);
763 /* Read control and alarm 0 registers. */
764 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
769 /* Set alarm 0, using 24-hour and day-of-month modes. */
770 regs[3] = bin2bcd(t->time.tm_sec);
771 regs[4] = bin2bcd(t->time.tm_min);
772 regs[5] = bin2bcd(t->time.tm_hour);
774 regs[7] = bin2bcd(t->time.tm_mday);
775 regs[8] = bin2bcd(t->time.tm_mon + 1);
777 /* Clear the alarm 0 interrupt flag. */
778 regs[6] &= ~MCP794XX_BIT_ALMX_IF;
779 /* Set alarm match: second, minute, hour, day, date, month. */
780 regs[6] |= MCP794XX_MSK_ALMX_MATCH;
781 /* Disable interrupt. We will not enable until completely programmed */
782 regs[0] &= ~MCP794XX_BIT_ALM0_EN;
784 ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
791 regs[0] |= MCP794XX_BIT_ALM0_EN;
792 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
795 static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
797 struct ds1307 *ds1307 = dev_get_drvdata(dev);
799 if (!test_bit(HAS_ALARM, &ds1307->flags))
802 return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
803 MCP794XX_BIT_ALM0_EN,
804 enabled ? MCP794XX_BIT_ALM0_EN : 0);
807 static int m41txx_rtc_read_offset(struct device *dev, long *offset)
809 struct ds1307 *ds1307 = dev_get_drvdata(dev);
810 unsigned int ctrl_reg;
813 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
815 val = ctrl_reg & M41TXX_M_CALIBRATION;
817 /* check if positive */
818 if (ctrl_reg & M41TXX_BIT_CALIB_SIGN)
819 *offset = (val * M41TXX_POS_OFFSET_STEP_PPB);
821 *offset = -(val * M41TXX_NEG_OFFSET_STEP_PPB);
826 static int m41txx_rtc_set_offset(struct device *dev, long offset)
828 struct ds1307 *ds1307 = dev_get_drvdata(dev);
829 unsigned int ctrl_reg;
831 if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET))
835 ctrl_reg = DIV_ROUND_CLOSEST(offset,
836 M41TXX_POS_OFFSET_STEP_PPB);
837 ctrl_reg |= M41TXX_BIT_CALIB_SIGN;
839 ctrl_reg = DIV_ROUND_CLOSEST(abs(offset),
840 M41TXX_NEG_OFFSET_STEP_PPB);
843 return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL,
844 M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN,
848 static const struct rtc_class_ops rx8130_rtc_ops = {
849 .read_time = ds1307_get_time,
850 .set_time = ds1307_set_time,
851 .read_alarm = rx8130_read_alarm,
852 .set_alarm = rx8130_set_alarm,
853 .alarm_irq_enable = rx8130_alarm_irq_enable,
856 static const struct rtc_class_ops mcp794xx_rtc_ops = {
857 .read_time = ds1307_get_time,
858 .set_time = ds1307_set_time,
859 .read_alarm = mcp794xx_read_alarm,
860 .set_alarm = mcp794xx_set_alarm,
861 .alarm_irq_enable = mcp794xx_alarm_irq_enable,
864 static const struct rtc_class_ops m41txx_rtc_ops = {
865 .read_time = ds1307_get_time,
866 .set_time = ds1307_set_time,
867 .read_alarm = ds1337_read_alarm,
868 .set_alarm = ds1337_set_alarm,
869 .alarm_irq_enable = ds1307_alarm_irq_enable,
870 .read_offset = m41txx_rtc_read_offset,
871 .set_offset = m41txx_rtc_set_offset,
874 static const struct chip_desc chips[last_ds_type] = {
885 .century_reg = DS1307_REG_MONTH,
886 .century_bit = DS1337_BIT_CENTURY,
894 .century_reg = DS1307_REG_MONTH,
895 .century_bit = DS1337_BIT_CENTURY,
896 .bbsqi_bit = DS1339_BIT_BBSQI,
897 .trickle_charger_reg = 0x10,
898 .do_trickle_setup = &do_trickle_setup_ds1339,
901 .century_reg = DS1307_REG_HOUR,
902 .century_enable_bit = DS1340_BIT_CENTURY_EN,
903 .century_bit = DS1340_BIT_CENTURY,
904 .do_trickle_setup = &do_trickle_setup_ds1339,
905 .trickle_charger_reg = 0x08,
908 .century_reg = DS1307_REG_MONTH,
909 .century_bit = DS1337_BIT_CENTURY,
913 .trickle_charger_reg = 0x0a,
917 .century_reg = DS1307_REG_MONTH,
918 .century_bit = DS1337_BIT_CENTURY,
919 .bbsqi_bit = DS3231_BIT_BBSQW,
923 /* this is battery backed SRAM */
924 .nvram_offset = 0x20,
925 .nvram_size = 4, /* 32bit (4 word x 8 bit) */
927 .irq_handler = rx8130_irq,
928 .rtc_ops = &rx8130_rtc_ops,
931 .rtc_ops = &m41txx_rtc_ops,
934 .rtc_ops = &m41txx_rtc_ops,
937 /* this is battery backed SRAM */
940 .rtc_ops = &m41txx_rtc_ops,
944 /* this is battery backed SRAM */
945 .nvram_offset = 0x20,
947 .irq_handler = mcp794xx_irq,
948 .rtc_ops = &mcp794xx_rtc_ops,
952 static const struct i2c_device_id ds1307_id[] = {
953 { "ds1307", ds_1307 },
954 { "ds1308", ds_1308 },
955 { "ds1337", ds_1337 },
956 { "ds1338", ds_1338 },
957 { "ds1339", ds_1339 },
958 { "ds1388", ds_1388 },
959 { "ds1340", ds_1340 },
960 { "ds1341", ds_1341 },
961 { "ds3231", ds_3231 },
963 { "m41t00", m41t00 },
964 { "m41t11", m41t11 },
965 { "mcp7940x", mcp794xx },
966 { "mcp7941x", mcp794xx },
967 { "pt7c4338", ds_1307 },
968 { "rx8025", rx_8025 },
969 { "isl12057", ds_1337 },
970 { "rx8130", rx_8130 },
973 MODULE_DEVICE_TABLE(i2c, ds1307_id);
976 static const struct of_device_id ds1307_of_match[] = {
978 .compatible = "dallas,ds1307",
979 .data = (void *)ds_1307
982 .compatible = "dallas,ds1308",
983 .data = (void *)ds_1308
986 .compatible = "dallas,ds1337",
987 .data = (void *)ds_1337
990 .compatible = "dallas,ds1338",
991 .data = (void *)ds_1338
994 .compatible = "dallas,ds1339",
995 .data = (void *)ds_1339
998 .compatible = "dallas,ds1388",
999 .data = (void *)ds_1388
1002 .compatible = "dallas,ds1340",
1003 .data = (void *)ds_1340
1006 .compatible = "dallas,ds1341",
1007 .data = (void *)ds_1341
1010 .compatible = "maxim,ds3231",
1011 .data = (void *)ds_3231
1014 .compatible = "st,m41t0",
1015 .data = (void *)m41t0
1018 .compatible = "st,m41t00",
1019 .data = (void *)m41t00
1022 .compatible = "st,m41t11",
1023 .data = (void *)m41t11
1026 .compatible = "microchip,mcp7940x",
1027 .data = (void *)mcp794xx
1030 .compatible = "microchip,mcp7941x",
1031 .data = (void *)mcp794xx
1034 .compatible = "pericom,pt7c4338",
1035 .data = (void *)ds_1307
1038 .compatible = "epson,rx8025",
1039 .data = (void *)rx_8025
1042 .compatible = "isil,isl12057",
1043 .data = (void *)ds_1337
1046 .compatible = "epson,rx8130",
1047 .data = (void *)rx_8130
1051 MODULE_DEVICE_TABLE(of, ds1307_of_match);
1055 static const struct acpi_device_id ds1307_acpi_ids[] = {
1056 { .id = "DS1307", .driver_data = ds_1307 },
1057 { .id = "DS1308", .driver_data = ds_1308 },
1058 { .id = "DS1337", .driver_data = ds_1337 },
1059 { .id = "DS1338", .driver_data = ds_1338 },
1060 { .id = "DS1339", .driver_data = ds_1339 },
1061 { .id = "DS1388", .driver_data = ds_1388 },
1062 { .id = "DS1340", .driver_data = ds_1340 },
1063 { .id = "DS1341", .driver_data = ds_1341 },
1064 { .id = "DS3231", .driver_data = ds_3231 },
1065 { .id = "M41T0", .driver_data = m41t0 },
1066 { .id = "M41T00", .driver_data = m41t00 },
1067 { .id = "M41T11", .driver_data = m41t11 },
1068 { .id = "MCP7940X", .driver_data = mcp794xx },
1069 { .id = "MCP7941X", .driver_data = mcp794xx },
1070 { .id = "PT7C4338", .driver_data = ds_1307 },
1071 { .id = "RX8025", .driver_data = rx_8025 },
1072 { .id = "ISL12057", .driver_data = ds_1337 },
1073 { .id = "RX8130", .driver_data = rx_8130 },
1076 MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids);
1080 * The ds1337 and ds1339 both have two alarms, but we only use the first
1081 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
1082 * signal; ds1339 chips have only one alarm signal.
1084 static irqreturn_t ds1307_irq(int irq, void *dev_id)
1086 struct ds1307 *ds1307 = dev_id;
1087 struct mutex *lock = &ds1307->rtc->ops_lock;
1091 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
1095 if (stat & DS1337_BIT_A1I) {
1096 stat &= ~DS1337_BIT_A1I;
1097 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
1099 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1100 DS1337_BIT_A1IE, 0);
1104 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
1113 /*----------------------------------------------------------------------*/
1115 static const struct rtc_class_ops ds13xx_rtc_ops = {
1116 .read_time = ds1307_get_time,
1117 .set_time = ds1307_set_time,
1118 .read_alarm = ds1337_read_alarm,
1119 .set_alarm = ds1337_set_alarm,
1120 .alarm_irq_enable = ds1307_alarm_irq_enable,
1123 static ssize_t frequency_test_store(struct device *dev,
1124 struct device_attribute *attr,
1125 const char *buf, size_t count)
1127 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
1131 ret = kstrtobool(buf, &freq_test_en);
1133 dev_err(dev, "Failed to store RTC Frequency Test attribute\n");
1137 regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT,
1138 freq_test_en ? M41TXX_BIT_FT : 0);
1143 static ssize_t frequency_test_show(struct device *dev,
1144 struct device_attribute *attr,
1147 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
1148 unsigned int ctrl_reg;
1150 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
1152 return scnprintf(buf, PAGE_SIZE, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" :
1156 static DEVICE_ATTR_RW(frequency_test);
1158 static struct attribute *rtc_freq_test_attrs[] = {
1159 &dev_attr_frequency_test.attr,
1163 static const struct attribute_group rtc_freq_test_attr_group = {
1164 .attrs = rtc_freq_test_attrs,
1167 static int ds1307_add_frequency_test(struct ds1307 *ds1307)
1171 switch (ds1307->type) {
1175 err = rtc_add_group(ds1307->rtc, &rtc_freq_test_attr_group);
1186 /*----------------------------------------------------------------------*/
1188 static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
1191 struct ds1307 *ds1307 = priv;
1192 const struct chip_desc *chip = &chips[ds1307->type];
1194 return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset,
1198 static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
1201 struct ds1307 *ds1307 = priv;
1202 const struct chip_desc *chip = &chips[ds1307->type];
1204 return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset,
1208 /*----------------------------------------------------------------------*/
1210 static u8 ds1307_trickle_init(struct ds1307 *ds1307,
1211 const struct chip_desc *chip)
1216 if (!chip->do_trickle_setup)
1219 if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
1223 if (device_property_read_bool(ds1307->dev, "trickle-diode-disable"))
1226 return chip->do_trickle_setup(ds1307, ohms, diode);
1229 /*----------------------------------------------------------------------*/
1231 #if IS_REACHABLE(CONFIG_HWMON)
1234 * Temperature sensor support for ds3231 devices.
1237 #define DS3231_REG_TEMPERATURE 0x11
1240 * A user-initiated temperature conversion is not started by this function,
1241 * so the temperature is updated once every 64 seconds.
1243 static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
1245 struct ds1307 *ds1307 = dev_get_drvdata(dev);
1250 ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
1251 temp_buf, sizeof(temp_buf));
1255 * Temperature is represented as a 10-bit code with a resolution of
1256 * 0.25 degree celsius and encoded in two's complement format.
1258 temp = (temp_buf[0] << 8) | temp_buf[1];
1265 static ssize_t ds3231_hwmon_show_temp(struct device *dev,
1266 struct device_attribute *attr, char *buf)
1271 ret = ds3231_hwmon_read_temp(dev, &temp);
1275 return sprintf(buf, "%d\n", temp);
1277 static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp,
1280 static struct attribute *ds3231_hwmon_attrs[] = {
1281 &sensor_dev_attr_temp1_input.dev_attr.attr,
1284 ATTRIBUTE_GROUPS(ds3231_hwmon);
1286 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1290 if (ds1307->type != ds_3231)
1293 dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
1295 ds3231_hwmon_groups);
1297 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
1304 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1308 #endif /* CONFIG_RTC_DRV_DS1307_HWMON */
1310 /*----------------------------------------------------------------------*/
1313 * Square-wave output support for DS3231
1314 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
1316 #ifdef CONFIG_COMMON_CLK
1323 #define clk_sqw_to_ds1307(clk) \
1324 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
1325 #define clk_32khz_to_ds1307(clk) \
1326 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
1328 static int ds3231_clk_sqw_rates[] = {
1335 static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
1337 struct mutex *lock = &ds1307->rtc->ops_lock;
1341 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1348 static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
1349 unsigned long parent_rate)
1351 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1355 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1358 if (control & DS1337_BIT_RS1)
1360 if (control & DS1337_BIT_RS2)
1363 return ds3231_clk_sqw_rates[rate_sel];
1366 static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
1367 unsigned long *prate)
1371 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
1372 if (ds3231_clk_sqw_rates[i] <= rate)
1373 return ds3231_clk_sqw_rates[i];
1379 static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
1380 unsigned long parent_rate)
1382 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1386 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
1388 if (ds3231_clk_sqw_rates[rate_sel] == rate)
1392 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
1396 control |= DS1337_BIT_RS1;
1398 control |= DS1337_BIT_RS2;
1400 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
1404 static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
1406 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1408 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
1411 static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
1413 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1415 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
1418 static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
1420 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1423 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1427 return !(control & DS1337_BIT_INTCN);
1430 static const struct clk_ops ds3231_clk_sqw_ops = {
1431 .prepare = ds3231_clk_sqw_prepare,
1432 .unprepare = ds3231_clk_sqw_unprepare,
1433 .is_prepared = ds3231_clk_sqw_is_prepared,
1434 .recalc_rate = ds3231_clk_sqw_recalc_rate,
1435 .round_rate = ds3231_clk_sqw_round_rate,
1436 .set_rate = ds3231_clk_sqw_set_rate,
1439 static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
1440 unsigned long parent_rate)
1445 static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
1447 struct mutex *lock = &ds1307->rtc->ops_lock;
1451 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
1453 enable ? DS3231_BIT_EN32KHZ : 0);
1459 static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
1461 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1463 return ds3231_clk_32khz_control(ds1307, true);
1466 static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
1468 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1470 ds3231_clk_32khz_control(ds1307, false);
1473 static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
1475 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1478 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
1482 return !!(status & DS3231_BIT_EN32KHZ);
1485 static const struct clk_ops ds3231_clk_32khz_ops = {
1486 .prepare = ds3231_clk_32khz_prepare,
1487 .unprepare = ds3231_clk_32khz_unprepare,
1488 .is_prepared = ds3231_clk_32khz_is_prepared,
1489 .recalc_rate = ds3231_clk_32khz_recalc_rate,
1492 static struct clk_init_data ds3231_clks_init[] = {
1493 [DS3231_CLK_SQW] = {
1494 .name = "ds3231_clk_sqw",
1495 .ops = &ds3231_clk_sqw_ops,
1497 [DS3231_CLK_32KHZ] = {
1498 .name = "ds3231_clk_32khz",
1499 .ops = &ds3231_clk_32khz_ops,
1503 static int ds3231_clks_register(struct ds1307 *ds1307)
1505 struct device_node *node = ds1307->dev->of_node;
1506 struct clk_onecell_data *onecell;
1509 onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
1513 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
1514 onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
1515 sizeof(onecell->clks[0]), GFP_KERNEL);
1519 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
1520 struct clk_init_data init = ds3231_clks_init[i];
1523 * Interrupt signal due to alarm conditions and square-wave
1524 * output share same pin, so don't initialize both.
1526 if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags))
1529 /* optional override of the clockname */
1530 of_property_read_string_index(node, "clock-output-names", i,
1532 ds1307->clks[i].init = &init;
1534 onecell->clks[i] = devm_clk_register(ds1307->dev,
1536 if (IS_ERR(onecell->clks[i]))
1537 return PTR_ERR(onecell->clks[i]);
1543 of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
1548 static void ds1307_clks_register(struct ds1307 *ds1307)
1552 if (ds1307->type != ds_3231)
1555 ret = ds3231_clks_register(ds1307);
1557 dev_warn(ds1307->dev, "unable to register clock device %d\n",
1564 static void ds1307_clks_register(struct ds1307 *ds1307)
1568 #endif /* CONFIG_COMMON_CLK */
1570 static const struct regmap_config regmap_config = {
1575 static int ds1307_probe(struct i2c_client *client,
1576 const struct i2c_device_id *id)
1578 struct ds1307 *ds1307;
1581 const struct chip_desc *chip;
1583 bool ds1307_can_wakeup_device = false;
1584 unsigned char regs[8];
1585 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
1586 u8 trickle_charger_setup = 0;
1588 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
1592 dev_set_drvdata(&client->dev, ds1307);
1593 ds1307->dev = &client->dev;
1594 ds1307->name = client->name;
1596 ds1307->regmap = devm_regmap_init_i2c(client, ®map_config);
1597 if (IS_ERR(ds1307->regmap)) {
1598 dev_err(ds1307->dev, "regmap allocation failed\n");
1599 return PTR_ERR(ds1307->regmap);
1602 i2c_set_clientdata(client, ds1307);
1604 if (client->dev.of_node) {
1605 ds1307->type = (enum ds_type)
1606 of_device_get_match_data(&client->dev);
1607 chip = &chips[ds1307->type];
1609 chip = &chips[id->driver_data];
1610 ds1307->type = id->driver_data;
1612 const struct acpi_device_id *acpi_id;
1614 acpi_id = acpi_match_device(ACPI_PTR(ds1307_acpi_ids),
1618 chip = &chips[acpi_id->driver_data];
1619 ds1307->type = acpi_id->driver_data;
1622 want_irq = client->irq > 0 && chip->alarm;
1625 trickle_charger_setup = ds1307_trickle_init(ds1307, chip);
1626 else if (pdata->trickle_charger_setup)
1627 trickle_charger_setup = pdata->trickle_charger_setup;
1629 if (trickle_charger_setup && chip->trickle_charger_reg) {
1630 trickle_charger_setup |= DS13XX_TRICKLE_CHARGER_MAGIC;
1631 dev_dbg(ds1307->dev,
1632 "writing trickle charger info 0x%x to 0x%x\n",
1633 trickle_charger_setup, chip->trickle_charger_reg);
1634 regmap_write(ds1307->regmap, chip->trickle_charger_reg,
1635 trickle_charger_setup);
1640 * For devices with no IRQ directly connected to the SoC, the RTC chip
1641 * can be forced as a wakeup source by stating that explicitly in
1642 * the device's .dts file using the "wakeup-source" boolean property.
1643 * If the "wakeup-source" property is set, don't request an IRQ.
1644 * This will guarantee the 'wakealarm' sysfs entry is available on the device,
1645 * if supported by the RTC.
1647 if (chip->alarm && of_property_read_bool(client->dev.of_node,
1649 ds1307_can_wakeup_device = true;
1652 switch (ds1307->type) {
1657 /* get registers that the "rtc" read below won't read... */
1658 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
1661 dev_dbg(ds1307->dev, "read error %d\n", err);
1665 /* oscillator off? turn it on, so clock can tick. */
1666 if (regs[0] & DS1337_BIT_nEOSC)
1667 regs[0] &= ~DS1337_BIT_nEOSC;
1670 * Using IRQ or defined as wakeup-source?
1671 * Disable the square wave and both alarms.
1672 * For some variants, be sure alarms can trigger when we're
1673 * running on Vbackup (BBSQI/BBSQW)
1675 if (want_irq || ds1307_can_wakeup_device) {
1676 regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit;
1677 regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
1680 regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
1683 /* oscillator fault? clear flag, and warn */
1684 if (regs[1] & DS1337_BIT_OSF) {
1685 regmap_write(ds1307->regmap, DS1337_REG_STATUS,
1686 regs[1] & ~DS1337_BIT_OSF);
1687 dev_warn(ds1307->dev, "SET TIME!\n");
1692 err = regmap_bulk_read(ds1307->regmap,
1693 RX8025_REG_CTRL1 << 4 | 0x08, regs, 2);
1695 dev_dbg(ds1307->dev, "read error %d\n", err);
1699 /* oscillator off? turn it on, so clock can tick. */
1700 if (!(regs[1] & RX8025_BIT_XST)) {
1701 regs[1] |= RX8025_BIT_XST;
1702 regmap_write(ds1307->regmap,
1703 RX8025_REG_CTRL2 << 4 | 0x08,
1705 dev_warn(ds1307->dev,
1706 "oscillator stop detected - SET TIME!\n");
1709 if (regs[1] & RX8025_BIT_PON) {
1710 regs[1] &= ~RX8025_BIT_PON;
1711 regmap_write(ds1307->regmap,
1712 RX8025_REG_CTRL2 << 4 | 0x08,
1714 dev_warn(ds1307->dev, "power-on detected\n");
1717 if (regs[1] & RX8025_BIT_VDET) {
1718 regs[1] &= ~RX8025_BIT_VDET;
1719 regmap_write(ds1307->regmap,
1720 RX8025_REG_CTRL2 << 4 | 0x08,
1722 dev_warn(ds1307->dev, "voltage drop detected\n");
1725 /* make sure we are running in 24hour mode */
1726 if (!(regs[0] & RX8025_BIT_2412)) {
1729 /* switch to 24 hour mode */
1730 regmap_write(ds1307->regmap,
1731 RX8025_REG_CTRL1 << 4 | 0x08,
1732 regs[0] | RX8025_BIT_2412);
1734 err = regmap_bulk_read(ds1307->regmap,
1735 RX8025_REG_CTRL1 << 4 | 0x08,
1738 dev_dbg(ds1307->dev, "read error %d\n", err);
1743 hour = bcd2bin(regs[DS1307_REG_HOUR]);
1746 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1749 regmap_write(ds1307->regmap,
1750 DS1307_REG_HOUR << 4 | 0x08, hour);
1757 /* read RTC registers */
1758 err = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
1761 dev_dbg(ds1307->dev, "read error %d\n", err);
1765 if (ds1307->type == mcp794xx &&
1766 !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
1767 regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1768 regs[DS1307_REG_WDAY] |
1769 MCP794XX_BIT_VBATEN);
1772 tmp = regs[DS1307_REG_HOUR];
1773 switch (ds1307->type) {
1779 * NOTE: ignores century bits; fix before deploying
1780 * systems that will run through year 2100.
1786 if (!(tmp & DS1307_BIT_12HR))
1790 * Be sure we're in 24 hour mode. Multi-master systems
1793 tmp = bcd2bin(tmp & 0x1f);
1796 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1798 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR,
1802 if (want_irq || ds1307_can_wakeup_device) {
1803 device_set_wakeup_capable(ds1307->dev, true);
1804 set_bit(HAS_ALARM, &ds1307->flags);
1807 ds1307->rtc = devm_rtc_allocate_device(ds1307->dev);
1808 if (IS_ERR(ds1307->rtc))
1809 return PTR_ERR(ds1307->rtc);
1811 if (ds1307_can_wakeup_device && !want_irq) {
1812 dev_info(ds1307->dev,
1813 "'wakeup-source' is set, request for an IRQ is disabled!\n");
1814 /* We cannot support UIE mode if we do not have an IRQ line */
1815 ds1307->rtc->uie_unsupported = 1;
1819 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL,
1820 chip->irq_handler ?: ds1307_irq,
1821 IRQF_SHARED | IRQF_ONESHOT,
1822 ds1307->name, ds1307);
1825 device_set_wakeup_capable(ds1307->dev, false);
1826 clear_bit(HAS_ALARM, &ds1307->flags);
1827 dev_err(ds1307->dev, "unable to request IRQ!\n");
1829 dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
1833 ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops;
1834 err = ds1307_add_frequency_test(ds1307);
1838 err = rtc_register_device(ds1307->rtc);
1842 if (chip->nvram_size) {
1843 struct nvmem_config nvmem_cfg = {
1844 .name = "ds1307_nvram",
1847 .size = chip->nvram_size,
1848 .reg_read = ds1307_nvram_read,
1849 .reg_write = ds1307_nvram_write,
1853 ds1307->rtc->nvram_old_abi = true;
1854 rtc_nvmem_register(ds1307->rtc, &nvmem_cfg);
1857 ds1307_hwmon_register(ds1307);
1858 ds1307_clks_register(ds1307);
1866 static struct i2c_driver ds1307_driver = {
1868 .name = "rtc-ds1307",
1869 .of_match_table = of_match_ptr(ds1307_of_match),
1870 .acpi_match_table = ACPI_PTR(ds1307_acpi_ids),
1872 .probe = ds1307_probe,
1873 .id_table = ds1307_id,
1876 module_i2c_driver(ds1307_driver);
1878 MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
1879 MODULE_LICENSE("GPL");