drivers/rtc/rtc-omap.c

   1 /*
   2  * TI OMAP Real Time Clock interface for Linux
   3  *
   4  * Copyright (C) 2003 MontaVista Software, Inc.
   5  * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
   6  *
   7  * Copyright (C) 2006 David Brownell (new RTC framework)
   8  * Copyright (C) 2014 Johan Hovold <johan@kernel.org>
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * as published by the Free Software Foundation; either version
  13  * 2 of the License, or (at your option) any later version.
  14  */
  15
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <linux/bcd.h>
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22 #include <linux/ioport.h>
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27 #include <linux/pinctrl/pinctrl.h>
  28 #include <linux/pinctrl/pinconf.h>
  29 #include <linux/pinctrl/pinconf-generic.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/rtc.h>
  33
  34 /*
  35  * The OMAP RTC is a year/month/day/hours/minutes/seconds BCD clock
  36  * with century-range alarm matching, driven by the 32kHz clock.
  37  *
  38  * The main user-visible ways it differs from PC RTCs are by omitting
  39  * "don't care" alarm fields and sub-second periodic IRQs, and having
  40  * an autoadjust mechanism to calibrate to the true oscillator rate.
  41  *
  42  * Board-specific wiring options include using split power mode with
  43  * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset),
  44  * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from
  45  * low power modes) for OMAP1 boards (OMAP-L138 has this built into
  46  * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment.
  47  */
  48
  49 /* RTC registers */
  50 #define OMAP_RTC_SECONDS_REG            0x00
  51 #define OMAP_RTC_MINUTES_REG            0x04
  52 #define OMAP_RTC_HOURS_REG              0x08
  53 #define OMAP_RTC_DAYS_REG               0x0C
  54 #define OMAP_RTC_MONTHS_REG             0x10
  55 #define OMAP_RTC_YEARS_REG              0x14
  56 #define OMAP_RTC_WEEKS_REG              0x18
  57
  58 #define OMAP_RTC_ALARM_SECONDS_REG      0x20
  59 #define OMAP_RTC_ALARM_MINUTES_REG      0x24
  60 #define OMAP_RTC_ALARM_HOURS_REG        0x28
  61 #define OMAP_RTC_ALARM_DAYS_REG         0x2c
  62 #define OMAP_RTC_ALARM_MONTHS_REG       0x30
  63 #define OMAP_RTC_ALARM_YEARS_REG        0x34
  64
  65 #define OMAP_RTC_CTRL_REG               0x40
  66 #define OMAP_RTC_STATUS_REG             0x44
  67 #define OMAP_RTC_INTERRUPTS_REG         0x48
  68
  69 #define OMAP_RTC_COMP_LSB_REG           0x4c
  70 #define OMAP_RTC_COMP_MSB_REG           0x50
  71 #define OMAP_RTC_OSC_REG                0x54
  72
  73 #define OMAP_RTC_SCRATCH0_REG           0x60
  74 #define OMAP_RTC_SCRATCH1_REG           0x64
  75 #define OMAP_RTC_SCRATCH2_REG           0x68
  76
  77 #define OMAP_RTC_KICK0_REG              0x6c
  78 #define OMAP_RTC_KICK1_REG              0x70
  79
  80 #define OMAP_RTC_IRQWAKEEN              0x7c
  81
  82 #define OMAP_RTC_ALARM2_SECONDS_REG     0x80
  83 #define OMAP_RTC_ALARM2_MINUTES_REG     0x84
  84 #define OMAP_RTC_ALARM2_HOURS_REG       0x88
  85 #define OMAP_RTC_ALARM2_DAYS_REG        0x8c
  86 #define OMAP_RTC_ALARM2_MONTHS_REG      0x90
  87 #define OMAP_RTC_ALARM2_YEARS_REG       0x94
  88
  89 #define OMAP_RTC_PMIC_REG               0x98
  90
  91 /* OMAP_RTC_CTRL_REG bit fields: */
  92 #define OMAP_RTC_CTRL_SPLIT             BIT(7)
  93 #define OMAP_RTC_CTRL_DISABLE           BIT(6)
  94 #define OMAP_RTC_CTRL_SET_32_COUNTER    BIT(5)
  95 #define OMAP_RTC_CTRL_TEST              BIT(4)
  96 #define OMAP_RTC_CTRL_MODE_12_24        BIT(3)
  97 #define OMAP_RTC_CTRL_AUTO_COMP         BIT(2)
  98 #define OMAP_RTC_CTRL_ROUND_30S         BIT(1)
  99 #define OMAP_RTC_CTRL_STOP              BIT(0)
 100
 101 /* OMAP_RTC_STATUS_REG bit fields: */
 102 #define OMAP_RTC_STATUS_POWER_UP        BIT(7)
 103 #define OMAP_RTC_STATUS_ALARM2          BIT(7)
 104 #define OMAP_RTC_STATUS_ALARM           BIT(6)
 105 #define OMAP_RTC_STATUS_1D_EVENT        BIT(5)
 106 #define OMAP_RTC_STATUS_1H_EVENT        BIT(4)
 107 #define OMAP_RTC_STATUS_1M_EVENT        BIT(3)
 108 #define OMAP_RTC_STATUS_1S_EVENT        BIT(2)
 109 #define OMAP_RTC_STATUS_RUN             BIT(1)
 110 #define OMAP_RTC_STATUS_BUSY            BIT(0)
 111
 112 /* OMAP_RTC_INTERRUPTS_REG bit fields: */
 113 #define OMAP_RTC_INTERRUPTS_IT_ALARM2   BIT(4)
 114 #define OMAP_RTC_INTERRUPTS_IT_ALARM    BIT(3)
 115 #define OMAP_RTC_INTERRUPTS_IT_TIMER    BIT(2)
 116
 117 /* OMAP_RTC_OSC_REG bit fields: */
 118 #define OMAP_RTC_OSC_32KCLK_EN          BIT(6)
 119 #define OMAP_RTC_OSC_SEL_32KCLK_SRC     BIT(3)
 120 #define OMAP_RTC_OSC_OSC32K_GZ_DISABLE  BIT(4)
 121
 122 /* OMAP_RTC_IRQWAKEEN bit fields: */
 123 #define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN BIT(1)
 124
 125 /* OMAP_RTC_PMIC bit fields: */
 126 #define OMAP_RTC_PMIC_POWER_EN_EN       BIT(16)
 127 #define OMAP_RTC_PMIC_EXT_WKUP_EN(x)    BIT(x)
 128 #define OMAP_RTC_PMIC_EXT_WKUP_POL(x)   BIT(4 + x)
 129
 130 /* OMAP_RTC_KICKER values */
 131 #define KICK0_VALUE                     0x83e70b13
 132 #define KICK1_VALUE                     0x95a4f1e0
 133
 134 struct omap_rtc;
 135
 136 struct omap_rtc_device_type {
 137         bool has_32kclk_en;
 138         bool has_irqwakeen;
 139         bool has_pmic_mode;
 140         bool has_power_up_reset;
 141         void (*lock)(struct omap_rtc *rtc);
 142         void (*unlock)(struct omap_rtc *rtc);
 143 };
 144
 145 struct omap_rtc {
 146         struct rtc_device *rtc;
 147         void __iomem *base;
 148         struct clk *clk;
 149         int irq_alarm;
 150         int irq_timer;
 151         u8 interrupts_reg;
 152         bool is_pmic_controller;
 153         bool has_ext_clk;
 154         bool is_suspending;
 155         const struct omap_rtc_device_type *type;
 156         struct pinctrl_dev *pctldev;
 157 };
 158
 159 static inline u8 rtc_read(struct omap_rtc *rtc, unsigned int reg)
 160 {
 161         return readb(rtc->base + reg);
 162 }
 163
 164 static inline u32 rtc_readl(struct omap_rtc *rtc, unsigned int reg)
 165 {
 166         return readl(rtc->base + reg);
 167 }
 168
 169 static inline void rtc_write(struct omap_rtc *rtc, unsigned int reg, u8 val)
 170 {
 171         writeb(val, rtc->base + reg);
 172 }
 173
 174 static inline void rtc_writel(struct omap_rtc *rtc, unsigned int reg, u32 val)
 175 {
 176         writel(val, rtc->base + reg);
 177 }
 178
 179 static void am3352_rtc_unlock(struct omap_rtc *rtc)
 180 {
 181         rtc_writel(rtc, OMAP_RTC_KICK0_REG, KICK0_VALUE);
 182         rtc_writel(rtc, OMAP_RTC_KICK1_REG, KICK1_VALUE);
 183 }
 184
 185 static void am3352_rtc_lock(struct omap_rtc *rtc)
 186 {
 187         rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0);
 188         rtc_writel(rtc, OMAP_RTC_KICK1_REG, 0);
 189 }
 190
 191 static void default_rtc_unlock(struct omap_rtc *rtc)
 192 {
 193 }
 194
 195 static void default_rtc_lock(struct omap_rtc *rtc)
 196 {
 197 }
 198
 199 /*
 200  * We rely on the rtc framework to handle locking (rtc->ops_lock),
 201  * so the only other requirement is that register accesses which
 202  * require BUSY to be clear are made with IRQs locally disabled
 203  */
 204 static void rtc_wait_not_busy(struct omap_rtc *rtc)
 205 {
 206         int count;
 207         u8 status;
 208
 209         /* BUSY may stay active for 1/32768 second (~30 usec) */
 210         for (count = 0; count < 50; count++) {
 211                 status = rtc_read(rtc, OMAP_RTC_STATUS_REG);
 212                 if (!(status & OMAP_RTC_STATUS_BUSY))
 213                         break;
 214                 udelay(1);
 215         }
 216         /* now we have ~15 usec to read/write various registers */
 217 }
 218
 219 static irqreturn_t rtc_irq(int irq, void *dev_id)
 220 {
 221         struct omap_rtc *rtc = dev_id;
 222         unsigned long events = 0;
 223         u8 irq_data;
 224
 225         irq_data = rtc_read(rtc, OMAP_RTC_STATUS_REG);
 226
 227         /* alarm irq? */
 228         if (irq_data & OMAP_RTC_STATUS_ALARM) {
 229                 rtc->type->unlock(rtc);
 230                 rtc_write(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM);
 231                 rtc->type->lock(rtc);
 232                 events |= RTC_IRQF | RTC_AF;
 233         }
 234
 235         /* 1/sec periodic/update irq? */
 236         if (irq_data & OMAP_RTC_STATUS_1S_EVENT)
 237                 events |= RTC_IRQF | RTC_UF;
 238
 239         rtc_update_irq(rtc->rtc, 1, events);
 240
 241         return IRQ_HANDLED;
 242 }
 243
 244 static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
 245 {
 246         struct omap_rtc *rtc = dev_get_drvdata(dev);
 247         u8 reg, irqwake_reg = 0;
 248
 249         local_irq_disable();
 250         rtc_wait_not_busy(rtc);
 251         reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
 252         if (rtc->type->has_irqwakeen)
 253                 irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
 254
 255         if (enabled) {
 256                 reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
 257                 irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
 258         } else {
 259                 reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
 260                 irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
 261         }
 262         rtc_wait_not_busy(rtc);
 263         rtc->type->unlock(rtc);
 264         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
 265         if (rtc->type->has_irqwakeen)
 266                 rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
 267         rtc->type->lock(rtc);
 268         local_irq_enable();
 269
 270         return 0;
 271 }
 272
 273 /* this hardware doesn't support "don't care" alarm fields */
 274 static int tm2bcd(struct rtc_time *tm)
 275 {
 276         tm->tm_sec = bin2bcd(tm->tm_sec);
 277         tm->tm_min = bin2bcd(tm->tm_min);
 278         tm->tm_hour = bin2bcd(tm->tm_hour);
 279         tm->tm_mday = bin2bcd(tm->tm_mday);
 280
 281         tm->tm_mon = bin2bcd(tm->tm_mon + 1);
 282
 283         /* epoch == 1900 */
 284         if (tm->tm_year < 100 || tm->tm_year > 199)
 285                 return -EINVAL;
 286         tm->tm_year = bin2bcd(tm->tm_year - 100);
 287
 288         return 0;
 289 }
 290
 291 static void bcd2tm(struct rtc_time *tm)
 292 {
 293         tm->tm_sec = bcd2bin(tm->tm_sec);
 294         tm->tm_min = bcd2bin(tm->tm_min);
 295         tm->tm_hour = bcd2bin(tm->tm_hour);
 296         tm->tm_mday = bcd2bin(tm->tm_mday);
 297         tm->tm_mon = bcd2bin(tm->tm_mon) - 1;
 298         /* epoch == 1900 */
 299         tm->tm_year = bcd2bin(tm->tm_year) + 100;
 300 }
 301
 302 static void omap_rtc_read_time_raw(struct omap_rtc *rtc, struct rtc_time *tm)
 303 {
 304         tm->tm_sec = rtc_read(rtc, OMAP_RTC_SECONDS_REG);
 305         tm->tm_min = rtc_read(rtc, OMAP_RTC_MINUTES_REG);
 306         tm->tm_hour = rtc_read(rtc, OMAP_RTC_HOURS_REG);
 307         tm->tm_mday = rtc_read(rtc, OMAP_RTC_DAYS_REG);
 308         tm->tm_mon = rtc_read(rtc, OMAP_RTC_MONTHS_REG);
 309         tm->tm_year = rtc_read(rtc, OMAP_RTC_YEARS_REG);
 310 }
 311
 312 static int omap_rtc_read_time(struct device *dev, struct rtc_time *tm)
 313 {
 314         struct omap_rtc *rtc = dev_get_drvdata(dev);
 315
 316         /* we don't report wday/yday/isdst ... */
 317         local_irq_disable();
 318         rtc_wait_not_busy(rtc);
 319         omap_rtc_read_time_raw(rtc, tm);
 320         local_irq_enable();
 321
 322         bcd2tm(tm);
 323
 324         return 0;
 325 }
 326
 327 static int omap_rtc_set_time(struct device *dev, struct rtc_time *tm)
 328 {
 329         struct omap_rtc *rtc = dev_get_drvdata(dev);
 330
 331         if (tm2bcd(tm) < 0)
 332                 return -EINVAL;
 333
 334         local_irq_disable();
 335         rtc_wait_not_busy(rtc);
 336
 337         rtc->type->unlock(rtc);
 338         rtc_write(rtc, OMAP_RTC_YEARS_REG, tm->tm_year);
 339         rtc_write(rtc, OMAP_RTC_MONTHS_REG, tm->tm_mon);
 340         rtc_write(rtc, OMAP_RTC_DAYS_REG, tm->tm_mday);
 341         rtc_write(rtc, OMAP_RTC_HOURS_REG, tm->tm_hour);
 342         rtc_write(rtc, OMAP_RTC_MINUTES_REG, tm->tm_min);
 343         rtc_write(rtc, OMAP_RTC_SECONDS_REG, tm->tm_sec);
 344         rtc->type->lock(rtc);
 345
 346         local_irq_enable();
 347
 348         return 0;
 349 }
 350
 351 static int omap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
 352 {
 353         struct omap_rtc *rtc = dev_get_drvdata(dev);
 354         u8 interrupts;
 355
 356         local_irq_disable();
 357         rtc_wait_not_busy(rtc);
 358
 359         alm->time.tm_sec = rtc_read(rtc, OMAP_RTC_ALARM_SECONDS_REG);
 360         alm->time.tm_min = rtc_read(rtc, OMAP_RTC_ALARM_MINUTES_REG);
 361         alm->time.tm_hour = rtc_read(rtc, OMAP_RTC_ALARM_HOURS_REG);
 362         alm->time.tm_mday = rtc_read(rtc, OMAP_RTC_ALARM_DAYS_REG);
 363         alm->time.tm_mon = rtc_read(rtc, OMAP_RTC_ALARM_MONTHS_REG);
 364         alm->time.tm_year = rtc_read(rtc, OMAP_RTC_ALARM_YEARS_REG);
 365
 366         local_irq_enable();
 367
 368         bcd2tm(&alm->time);
 369
 370         interrupts = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
 371         alm->enabled = !!(interrupts & OMAP_RTC_INTERRUPTS_IT_ALARM);
 372
 373         return 0;
 374 }
 375
 376 static int omap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
 377 {
 378         struct omap_rtc *rtc = dev_get_drvdata(dev);
 379         u8 reg, irqwake_reg = 0;
 380
 381         if (tm2bcd(&alm->time) < 0)
 382                 return -EINVAL;
 383
 384         local_irq_disable();
 385         rtc_wait_not_busy(rtc);
 386
 387         rtc->type->unlock(rtc);
 388         rtc_write(rtc, OMAP_RTC_ALARM_YEARS_REG, alm->time.tm_year);
 389         rtc_write(rtc, OMAP_RTC_ALARM_MONTHS_REG, alm->time.tm_mon);
 390         rtc_write(rtc, OMAP_RTC_ALARM_DAYS_REG, alm->time.tm_mday);
 391         rtc_write(rtc, OMAP_RTC_ALARM_HOURS_REG, alm->time.tm_hour);
 392         rtc_write(rtc, OMAP_RTC_ALARM_MINUTES_REG, alm->time.tm_min);
 393         rtc_write(rtc, OMAP_RTC_ALARM_SECONDS_REG, alm->time.tm_sec);
 394
 395         reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
 396         if (rtc->type->has_irqwakeen)
 397                 irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
 398
 399         if (alm->enabled) {
 400                 reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
 401                 irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
 402         } else {
 403                 reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
 404                 irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
 405         }
 406         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
 407         if (rtc->type->has_irqwakeen)
 408                 rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
 409         rtc->type->lock(rtc);
 410
 411         local_irq_enable();
 412
 413         return 0;
 414 }
 415
 416 static struct omap_rtc *omap_rtc_power_off_rtc;
 417
 418 /**
 419  * omap_rtc_power_off_program: Set the pmic power off sequence. The RTC
 420  * generates pmic_pwr_enable control, which can be used to control an external
 421  * PMIC.
 422  */
 423 int omap_rtc_power_off_program(struct device *dev)
 424 {
 425         struct omap_rtc *rtc = omap_rtc_power_off_rtc;
 426         struct rtc_time tm;
 427         unsigned long now;
 428         int seconds;
 429         u32 val;
 430
 431         rtc->type->unlock(rtc);
 432         /* enable pmic_power_en control */
 433         val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
 434         rtc_writel(rtc, OMAP_RTC_PMIC_REG, val | OMAP_RTC_PMIC_POWER_EN_EN);
 435
 436 again:
 437         /* Clear any existing ALARM2 event */
 438         rtc_writel(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM2);
 439
 440         /* set alarm one second from now */
 441         omap_rtc_read_time_raw(rtc, &tm);
 442         seconds = tm.tm_sec;
 443         bcd2tm(&tm);
 444         rtc_tm_to_time(&tm, &now);
 445         rtc_time_to_tm(now + 1, &tm);
 446
 447         if (tm2bcd(&tm) < 0) {
 448                 dev_err(&rtc->rtc->dev, "power off failed\n");
 449                 rtc->type->lock(rtc);
 450                 return -EINVAL;
 451         }
 452
 453         rtc_wait_not_busy(rtc);
 454
 455         rtc_write(rtc, OMAP_RTC_ALARM2_SECONDS_REG, tm.tm_sec);
 456         rtc_write(rtc, OMAP_RTC_ALARM2_MINUTES_REG, tm.tm_min);
 457         rtc_write(rtc, OMAP_RTC_ALARM2_HOURS_REG, tm.tm_hour);
 458         rtc_write(rtc, OMAP_RTC_ALARM2_DAYS_REG, tm.tm_mday);
 459         rtc_write(rtc, OMAP_RTC_ALARM2_MONTHS_REG, tm.tm_mon);
 460         rtc_write(rtc, OMAP_RTC_ALARM2_YEARS_REG, tm.tm_year);
 461
 462         /*
 463          * enable ALARM2 interrupt
 464          *
 465          * NOTE: this fails on AM3352 if rtc_write (writeb) is used
 466          */
 467         val = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
 468         rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG,
 469                         val | OMAP_RTC_INTERRUPTS_IT_ALARM2);
 470
 471         /* Retry in case roll over happened before alarm was armed. */
 472         if (rtc_read(rtc, OMAP_RTC_SECONDS_REG) != seconds) {
 473                 val = rtc_read(rtc, OMAP_RTC_STATUS_REG);
 474                 if (!(val & OMAP_RTC_STATUS_ALARM2))
 475                         goto again;
 476         }
 477
 478         rtc->type->lock(rtc);
 479
 480         return 0;
 481 }
 482 EXPORT_SYMBOL(omap_rtc_power_off_program);
 483
 484 /*
 485  * omap_rtc_poweroff: RTC-controlled power off
 486  *
 487  * The RTC can be used to control an external PMIC via the pmic_power_en pin,
 488  * which can be configured to transition to OFF on ALARM2 events.
 489  *
 490  * Notes:
 491  * The one-second alarm offset is the shortest offset possible as the alarm
 492  * registers must be set before the next timer update and the offset
 493  * calculation is too heavy for everything to be done within a single access
 494  * period (~15 us).
 495  *
 496  * Called with local interrupts disabled.
 497  */
 498 static void omap_rtc_power_off(void)
 499 {
 500         struct rtc_device *rtc = omap_rtc_power_off_rtc->rtc;
 501         u32 val;
 502
 503         omap_rtc_power_off_program(rtc->dev.parent);
 504
 505         /* Set PMIC power enable and EXT_WAKEUP in case PB power on is used */
 506         omap_rtc_power_off_rtc->type->unlock(omap_rtc_power_off_rtc);
 507         val = rtc_readl(omap_rtc_power_off_rtc, OMAP_RTC_PMIC_REG);
 508         val |= OMAP_RTC_PMIC_POWER_EN_EN | OMAP_RTC_PMIC_EXT_WKUP_POL(0) |
 509                         OMAP_RTC_PMIC_EXT_WKUP_EN(0);
 510         rtc_writel(omap_rtc_power_off_rtc, OMAP_RTC_PMIC_REG, val);
 511         omap_rtc_power_off_rtc->type->lock(omap_rtc_power_off_rtc);
 512
 513         /*
 514          * Wait for alarm to trigger (within one second) and external PMIC to
 515          * power off the system. Add a 500 ms margin for external latencies
 516          * (e.g. debounce circuits).
 517          */
 518         mdelay(1500);
 519 }
 520
 521 static const struct rtc_class_ops omap_rtc_ops = {
 522         .read_time      = omap_rtc_read_time,
 523         .set_time       = omap_rtc_set_time,
 524         .read_alarm     = omap_rtc_read_alarm,
 525         .set_alarm      = omap_rtc_set_alarm,
 526         .alarm_irq_enable = omap_rtc_alarm_irq_enable,
 527 };
 528
 529 static const struct omap_rtc_device_type omap_rtc_default_type = {
 530         .has_power_up_reset = true,
 531         .lock           = default_rtc_lock,
 532         .unlock         = default_rtc_unlock,
 533 };
 534
 535 static const struct omap_rtc_device_type omap_rtc_am3352_type = {
 536         .has_32kclk_en  = true,
 537         .has_irqwakeen  = true,
 538         .has_pmic_mode  = true,
 539         .lock           = am3352_rtc_lock,
 540         .unlock         = am3352_rtc_unlock,
 541 };
 542
 543 static const struct omap_rtc_device_type omap_rtc_da830_type = {
 544         .lock           = am3352_rtc_lock,
 545         .unlock         = am3352_rtc_unlock,
 546 };
 547
 548 static const struct platform_device_id omap_rtc_id_table[] = {
 549         {
 550                 .name   = "omap_rtc",
 551                 .driver_data = (kernel_ulong_t)&omap_rtc_default_type,
 552         }, {
 553                 .name   = "am3352-rtc",
 554                 .driver_data = (kernel_ulong_t)&omap_rtc_am3352_type,
 555         }, {
 556                 .name   = "da830-rtc",
 557                 .driver_data = (kernel_ulong_t)&omap_rtc_da830_type,
 558         }, {
 559                 /* sentinel */
 560         }
 561 };
 562 MODULE_DEVICE_TABLE(platform, omap_rtc_id_table);
 563
 564 static const struct of_device_id omap_rtc_of_match[] = {
 565         {
 566                 .compatible     = "ti,am3352-rtc",
 567                 .data           = &omap_rtc_am3352_type,
 568         }, {
 569                 .compatible     = "ti,da830-rtc",
 570                 .data           = &omap_rtc_da830_type,
 571         }, {
 572                 /* sentinel */
 573         }
 574 };
 575 MODULE_DEVICE_TABLE(of, omap_rtc_of_match);
 576
 577 static const struct pinctrl_pin_desc rtc_pins_desc[] = {
 578         PINCTRL_PIN(0, "ext_wakeup0"),
 579         PINCTRL_PIN(1, "ext_wakeup1"),
 580         PINCTRL_PIN(2, "ext_wakeup2"),
 581         PINCTRL_PIN(3, "ext_wakeup3"),
 582 };
 583
 584 static int rtc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
 585 {
 586         return 0;
 587 }
 588
 589 static const char *rtc_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
 590                                         unsigned int group)
 591 {
 592         return NULL;
 593 }
 594
 595 static const struct pinctrl_ops rtc_pinctrl_ops = {
 596         .get_groups_count = rtc_pinctrl_get_groups_count,
 597         .get_group_name = rtc_pinctrl_get_group_name,
 598         .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
 599         .dt_free_map = pinconf_generic_dt_free_map,
 600 };
 601
 602 #define PIN_CONFIG_ACTIVE_HIGH          (PIN_CONFIG_END + 1)
 603
 604 static const struct pinconf_generic_params rtc_params[] = {
 605         {"ti,active-high", PIN_CONFIG_ACTIVE_HIGH, 0},
 606 };
 607
 608 #ifdef CONFIG_DEBUG_FS
 609 static const struct pin_config_item rtc_conf_items[ARRAY_SIZE(rtc_params)] = {
 610         PCONFDUMP(PIN_CONFIG_ACTIVE_HIGH, "input active high", NULL, false),
 611 };
 612 #endif
 613
 614 static int rtc_pinconf_get(struct pinctrl_dev *pctldev,
 615                         unsigned int pin, unsigned long *config)
 616 {
 617         struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev);
 618         unsigned int param = pinconf_to_config_param(*config);
 619         u32 val;
 620         u16 arg = 0;
 621
 622         val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
 623
 624         switch (param) {
 625         case PIN_CONFIG_INPUT_ENABLE:
 626                 if (!(val & OMAP_RTC_PMIC_EXT_WKUP_EN(pin)))
 627                         return -EINVAL;
 628                 break;
 629         case PIN_CONFIG_ACTIVE_HIGH:
 630                 if (val & OMAP_RTC_PMIC_EXT_WKUP_POL(pin))
 631                         return -EINVAL;
 632                 break;
 633         default:
 634                 return -ENOTSUPP;
 635         };
 636
 637         *config = pinconf_to_config_packed(param, arg);
 638
 639         return 0;
 640 }
 641
 642 static int rtc_pinconf_set(struct pinctrl_dev *pctldev,
 643                         unsigned int pin, unsigned long *configs,
 644                         unsigned int num_configs)
 645 {
 646         struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev);
 647         u32 val;
 648         unsigned int param;
 649         u32 param_val;
 650         int i;
 651
 652         val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
 653
 654         /* active low by default */
 655         val |= OMAP_RTC_PMIC_EXT_WKUP_POL(pin);
 656
 657         for (i = 0; i < num_configs; i++) {
 658                 param = pinconf_to_config_param(configs[i]);
 659                 param_val = pinconf_to_config_argument(configs[i]);
 660
 661                 switch (param) {
 662                 case PIN_CONFIG_INPUT_ENABLE:
 663                         if (param_val)
 664                                 val |= OMAP_RTC_PMIC_EXT_WKUP_EN(pin);
 665                         else
 666                                 val &= ~OMAP_RTC_PMIC_EXT_WKUP_EN(pin);
 667                         break;
 668                 case PIN_CONFIG_ACTIVE_HIGH:
 669                         val &= ~OMAP_RTC_PMIC_EXT_WKUP_POL(pin);
 670                         break;
 671                 default:
 672                         dev_err(&rtc->rtc->dev, "Property %u not supported\n",
 673                                 param);
 674                         return -ENOTSUPP;
 675                 }
 676         }
 677
 678         rtc->type->unlock(rtc);
 679         rtc_writel(rtc, OMAP_RTC_PMIC_REG, val);
 680         rtc->type->lock(rtc);
 681
 682         return 0;
 683 }
 684
 685 static const struct pinconf_ops rtc_pinconf_ops = {
 686         .is_generic = true,
 687         .pin_config_get = rtc_pinconf_get,
 688         .pin_config_set = rtc_pinconf_set,
 689 };
 690
 691 static struct pinctrl_desc rtc_pinctrl_desc = {
 692         .pins = rtc_pins_desc,
 693         .npins = ARRAY_SIZE(rtc_pins_desc),
 694         .pctlops = &rtc_pinctrl_ops,
 695         .confops = &rtc_pinconf_ops,
 696         .custom_params = rtc_params,
 697         .num_custom_params = ARRAY_SIZE(rtc_params),
 698 #ifdef CONFIG_DEBUG_FS
 699         .custom_conf_items = rtc_conf_items,
 700 #endif
 701         .owner = THIS_MODULE,
 702 };
 703
 704 static int omap_rtc_scratch_read(void *priv, unsigned int offset, void *_val,
 705                                  size_t bytes)
 706 {
 707         struct omap_rtc *rtc = priv;
 708         u32 *val = _val;
 709         int i;
 710
 711         for (i = 0; i < bytes / 4; i++)
 712                 val[i] = rtc_readl(rtc,
 713                                    OMAP_RTC_SCRATCH0_REG + offset + (i * 4));
 714
 715         return 0;
 716 }
 717
 718 static int omap_rtc_scratch_write(void *priv, unsigned int offset, void *_val,
 719                                   size_t bytes)
 720 {
 721         struct omap_rtc *rtc = priv;
 722         u32 *val = _val;
 723         int i;
 724
 725         rtc->type->unlock(rtc);
 726         for (i = 0; i < bytes / 4; i++)
 727                 rtc_writel(rtc,
 728                            OMAP_RTC_SCRATCH0_REG + offset + (i * 4), val[i]);
 729         rtc->type->lock(rtc);
 730
 731         return 0;
 732 }
 733
 734 static struct nvmem_config omap_rtc_nvmem_config = {
 735         .name = "omap_rtc_scratch",
 736         .word_size = 4,
 737         .stride = 4,
 738         .size = OMAP_RTC_KICK0_REG - OMAP_RTC_SCRATCH0_REG,
 739         .reg_read = omap_rtc_scratch_read,
 740         .reg_write = omap_rtc_scratch_write,
 741 };
 742
 743 static int omap_rtc_probe(struct platform_device *pdev)
 744 {
 745         struct omap_rtc *rtc;
 746         struct resource *res;
 747         u8 reg, mask, new_ctrl;
 748         const struct platform_device_id *id_entry;
 749         const struct of_device_id *of_id;
 750         int ret;
 751
 752         rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
 753         if (!rtc)
 754                 return -ENOMEM;
 755
 756         of_id = of_match_device(omap_rtc_of_match, &pdev->dev);
 757         if (of_id) {
 758                 rtc->type = of_id->data;
 759                 rtc->is_pmic_controller = rtc->type->has_pmic_mode &&
 760                         of_device_is_system_power_controller(pdev->dev.of_node);
 761         } else {
 762                 id_entry = platform_get_device_id(pdev);
 763                 rtc->type = (void *)id_entry->driver_data;
 764         }
 765
 766         rtc->irq_timer = platform_get_irq(pdev, 0);
 767         if (rtc->irq_timer <= 0)
 768                 return -ENOENT;
 769
 770         rtc->irq_alarm = platform_get_irq(pdev, 1);
 771         if (rtc->irq_alarm <= 0)
 772                 return -ENOENT;
 773
 774         rtc->clk = devm_clk_get(&pdev->dev, "ext-clk");
 775         if (!IS_ERR(rtc->clk))
 776                 rtc->has_ext_clk = true;
 777         else
 778                 rtc->clk = devm_clk_get(&pdev->dev, "int-clk");
 779
 780         if (!IS_ERR(rtc->clk))
 781                 clk_prepare_enable(rtc->clk);
 782
 783         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 784         rtc->base = devm_ioremap_resource(&pdev->dev, res);
 785         if (IS_ERR(rtc->base)) {
 786                 clk_disable_unprepare(rtc->clk);
 787                 return PTR_ERR(rtc->base);
 788         }
 789
 790         platform_set_drvdata(pdev, rtc);
 791
 792         /* Enable the clock/module so that we can access the registers */
 793         pm_runtime_enable(&pdev->dev);
 794         pm_runtime_get_sync(&pdev->dev);
 795
 796         rtc->type->unlock(rtc);
 797
 798         /*
 799          * disable interrupts
 800          *
 801          * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used
 802          */
 803         rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
 804
 805         /* enable RTC functional clock */
 806         if (rtc->type->has_32kclk_en) {
 807                 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
 808                 rtc_writel(rtc, OMAP_RTC_OSC_REG,
 809                                 reg | OMAP_RTC_OSC_32KCLK_EN);
 810         }
 811
 812         /* clear old status */
 813         reg = rtc_read(rtc, OMAP_RTC_STATUS_REG);
 814
 815         mask = OMAP_RTC_STATUS_ALARM;
 816
 817         if (rtc->type->has_pmic_mode)
 818                 mask |= OMAP_RTC_STATUS_ALARM2;
 819
 820         if (rtc->type->has_power_up_reset) {
 821                 mask |= OMAP_RTC_STATUS_POWER_UP;
 822                 if (reg & OMAP_RTC_STATUS_POWER_UP)
 823                         dev_info(&pdev->dev, "RTC power up reset detected\n");
 824         }
 825
 826         if (reg & mask)
 827                 rtc_write(rtc, OMAP_RTC_STATUS_REG, reg & mask);
 828
 829         /* On boards with split power, RTC_ON_NOFF won't reset the RTC */
 830         reg = rtc_read(rtc, OMAP_RTC_CTRL_REG);
 831         if (reg & OMAP_RTC_CTRL_STOP)
 832                 dev_info(&pdev->dev, "already running\n");
 833
 834         /* force to 24 hour mode */
 835         new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP);
 836         new_ctrl |= OMAP_RTC_CTRL_STOP;
 837
 838         /*
 839          * BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
 840          *
 841          *  - Device wake-up capability setting should come through chip
 842          *    init logic. OMAP1 boards should initialize the "wakeup capable"
 843          *    flag in the platform device if the board is wired right for
 844          *    being woken up by RTC alarm. For OMAP-L138, this capability
 845          *    is built into the SoC by the "Deep Sleep" capability.
 846          *
 847          *  - Boards wired so RTC_ON_nOFF is used as the reset signal,
 848          *    rather than nPWRON_RESET, should forcibly enable split
 849          *    power mode.  (Some chip errata report that RTC_CTRL_SPLIT
 850          *    is write-only, and always reads as zero...)
 851          */
 852
 853         if (new_ctrl & OMAP_RTC_CTRL_SPLIT)
 854                 dev_info(&pdev->dev, "split power mode\n");
 855
 856         if (reg != new_ctrl)
 857                 rtc_write(rtc, OMAP_RTC_CTRL_REG, new_ctrl);
 858
 859         /*
 860          * If we have the external clock then switch to it so we can keep
 861          * ticking across suspend.
 862          */
 863         if (rtc->has_ext_clk) {
 864                 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
 865                 reg &= ~OMAP_RTC_OSC_OSC32K_GZ_DISABLE;
 866                 reg |= OMAP_RTC_OSC_32KCLK_EN | OMAP_RTC_OSC_SEL_32KCLK_SRC;
 867                 rtc_writel(rtc, OMAP_RTC_OSC_REG, reg);
 868         }
 869
 870         rtc->type->lock(rtc);
 871
 872         device_init_wakeup(&pdev->dev, true);
 873
 874         rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
 875         if (IS_ERR(rtc->rtc)) {
 876                 ret = PTR_ERR(rtc->rtc);
 877                 goto err;
 878         }
 879
 880         rtc->rtc->ops = &omap_rtc_ops;
 881         omap_rtc_nvmem_config.priv = rtc;
 882
 883         /* handle periodic and alarm irqs */
 884         ret = devm_request_irq(&pdev->dev, rtc->irq_timer, rtc_irq, 0,
 885                         dev_name(&rtc->rtc->dev), rtc);
 886         if (ret)
 887                 goto err;
 888
 889         if (rtc->irq_timer != rtc->irq_alarm) {
 890                 ret = devm_request_irq(&pdev->dev, rtc->irq_alarm, rtc_irq, 0,
 891                                 dev_name(&rtc->rtc->dev), rtc);
 892                 if (ret)
 893                         goto err;
 894         }
 895
 896         /* Support ext_wakeup pinconf */
 897         rtc_pinctrl_desc.name = dev_name(&pdev->dev);
 898
 899         rtc->pctldev = pinctrl_register(&rtc_pinctrl_desc, &pdev->dev, rtc);
 900         if (IS_ERR(rtc->pctldev)) {
 901                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 902                 ret = PTR_ERR(rtc->pctldev);
 903                 goto err;
 904         }
 905
 906         ret = rtc_register_device(rtc->rtc);
 907         if (ret)
 908                 goto err_deregister_pinctrl;
 909
 910         rtc_nvmem_register(rtc->rtc, &omap_rtc_nvmem_config);
 911
 912         if (rtc->is_pmic_controller) {
 913                 if (!pm_power_off) {
 914                         omap_rtc_power_off_rtc = rtc;
 915                         pm_power_off = omap_rtc_power_off;
 916                 }
 917         }
 918
 919         return 0;
 920
 921 err_deregister_pinctrl:
 922         pinctrl_unregister(rtc->pctldev);
 923 err:
 924         clk_disable_unprepare(rtc->clk);
 925         device_init_wakeup(&pdev->dev, false);
 926         rtc->type->lock(rtc);
 927         pm_runtime_put_sync(&pdev->dev);
 928         pm_runtime_disable(&pdev->dev);
 929
 930         return ret;
 931 }
 932
 933 static int omap_rtc_remove(struct platform_device *pdev)
 934 {
 935         struct omap_rtc *rtc = platform_get_drvdata(pdev);
 936         u8 reg;
 937
 938         if (pm_power_off == omap_rtc_power_off &&
 939                         omap_rtc_power_off_rtc == rtc) {
 940                 pm_power_off = NULL;
 941                 omap_rtc_power_off_rtc = NULL;
 942         }
 943
 944         device_init_wakeup(&pdev->dev, 0);
 945
 946         if (!IS_ERR(rtc->clk))
 947                 clk_disable_unprepare(rtc->clk);
 948
 949         rtc->type->unlock(rtc);
 950         /* leave rtc running, but disable irqs */
 951         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
 952
 953         if (rtc->has_ext_clk) {
 954                 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
 955                 reg &= ~OMAP_RTC_OSC_SEL_32KCLK_SRC;
 956                 rtc_write(rtc, OMAP_RTC_OSC_REG, reg);
 957         }
 958
 959         rtc->type->lock(rtc);
 960
 961         /* Disable the clock/module */
 962         pm_runtime_put_sync(&pdev->dev);
 963         pm_runtime_disable(&pdev->dev);
 964
 965         /* Remove ext_wakeup pinconf */
 966         pinctrl_unregister(rtc->pctldev);
 967
 968         return 0;
 969 }
 970
 971 static int __maybe_unused omap_rtc_suspend(struct device *dev)
 972 {
 973         struct omap_rtc *rtc = dev_get_drvdata(dev);
 974
 975         rtc->interrupts_reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
 976
 977         rtc->type->unlock(rtc);
 978         /*
 979          * FIXME: the RTC alarm is not currently acting as a wakeup event
 980          * source on some platforms, and in fact this enable() call is just
 981          * saving a flag that's never used...
 982          */
 983         if (device_may_wakeup(dev))
 984                 enable_irq_wake(rtc->irq_alarm);
 985         else
 986                 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
 987         rtc->type->lock(rtc);
 988
 989         rtc->is_suspending = true;
 990
 991         return 0;
 992 }
 993
 994 static int __maybe_unused omap_rtc_resume(struct device *dev)
 995 {
 996         struct omap_rtc *rtc = dev_get_drvdata(dev);
 997
 998         rtc->type->unlock(rtc);
 999         if (device_may_wakeup(dev))
1000                 disable_irq_wake(rtc->irq_alarm);
1001         else
1002                 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, rtc->interrupts_reg);
1003         rtc->type->lock(rtc);
1004
1005         rtc->is_suspending = false;
1006
1007         return 0;
1008 }
1009
1010 static int __maybe_unused omap_rtc_runtime_suspend(struct device *dev)
1011 {
1012         struct omap_rtc *rtc = dev_get_drvdata(dev);
1013
1014         if (rtc->is_suspending && !rtc->has_ext_clk)
1015                 return -EBUSY;
1016
1017         return 0;
1018 }
1019
1020 static const struct dev_pm_ops omap_rtc_pm_ops = {
1021         SET_SYSTEM_SLEEP_PM_OPS(omap_rtc_suspend, omap_rtc_resume)
1022         SET_RUNTIME_PM_OPS(omap_rtc_runtime_suspend, NULL, NULL)
1023 };
1024
1025 static void omap_rtc_shutdown(struct platform_device *pdev)
1026 {
1027         struct omap_rtc *rtc = platform_get_drvdata(pdev);
1028         u8 mask;
1029
1030         /*
1031          * Keep the ALARM interrupt enabled to allow the system to power up on
1032          * alarm events.
1033          */
1034         rtc->type->unlock(rtc);
1035         mask = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
1036         mask &= OMAP_RTC_INTERRUPTS_IT_ALARM;
1037         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, mask);
1038         rtc->type->lock(rtc);
1039 }
1040
1041 static struct platform_driver omap_rtc_driver = {
1042         .probe          = omap_rtc_probe,
1043         .remove         = omap_rtc_remove,
1044         .shutdown       = omap_rtc_shutdown,
1045         .driver         = {
1046                 .name   = "omap_rtc",
1047                 .pm     = &omap_rtc_pm_ops,
1048                 .of_match_table = omap_rtc_of_match,
1049         },
1050         .id_table       = omap_rtc_id_table,
1051 };
1052
1053 module_platform_driver(omap_rtc_driver);
1054
1055 MODULE_ALIAS("platform:omap_rtc");
1056 MODULE_AUTHOR("George G. Davis (and others)");
1057 MODULE_LICENSE("GPL");