1 // SPDX-License-Identifier: GPL-2.0-only
3 * An SPI driver for the Philips PCF2123 RTC
4 * Copyright 2009 Cyber Switching, Inc.
6 * Author: Chris Verges <chrisv@cyberswitching.com>
7 * Maintainers: http://www.cyberswitching.com
9 * based on the RS5C348 driver in this same directory.
11 * Thanks to Christian Pellegrin <chripell@fsfe.org> for
12 * the sysfs contributions to this driver.
14 * Please note that the CS is active high, so platform data
15 * should look something like:
17 * static struct spi_board_info ek_spi_devices[] = {
20 * .modalias = "rtc-pcf2123",
22 * .controller_data = (void *)AT91_PIN_PA10,
23 * .max_speed_hz = 1000 * 1000,
24 * .mode = SPI_CS_HIGH,
31 #include <linux/bcd.h>
32 #include <linux/delay.h>
33 #include <linux/device.h>
34 #include <linux/errno.h>
35 #include <linux/init.h>
36 #include <linux/kernel.h>
38 #include <linux/string.h>
39 #include <linux/slab.h>
40 #include <linux/rtc.h>
41 #include <linux/spi/spi.h>
42 #include <linux/module.h>
43 #include <linux/regmap.h>
46 #define PCF2123_REG_CTRL1 (0x00) /* Control Register 1 */
47 #define PCF2123_REG_CTRL2 (0x01) /* Control Register 2 */
48 #define PCF2123_REG_SC (0x02) /* datetime */
49 #define PCF2123_REG_MN (0x03)
50 #define PCF2123_REG_HR (0x04)
51 #define PCF2123_REG_DM (0x05)
52 #define PCF2123_REG_DW (0x06)
53 #define PCF2123_REG_MO (0x07)
54 #define PCF2123_REG_YR (0x08)
55 #define PCF2123_REG_ALRM_MN (0x09) /* Alarm Registers */
56 #define PCF2123_REG_ALRM_HR (0x0a)
57 #define PCF2123_REG_ALRM_DM (0x0b)
58 #define PCF2123_REG_ALRM_DW (0x0c)
59 #define PCF2123_REG_OFFSET (0x0d) /* Clock Rate Offset Register */
60 #define PCF2123_REG_TMR_CLKOUT (0x0e) /* Timer Registers */
61 #define PCF2123_REG_CTDWN_TMR (0x0f)
63 /* PCF2123_REG_CTRL1 BITS */
64 #define CTRL1_CLEAR (0) /* Clear */
65 #define CTRL1_CORR_INT BIT(1) /* Correction irq enable */
66 #define CTRL1_12_HOUR BIT(2) /* 12 hour time */
67 #define CTRL1_SW_RESET (BIT(3) | BIT(4) | BIT(6)) /* Software reset */
68 #define CTRL1_STOP BIT(5) /* Stop the clock */
69 #define CTRL1_EXT_TEST BIT(7) /* External clock test mode */
71 /* PCF2123_REG_CTRL2 BITS */
72 #define CTRL2_TIE BIT(0) /* Countdown timer irq enable */
73 #define CTRL2_AIE BIT(1) /* Alarm irq enable */
74 #define CTRL2_TF BIT(2) /* Countdown timer flag */
75 #define CTRL2_AF BIT(3) /* Alarm flag */
76 #define CTRL2_TI_TP BIT(4) /* Irq pin generates pulse */
77 #define CTRL2_MSF BIT(5) /* Minute or second irq flag */
78 #define CTRL2_SI BIT(6) /* Second irq enable */
79 #define CTRL2_MI BIT(7) /* Minute irq enable */
81 /* PCF2123_REG_SC BITS */
82 #define OSC_HAS_STOPPED BIT(7) /* Clock has been stopped */
84 /* PCF2123_REG_ALRM_XX BITS */
85 #define ALRM_ENABLE BIT(7) /* MN, HR, DM, or DW alarm enable */
87 /* PCF2123_REG_TMR_CLKOUT BITS */
88 #define CD_TMR_4096KHZ (0) /* 4096 KHz countdown timer */
89 #define CD_TMR_64HZ (1) /* 64 Hz countdown timer */
90 #define CD_TMR_1HZ (2) /* 1 Hz countdown timer */
91 #define CD_TMR_60th_HZ (3) /* 60th Hz countdown timer */
92 #define CD_TMR_TE BIT(3) /* Countdown timer enable */
94 /* PCF2123_REG_OFFSET BITS */
95 #define OFFSET_SIGN_BIT 6 /* 2's complement sign bit */
96 #define OFFSET_COARSE BIT(7) /* Coarse mode offset */
97 #define OFFSET_STEP (2170) /* Offset step in parts per billion */
98 #define OFFSET_MASK GENMASK(6, 0) /* Offset value */
100 /* READ/WRITE ADDRESS BITS */
101 #define PCF2123_WRITE BIT(4)
102 #define PCF2123_READ (BIT(4) | BIT(7))
105 static struct spi_driver pcf2123_driver;
107 struct pcf2123_plat_data {
108 struct rtc_device *rtc;
112 static const struct regmap_config pcf2123_regmap_config = {
115 .read_flag_mask = PCF2123_READ,
116 .write_flag_mask = PCF2123_WRITE,
117 .max_register = PCF2123_REG_CTDWN_TMR,
120 static int pcf2123_read_offset(struct device *dev, long *offset)
122 struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
126 ret = regmap_read(pdata->map, PCF2123_REG_OFFSET, ®);
130 val = sign_extend32((reg & OFFSET_MASK), OFFSET_SIGN_BIT);
132 if (reg & OFFSET_COARSE)
135 *offset = ((long)val) * OFFSET_STEP;
141 * The offset register is a 7 bit signed value with a coarse bit in bit 7.
142 * The main difference between the two is normal offset adjusts the first
143 * second of n minutes every other hour, with 61, 62 and 63 being shoved
144 * into the 60th minute.
145 * The coarse adjustment does the same, but every hour.
146 * the two overlap, with every even normal offset value corresponding
147 * to a coarse offset. Based on this algorithm, it seems that despite the
148 * name, coarse offset is a better fit for overlapping values.
150 static int pcf2123_set_offset(struct device *dev, long offset)
152 struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
155 if (offset > OFFSET_STEP * 127)
157 else if (offset < OFFSET_STEP * -128)
160 reg = DIV_ROUND_CLOSEST(offset, OFFSET_STEP);
162 /* choose fine offset only for odd values in the normal range */
163 if (reg & 1 && reg <= 63 && reg >= -64) {
164 /* Normal offset. Clear the coarse bit */
165 reg &= ~OFFSET_COARSE;
167 /* Coarse offset. Divide by 2 and set the coarse bit */
169 reg |= OFFSET_COARSE;
172 return regmap_write(pdata->map, PCF2123_REG_OFFSET, (unsigned int)reg);
175 static int pcf2123_rtc_read_time(struct device *dev, struct rtc_time *tm)
177 struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
181 ret = regmap_bulk_read(pdata->map, PCF2123_REG_SC, rxbuf,
186 if (rxbuf[0] & OSC_HAS_STOPPED) {
187 dev_info(dev, "clock was stopped. Time is not valid\n");
191 tm->tm_sec = bcd2bin(rxbuf[0] & 0x7F);
192 tm->tm_min = bcd2bin(rxbuf[1] & 0x7F);
193 tm->tm_hour = bcd2bin(rxbuf[2] & 0x3F); /* rtc hr 0-23 */
194 tm->tm_mday = bcd2bin(rxbuf[3] & 0x3F);
195 tm->tm_wday = rxbuf[4] & 0x07;
196 tm->tm_mon = bcd2bin(rxbuf[5] & 0x1F) - 1; /* rtc mn 1-12 */
197 tm->tm_year = bcd2bin(rxbuf[6]);
198 if (tm->tm_year < 70)
199 tm->tm_year += 100; /* assume we are in 1970...2069 */
201 dev_dbg(dev, "%s: tm is %ptR\n", __func__, tm);
206 static int pcf2123_rtc_set_time(struct device *dev, struct rtc_time *tm)
208 struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
212 dev_dbg(dev, "%s: tm is %ptR\n", __func__, tm);
214 /* Stop the counter first */
215 ret = regmap_write(pdata->map, PCF2123_REG_CTRL1, CTRL1_STOP);
219 /* Set the new time */
220 txbuf[0] = bin2bcd(tm->tm_sec & 0x7F);
221 txbuf[1] = bin2bcd(tm->tm_min & 0x7F);
222 txbuf[2] = bin2bcd(tm->tm_hour & 0x3F);
223 txbuf[3] = bin2bcd(tm->tm_mday & 0x3F);
224 txbuf[4] = tm->tm_wday & 0x07;
225 txbuf[5] = bin2bcd((tm->tm_mon + 1) & 0x1F); /* rtc mn 1-12 */
226 txbuf[6] = bin2bcd(tm->tm_year < 100 ? tm->tm_year : tm->tm_year - 100);
228 ret = regmap_bulk_write(pdata->map, PCF2123_REG_SC, txbuf,
233 /* Start the counter */
234 ret = regmap_write(pdata->map, PCF2123_REG_CTRL1, CTRL1_CLEAR);
241 static int pcf2123_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
243 struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
246 unsigned int val = 0;
248 ret = regmap_bulk_read(pdata->map, PCF2123_REG_ALRM_MN, rxbuf,
253 alm->time.tm_min = bcd2bin(rxbuf[0] & 0x7F);
254 alm->time.tm_hour = bcd2bin(rxbuf[1] & 0x3F);
255 alm->time.tm_mday = bcd2bin(rxbuf[2] & 0x3F);
256 alm->time.tm_wday = bcd2bin(rxbuf[3] & 0x07);
258 dev_dbg(dev, "%s: alm is %ptR\n", __func__, &alm->time);
260 ret = regmap_read(pdata->map, PCF2123_REG_CTRL2, &val);
264 alm->enabled = !!(val & CTRL2_AIE);
269 static int pcf2123_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
271 struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
275 dev_dbg(dev, "%s: alm is %ptR\n", __func__, &alm->time);
277 /* Ensure alarm flag is clear */
278 ret = regmap_update_bits(pdata->map, PCF2123_REG_CTRL2, CTRL2_AF, 0);
282 /* Disable alarm interrupt */
283 ret = regmap_update_bits(pdata->map, PCF2123_REG_CTRL2, CTRL2_AIE, 0);
288 txbuf[0] = bin2bcd(alm->time.tm_min & 0x7F);
289 txbuf[1] = bin2bcd(alm->time.tm_hour & 0x3F);
290 txbuf[2] = bin2bcd(alm->time.tm_mday & 0x3F);
291 txbuf[3] = bin2bcd(alm->time.tm_wday & 0x07);
293 ret = regmap_bulk_write(pdata->map, PCF2123_REG_ALRM_MN, txbuf,
298 /* Enable alarm interrupt */
300 ret = regmap_update_bits(pdata->map, PCF2123_REG_CTRL2,
301 CTRL2_AIE, CTRL2_AIE);
309 static irqreturn_t pcf2123_rtc_irq(int irq, void *dev)
311 struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
312 struct mutex *lock = &pdata->rtc->ops_lock;
313 unsigned int val = 0;
317 regmap_read(pdata->map, PCF2123_REG_CTRL2, &val);
320 if (val & CTRL2_AF) {
323 /* Clear alarm flag */
324 regmap_update_bits(pdata->map, PCF2123_REG_CTRL2, CTRL2_AF, 0);
326 rtc_update_irq(pdata->rtc, 1, RTC_IRQF | RTC_AF);
334 static int pcf2123_reset(struct device *dev)
336 struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
338 unsigned int val = 0;
340 ret = regmap_write(pdata->map, PCF2123_REG_CTRL1, CTRL1_SW_RESET);
344 /* Stop the counter */
345 dev_dbg(dev, "stopping RTC\n");
346 ret = regmap_write(pdata->map, PCF2123_REG_CTRL1, CTRL1_STOP);
350 /* See if the counter was actually stopped */
351 dev_dbg(dev, "checking for presence of RTC\n");
352 ret = regmap_read(pdata->map, PCF2123_REG_CTRL1, &val);
356 dev_dbg(dev, "received data from RTC (0x%08X)\n", val);
357 if (!(val & CTRL1_STOP))
360 /* Start the counter */
361 ret = regmap_write(pdata->map, PCF2123_REG_CTRL1, CTRL1_CLEAR);
368 static const struct rtc_class_ops pcf2123_rtc_ops = {
369 .read_time = pcf2123_rtc_read_time,
370 .set_time = pcf2123_rtc_set_time,
371 .read_offset = pcf2123_read_offset,
372 .set_offset = pcf2123_set_offset,
373 .read_alarm = pcf2123_rtc_read_alarm,
374 .set_alarm = pcf2123_rtc_set_alarm,
377 static int pcf2123_probe(struct spi_device *spi)
379 struct rtc_device *rtc;
381 struct pcf2123_plat_data *pdata;
384 pdata = devm_kzalloc(&spi->dev, sizeof(struct pcf2123_plat_data),
388 spi->dev.platform_data = pdata;
390 pdata->map = devm_regmap_init_spi(spi, &pcf2123_regmap_config);
392 if (IS_ERR(pdata->map)) {
393 dev_err(&spi->dev, "regmap init failed.\n");
397 ret = pcf2123_rtc_read_time(&spi->dev, &tm);
399 ret = pcf2123_reset(&spi->dev);
401 dev_err(&spi->dev, "chip not found\n");
406 dev_info(&spi->dev, "spiclk %u KHz.\n",
407 (spi->max_speed_hz + 500) / 1000);
409 /* Finalize the initialization */
410 rtc = devm_rtc_device_register(&spi->dev, pcf2123_driver.driver.name,
411 &pcf2123_rtc_ops, THIS_MODULE);
414 dev_err(&spi->dev, "failed to register.\n");
421 /* Register alarm irq */
423 ret = devm_request_threaded_irq(&spi->dev, spi->irq, NULL,
425 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
426 pcf2123_driver.driver.name, &spi->dev);
428 device_init_wakeup(&spi->dev, true);
430 dev_err(&spi->dev, "could not request irq.\n");
433 /* The PCF2123's alarm only has minute accuracy. Must add timer
434 * support to this driver to generate interrupts more than once
437 pdata->rtc->uie_unsupported = 1;
442 spi->dev.platform_data = NULL;
447 static const struct of_device_id pcf2123_dt_ids[] = {
448 { .compatible = "nxp,rtc-pcf2123", },
449 { .compatible = "microcrystal,rv2123", },
452 MODULE_DEVICE_TABLE(of, pcf2123_dt_ids);
455 static struct spi_driver pcf2123_driver = {
457 .name = "rtc-pcf2123",
458 .of_match_table = of_match_ptr(pcf2123_dt_ids),
460 .probe = pcf2123_probe,
463 module_spi_driver(pcf2123_driver);
465 MODULE_AUTHOR("Chris Verges <chrisv@cyberswitching.com>");
466 MODULE_DESCRIPTION("NXP PCF2123 RTC driver");
467 MODULE_LICENSE("GPL");