1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
5 #include <linux/init.h>
7 #include <linux/kernel.h>
8 #include <linux/module.h>
10 #include <linux/of_device.h>
11 #include <linux/platform_device.h>
12 #include <linux/rtc.h>
13 #include <linux/clk.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/regmap.h>
17 #define SNVS_LPREGISTER_OFFSET 0x34
19 /* These register offsets are relative to LP (Low Power) range */
20 #define SNVS_LPCR 0x04
21 #define SNVS_LPSR 0x18
22 #define SNVS_LPSRTCMR 0x1c
23 #define SNVS_LPSRTCLR 0x20
24 #define SNVS_LPTAR 0x24
25 #define SNVS_LPPGDR 0x30
27 #define SNVS_LPCR_SRTC_ENV (1 << 0)
28 #define SNVS_LPCR_LPTA_EN (1 << 1)
29 #define SNVS_LPCR_LPWUI_EN (1 << 3)
30 #define SNVS_LPSR_LPTA (1 << 0)
32 #define SNVS_LPPGDR_INIT 0x41736166
33 #define CNTR_TO_SECS_SH 15
35 struct snvs_rtc_data {
36 struct rtc_device *rtc;
37 struct regmap *regmap;
43 static u32 rtc_read_lp_counter(struct snvs_rtc_data *data)
49 regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &val);
52 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &val);
55 regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &val);
58 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &val);
60 } while (read1 != read2);
62 /* Convert 47-bit counter to 32-bit raw second count */
63 return (u32) (read1 >> CNTR_TO_SECS_SH);
66 static void rtc_write_sync_lp(struct snvs_rtc_data *data)
68 u32 count1, count2, count3;
71 /* Wait for 3 CKIL cycles */
72 for (i = 0; i < 3; i++) {
74 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
75 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count2);
76 } while (count1 != count2);
78 /* Now wait until counter value changes */
81 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count2);
82 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count3);
83 } while (count2 != count3);
84 } while (count3 == count1);
88 static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
93 regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_SRTC_ENV,
94 enable ? SNVS_LPCR_SRTC_ENV : 0);
97 regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr);
100 if (lpcr & SNVS_LPCR_SRTC_ENV)
103 if (!(lpcr & SNVS_LPCR_SRTC_ENV))
114 static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm)
116 struct snvs_rtc_data *data = dev_get_drvdata(dev);
117 unsigned long time = rtc_read_lp_counter(data);
119 rtc_time_to_tm(time, tm);
124 static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm)
126 struct snvs_rtc_data *data = dev_get_drvdata(dev);
130 rtc_tm_to_time(tm, &time);
132 /* Disable RTC first */
133 ret = snvs_rtc_enable(data, false);
137 /* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */
138 regmap_write(data->regmap, data->offset + SNVS_LPSRTCLR, time << CNTR_TO_SECS_SH);
139 regmap_write(data->regmap, data->offset + SNVS_LPSRTCMR, time >> (32 - CNTR_TO_SECS_SH));
141 /* Enable RTC again */
142 ret = snvs_rtc_enable(data, true);
147 static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
149 struct snvs_rtc_data *data = dev_get_drvdata(dev);
152 regmap_read(data->regmap, data->offset + SNVS_LPTAR, &lptar);
153 rtc_time_to_tm(lptar, &alrm->time);
155 regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
156 alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0;
161 static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
163 struct snvs_rtc_data *data = dev_get_drvdata(dev);
165 regmap_update_bits(data->regmap, data->offset + SNVS_LPCR,
166 (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN),
167 enable ? (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN) : 0);
169 rtc_write_sync_lp(data);
174 static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
176 struct snvs_rtc_data *data = dev_get_drvdata(dev);
177 struct rtc_time *alrm_tm = &alrm->time;
180 rtc_tm_to_time(alrm_tm, &time);
182 regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0);
183 rtc_write_sync_lp(data);
184 regmap_write(data->regmap, data->offset + SNVS_LPTAR, time);
186 /* Clear alarm interrupt status bit */
187 regmap_write(data->regmap, data->offset + SNVS_LPSR, SNVS_LPSR_LPTA);
189 return snvs_rtc_alarm_irq_enable(dev, alrm->enabled);
192 static const struct rtc_class_ops snvs_rtc_ops = {
193 .read_time = snvs_rtc_read_time,
194 .set_time = snvs_rtc_set_time,
195 .read_alarm = snvs_rtc_read_alarm,
196 .set_alarm = snvs_rtc_set_alarm,
197 .alarm_irq_enable = snvs_rtc_alarm_irq_enable,
200 static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id)
202 struct device *dev = dev_id;
203 struct snvs_rtc_data *data = dev_get_drvdata(dev);
207 regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
209 if (lpsr & SNVS_LPSR_LPTA) {
210 events |= (RTC_AF | RTC_IRQF);
212 /* RTC alarm should be one-shot */
213 snvs_rtc_alarm_irq_enable(dev, 0);
215 rtc_update_irq(data->rtc, 1, events);
218 /* clear interrupt status */
219 regmap_write(data->regmap, data->offset + SNVS_LPSR, lpsr);
221 return events ? IRQ_HANDLED : IRQ_NONE;
224 static const struct regmap_config snvs_rtc_config = {
230 static int snvs_rtc_probe(struct platform_device *pdev)
232 struct snvs_rtc_data *data;
233 struct resource *res;
237 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
241 data->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap");
243 if (IS_ERR(data->regmap)) {
244 dev_warn(&pdev->dev, "snvs rtc: you use old dts file, please update it\n");
245 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
247 mmio = devm_ioremap_resource(&pdev->dev, res);
249 return PTR_ERR(mmio);
251 data->regmap = devm_regmap_init_mmio(&pdev->dev, mmio, &snvs_rtc_config);
253 data->offset = SNVS_LPREGISTER_OFFSET;
254 of_property_read_u32(pdev->dev.of_node, "offset", &data->offset);
257 if (IS_ERR(data->regmap)) {
258 dev_err(&pdev->dev, "Can't find snvs syscon\n");
262 data->irq = platform_get_irq(pdev, 0);
266 data->clk = devm_clk_get(&pdev->dev, "snvs-rtc");
267 if (IS_ERR(data->clk)) {
270 ret = clk_prepare_enable(data->clk);
273 "Could not prepare or enable the snvs clock\n");
278 platform_set_drvdata(pdev, data);
280 /* Initialize glitch detect */
281 regmap_write(data->regmap, data->offset + SNVS_LPPGDR, SNVS_LPPGDR_INIT);
283 /* Clear interrupt status */
284 regmap_write(data->regmap, data->offset + SNVS_LPSR, 0xffffffff);
287 ret = snvs_rtc_enable(data, true);
289 dev_err(&pdev->dev, "failed to enable rtc %d\n", ret);
290 goto error_rtc_device_register;
293 device_init_wakeup(&pdev->dev, true);
295 ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler,
296 IRQF_SHARED, "rtc alarm", &pdev->dev);
298 dev_err(&pdev->dev, "failed to request irq %d: %d\n",
300 goto error_rtc_device_register;
303 data->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
304 &snvs_rtc_ops, THIS_MODULE);
305 if (IS_ERR(data->rtc)) {
306 ret = PTR_ERR(data->rtc);
307 dev_err(&pdev->dev, "failed to register rtc: %d\n", ret);
308 goto error_rtc_device_register;
313 error_rtc_device_register:
315 clk_disable_unprepare(data->clk);
320 #ifdef CONFIG_PM_SLEEP
321 static int snvs_rtc_suspend(struct device *dev)
323 struct snvs_rtc_data *data = dev_get_drvdata(dev);
325 if (device_may_wakeup(dev))
326 return enable_irq_wake(data->irq);
331 static int snvs_rtc_suspend_noirq(struct device *dev)
333 struct snvs_rtc_data *data = dev_get_drvdata(dev);
336 clk_disable_unprepare(data->clk);
341 static int snvs_rtc_resume(struct device *dev)
343 struct snvs_rtc_data *data = dev_get_drvdata(dev);
345 if (device_may_wakeup(dev))
346 return disable_irq_wake(data->irq);
351 static int snvs_rtc_resume_noirq(struct device *dev)
353 struct snvs_rtc_data *data = dev_get_drvdata(dev);
356 return clk_prepare_enable(data->clk);
361 static const struct dev_pm_ops snvs_rtc_pm_ops = {
362 .suspend = snvs_rtc_suspend,
363 .suspend_noirq = snvs_rtc_suspend_noirq,
364 .resume = snvs_rtc_resume,
365 .resume_noirq = snvs_rtc_resume_noirq,
368 #define SNVS_RTC_PM_OPS (&snvs_rtc_pm_ops)
372 #define SNVS_RTC_PM_OPS NULL
376 static const struct of_device_id snvs_dt_ids[] = {
377 { .compatible = "fsl,sec-v4.0-mon-rtc-lp", },
380 MODULE_DEVICE_TABLE(of, snvs_dt_ids);
382 static struct platform_driver snvs_rtc_driver = {
385 .pm = SNVS_RTC_PM_OPS,
386 .of_match_table = snvs_dt_ids,
388 .probe = snvs_rtc_probe,
390 module_platform_driver(snvs_rtc_driver);
392 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
393 MODULE_DESCRIPTION("Freescale SNVS RTC Driver");
394 MODULE_LICENSE("GPL");