1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
5 #include <linux/init.h>
7 #include <linux/kernel.h>
8 #include <linux/module.h>
10 #include <linux/of_device.h>
11 #include <linux/platform_device.h>
12 #include <linux/pm_wakeirq.h>
13 #include <linux/rtc.h>
14 #include <linux/clk.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/regmap.h>
18 #define SNVS_LPREGISTER_OFFSET 0x34
20 /* These register offsets are relative to LP (Low Power) range */
21 #define SNVS_LPCR 0x04
22 #define SNVS_LPSR 0x18
23 #define SNVS_LPSRTCMR 0x1c
24 #define SNVS_LPSRTCLR 0x20
25 #define SNVS_LPTAR 0x24
26 #define SNVS_LPPGDR 0x30
28 #define SNVS_LPCR_SRTC_ENV (1 << 0)
29 #define SNVS_LPCR_LPTA_EN (1 << 1)
30 #define SNVS_LPCR_LPWUI_EN (1 << 3)
31 #define SNVS_LPSR_LPTA (1 << 0)
33 #define SNVS_LPPGDR_INIT 0x41736166
34 #define CNTR_TO_SECS_SH 15
36 struct snvs_rtc_data {
37 struct rtc_device *rtc;
38 struct regmap *regmap;
44 /* Read 64 bit timer register, which could be in inconsistent state */
45 static u64 rtc_read_lpsrt(struct snvs_rtc_data *data)
49 regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &msb);
50 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &lsb);
51 return (u64)msb << 32 | lsb;
54 /* Read the secure real time counter, taking care to deal with the cases of the
55 * counter updating while being read.
57 static u32 rtc_read_lp_counter(struct snvs_rtc_data *data)
60 unsigned int timeout = 100;
62 /* As expected, the registers might update between the read of the LSB
63 * reg and the MSB reg. It's also possible that one register might be
64 * in partially modified state as well.
66 read1 = rtc_read_lpsrt(data);
69 read1 = rtc_read_lpsrt(data);
70 } while (read1 != read2 && --timeout);
72 dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
74 /* Convert 47-bit counter to 32-bit raw second count */
75 return (u32) (read1 >> CNTR_TO_SECS_SH);
78 /* Just read the lsb from the counter, dealing with inconsistent state */
79 static int rtc_read_lp_counter_lsb(struct snvs_rtc_data *data, u32 *lsb)
82 unsigned int timeout = 100;
84 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
87 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
88 } while (count1 != count2 && --timeout);
90 dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
98 static int rtc_write_sync_lp(struct snvs_rtc_data *data)
102 unsigned int timeout = 1000;
105 ret = rtc_read_lp_counter_lsb(data, &count1);
109 /* Wait for 3 CKIL cycles, about 61.0-91.5 µs */
111 ret = rtc_read_lp_counter_lsb(data, &count2);
114 elapsed = count2 - count1; /* wrap around _is_ handled! */
115 } while (elapsed < 3 && --timeout);
117 dev_err(&data->rtc->dev, "Timeout waiting for LPSRT Counter to change\n");
123 static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
128 regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_SRTC_ENV,
129 enable ? SNVS_LPCR_SRTC_ENV : 0);
132 regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr);
135 if (lpcr & SNVS_LPCR_SRTC_ENV)
138 if (!(lpcr & SNVS_LPCR_SRTC_ENV))
149 static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm)
151 struct snvs_rtc_data *data = dev_get_drvdata(dev);
152 unsigned long time = rtc_read_lp_counter(data);
154 rtc_time_to_tm(time, tm);
159 static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm)
161 struct snvs_rtc_data *data = dev_get_drvdata(dev);
165 rtc_tm_to_time(tm, &time);
167 /* Disable RTC first */
168 ret = snvs_rtc_enable(data, false);
172 /* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */
173 regmap_write(data->regmap, data->offset + SNVS_LPSRTCLR, time << CNTR_TO_SECS_SH);
174 regmap_write(data->regmap, data->offset + SNVS_LPSRTCMR, time >> (32 - CNTR_TO_SECS_SH));
176 /* Enable RTC again */
177 ret = snvs_rtc_enable(data, true);
182 static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
184 struct snvs_rtc_data *data = dev_get_drvdata(dev);
187 regmap_read(data->regmap, data->offset + SNVS_LPTAR, &lptar);
188 rtc_time_to_tm(lptar, &alrm->time);
190 regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
191 alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0;
196 static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
198 struct snvs_rtc_data *data = dev_get_drvdata(dev);
200 regmap_update_bits(data->regmap, data->offset + SNVS_LPCR,
201 (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN),
202 enable ? (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN) : 0);
204 return rtc_write_sync_lp(data);
207 static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
209 struct snvs_rtc_data *data = dev_get_drvdata(dev);
210 struct rtc_time *alrm_tm = &alrm->time;
214 rtc_tm_to_time(alrm_tm, &time);
216 regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0);
217 ret = rtc_write_sync_lp(data);
220 regmap_write(data->regmap, data->offset + SNVS_LPTAR, time);
222 /* Clear alarm interrupt status bit */
223 regmap_write(data->regmap, data->offset + SNVS_LPSR, SNVS_LPSR_LPTA);
225 return snvs_rtc_alarm_irq_enable(dev, alrm->enabled);
228 static const struct rtc_class_ops snvs_rtc_ops = {
229 .read_time = snvs_rtc_read_time,
230 .set_time = snvs_rtc_set_time,
231 .read_alarm = snvs_rtc_read_alarm,
232 .set_alarm = snvs_rtc_set_alarm,
233 .alarm_irq_enable = snvs_rtc_alarm_irq_enable,
236 static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id)
238 struct device *dev = dev_id;
239 struct snvs_rtc_data *data = dev_get_drvdata(dev);
244 clk_enable(data->clk);
246 regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
248 if (lpsr & SNVS_LPSR_LPTA) {
249 events |= (RTC_AF | RTC_IRQF);
251 /* RTC alarm should be one-shot */
252 snvs_rtc_alarm_irq_enable(dev, 0);
254 rtc_update_irq(data->rtc, 1, events);
257 /* clear interrupt status */
258 regmap_write(data->regmap, data->offset + SNVS_LPSR, lpsr);
261 clk_disable(data->clk);
263 return events ? IRQ_HANDLED : IRQ_NONE;
266 static const struct regmap_config snvs_rtc_config = {
272 static int snvs_rtc_probe(struct platform_device *pdev)
274 struct snvs_rtc_data *data;
278 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
282 data->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap");
284 if (IS_ERR(data->regmap)) {
285 dev_warn(&pdev->dev, "snvs rtc: you use old dts file, please update it\n");
287 mmio = devm_platform_ioremap_resource(pdev, 0);
289 return PTR_ERR(mmio);
291 data->regmap = devm_regmap_init_mmio(&pdev->dev, mmio, &snvs_rtc_config);
293 data->offset = SNVS_LPREGISTER_OFFSET;
294 of_property_read_u32(pdev->dev.of_node, "offset", &data->offset);
297 if (IS_ERR(data->regmap)) {
298 dev_err(&pdev->dev, "Can't find snvs syscon\n");
302 data->irq = platform_get_irq(pdev, 0);
306 data->clk = devm_clk_get(&pdev->dev, "snvs-rtc");
307 if (IS_ERR(data->clk)) {
310 ret = clk_prepare_enable(data->clk);
313 "Could not prepare or enable the snvs clock\n");
318 platform_set_drvdata(pdev, data);
320 /* Initialize glitch detect */
321 regmap_write(data->regmap, data->offset + SNVS_LPPGDR, SNVS_LPPGDR_INIT);
323 /* Clear interrupt status */
324 regmap_write(data->regmap, data->offset + SNVS_LPSR, 0xffffffff);
327 ret = snvs_rtc_enable(data, true);
329 dev_err(&pdev->dev, "failed to enable rtc %d\n", ret);
330 goto error_rtc_device_register;
333 device_init_wakeup(&pdev->dev, true);
334 ret = dev_pm_set_wake_irq(&pdev->dev, data->irq);
336 dev_err(&pdev->dev, "failed to enable irq wake\n");
338 ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler,
339 IRQF_SHARED, "rtc alarm", &pdev->dev);
341 dev_err(&pdev->dev, "failed to request irq %d: %d\n",
343 goto error_rtc_device_register;
346 data->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
347 &snvs_rtc_ops, THIS_MODULE);
348 if (IS_ERR(data->rtc)) {
349 ret = PTR_ERR(data->rtc);
350 dev_err(&pdev->dev, "failed to register rtc: %d\n", ret);
351 goto error_rtc_device_register;
356 error_rtc_device_register:
358 clk_disable_unprepare(data->clk);
363 static int __maybe_unused snvs_rtc_suspend_noirq(struct device *dev)
365 struct snvs_rtc_data *data = dev_get_drvdata(dev);
368 clk_disable_unprepare(data->clk);
373 static int __maybe_unused snvs_rtc_resume_noirq(struct device *dev)
375 struct snvs_rtc_data *data = dev_get_drvdata(dev);
378 return clk_prepare_enable(data->clk);
383 static const struct dev_pm_ops snvs_rtc_pm_ops = {
384 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(snvs_rtc_suspend_noirq, snvs_rtc_resume_noirq)
387 static const struct of_device_id snvs_dt_ids[] = {
388 { .compatible = "fsl,sec-v4.0-mon-rtc-lp", },
391 MODULE_DEVICE_TABLE(of, snvs_dt_ids);
393 static struct platform_driver snvs_rtc_driver = {
396 .pm = &snvs_rtc_pm_ops,
397 .of_match_table = snvs_dt_ids,
399 .probe = snvs_rtc_probe,
401 module_platform_driver(snvs_rtc_driver);
403 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
404 MODULE_DESCRIPTION("Freescale SNVS RTC Driver");
405 MODULE_LICENSE("GPL");