2 * An RTC driver for Allwinner A31/A23
4 * Copyright (c) 2014, Chen-Yu Tsai <wens@csie.org>
8 * An RTC driver for Allwinner A10/A20
10 * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
23 #include <linux/clk.h>
24 #include <linux/clk-provider.h>
25 #include <linux/delay.h>
26 #include <linux/err.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
34 #include <linux/of_address.h>
35 #include <linux/of_device.h>
36 #include <linux/platform_device.h>
37 #include <linux/rtc.h>
38 #include <linux/slab.h>
39 #include <linux/types.h>
41 /* Control register */
42 #define SUN6I_LOSC_CTRL 0x0000
43 #define SUN6I_LOSC_CTRL_KEY (0x16aa << 16)
44 #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9)
45 #define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8)
46 #define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7)
47 #define SUN6I_LOSC_CTRL_EXT_OSC BIT(0)
48 #define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7)
50 #define SUN6I_LOSC_CLK_PRESCAL 0x0008
53 #define SUN6I_RTC_YMD 0x0010
54 #define SUN6I_RTC_HMS 0x0014
56 /* Alarm 0 (counter) */
57 #define SUN6I_ALRM_COUNTER 0x0020
58 #define SUN6I_ALRM_CUR_VAL 0x0024
59 #define SUN6I_ALRM_EN 0x0028
60 #define SUN6I_ALRM_EN_CNT_EN BIT(0)
61 #define SUN6I_ALRM_IRQ_EN 0x002c
62 #define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0)
63 #define SUN6I_ALRM_IRQ_STA 0x0030
64 #define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0)
66 /* Alarm 1 (wall clock) */
67 #define SUN6I_ALRM1_EN 0x0044
68 #define SUN6I_ALRM1_IRQ_EN 0x0048
69 #define SUN6I_ALRM1_IRQ_STA 0x004c
70 #define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND BIT(0)
73 #define SUN6I_ALARM_CONFIG 0x0050
74 #define SUN6I_ALARM_CONFIG_WAKEUP BIT(0)
76 #define SUN6I_LOSC_OUT_GATING 0x0060
77 #define SUN6I_LOSC_OUT_GATING_EN_OFFSET 0
82 #define SUN6I_DATE_GET_DAY_VALUE(x) ((x) & 0x0000001f)
83 #define SUN6I_DATE_GET_MON_VALUE(x) (((x) & 0x00000f00) >> 8)
84 #define SUN6I_DATE_GET_YEAR_VALUE(x) (((x) & 0x003f0000) >> 16)
85 #define SUN6I_LEAP_GET_VALUE(x) (((x) & 0x00400000) >> 22)
90 #define SUN6I_TIME_GET_SEC_VALUE(x) ((x) & 0x0000003f)
91 #define SUN6I_TIME_GET_MIN_VALUE(x) (((x) & 0x00003f00) >> 8)
92 #define SUN6I_TIME_GET_HOUR_VALUE(x) (((x) & 0x001f0000) >> 16)
97 #define SUN6I_DATE_SET_DAY_VALUE(x) ((x) & 0x0000001f)
98 #define SUN6I_DATE_SET_MON_VALUE(x) ((x) << 8 & 0x00000f00)
99 #define SUN6I_DATE_SET_YEAR_VALUE(x) ((x) << 16 & 0x003f0000)
100 #define SUN6I_LEAP_SET_VALUE(x) ((x) << 22 & 0x00400000)
105 #define SUN6I_TIME_SET_SEC_VALUE(x) ((x) & 0x0000003f)
106 #define SUN6I_TIME_SET_MIN_VALUE(x) ((x) << 8 & 0x00003f00)
107 #define SUN6I_TIME_SET_HOUR_VALUE(x) ((x) << 16 & 0x001f0000)
110 * The year parameter passed to the driver is usually an offset relative to
111 * the year 1900. This macro is used to convert this offset to another one
112 * relative to the minimum year allowed by the hardware.
114 * The year range is 1970 - 2033. This range is selected to match Allwinner's
115 * driver, even though it is somewhat limited.
117 #define SUN6I_YEAR_MIN 1970
118 #define SUN6I_YEAR_MAX 2033
119 #define SUN6I_YEAR_OFF (SUN6I_YEAR_MIN - 1900)
122 * There are other differences between models, including:
124 * - number of GPIO pins that can be configured to hold a certain level
125 * - crypto-key related registers (H5, H6)
126 * - boot process related (super standby, secondary processor entry address)
127 * registers (R40, H6)
128 * - SYS power domain controls (R40)
129 * - DCXO controls (H6)
130 * - RC oscillator calibration (H6)
132 * These functions are not covered by this driver.
134 struct sun6i_rtc_clk_data {
135 unsigned long rc_osc_rate;
136 unsigned int fixed_prescaler : 16;
137 unsigned int has_prescaler : 1;
138 unsigned int has_out_clk : 1;
139 unsigned int export_iosc : 1;
142 struct sun6i_rtc_dev {
143 struct rtc_device *rtc;
145 const struct sun6i_rtc_clk_data *data;
151 struct clk_hw *int_osc;
153 struct clk *ext_losc;
158 static struct sun6i_rtc_dev *sun6i_rtc;
160 static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw,
161 unsigned long parent_rate)
163 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
166 val = readl(rtc->base + SUN6I_LOSC_CTRL);
167 if (val & SUN6I_LOSC_CTRL_EXT_OSC)
170 if (rtc->data->fixed_prescaler)
171 parent_rate /= rtc->data->fixed_prescaler;
173 if (rtc->data->has_prescaler) {
174 val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL);
175 val &= GENMASK(4, 0);
178 return parent_rate / (val + 1);
181 static u8 sun6i_rtc_osc_get_parent(struct clk_hw *hw)
183 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
185 return readl(rtc->base + SUN6I_LOSC_CTRL) & SUN6I_LOSC_CTRL_EXT_OSC;
188 static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index)
190 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
197 spin_lock_irqsave(&rtc->lock, flags);
198 val = readl(rtc->base + SUN6I_LOSC_CTRL);
199 val &= ~SUN6I_LOSC_CTRL_EXT_OSC;
200 val |= SUN6I_LOSC_CTRL_KEY;
201 val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0;
202 writel(val, rtc->base + SUN6I_LOSC_CTRL);
203 spin_unlock_irqrestore(&rtc->lock, flags);
208 static const struct clk_ops sun6i_rtc_osc_ops = {
209 .recalc_rate = sun6i_rtc_osc_recalc_rate,
211 .get_parent = sun6i_rtc_osc_get_parent,
212 .set_parent = sun6i_rtc_osc_set_parent,
215 static void __init sun6i_rtc_clk_init(struct device_node *node,
216 const struct sun6i_rtc_clk_data *data)
218 struct clk_hw_onecell_data *clk_data;
219 struct sun6i_rtc_dev *rtc;
220 struct clk_init_data init = {
221 .ops = &sun6i_rtc_osc_ops,
224 const char *iosc_name = "rtc-int-osc";
225 const char *clkout_name = "osc32k-out";
226 const char *parents[2];
228 rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
233 clk_data = kzalloc(struct_size(clk_data, hws, 3), GFP_KERNEL);
239 spin_lock_init(&rtc->lock);
241 rtc->base = of_io_request_and_map(node, 0, of_node_full_name(node));
242 if (IS_ERR(rtc->base)) {
243 pr_crit("Can't map RTC registers");
247 /* Switch to the external, more precise, oscillator */
248 writel(SUN6I_LOSC_CTRL_KEY | SUN6I_LOSC_CTRL_EXT_OSC,
249 rtc->base + SUN6I_LOSC_CTRL);
251 /* Yes, I know, this is ugly. */
254 /* Deal with old DTs */
255 if (!of_get_property(node, "clocks", NULL))
258 /* Only read IOSC name from device tree if it is exported */
259 if (rtc->data->export_iosc)
260 of_property_read_string_index(node, "clock-output-names", 2,
263 rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL,
266 rtc->data->rc_osc_rate,
268 if (IS_ERR(rtc->int_osc)) {
269 pr_crit("Couldn't register the internal oscillator\n");
273 parents[0] = clk_hw_get_name(rtc->int_osc);
274 parents[1] = of_clk_get_parent_name(node, 0);
276 rtc->hw.init = &init;
278 init.parent_names = parents;
279 init.num_parents = of_clk_get_parent_count(node) + 1;
280 of_property_read_string_index(node, "clock-output-names", 0,
283 rtc->losc = clk_register(NULL, &rtc->hw);
284 if (IS_ERR(rtc->losc)) {
285 pr_crit("Couldn't register the LOSC clock\n");
289 of_property_read_string_index(node, "clock-output-names", 1,
291 rtc->ext_losc = clk_register_gate(NULL, clkout_name, rtc->hw.init->name,
292 0, rtc->base + SUN6I_LOSC_OUT_GATING,
293 SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0,
295 if (IS_ERR(rtc->ext_losc)) {
296 pr_crit("Couldn't register the LOSC external gate\n");
301 clk_data->hws[0] = &rtc->hw;
302 clk_data->hws[1] = __clk_get_hw(rtc->ext_losc);
303 if (rtc->data->export_iosc) {
304 clk_data->hws[2] = rtc->int_osc;
307 of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
314 static const struct sun6i_rtc_clk_data sun6i_a31_rtc_data = {
315 .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */
319 static void __init sun6i_a31_rtc_clk_init(struct device_node *node)
321 sun6i_rtc_clk_init(node, &sun6i_a31_rtc_data);
323 CLK_OF_DECLARE_DRIVER(sun6i_a31_rtc_clk, "allwinner,sun6i-a31-rtc",
324 sun6i_a31_rtc_clk_init);
326 static const struct sun6i_rtc_clk_data sun8i_a23_rtc_data = {
327 .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */
332 static void __init sun8i_a23_rtc_clk_init(struct device_node *node)
334 sun6i_rtc_clk_init(node, &sun8i_a23_rtc_data);
336 CLK_OF_DECLARE_DRIVER(sun8i_a23_rtc_clk, "allwinner,sun8i-a23-rtc",
337 sun8i_a23_rtc_clk_init);
339 static const struct sun6i_rtc_clk_data sun8i_h3_rtc_data = {
340 .rc_osc_rate = 16000000,
341 .fixed_prescaler = 32,
347 static void __init sun8i_h3_rtc_clk_init(struct device_node *node)
349 sun6i_rtc_clk_init(node, &sun8i_h3_rtc_data);
351 CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc",
352 sun8i_h3_rtc_clk_init);
353 /* As far as we are concerned, clocks for H5 are the same as H3 */
354 CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc",
355 sun8i_h3_rtc_clk_init);
357 static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = {
358 .rc_osc_rate = 32000,
362 static void __init sun8i_v3_rtc_clk_init(struct device_node *node)
364 sun6i_rtc_clk_init(node, &sun8i_v3_rtc_data);
366 CLK_OF_DECLARE_DRIVER(sun8i_v3_rtc_clk, "allwinner,sun8i-v3-rtc",
367 sun8i_v3_rtc_clk_init);
369 static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id)
371 struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id;
372 irqreturn_t ret = IRQ_NONE;
375 spin_lock(&chip->lock);
376 val = readl(chip->base + SUN6I_ALRM_IRQ_STA);
378 if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) {
379 val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND;
380 writel(val, chip->base + SUN6I_ALRM_IRQ_STA);
382 rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
386 spin_unlock(&chip->lock);
391 static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip)
394 u32 alrm_irq_val = 0;
395 u32 alrm_wake_val = 0;
399 alrm_val = SUN6I_ALRM_EN_CNT_EN;
400 alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN;
401 alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP;
403 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
404 chip->base + SUN6I_ALRM_IRQ_STA);
407 spin_lock_irqsave(&chip->lock, flags);
408 writel(alrm_val, chip->base + SUN6I_ALRM_EN);
409 writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN);
410 writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG);
411 spin_unlock_irqrestore(&chip->lock, flags);
414 static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
416 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
420 * read again in case it changes
423 date = readl(chip->base + SUN6I_RTC_YMD);
424 time = readl(chip->base + SUN6I_RTC_HMS);
425 } while ((date != readl(chip->base + SUN6I_RTC_YMD)) ||
426 (time != readl(chip->base + SUN6I_RTC_HMS)));
428 rtc_tm->tm_sec = SUN6I_TIME_GET_SEC_VALUE(time);
429 rtc_tm->tm_min = SUN6I_TIME_GET_MIN_VALUE(time);
430 rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time);
432 rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date);
433 rtc_tm->tm_mon = SUN6I_DATE_GET_MON_VALUE(date);
434 rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date);
439 * switch from (data_year->min)-relative offset to
440 * a (1900)-relative one
442 rtc_tm->tm_year += SUN6I_YEAR_OFF;
447 static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
449 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
454 spin_lock_irqsave(&chip->lock, flags);
455 alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN);
456 alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA);
457 spin_unlock_irqrestore(&chip->lock, flags);
459 wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN);
460 wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN);
461 rtc_time_to_tm(chip->alarm, &wkalrm->time);
466 static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
468 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
469 struct rtc_time *alrm_tm = &wkalrm->time;
470 struct rtc_time tm_now;
471 unsigned long time_now = 0;
472 unsigned long time_set = 0;
473 unsigned long time_gap = 0;
476 ret = sun6i_rtc_gettime(dev, &tm_now);
478 dev_err(dev, "Error in getting time\n");
482 rtc_tm_to_time(alrm_tm, &time_set);
483 rtc_tm_to_time(&tm_now, &time_now);
484 if (time_set <= time_now) {
485 dev_err(dev, "Date to set in the past\n");
489 time_gap = time_set - time_now;
491 if (time_gap > U32_MAX) {
492 dev_err(dev, "Date too far in the future\n");
496 sun6i_rtc_setaie(0, chip);
497 writel(0, chip->base + SUN6I_ALRM_COUNTER);
498 usleep_range(100, 300);
500 writel(time_gap, chip->base + SUN6I_ALRM_COUNTER);
501 chip->alarm = time_set;
503 sun6i_rtc_setaie(wkalrm->enabled, chip);
508 static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset,
509 unsigned int mask, unsigned int ms_timeout)
511 const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout);
515 reg = readl(chip->base + offset);
521 } while (time_before(jiffies, timeout));
526 static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
528 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
533 year = rtc_tm->tm_year + 1900;
534 if (year < SUN6I_YEAR_MIN || year > SUN6I_YEAR_MAX) {
535 dev_err(dev, "rtc only supports year in range %d - %d\n",
536 SUN6I_YEAR_MIN, SUN6I_YEAR_MAX);
540 rtc_tm->tm_year -= SUN6I_YEAR_OFF;
543 date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) |
544 SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) |
545 SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year);
547 if (is_leap_year(year))
548 date |= SUN6I_LEAP_SET_VALUE(1);
550 time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) |
551 SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min) |
552 SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour);
554 /* Check whether registers are writable */
555 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
556 SUN6I_LOSC_CTRL_ACC_MASK, 50)) {
557 dev_err(dev, "rtc is still busy.\n");
561 writel(time, chip->base + SUN6I_RTC_HMS);
564 * After writing the RTC HH-MM-SS register, the
565 * SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not
566 * be cleared until the real writing operation is finished
569 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
570 SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) {
571 dev_err(dev, "Failed to set rtc time.\n");
575 writel(date, chip->base + SUN6I_RTC_YMD);
578 * After writing the RTC YY-MM-DD register, the
579 * SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not
580 * be cleared until the real writing operation is finished
583 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
584 SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) {
585 dev_err(dev, "Failed to set rtc time.\n");
592 static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
594 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
597 sun6i_rtc_setaie(enabled, chip);
602 static const struct rtc_class_ops sun6i_rtc_ops = {
603 .read_time = sun6i_rtc_gettime,
604 .set_time = sun6i_rtc_settime,
605 .read_alarm = sun6i_rtc_getalarm,
606 .set_alarm = sun6i_rtc_setalarm,
607 .alarm_irq_enable = sun6i_rtc_alarm_irq_enable
610 static int sun6i_rtc_probe(struct platform_device *pdev)
612 struct sun6i_rtc_dev *chip = sun6i_rtc;
618 platform_set_drvdata(pdev, chip);
619 chip->dev = &pdev->dev;
621 chip->irq = platform_get_irq(pdev, 0);
623 dev_err(&pdev->dev, "No IRQ resource\n");
627 ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq,
628 0, dev_name(&pdev->dev), chip);
630 dev_err(&pdev->dev, "Could not request IRQ\n");
634 /* clear the alarm counter value */
635 writel(0, chip->base + SUN6I_ALRM_COUNTER);
637 /* disable counter alarm */
638 writel(0, chip->base + SUN6I_ALRM_EN);
640 /* disable counter alarm interrupt */
641 writel(0, chip->base + SUN6I_ALRM_IRQ_EN);
643 /* disable week alarm */
644 writel(0, chip->base + SUN6I_ALRM1_EN);
646 /* disable week alarm interrupt */
647 writel(0, chip->base + SUN6I_ALRM1_IRQ_EN);
649 /* clear counter alarm pending interrupts */
650 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
651 chip->base + SUN6I_ALRM_IRQ_STA);
653 /* clear week alarm pending interrupts */
654 writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND,
655 chip->base + SUN6I_ALRM1_IRQ_STA);
657 /* disable alarm wakeup */
658 writel(0, chip->base + SUN6I_ALARM_CONFIG);
660 clk_prepare_enable(chip->losc);
662 chip->rtc = devm_rtc_device_register(&pdev->dev, "rtc-sun6i",
663 &sun6i_rtc_ops, THIS_MODULE);
664 if (IS_ERR(chip->rtc)) {
665 dev_err(&pdev->dev, "unable to register device\n");
666 return PTR_ERR(chip->rtc);
669 dev_info(&pdev->dev, "RTC enabled\n");
675 * As far as RTC functionality goes, all models are the same. The
676 * datasheets claim that different models have different number of
677 * registers available for non-volatile storage, but experiments show
678 * that all SoCs have 16 registers available for this purpose.
680 static const struct of_device_id sun6i_rtc_dt_ids[] = {
681 { .compatible = "allwinner,sun6i-a31-rtc" },
682 { .compatible = "allwinner,sun8i-a23-rtc" },
683 { .compatible = "allwinner,sun8i-h3-rtc" },
684 { .compatible = "allwinner,sun8i-v3-rtc" },
685 { .compatible = "allwinner,sun50i-h5-rtc" },
688 MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids);
690 static struct platform_driver sun6i_rtc_driver = {
691 .probe = sun6i_rtc_probe,
694 .of_match_table = sun6i_rtc_dt_ids,
697 builtin_platform_driver(sun6i_rtc_driver);