1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * An RTC driver for Allwinner A31/A23
5 * Copyright (c) 2014, Chen-Yu Tsai <wens@csie.org>
9 * An RTC driver for Allwinner A10/A20
11 * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com>
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
16 #include <linux/delay.h>
17 #include <linux/err.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
25 #include <linux/of_address.h>
26 #include <linux/of_device.h>
27 #include <linux/platform_device.h>
28 #include <linux/rtc.h>
29 #include <linux/slab.h>
30 #include <linux/types.h>
32 /* Control register */
33 #define SUN6I_LOSC_CTRL 0x0000
34 #define SUN6I_LOSC_CTRL_KEY (0x16aa << 16)
35 #define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS BIT(15)
36 #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9)
37 #define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8)
38 #define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7)
39 #define SUN6I_LOSC_CTRL_EXT_LOSC_EN BIT(4)
40 #define SUN6I_LOSC_CTRL_EXT_OSC BIT(0)
41 #define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7)
43 #define SUN6I_LOSC_CLK_PRESCAL 0x0008
46 #define SUN6I_RTC_YMD 0x0010
47 #define SUN6I_RTC_HMS 0x0014
49 /* Alarm 0 (counter) */
50 #define SUN6I_ALRM_COUNTER 0x0020
51 #define SUN6I_ALRM_CUR_VAL 0x0024
52 #define SUN6I_ALRM_EN 0x0028
53 #define SUN6I_ALRM_EN_CNT_EN BIT(0)
54 #define SUN6I_ALRM_IRQ_EN 0x002c
55 #define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0)
56 #define SUN6I_ALRM_IRQ_STA 0x0030
57 #define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0)
59 /* Alarm 1 (wall clock) */
60 #define SUN6I_ALRM1_EN 0x0044
61 #define SUN6I_ALRM1_IRQ_EN 0x0048
62 #define SUN6I_ALRM1_IRQ_STA 0x004c
63 #define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND BIT(0)
66 #define SUN6I_ALARM_CONFIG 0x0050
67 #define SUN6I_ALARM_CONFIG_WAKEUP BIT(0)
69 #define SUN6I_LOSC_OUT_GATING 0x0060
70 #define SUN6I_LOSC_OUT_GATING_EN_OFFSET 0
75 #define SUN6I_DATE_GET_DAY_VALUE(x) ((x) & 0x0000001f)
76 #define SUN6I_DATE_GET_MON_VALUE(x) (((x) & 0x00000f00) >> 8)
77 #define SUN6I_DATE_GET_YEAR_VALUE(x) (((x) & 0x003f0000) >> 16)
78 #define SUN6I_LEAP_GET_VALUE(x) (((x) & 0x00400000) >> 22)
83 #define SUN6I_TIME_GET_SEC_VALUE(x) ((x) & 0x0000003f)
84 #define SUN6I_TIME_GET_MIN_VALUE(x) (((x) & 0x00003f00) >> 8)
85 #define SUN6I_TIME_GET_HOUR_VALUE(x) (((x) & 0x001f0000) >> 16)
90 #define SUN6I_DATE_SET_DAY_VALUE(x) ((x) & 0x0000001f)
91 #define SUN6I_DATE_SET_MON_VALUE(x) ((x) << 8 & 0x00000f00)
92 #define SUN6I_DATE_SET_YEAR_VALUE(x) ((x) << 16 & 0x003f0000)
93 #define SUN6I_LEAP_SET_VALUE(x) ((x) << 22 & 0x00400000)
98 #define SUN6I_TIME_SET_SEC_VALUE(x) ((x) & 0x0000003f)
99 #define SUN6I_TIME_SET_MIN_VALUE(x) ((x) << 8 & 0x00003f00)
100 #define SUN6I_TIME_SET_HOUR_VALUE(x) ((x) << 16 & 0x001f0000)
103 * The year parameter passed to the driver is usually an offset relative to
104 * the year 1900. This macro is used to convert this offset to another one
105 * relative to the minimum year allowed by the hardware.
107 * The year range is 1970 - 2033. This range is selected to match Allwinner's
108 * driver, even though it is somewhat limited.
110 #define SUN6I_YEAR_MIN 1970
111 #define SUN6I_YEAR_MAX 2033
112 #define SUN6I_YEAR_OFF (SUN6I_YEAR_MIN - 1900)
115 * There are other differences between models, including:
117 * - number of GPIO pins that can be configured to hold a certain level
118 * - crypto-key related registers (H5, H6)
119 * - boot process related (super standby, secondary processor entry address)
120 * registers (R40, H6)
121 * - SYS power domain controls (R40)
122 * - DCXO controls (H6)
123 * - RC oscillator calibration (H6)
125 * These functions are not covered by this driver.
127 struct sun6i_rtc_clk_data {
128 unsigned long rc_osc_rate;
129 unsigned int fixed_prescaler : 16;
130 unsigned int has_prescaler : 1;
131 unsigned int has_out_clk : 1;
132 unsigned int export_iosc : 1;
133 unsigned int has_losc_en : 1;
134 unsigned int has_auto_swt : 1;
137 struct sun6i_rtc_dev {
138 struct rtc_device *rtc;
139 const struct sun6i_rtc_clk_data *data;
145 struct clk_hw *int_osc;
147 struct clk *ext_losc;
152 static struct sun6i_rtc_dev *sun6i_rtc;
154 static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw,
155 unsigned long parent_rate)
157 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
160 val = readl(rtc->base + SUN6I_LOSC_CTRL);
161 if (val & SUN6I_LOSC_CTRL_EXT_OSC)
164 if (rtc->data->fixed_prescaler)
165 parent_rate /= rtc->data->fixed_prescaler;
167 if (rtc->data->has_prescaler) {
168 val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL);
169 val &= GENMASK(4, 0);
172 return parent_rate / (val + 1);
175 static u8 sun6i_rtc_osc_get_parent(struct clk_hw *hw)
177 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
179 return readl(rtc->base + SUN6I_LOSC_CTRL) & SUN6I_LOSC_CTRL_EXT_OSC;
182 static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index)
184 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
191 spin_lock_irqsave(&rtc->lock, flags);
192 val = readl(rtc->base + SUN6I_LOSC_CTRL);
193 val &= ~SUN6I_LOSC_CTRL_EXT_OSC;
194 val |= SUN6I_LOSC_CTRL_KEY;
195 val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0;
196 if (rtc->data->has_losc_en) {
197 val &= ~SUN6I_LOSC_CTRL_EXT_LOSC_EN;
198 val |= index ? SUN6I_LOSC_CTRL_EXT_LOSC_EN : 0;
200 writel(val, rtc->base + SUN6I_LOSC_CTRL);
201 spin_unlock_irqrestore(&rtc->lock, flags);
206 static const struct clk_ops sun6i_rtc_osc_ops = {
207 .recalc_rate = sun6i_rtc_osc_recalc_rate,
209 .get_parent = sun6i_rtc_osc_get_parent,
210 .set_parent = sun6i_rtc_osc_set_parent,
213 static void __init sun6i_rtc_clk_init(struct device_node *node,
214 const struct sun6i_rtc_clk_data *data)
216 struct clk_hw_onecell_data *clk_data;
217 struct sun6i_rtc_dev *rtc;
218 struct clk_init_data init = {
219 .ops = &sun6i_rtc_osc_ops,
222 const char *iosc_name = "rtc-int-osc";
223 const char *clkout_name = "osc32k-out";
224 const char *parents[2];
227 rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
232 clk_data = kzalloc(struct_size(clk_data, hws, 3), GFP_KERNEL);
238 spin_lock_init(&rtc->lock);
240 rtc->base = of_io_request_and_map(node, 0, of_node_full_name(node));
241 if (IS_ERR(rtc->base)) {
242 pr_crit("Can't map RTC registers");
246 reg = SUN6I_LOSC_CTRL_KEY;
247 if (rtc->data->has_auto_swt) {
248 /* Bypass auto-switch to int osc, on ext losc failure */
249 reg |= SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS;
250 writel(reg, rtc->base + SUN6I_LOSC_CTRL);
253 /* Switch to the external, more precise, oscillator */
254 reg |= SUN6I_LOSC_CTRL_EXT_OSC;
255 if (rtc->data->has_losc_en)
256 reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN;
257 writel(reg, rtc->base + SUN6I_LOSC_CTRL);
259 /* Yes, I know, this is ugly. */
262 /* Deal with old DTs */
263 if (!of_get_property(node, "clocks", NULL))
266 /* Only read IOSC name from device tree if it is exported */
267 if (rtc->data->export_iosc)
268 of_property_read_string_index(node, "clock-output-names", 2,
271 rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL,
274 rtc->data->rc_osc_rate,
276 if (IS_ERR(rtc->int_osc)) {
277 pr_crit("Couldn't register the internal oscillator\n");
281 parents[0] = clk_hw_get_name(rtc->int_osc);
282 parents[1] = of_clk_get_parent_name(node, 0);
284 rtc->hw.init = &init;
286 init.parent_names = parents;
287 init.num_parents = of_clk_get_parent_count(node) + 1;
288 of_property_read_string_index(node, "clock-output-names", 0,
291 rtc->losc = clk_register(NULL, &rtc->hw);
292 if (IS_ERR(rtc->losc)) {
293 pr_crit("Couldn't register the LOSC clock\n");
297 of_property_read_string_index(node, "clock-output-names", 1,
299 rtc->ext_losc = clk_register_gate(NULL, clkout_name, init.name,
300 0, rtc->base + SUN6I_LOSC_OUT_GATING,
301 SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0,
303 if (IS_ERR(rtc->ext_losc)) {
304 pr_crit("Couldn't register the LOSC external gate\n");
309 clk_data->hws[0] = &rtc->hw;
310 clk_data->hws[1] = __clk_get_hw(rtc->ext_losc);
311 if (rtc->data->export_iosc) {
312 clk_data->hws[2] = rtc->int_osc;
315 of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
322 static const struct sun6i_rtc_clk_data sun6i_a31_rtc_data = {
323 .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */
327 static void __init sun6i_a31_rtc_clk_init(struct device_node *node)
329 sun6i_rtc_clk_init(node, &sun6i_a31_rtc_data);
331 CLK_OF_DECLARE_DRIVER(sun6i_a31_rtc_clk, "allwinner,sun6i-a31-rtc",
332 sun6i_a31_rtc_clk_init);
334 static const struct sun6i_rtc_clk_data sun8i_a23_rtc_data = {
335 .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */
340 static void __init sun8i_a23_rtc_clk_init(struct device_node *node)
342 sun6i_rtc_clk_init(node, &sun8i_a23_rtc_data);
344 CLK_OF_DECLARE_DRIVER(sun8i_a23_rtc_clk, "allwinner,sun8i-a23-rtc",
345 sun8i_a23_rtc_clk_init);
347 static const struct sun6i_rtc_clk_data sun8i_h3_rtc_data = {
348 .rc_osc_rate = 16000000,
349 .fixed_prescaler = 32,
355 static void __init sun8i_h3_rtc_clk_init(struct device_node *node)
357 sun6i_rtc_clk_init(node, &sun8i_h3_rtc_data);
359 CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc",
360 sun8i_h3_rtc_clk_init);
361 /* As far as we are concerned, clocks for H5 are the same as H3 */
362 CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc",
363 sun8i_h3_rtc_clk_init);
365 static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = {
366 .rc_osc_rate = 16000000,
367 .fixed_prescaler = 32,
375 static void __init sun50i_h6_rtc_clk_init(struct device_node *node)
377 sun6i_rtc_clk_init(node, &sun50i_h6_rtc_data);
379 CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc",
380 sun50i_h6_rtc_clk_init);
382 static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = {
383 .rc_osc_rate = 32000,
387 static void __init sun8i_v3_rtc_clk_init(struct device_node *node)
389 sun6i_rtc_clk_init(node, &sun8i_v3_rtc_data);
391 CLK_OF_DECLARE_DRIVER(sun8i_v3_rtc_clk, "allwinner,sun8i-v3-rtc",
392 sun8i_v3_rtc_clk_init);
394 static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id)
396 struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id;
397 irqreturn_t ret = IRQ_NONE;
400 spin_lock(&chip->lock);
401 val = readl(chip->base + SUN6I_ALRM_IRQ_STA);
403 if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) {
404 val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND;
405 writel(val, chip->base + SUN6I_ALRM_IRQ_STA);
407 rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
411 spin_unlock(&chip->lock);
416 static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip)
419 u32 alrm_irq_val = 0;
420 u32 alrm_wake_val = 0;
424 alrm_val = SUN6I_ALRM_EN_CNT_EN;
425 alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN;
426 alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP;
428 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
429 chip->base + SUN6I_ALRM_IRQ_STA);
432 spin_lock_irqsave(&chip->lock, flags);
433 writel(alrm_val, chip->base + SUN6I_ALRM_EN);
434 writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN);
435 writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG);
436 spin_unlock_irqrestore(&chip->lock, flags);
439 static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
441 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
445 * read again in case it changes
448 date = readl(chip->base + SUN6I_RTC_YMD);
449 time = readl(chip->base + SUN6I_RTC_HMS);
450 } while ((date != readl(chip->base + SUN6I_RTC_YMD)) ||
451 (time != readl(chip->base + SUN6I_RTC_HMS)));
453 rtc_tm->tm_sec = SUN6I_TIME_GET_SEC_VALUE(time);
454 rtc_tm->tm_min = SUN6I_TIME_GET_MIN_VALUE(time);
455 rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time);
457 rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date);
458 rtc_tm->tm_mon = SUN6I_DATE_GET_MON_VALUE(date);
459 rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date);
464 * switch from (data_year->min)-relative offset to
465 * a (1900)-relative one
467 rtc_tm->tm_year += SUN6I_YEAR_OFF;
472 static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
474 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
479 spin_lock_irqsave(&chip->lock, flags);
480 alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN);
481 alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA);
482 spin_unlock_irqrestore(&chip->lock, flags);
484 wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN);
485 wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN);
486 rtc_time_to_tm(chip->alarm, &wkalrm->time);
491 static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
493 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
494 struct rtc_time *alrm_tm = &wkalrm->time;
495 struct rtc_time tm_now;
496 unsigned long time_now = 0;
497 unsigned long time_set = 0;
498 unsigned long time_gap = 0;
501 ret = sun6i_rtc_gettime(dev, &tm_now);
503 dev_err(dev, "Error in getting time\n");
507 rtc_tm_to_time(alrm_tm, &time_set);
508 rtc_tm_to_time(&tm_now, &time_now);
509 if (time_set <= time_now) {
510 dev_err(dev, "Date to set in the past\n");
514 time_gap = time_set - time_now;
516 if (time_gap > U32_MAX) {
517 dev_err(dev, "Date too far in the future\n");
521 sun6i_rtc_setaie(0, chip);
522 writel(0, chip->base + SUN6I_ALRM_COUNTER);
523 usleep_range(100, 300);
525 writel(time_gap, chip->base + SUN6I_ALRM_COUNTER);
526 chip->alarm = time_set;
528 sun6i_rtc_setaie(wkalrm->enabled, chip);
533 static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset,
534 unsigned int mask, unsigned int ms_timeout)
536 const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout);
540 reg = readl(chip->base + offset);
546 } while (time_before(jiffies, timeout));
551 static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
553 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
558 year = rtc_tm->tm_year + 1900;
559 if (year < SUN6I_YEAR_MIN || year > SUN6I_YEAR_MAX) {
560 dev_err(dev, "rtc only supports year in range %d - %d\n",
561 SUN6I_YEAR_MIN, SUN6I_YEAR_MAX);
565 rtc_tm->tm_year -= SUN6I_YEAR_OFF;
568 date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) |
569 SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) |
570 SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year);
572 if (is_leap_year(year))
573 date |= SUN6I_LEAP_SET_VALUE(1);
575 time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) |
576 SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min) |
577 SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour);
579 /* Check whether registers are writable */
580 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
581 SUN6I_LOSC_CTRL_ACC_MASK, 50)) {
582 dev_err(dev, "rtc is still busy.\n");
586 writel(time, chip->base + SUN6I_RTC_HMS);
589 * After writing the RTC HH-MM-SS register, the
590 * SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not
591 * be cleared until the real writing operation is finished
594 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
595 SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) {
596 dev_err(dev, "Failed to set rtc time.\n");
600 writel(date, chip->base + SUN6I_RTC_YMD);
603 * After writing the RTC YY-MM-DD register, the
604 * SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not
605 * be cleared until the real writing operation is finished
608 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
609 SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) {
610 dev_err(dev, "Failed to set rtc time.\n");
617 static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
619 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
622 sun6i_rtc_setaie(enabled, chip);
627 static const struct rtc_class_ops sun6i_rtc_ops = {
628 .read_time = sun6i_rtc_gettime,
629 .set_time = sun6i_rtc_settime,
630 .read_alarm = sun6i_rtc_getalarm,
631 .set_alarm = sun6i_rtc_setalarm,
632 .alarm_irq_enable = sun6i_rtc_alarm_irq_enable
635 #ifdef CONFIG_PM_SLEEP
636 /* Enable IRQ wake on suspend, to wake up from RTC. */
637 static int sun6i_rtc_suspend(struct device *dev)
639 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
641 if (device_may_wakeup(dev))
642 enable_irq_wake(chip->irq);
647 /* Disable IRQ wake on resume. */
648 static int sun6i_rtc_resume(struct device *dev)
650 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
652 if (device_may_wakeup(dev))
653 disable_irq_wake(chip->irq);
659 static SIMPLE_DEV_PM_OPS(sun6i_rtc_pm_ops,
660 sun6i_rtc_suspend, sun6i_rtc_resume);
662 static int sun6i_rtc_probe(struct platform_device *pdev)
664 struct sun6i_rtc_dev *chip = sun6i_rtc;
670 platform_set_drvdata(pdev, chip);
672 chip->irq = platform_get_irq(pdev, 0);
676 ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq,
677 0, dev_name(&pdev->dev), chip);
679 dev_err(&pdev->dev, "Could not request IRQ\n");
683 /* clear the alarm counter value */
684 writel(0, chip->base + SUN6I_ALRM_COUNTER);
686 /* disable counter alarm */
687 writel(0, chip->base + SUN6I_ALRM_EN);
689 /* disable counter alarm interrupt */
690 writel(0, chip->base + SUN6I_ALRM_IRQ_EN);
692 /* disable week alarm */
693 writel(0, chip->base + SUN6I_ALRM1_EN);
695 /* disable week alarm interrupt */
696 writel(0, chip->base + SUN6I_ALRM1_IRQ_EN);
698 /* clear counter alarm pending interrupts */
699 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
700 chip->base + SUN6I_ALRM_IRQ_STA);
702 /* clear week alarm pending interrupts */
703 writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND,
704 chip->base + SUN6I_ALRM1_IRQ_STA);
706 /* disable alarm wakeup */
707 writel(0, chip->base + SUN6I_ALARM_CONFIG);
709 clk_prepare_enable(chip->losc);
711 device_init_wakeup(&pdev->dev, 1);
713 chip->rtc = devm_rtc_device_register(&pdev->dev, "rtc-sun6i",
714 &sun6i_rtc_ops, THIS_MODULE);
715 if (IS_ERR(chip->rtc)) {
716 dev_err(&pdev->dev, "unable to register device\n");
717 return PTR_ERR(chip->rtc);
720 dev_info(&pdev->dev, "RTC enabled\n");
726 * As far as RTC functionality goes, all models are the same. The
727 * datasheets claim that different models have different number of
728 * registers available for non-volatile storage, but experiments show
729 * that all SoCs have 16 registers available for this purpose.
731 static const struct of_device_id sun6i_rtc_dt_ids[] = {
732 { .compatible = "allwinner,sun6i-a31-rtc" },
733 { .compatible = "allwinner,sun8i-a23-rtc" },
734 { .compatible = "allwinner,sun8i-h3-rtc" },
735 { .compatible = "allwinner,sun8i-r40-rtc" },
736 { .compatible = "allwinner,sun8i-v3-rtc" },
737 { .compatible = "allwinner,sun50i-h5-rtc" },
738 { .compatible = "allwinner,sun50i-h6-rtc" },
741 MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids);
743 static struct platform_driver sun6i_rtc_driver = {
744 .probe = sun6i_rtc_probe,
747 .of_match_table = sun6i_rtc_dt_ids,
748 .pm = &sun6i_rtc_pm_ops,
751 builtin_platform_driver(sun6i_rtc_driver);