2 * Xilinx Zynq Ultrascale+ MPSoC Real Time Clock Driver
4 * Copyright (C) 2015 Xilinx, Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/delay.h>
21 #include <linux/init.h>
23 #include <linux/module.h>
25 #include <linux/platform_device.h>
26 #include <linux/rtc.h>
29 #define RTC_SET_TM_WR 0x00
30 #define RTC_SET_TM_RD 0x04
31 #define RTC_CALIB_WR 0x08
32 #define RTC_CALIB_RD 0x0C
33 #define RTC_CUR_TM 0x10
34 #define RTC_CUR_TICK 0x14
36 #define RTC_INT_STS 0x20
37 #define RTC_INT_MASK 0x24
38 #define RTC_INT_EN 0x28
39 #define RTC_INT_DIS 0x2C
42 #define RTC_FR_EN BIT(20)
43 #define RTC_FR_DATSHIFT 16
44 #define RTC_TICK_MASK 0xFFFF
45 #define RTC_INT_SEC BIT(0)
46 #define RTC_INT_ALRM BIT(1)
47 #define RTC_OSC_EN BIT(24)
48 #define RTC_BATT_EN BIT(31)
50 #define RTC_CALIB_DEF 0x198233
51 #define RTC_CALIB_MASK 0x1FFFFF
54 struct rtc_device *rtc;
55 void __iomem *reg_base;
61 static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm)
63 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
64 unsigned long new_time;
67 * The value written will be updated after 1 sec into the
68 * seconds read register, so we need to program time +1 sec
69 * to get the correct time on read.
71 new_time = rtc_tm_to_time64(tm) + 1;
74 * Writing into calibration register will clear the Tick Counter and
75 * force the next second to be signaled exactly in 1 second period
77 xrtcdev->calibval &= RTC_CALIB_MASK;
78 writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
80 writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR);
83 * Clear the rtc interrupt status register after setting the
84 * time. During a read_time function, the code should read the
85 * RTC_INT_STATUS register and if bit 0 is still 0, it means
86 * that one second has not elapsed yet since RTC was set and
87 * the current time should be read from SET_TIME_READ register;
88 * otherwise, CURRENT_TIME register is read to report the time
90 writel(RTC_INT_SEC, xrtcdev->reg_base + RTC_INT_STS);
95 static int xlnx_rtc_read_time(struct device *dev, struct rtc_time *tm)
98 unsigned long read_time;
99 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
101 status = readl(xrtcdev->reg_base + RTC_INT_STS);
103 if (status & RTC_INT_SEC) {
105 * RTC has updated the CURRENT_TIME with the time written into
106 * SET_TIME_WRITE register.
108 rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_CUR_TM), tm);
111 * Time written in SET_TIME_WRITE has not yet updated into
112 * the seconds read register, so read the time from the
113 * SET_TIME_WRITE instead of CURRENT_TIME register.
114 * Since we add +1 sec while writing, we need to -1 sec while
117 read_time = readl(xrtcdev->reg_base + RTC_SET_TM_RD) - 1;
118 rtc_time64_to_tm(read_time, tm);
124 static int xlnx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
126 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
128 rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_ALRM), &alrm->time);
129 alrm->enabled = readl(xrtcdev->reg_base + RTC_INT_MASK) & RTC_INT_ALRM;
134 static int xlnx_rtc_alarm_irq_enable(struct device *dev, u32 enabled)
136 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
139 writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_EN);
141 writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS);
146 static int xlnx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
148 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
149 unsigned long alarm_time;
151 alarm_time = rtc_tm_to_time64(&alrm->time);
153 writel((u32)alarm_time, (xrtcdev->reg_base + RTC_ALRM));
155 xlnx_rtc_alarm_irq_enable(dev, alrm->enabled);
160 static void xlnx_init_rtc(struct xlnx_rtc_dev *xrtcdev)
164 /* Enable RTC switch to battery when VCC_PSAUX is not available */
165 rtc_ctrl = readl(xrtcdev->reg_base + RTC_CTRL);
166 rtc_ctrl |= RTC_BATT_EN;
167 writel(rtc_ctrl, xrtcdev->reg_base + RTC_CTRL);
170 * Based on crystal freq of 33.330 KHz
171 * set the seconds counter and enable, set fractions counter
172 * to default value suggested as per design spec
173 * to correct RTC delay in frequency over period of time.
175 xrtcdev->calibval &= RTC_CALIB_MASK;
176 writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
179 static const struct rtc_class_ops xlnx_rtc_ops = {
180 .set_time = xlnx_rtc_set_time,
181 .read_time = xlnx_rtc_read_time,
182 .read_alarm = xlnx_rtc_read_alarm,
183 .set_alarm = xlnx_rtc_set_alarm,
184 .alarm_irq_enable = xlnx_rtc_alarm_irq_enable,
187 static irqreturn_t xlnx_rtc_interrupt(int irq, void *id)
189 struct xlnx_rtc_dev *xrtcdev = (struct xlnx_rtc_dev *)id;
192 status = readl(xrtcdev->reg_base + RTC_INT_STS);
193 /* Check if interrupt asserted */
194 if (!(status & (RTC_INT_SEC | RTC_INT_ALRM)))
197 /* Clear RTC_INT_ALRM interrupt only */
198 writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_STS);
200 if (status & RTC_INT_ALRM)
201 rtc_update_irq(xrtcdev->rtc, 1, RTC_IRQF | RTC_AF);
206 static int xlnx_rtc_probe(struct platform_device *pdev)
208 struct xlnx_rtc_dev *xrtcdev;
209 struct resource *res;
212 xrtcdev = devm_kzalloc(&pdev->dev, sizeof(*xrtcdev), GFP_KERNEL);
216 platform_set_drvdata(pdev, xrtcdev);
218 xrtcdev->rtc = devm_rtc_allocate_device(&pdev->dev);
219 if (IS_ERR(xrtcdev->rtc))
220 return PTR_ERR(xrtcdev->rtc);
222 xrtcdev->rtc->ops = &xlnx_rtc_ops;
223 xrtcdev->rtc->range_max = U32_MAX;
225 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
227 xrtcdev->reg_base = devm_ioremap_resource(&pdev->dev, res);
228 if (IS_ERR(xrtcdev->reg_base))
229 return PTR_ERR(xrtcdev->reg_base);
231 xrtcdev->alarm_irq = platform_get_irq_byname(pdev, "alarm");
232 if (xrtcdev->alarm_irq < 0) {
233 dev_err(&pdev->dev, "no irq resource\n");
234 return xrtcdev->alarm_irq;
236 ret = devm_request_irq(&pdev->dev, xrtcdev->alarm_irq,
237 xlnx_rtc_interrupt, 0,
238 dev_name(&pdev->dev), xrtcdev);
240 dev_err(&pdev->dev, "request irq failed\n");
244 xrtcdev->sec_irq = platform_get_irq_byname(pdev, "sec");
245 if (xrtcdev->sec_irq < 0) {
246 dev_err(&pdev->dev, "no irq resource\n");
247 return xrtcdev->sec_irq;
249 ret = devm_request_irq(&pdev->dev, xrtcdev->sec_irq,
250 xlnx_rtc_interrupt, 0,
251 dev_name(&pdev->dev), xrtcdev);
253 dev_err(&pdev->dev, "request irq failed\n");
257 ret = of_property_read_u32(pdev->dev.of_node, "calibration",
260 xrtcdev->calibval = RTC_CALIB_DEF;
262 xlnx_init_rtc(xrtcdev);
264 device_init_wakeup(&pdev->dev, 1);
266 return rtc_register_device(xrtcdev->rtc);
269 static int xlnx_rtc_remove(struct platform_device *pdev)
271 xlnx_rtc_alarm_irq_enable(&pdev->dev, 0);
272 device_init_wakeup(&pdev->dev, 0);
277 static int __maybe_unused xlnx_rtc_suspend(struct device *dev)
279 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
281 if (device_may_wakeup(dev))
282 enable_irq_wake(xrtcdev->alarm_irq);
284 xlnx_rtc_alarm_irq_enable(dev, 0);
289 static int __maybe_unused xlnx_rtc_resume(struct device *dev)
291 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
293 if (device_may_wakeup(dev))
294 disable_irq_wake(xrtcdev->alarm_irq);
296 xlnx_rtc_alarm_irq_enable(dev, 1);
301 static SIMPLE_DEV_PM_OPS(xlnx_rtc_pm_ops, xlnx_rtc_suspend, xlnx_rtc_resume);
303 static const struct of_device_id xlnx_rtc_of_match[] = {
304 {.compatible = "xlnx,zynqmp-rtc" },
307 MODULE_DEVICE_TABLE(of, xlnx_rtc_of_match);
309 static struct platform_driver xlnx_rtc_driver = {
310 .probe = xlnx_rtc_probe,
311 .remove = xlnx_rtc_remove,
313 .name = KBUILD_MODNAME,
314 .pm = &xlnx_rtc_pm_ops,
315 .of_match_table = xlnx_rtc_of_match,
319 module_platform_driver(xlnx_rtc_driver);
321 MODULE_DESCRIPTION("Xilinx Zynq MPSoC RTC driver");
322 MODULE_AUTHOR("Xilinx Inc.");
323 MODULE_LICENSE("GPL v2");