2 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
3 * Copyright (c) 2014- QLogic Corporation.
7 * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License (GPL) Version 2 as
11 * published by the Free Software Foundation
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
20 #include "bfa_modules.h"
24 bfa_hwcb_reginit(struct bfa_s *bfa)
26 struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
27 void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
28 int fn = bfa_ioc_pcifn(&bfa->ioc);
31 bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS);
32 bfa_regs->intr_mask = (kva + HOSTFN0_INT_MSK);
34 bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS);
35 bfa_regs->intr_mask = (kva + HOSTFN1_INT_MSK);
40 bfa_hwcb_reqq_ack_msix(struct bfa_s *bfa, int reqq)
42 writel(__HFN_INT_CPE_Q0 << CPE_Q_NUM(bfa_ioc_pcifn(&bfa->ioc), reqq),
43 bfa->iocfc.bfa_regs.intr_status);
47 * Actions to respond RME Interrupt for Crossbow ASIC:
48 * - Write 1 to Interrupt Status register
49 * INTX - done in bfa_intx()
50 * MSIX - done in bfa_hwcb_rspq_ack_msix()
51 * - Update CI (only if new CI)
54 bfa_hwcb_rspq_ack_msix(struct bfa_s *bfa, int rspq, u32 ci)
56 writel(__HFN_INT_RME_Q0 << RME_Q_NUM(bfa_ioc_pcifn(&bfa->ioc), rspq),
57 bfa->iocfc.bfa_regs.intr_status);
59 if (bfa_rspq_ci(bfa, rspq) == ci)
62 bfa_rspq_ci(bfa, rspq) = ci;
63 writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]);
67 bfa_hwcb_rspq_ack(struct bfa_s *bfa, int rspq, u32 ci)
69 if (bfa_rspq_ci(bfa, rspq) == ci)
72 bfa_rspq_ci(bfa, rspq) = ci;
73 writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]);
77 bfa_hwcb_msix_getvecs(struct bfa_s *bfa, u32 *msix_vecs_bmap,
78 u32 *num_vecs, u32 *max_vec_bit)
80 #define __HFN_NUMINTS 13
81 if (bfa_ioc_pcifn(&bfa->ioc) == 0) {
82 *msix_vecs_bmap = (__HFN_INT_CPE_Q0 | __HFN_INT_CPE_Q1 |
83 __HFN_INT_CPE_Q2 | __HFN_INT_CPE_Q3 |
84 __HFN_INT_RME_Q0 | __HFN_INT_RME_Q1 |
85 __HFN_INT_RME_Q2 | __HFN_INT_RME_Q3 |
87 *max_vec_bit = __HFN_INT_MBOX_LPU0;
89 *msix_vecs_bmap = (__HFN_INT_CPE_Q4 | __HFN_INT_CPE_Q5 |
90 __HFN_INT_CPE_Q6 | __HFN_INT_CPE_Q7 |
91 __HFN_INT_RME_Q4 | __HFN_INT_RME_Q5 |
92 __HFN_INT_RME_Q6 | __HFN_INT_RME_Q7 |
94 *max_vec_bit = __HFN_INT_MBOX_LPU1;
97 *msix_vecs_bmap |= (__HFN_INT_ERR_EMC | __HFN_INT_ERR_LPU0 |
98 __HFN_INT_ERR_LPU1 | __HFN_INT_ERR_PSS);
99 *num_vecs = __HFN_NUMINTS;
103 * Dummy interrupt handler for handling spurious interrupts.
106 bfa_hwcb_msix_dummy(struct bfa_s *bfa, int vec)
111 * No special setup required for crossbow -- vector assignments are implicit.
114 bfa_hwcb_msix_init(struct bfa_s *bfa, int nvecs)
116 WARN_ON((nvecs != 1) && (nvecs != __HFN_NUMINTS));
118 bfa->msix.nvecs = nvecs;
119 bfa_hwcb_msix_uninstall(bfa);
123 bfa_hwcb_msix_ctrl_install(struct bfa_s *bfa)
127 if (bfa->msix.nvecs == 0)
130 if (bfa->msix.nvecs == 1) {
131 for (i = BFI_MSIX_CPE_QMIN_CB; i < BFI_MSIX_CB_MAX; i++)
132 bfa->msix.handler[i] = bfa_msix_all;
136 for (i = BFI_MSIX_RME_QMAX_CB+1; i < BFI_MSIX_CB_MAX; i++)
137 bfa->msix.handler[i] = bfa_msix_lpu_err;
141 bfa_hwcb_msix_queue_install(struct bfa_s *bfa)
145 if (bfa->msix.nvecs == 0)
148 if (bfa->msix.nvecs == 1) {
149 for (i = BFI_MSIX_CPE_QMIN_CB; i <= BFI_MSIX_RME_QMAX_CB; i++)
150 bfa->msix.handler[i] = bfa_msix_all;
154 for (i = BFI_MSIX_CPE_QMIN_CB; i <= BFI_MSIX_CPE_QMAX_CB; i++)
155 bfa->msix.handler[i] = bfa_msix_reqq;
157 for (i = BFI_MSIX_RME_QMIN_CB; i <= BFI_MSIX_RME_QMAX_CB; i++)
158 bfa->msix.handler[i] = bfa_msix_rspq;
162 bfa_hwcb_msix_uninstall(struct bfa_s *bfa)
166 for (i = 0; i < BFI_MSIX_CB_MAX; i++)
167 bfa->msix.handler[i] = bfa_hwcb_msix_dummy;
171 * No special enable/disable -- vector assignments are implicit.
174 bfa_hwcb_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix)
177 bfa->iocfc.hwif.hw_reqq_ack = bfa_hwcb_reqq_ack_msix;
178 bfa->iocfc.hwif.hw_rspq_ack = bfa_hwcb_rspq_ack_msix;
180 bfa->iocfc.hwif.hw_reqq_ack = NULL;
181 bfa->iocfc.hwif.hw_rspq_ack = bfa_hwcb_rspq_ack;
186 bfa_hwcb_msix_get_rme_range(struct bfa_s *bfa, u32 *start, u32 *end)
188 *start = BFI_MSIX_RME_QMIN_CB;
189 *end = BFI_MSIX_RME_QMAX_CB;