2 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
3 * Copyright (c) 2014- QLogic Corporation.
7 * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License (GPL) Version 2 as
11 * published by the Free Software Foundation
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
20 #include "bfa_modules.h"
23 BFA_TRC_FILE(HAL, IOCFC_CT);
26 * Dummy interrupt handler for handling spurious interrupt during chip-reinit.
29 bfa_hwct_msix_dummy(struct bfa_s *bfa, int vec)
34 bfa_hwct_reginit(struct bfa_s *bfa)
36 struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
37 void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
38 int fn = bfa_ioc_pcifn(&bfa->ioc);
41 bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS);
42 bfa_regs->intr_mask = (kva + HOSTFN0_INT_MSK);
44 bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS);
45 bfa_regs->intr_mask = (kva + HOSTFN1_INT_MSK);
50 bfa_hwct2_reginit(struct bfa_s *bfa)
52 struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
53 void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
55 bfa_regs->intr_status = (kva + CT2_HOSTFN_INT_STATUS);
56 bfa_regs->intr_mask = (kva + CT2_HOSTFN_INTR_MASK);
60 bfa_hwct_reqq_ack(struct bfa_s *bfa, int reqq)
64 r32 = readl(bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]);
65 writel(r32, bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]);
69 * Actions to respond RME Interrupt for Catapult ASIC:
70 * - Write 1 to Interrupt Status register (INTx only - done in bfa_intx())
71 * - Acknowledge by writing to RME Queue Control register
75 bfa_hwct_rspq_ack(struct bfa_s *bfa, int rspq, u32 ci)
79 r32 = readl(bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]);
80 writel(r32, bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]);
82 bfa_rspq_ci(bfa, rspq) = ci;
83 writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]);
87 * Actions to respond RME Interrupt for Catapult2 ASIC:
88 * - Write 1 to Interrupt Status register (INTx only - done in bfa_intx())
92 bfa_hwct2_rspq_ack(struct bfa_s *bfa, int rspq, u32 ci)
94 bfa_rspq_ci(bfa, rspq) = ci;
95 writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]);
99 bfa_hwct_msix_getvecs(struct bfa_s *bfa, u32 *msix_vecs_bmap,
100 u32 *num_vecs, u32 *max_vec_bit)
102 *msix_vecs_bmap = (1 << BFI_MSIX_CT_MAX) - 1;
103 *max_vec_bit = (1 << (BFI_MSIX_CT_MAX - 1));
104 *num_vecs = BFI_MSIX_CT_MAX;
108 * Setup MSI-X vector for catapult
111 bfa_hwct_msix_init(struct bfa_s *bfa, int nvecs)
113 WARN_ON((nvecs != 1) && (nvecs != BFI_MSIX_CT_MAX));
116 bfa->msix.nvecs = nvecs;
117 bfa_hwct_msix_uninstall(bfa);
121 bfa_hwct_msix_ctrl_install(struct bfa_s *bfa)
123 if (bfa->msix.nvecs == 0)
126 if (bfa->msix.nvecs == 1)
127 bfa->msix.handler[BFI_MSIX_LPU_ERR_CT] = bfa_msix_all;
129 bfa->msix.handler[BFI_MSIX_LPU_ERR_CT] = bfa_msix_lpu_err;
133 bfa_hwct_msix_queue_install(struct bfa_s *bfa)
137 if (bfa->msix.nvecs == 0)
140 if (bfa->msix.nvecs == 1) {
141 for (i = BFI_MSIX_CPE_QMIN_CT; i < BFI_MSIX_CT_MAX; i++)
142 bfa->msix.handler[i] = bfa_msix_all;
146 for (i = BFI_MSIX_CPE_QMIN_CT; i <= BFI_MSIX_CPE_QMAX_CT; i++)
147 bfa->msix.handler[i] = bfa_msix_reqq;
149 for (i = BFI_MSIX_RME_QMIN_CT; i <= BFI_MSIX_RME_QMAX_CT; i++)
150 bfa->msix.handler[i] = bfa_msix_rspq;
154 bfa_hwct_msix_uninstall(struct bfa_s *bfa)
158 for (i = 0; i < BFI_MSIX_CT_MAX; i++)
159 bfa->msix.handler[i] = bfa_hwct_msix_dummy;
163 * Enable MSI-X vectors
166 bfa_hwct_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix)
169 bfa_ioc_isr_mode_set(&bfa->ioc, msix);
173 bfa_hwct_msix_get_rme_range(struct bfa_s *bfa, u32 *start, u32 *end)
175 *start = BFI_MSIX_RME_QMIN_CT;
176 *end = BFI_MSIX_RME_QMAX_CT;