drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

   1 /*
   2  * Copyright (c) 2016 Linaro Ltd.
   3  * Copyright (c) 2016 Hisilicon Limited.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  */
  11
  12 #include "hisi_sas.h"
  13 #define DRV_NAME "hisi_sas_v2_hw"
  14
  15 /* global registers need init*/
  16 #define DLVRY_QUEUE_ENABLE              0x0
  17 #define IOST_BASE_ADDR_LO               0x8
  18 #define IOST_BASE_ADDR_HI               0xc
  19 #define ITCT_BASE_ADDR_LO               0x10
  20 #define ITCT_BASE_ADDR_HI               0x14
  21 #define IO_BROKEN_MSG_ADDR_LO           0x18
  22 #define IO_BROKEN_MSG_ADDR_HI           0x1c
  23 #define PHY_CONTEXT                     0x20
  24 #define PHY_STATE                       0x24
  25 #define PHY_PORT_NUM_MA                 0x28
  26 #define PORT_STATE                      0x2c
  27 #define PORT_STATE_PHY8_PORT_NUM_OFF    16
  28 #define PORT_STATE_PHY8_PORT_NUM_MSK    (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
  29 #define PORT_STATE_PHY8_CONN_RATE_OFF   20
  30 #define PORT_STATE_PHY8_CONN_RATE_MSK   (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
  31 #define PHY_CONN_RATE                   0x30
  32 #define HGC_TRANS_TASK_CNT_LIMIT        0x38
  33 #define AXI_AHB_CLK_CFG                 0x3c
  34 #define ITCT_CLR                        0x44
  35 #define ITCT_CLR_EN_OFF                 16
  36 #define ITCT_CLR_EN_MSK                 (0x1 << ITCT_CLR_EN_OFF)
  37 #define ITCT_DEV_OFF                    0
  38 #define ITCT_DEV_MSK                    (0x7ff << ITCT_DEV_OFF)
  39 #define AXI_USER1                       0x48
  40 #define AXI_USER2                       0x4c
  41 #define IO_SATA_BROKEN_MSG_ADDR_LO      0x58
  42 #define IO_SATA_BROKEN_MSG_ADDR_HI      0x5c
  43 #define SATA_INITI_D2H_STORE_ADDR_LO    0x60
  44 #define SATA_INITI_D2H_STORE_ADDR_HI    0x64
  45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
  46 #define HGC_SAS_TXFAIL_RETRY_CTRL       0x88
  47 #define HGC_GET_ITV_TIME                0x90
  48 #define DEVICE_MSG_WORK_MODE            0x94
  49 #define OPENA_WT_CONTI_TIME             0x9c
  50 #define I_T_NEXUS_LOSS_TIME             0xa0
  51 #define MAX_CON_TIME_LIMIT_TIME         0xa4
  52 #define BUS_INACTIVE_LIMIT_TIME         0xa8
  53 #define REJECT_TO_OPEN_LIMIT_TIME       0xac
  54 #define CFG_AGING_TIME                  0xbc
  55 #define HGC_DFX_CFG2                    0xc0
  56 #define HGC_IOMB_PROC1_STATUS   0x104
  57 #define CFG_1US_TIMER_TRSH              0xcc
  58 #define HGC_INVLD_DQE_INFO              0x148
  59 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF   9
  60 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK   (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
  61 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF   18
  62 #define INT_COAL_EN                     0x19c
  63 #define OQ_INT_COAL_TIME                0x1a0
  64 #define OQ_INT_COAL_CNT                 0x1a4
  65 #define ENT_INT_COAL_TIME               0x1a8
  66 #define ENT_INT_COAL_CNT                0x1ac
  67 #define OQ_INT_SRC                      0x1b0
  68 #define OQ_INT_SRC_MSK                  0x1b4
  69 #define ENT_INT_SRC1                    0x1b8
  70 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF    0
  71 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
  72 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF    8
  73 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
  74 #define ENT_INT_SRC2                    0x1bc
  75 #define ENT_INT_SRC3                    0x1c0
  76 #define ENT_INT_SRC3_ITC_INT_OFF        15
  77 #define ENT_INT_SRC3_ITC_INT_MSK        (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
  78 #define ENT_INT_SRC_MSK1                0x1c4
  79 #define ENT_INT_SRC_MSK2                0x1c8
  80 #define ENT_INT_SRC_MSK3                0x1cc
  81 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF  31
  82 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK  (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
  83 #define SAS_ECC_INTR_MSK                0x1ec
  84 #define HGC_ERR_STAT_EN                 0x238
  85 #define DLVRY_Q_0_BASE_ADDR_LO          0x260
  86 #define DLVRY_Q_0_BASE_ADDR_HI          0x264
  87 #define DLVRY_Q_0_DEPTH                 0x268
  88 #define DLVRY_Q_0_WR_PTR                0x26c
  89 #define DLVRY_Q_0_RD_PTR                0x270
  90 #define HYPER_STREAM_ID_EN_CFG          0xc80
  91 #define OQ0_INT_SRC_MSK                 0xc90
  92 #define COMPL_Q_0_BASE_ADDR_LO          0x4e0
  93 #define COMPL_Q_0_BASE_ADDR_HI          0x4e4
  94 #define COMPL_Q_0_DEPTH                 0x4e8
  95 #define COMPL_Q_0_WR_PTR                0x4ec
  96 #define COMPL_Q_0_RD_PTR                0x4f0
  97
  98 /* phy registers need init */
  99 #define PORT_BASE                       (0x2000)
 100
 101 #define PHY_CFG                         (PORT_BASE + 0x0)
 102 #define HARD_PHY_LINKRATE               (PORT_BASE + 0x4)
 103 #define PHY_CFG_ENA_OFF                 0
 104 #define PHY_CFG_ENA_MSK                 (0x1 << PHY_CFG_ENA_OFF)
 105 #define PHY_CFG_DC_OPT_OFF              2
 106 #define PHY_CFG_DC_OPT_MSK              (0x1 << PHY_CFG_DC_OPT_OFF)
 107 #define PROG_PHY_LINK_RATE              (PORT_BASE + 0x8)
 108 #define PROG_PHY_LINK_RATE_MAX_OFF      0
 109 #define PROG_PHY_LINK_RATE_MAX_MSK      (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
 110 #define PHY_CTRL                        (PORT_BASE + 0x14)
 111 #define PHY_CTRL_RESET_OFF              0
 112 #define PHY_CTRL_RESET_MSK              (0x1 << PHY_CTRL_RESET_OFF)
 113 #define SAS_PHY_CTRL                    (PORT_BASE + 0x20)
 114 #define SL_CFG                          (PORT_BASE + 0x84)
 115 #define PHY_PCN                         (PORT_BASE + 0x44)
 116 #define SL_TOUT_CFG                     (PORT_BASE + 0x8c)
 117 #define SL_CONTROL                      (PORT_BASE + 0x94)
 118 #define SL_CONTROL_NOTIFY_EN_OFF        0
 119 #define SL_CONTROL_NOTIFY_EN_MSK        (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
 120 #define SL_CONTROL_CTA_OFF              17
 121 #define SL_CONTROL_CTA_MSK              (0x1 << SL_CONTROL_CTA_OFF)
 122 #define TX_ID_DWORD0                    (PORT_BASE + 0x9c)
 123 #define TX_ID_DWORD1                    (PORT_BASE + 0xa0)
 124 #define TX_ID_DWORD2                    (PORT_BASE + 0xa4)
 125 #define TX_ID_DWORD3                    (PORT_BASE + 0xa8)
 126 #define TX_ID_DWORD4                    (PORT_BASE + 0xaC)
 127 #define TX_ID_DWORD5                    (PORT_BASE + 0xb0)
 128 #define TX_ID_DWORD6                    (PORT_BASE + 0xb4)
 129 #define TXID_AUTO                       (PORT_BASE + 0xb8)
 130 #define TXID_AUTO_CT3_OFF               1
 131 #define TXID_AUTO_CT3_MSK               (0x1 << TXID_AUTO_CT3_OFF)
 132 #define RX_IDAF_DWORD0                  (PORT_BASE + 0xc4)
 133 #define RX_IDAF_DWORD1                  (PORT_BASE + 0xc8)
 134 #define RX_IDAF_DWORD2                  (PORT_BASE + 0xcc)
 135 #define RX_IDAF_DWORD3                  (PORT_BASE + 0xd0)
 136 #define RX_IDAF_DWORD4                  (PORT_BASE + 0xd4)
 137 #define RX_IDAF_DWORD5                  (PORT_BASE + 0xd8)
 138 #define RX_IDAF_DWORD6                  (PORT_BASE + 0xdc)
 139 #define RXOP_CHECK_CFG_H                (PORT_BASE + 0xfc)
 140 #define DONE_RECEIVED_TIME              (PORT_BASE + 0x11c)
 141 #define CHL_INT0                        (PORT_BASE + 0x1b4)
 142 #define CHL_INT0_HOTPLUG_TOUT_OFF       0
 143 #define CHL_INT0_HOTPLUG_TOUT_MSK       (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
 144 #define CHL_INT0_SL_RX_BCST_ACK_OFF     1
 145 #define CHL_INT0_SL_RX_BCST_ACK_MSK     (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
 146 #define CHL_INT0_SL_PHY_ENABLE_OFF      2
 147 #define CHL_INT0_SL_PHY_ENABLE_MSK      (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
 148 #define CHL_INT0_NOT_RDY_OFF            4
 149 #define CHL_INT0_NOT_RDY_MSK            (0x1 << CHL_INT0_NOT_RDY_OFF)
 150 #define CHL_INT0_PHY_RDY_OFF            5
 151 #define CHL_INT0_PHY_RDY_MSK            (0x1 << CHL_INT0_PHY_RDY_OFF)
 152 #define CHL_INT1                        (PORT_BASE + 0x1b8)
 153 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF    15
 154 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
 155 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF    17
 156 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
 157 #define CHL_INT2                        (PORT_BASE + 0x1bc)
 158 #define CHL_INT0_MSK                    (PORT_BASE + 0x1c0)
 159 #define CHL_INT1_MSK                    (PORT_BASE + 0x1c4)
 160 #define CHL_INT2_MSK                    (PORT_BASE + 0x1c8)
 161 #define CHL_INT_COAL_EN                 (PORT_BASE + 0x1d0)
 162 #define PHY_CTRL_RDY_MSK                (PORT_BASE + 0x2b0)
 163 #define PHYCTRL_NOT_RDY_MSK             (PORT_BASE + 0x2b4)
 164 #define PHYCTRL_DWS_RESET_MSK           (PORT_BASE + 0x2b8)
 165 #define PHYCTRL_PHY_ENA_MSK             (PORT_BASE + 0x2bc)
 166 #define SL_RX_BCAST_CHK_MSK             (PORT_BASE + 0x2c0)
 167 #define PHYCTRL_OOB_RESTART_MSK         (PORT_BASE + 0x2c4)
 168 #define DMA_TX_STATUS                   (PORT_BASE + 0x2d0)
 169 #define DMA_TX_STATUS_BUSY_OFF          0
 170 #define DMA_TX_STATUS_BUSY_MSK          (0x1 << DMA_TX_STATUS_BUSY_OFF)
 171 #define DMA_RX_STATUS                   (PORT_BASE + 0x2e8)
 172 #define DMA_RX_STATUS_BUSY_OFF          0
 173 #define DMA_RX_STATUS_BUSY_MSK          (0x1 << DMA_RX_STATUS_BUSY_OFF)
 174
 175 #define AXI_CFG                         (0x5100)
 176 #define AM_CFG_MAX_TRANS                (0x5010)
 177 #define AM_CFG_SINGLE_PORT_MAX_TRANS    (0x5014)
 178
 179 /* HW dma structures */
 180 /* Delivery queue header */
 181 /* dw0 */
 182 #define CMD_HDR_ABORT_FLAG_OFF          0
 183 #define CMD_HDR_ABORT_FLAG_MSK          (0x3 << CMD_HDR_ABORT_FLAG_OFF)
 184 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF   2
 185 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK   (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
 186 #define CMD_HDR_RESP_REPORT_OFF         5
 187 #define CMD_HDR_RESP_REPORT_MSK         (0x1 << CMD_HDR_RESP_REPORT_OFF)
 188 #define CMD_HDR_TLR_CTRL_OFF            6
 189 #define CMD_HDR_TLR_CTRL_MSK            (0x3 << CMD_HDR_TLR_CTRL_OFF)
 190 #define CMD_HDR_PORT_OFF                18
 191 #define CMD_HDR_PORT_MSK                (0xf << CMD_HDR_PORT_OFF)
 192 #define CMD_HDR_PRIORITY_OFF            27
 193 #define CMD_HDR_PRIORITY_MSK            (0x1 << CMD_HDR_PRIORITY_OFF)
 194 #define CMD_HDR_CMD_OFF                 29
 195 #define CMD_HDR_CMD_MSK                 (0x7 << CMD_HDR_CMD_OFF)
 196 /* dw1 */
 197 #define CMD_HDR_DIR_OFF                 5
 198 #define CMD_HDR_DIR_MSK                 (0x3 << CMD_HDR_DIR_OFF)
 199 #define CMD_HDR_RESET_OFF               7
 200 #define CMD_HDR_RESET_MSK               (0x1 << CMD_HDR_RESET_OFF)
 201 #define CMD_HDR_VDTL_OFF                10
 202 #define CMD_HDR_VDTL_MSK                (0x1 << CMD_HDR_VDTL_OFF)
 203 #define CMD_HDR_FRAME_TYPE_OFF          11
 204 #define CMD_HDR_FRAME_TYPE_MSK          (0x1f << CMD_HDR_FRAME_TYPE_OFF)
 205 #define CMD_HDR_DEV_ID_OFF              16
 206 #define CMD_HDR_DEV_ID_MSK              (0xffff << CMD_HDR_DEV_ID_OFF)
 207 /* dw2 */
 208 #define CMD_HDR_CFL_OFF                 0
 209 #define CMD_HDR_CFL_MSK                 (0x1ff << CMD_HDR_CFL_OFF)
 210 #define CMD_HDR_NCQ_TAG_OFF             10
 211 #define CMD_HDR_NCQ_TAG_MSK             (0x1f << CMD_HDR_NCQ_TAG_OFF)
 212 #define CMD_HDR_MRFL_OFF                15
 213 #define CMD_HDR_MRFL_MSK                (0x1ff << CMD_HDR_MRFL_OFF)
 214 #define CMD_HDR_SG_MOD_OFF              24
 215 #define CMD_HDR_SG_MOD_MSK              (0x3 << CMD_HDR_SG_MOD_OFF)
 216 #define CMD_HDR_FIRST_BURST_OFF         26
 217 #define CMD_HDR_FIRST_BURST_MSK         (0x1 << CMD_HDR_SG_MOD_OFF)
 218 /* dw3 */
 219 #define CMD_HDR_IPTT_OFF                0
 220 #define CMD_HDR_IPTT_MSK                (0xffff << CMD_HDR_IPTT_OFF)
 221 /* dw6 */
 222 #define CMD_HDR_DIF_SGL_LEN_OFF         0
 223 #define CMD_HDR_DIF_SGL_LEN_MSK         (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
 224 #define CMD_HDR_DATA_SGL_LEN_OFF        16
 225 #define CMD_HDR_DATA_SGL_LEN_MSK        (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
 226 #define CMD_HDR_ABORT_IPTT_OFF          16
 227 #define CMD_HDR_ABORT_IPTT_MSK          (0xffff << CMD_HDR_ABORT_IPTT_OFF)
 228
 229 /* Completion header */
 230 /* dw0 */
 231 #define CMPLT_HDR_RSPNS_XFRD_OFF        10
 232 #define CMPLT_HDR_RSPNS_XFRD_MSK        (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
 233 #define CMPLT_HDR_ERX_OFF               12
 234 #define CMPLT_HDR_ERX_MSK               (0x1 << CMPLT_HDR_ERX_OFF)
 235 #define CMPLT_HDR_ABORT_STAT_OFF        13
 236 #define CMPLT_HDR_ABORT_STAT_MSK        (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
 237 /* abort_stat */
 238 #define STAT_IO_NOT_VALID               0x1
 239 #define STAT_IO_NO_DEVICE               0x2
 240 #define STAT_IO_COMPLETE                0x3
 241 #define STAT_IO_ABORTED                 0x4
 242 /* dw1 */
 243 #define CMPLT_HDR_IPTT_OFF              0
 244 #define CMPLT_HDR_IPTT_MSK              (0xffff << CMPLT_HDR_IPTT_OFF)
 245 #define CMPLT_HDR_DEV_ID_OFF            16
 246 #define CMPLT_HDR_DEV_ID_MSK            (0xffff << CMPLT_HDR_DEV_ID_OFF)
 247
 248 /* ITCT header */
 249 /* qw0 */
 250 #define ITCT_HDR_DEV_TYPE_OFF           0
 251 #define ITCT_HDR_DEV_TYPE_MSK           (0x3 << ITCT_HDR_DEV_TYPE_OFF)
 252 #define ITCT_HDR_VALID_OFF              2
 253 #define ITCT_HDR_VALID_MSK              (0x1 << ITCT_HDR_VALID_OFF)
 254 #define ITCT_HDR_MCR_OFF                5
 255 #define ITCT_HDR_MCR_MSK                (0xf << ITCT_HDR_MCR_OFF)
 256 #define ITCT_HDR_VLN_OFF                9
 257 #define ITCT_HDR_VLN_MSK                (0xf << ITCT_HDR_VLN_OFF)
 258 #define ITCT_HDR_PORT_ID_OFF            28
 259 #define ITCT_HDR_PORT_ID_MSK            (0xf << ITCT_HDR_PORT_ID_OFF)
 260 /* qw2 */
 261 #define ITCT_HDR_INLT_OFF               0
 262 #define ITCT_HDR_INLT_MSK               (0xffffULL << ITCT_HDR_INLT_OFF)
 263 #define ITCT_HDR_BITLT_OFF              16
 264 #define ITCT_HDR_BITLT_MSK              (0xffffULL << ITCT_HDR_BITLT_OFF)
 265 #define ITCT_HDR_MCTLT_OFF              32
 266 #define ITCT_HDR_MCTLT_MSK              (0xffffULL << ITCT_HDR_MCTLT_OFF)
 267 #define ITCT_HDR_RTOLT_OFF              48
 268 #define ITCT_HDR_RTOLT_MSK              (0xffffULL << ITCT_HDR_RTOLT_OFF)
 269
 270 struct hisi_sas_complete_v2_hdr {
 271         __le32 dw0;
 272         __le32 dw1;
 273         __le32 act;
 274         __le32 dw3;
 275 };
 276
 277 struct hisi_sas_err_record_v2 {
 278         /* dw0 */
 279         __le32 trans_tx_fail_type;
 280
 281         /* dw1 */
 282         __le32 trans_rx_fail_type;
 283
 284         /* dw2 */
 285         __le16 dma_tx_err_type;
 286         __le16 sipc_rx_err_type;
 287
 288         /* dw3 */
 289         __le32 dma_rx_err_type;
 290 };
 291
 292 enum {
 293         HISI_SAS_PHY_PHY_UPDOWN,
 294         HISI_SAS_PHY_CHNL_INT,
 295         HISI_SAS_PHY_INT_NR
 296 };
 297
 298 enum {
 299         TRANS_TX_FAIL_BASE = 0x0, /* dw0 */
 300         TRANS_RX_FAIL_BASE = 0x100, /* dw1 */
 301         DMA_TX_ERR_BASE = 0x200, /* dw2 bit 15-0 */
 302         SIPC_RX_ERR_BASE = 0x300, /* dw2 bit 31-16*/
 303         DMA_RX_ERR_BASE = 0x400, /* dw3 */
 304
 305         /* trans tx*/
 306         TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */
 307         TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */
 308         TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */
 309         TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */
 310         TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */
 311         RESERVED0, /* 0x5 */
 312         TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */
 313         TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */
 314         TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */
 315         TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */
 316         TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */
 317         TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */
 318         TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */
 319         TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */
 320         TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */
 321         TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */
 322         TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */
 323         TRANS_TX_ERR_FRAME_TXED, /* 0x11 */
 324         TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */
 325         TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */
 326         TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */
 327         TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */
 328         TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/
 329         TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */
 330         TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */
 331         TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */
 332         TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/
 333         TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/
 334         /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
 335         TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */
 336         /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
 337         TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */
 338         TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */
 339         /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
 340         TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */
 341
 342         /* trans rx */
 343         TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x100 */
 344         TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x101 for sata/stp */
 345         TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x102 for ssp/smp */
 346         /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x102 <] for sata/stp */
 347         TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x103 for sata/stp */
 348         TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x104 for sata/stp */
 349         TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x105 for smp */
 350         /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x105 <] for sata/stp */
 351         TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x106 for sata/stp*/
 352         TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x107 */
 353         TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x108 */
 354         TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x109 */
 355         TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x10a */
 356         RESERVED1, /* 0x10b */
 357         TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x10c */
 358         TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x10d */
 359         TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x10e */
 360         TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x10f */
 361         TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x110 for ssp/smp */
 362         TRANS_RX_ERR_WITH_BAD_HASH, /* 0x111 for ssp */
 363         /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x111 <] for sata/stp */
 364         TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x112 for ssp*/
 365         /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x112 <] for sata/stp */
 366         TRANS_RX_SSP_FRM_LEN_ERR, /* 0x113 for ssp */
 367         /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x113 <] for sata */
 368         RESERVED2, /* 0x114 */
 369         RESERVED3, /* 0x115 */
 370         RESERVED4, /* 0x116 */
 371         RESERVED5, /* 0x117 */
 372         TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x118 */
 373         TRANS_RX_SMP_FRM_LEN_ERR, /* 0x119 */
 374         TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x11a */
 375         RESERVED6, /* 0x11b */
 376         RESERVED7, /* 0x11c */
 377         RESERVED8, /* 0x11d */
 378         RESERVED9, /* 0x11e */
 379         TRANS_RX_R_ERR, /* 0x11f */
 380
 381         /* dma tx */
 382         DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x200 */
 383         DMA_TX_DIF_APP_ERR, /* 0x201 */
 384         DMA_TX_DIF_RPP_ERR, /* 0x202 */
 385         DMA_TX_DATA_SGL_OVERFLOW, /* 0x203 */
 386         DMA_TX_DIF_SGL_OVERFLOW, /* 0x204 */
 387         DMA_TX_UNEXP_XFER_ERR, /* 0x205 */
 388         DMA_TX_UNEXP_RETRANS_ERR, /* 0x206 */
 389         DMA_TX_XFER_LEN_OVERFLOW, /* 0x207 */
 390         DMA_TX_XFER_OFFSET_ERR, /* 0x208 */
 391         DMA_TX_RAM_ECC_ERR, /* 0x209 */
 392         DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x20a */
 393
 394         /* sipc rx */
 395         SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x300 */
 396         SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x301 */
 397         SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x302 */
 398         SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x303 */
 399         SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x304 */
 400         SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x305 */
 401         SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x306 */
 402         SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x307 */
 403         SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x308 */
 404         SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x309 */
 405         SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x30a */
 406
 407         /* dma rx */
 408         DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x400 */
 409         DMA_RX_DIF_APP_ERR, /* 0x401 */
 410         DMA_RX_DIF_RPP_ERR, /* 0x402 */
 411         DMA_RX_DATA_SGL_OVERFLOW, /* 0x403 */
 412         DMA_RX_DIF_SGL_OVERFLOW, /* 0x404 */
 413         DMA_RX_DATA_LEN_OVERFLOW, /* 0x405 */
 414         DMA_RX_DATA_LEN_UNDERFLOW, /* 0x406 */
 415         DMA_RX_DATA_OFFSET_ERR, /* 0x407 */
 416         RESERVED10, /* 0x408 */
 417         DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x409 */
 418         DMA_RX_RESP_BUF_OVERFLOW, /* 0x40a */
 419         DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x40b */
 420         DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x40c */
 421         DMA_RX_UNEXP_RDFRAME_ERR, /* 0x40d */
 422         DMA_RX_PIO_DATA_LEN_ERR, /* 0x40e */
 423         DMA_RX_RDSETUP_STATUS_ERR, /* 0x40f */
 424         DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x410 */
 425         DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x411 */
 426         DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x412 */
 427         DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x413 */
 428         DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x414 */
 429         DMA_RX_RDSETUP_OFFSET_ERR, /* 0x415 */
 430         DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x416 */
 431         DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x417 */
 432         DMA_RX_RAM_ECC_ERR, /* 0x418 */
 433         DMA_RX_UNKNOWN_FRM_ERR, /* 0x419 */
 434 };
 435
 436 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
 437
 438 #define DIR_NO_DATA 0
 439 #define DIR_TO_INI 1
 440 #define DIR_TO_DEVICE 2
 441 #define DIR_RESERVED 3
 442
 443 #define SATA_PROTOCOL_NONDATA           0x1
 444 #define SATA_PROTOCOL_PIO               0x2
 445 #define SATA_PROTOCOL_DMA               0x4
 446 #define SATA_PROTOCOL_FPDMA             0x8
 447 #define SATA_PROTOCOL_ATAPI             0x10
 448
 449 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
 450 {
 451         void __iomem *regs = hisi_hba->regs + off;
 452
 453         return readl(regs);
 454 }
 455
 456 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
 457 {
 458         void __iomem *regs = hisi_hba->regs + off;
 459
 460         return readl_relaxed(regs);
 461 }
 462
 463 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
 464 {
 465         void __iomem *regs = hisi_hba->regs + off;
 466
 467         writel(val, regs);
 468 }
 469
 470 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
 471                                  u32 off, u32 val)
 472 {
 473         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 474
 475         writel(val, regs);
 476 }
 477
 478 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
 479                                       int phy_no, u32 off)
 480 {
 481         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 482
 483         return readl(regs);
 484 }
 485
 486 /* This function needs to be protected from pre-emption. */
 487 static int
 488 slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba, int *slot_idx,
 489                        struct domain_device *device)
 490 {
 491         unsigned int index = 0;
 492         void *bitmap = hisi_hba->slot_index_tags;
 493         int sata_dev = dev_is_sata(device);
 494
 495         while (1) {
 496                 index = find_next_zero_bit(bitmap, hisi_hba->slot_index_count,
 497                                            index);
 498                 if (index >= hisi_hba->slot_index_count)
 499                         return -SAS_QUEUE_FULL;
 500                 /*
 501                  * SAS IPTT bit0 should be 1
 502                  */
 503                 if (sata_dev || (index & 1))
 504                         break;
 505                 index++;
 506         }
 507
 508         set_bit(index, bitmap);
 509         *slot_idx = index;
 510         return 0;
 511 }
 512
 513 static struct
 514 hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device)
 515 {
 516         struct hisi_hba *hisi_hba = device->port->ha->lldd_ha;
 517         struct hisi_sas_device *sas_dev = NULL;
 518         int i, sata_dev = dev_is_sata(device);
 519
 520         spin_lock(&hisi_hba->lock);
 521         for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
 522                 /*
 523                  * SATA device id bit0 should be 0
 524                  */
 525                 if (sata_dev && (i & 1))
 526                         continue;
 527                 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) {
 528                         hisi_hba->devices[i].device_id = i;
 529                         sas_dev = &hisi_hba->devices[i];
 530                         sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
 531                         sas_dev->dev_type = device->dev_type;
 532                         sas_dev->hisi_hba = hisi_hba;
 533                         sas_dev->sas_device = device;
 534                         break;
 535                 }
 536         }
 537         spin_unlock(&hisi_hba->lock);
 538
 539         return sas_dev;
 540 }
 541
 542 static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 543 {
 544         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 545
 546         cfg &= ~PHY_CFG_DC_OPT_MSK;
 547         cfg |= 1 << PHY_CFG_DC_OPT_OFF;
 548         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 549 }
 550
 551 static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 552 {
 553         struct sas_identify_frame identify_frame;
 554         u32 *identify_buffer;
 555
 556         memset(&identify_frame, 0, sizeof(identify_frame));
 557         identify_frame.dev_type = SAS_END_DEVICE;
 558         identify_frame.frame_type = 0;
 559         identify_frame._un1 = 1;
 560         identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
 561         identify_frame.target_bits = SAS_PROTOCOL_NONE;
 562         memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 563         memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 564         identify_frame.phy_id = phy_no;
 565         identify_buffer = (u32 *)(&identify_frame);
 566
 567         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
 568                         __swab32(identify_buffer[0]));
 569         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
 570                         __swab32(identify_buffer[1]));
 571         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
 572                         __swab32(identify_buffer[2]));
 573         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
 574                         __swab32(identify_buffer[3]));
 575         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
 576                         __swab32(identify_buffer[4]));
 577         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
 578                         __swab32(identify_buffer[5]));
 579 }
 580
 581 static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
 582                              struct hisi_sas_device *sas_dev)
 583 {
 584         struct domain_device *device = sas_dev->sas_device;
 585         struct device *dev = &hisi_hba->pdev->dev;
 586         u64 qw0, device_id = sas_dev->device_id;
 587         struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
 588         struct domain_device *parent_dev = device->parent;
 589         struct hisi_sas_port *port = device->port->lldd_port;
 590
 591         memset(itct, 0, sizeof(*itct));
 592
 593         /* qw0 */
 594         qw0 = 0;
 595         switch (sas_dev->dev_type) {
 596         case SAS_END_DEVICE:
 597         case SAS_EDGE_EXPANDER_DEVICE:
 598         case SAS_FANOUT_EXPANDER_DEVICE:
 599                 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
 600                 break;
 601         case SAS_SATA_DEV:
 602         case SAS_SATA_PENDING:
 603                 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
 604                         qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
 605                 else
 606                         qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
 607                 break;
 608         default:
 609                 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
 610                          sas_dev->dev_type);
 611         }
 612
 613         qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
 614                 (device->linkrate << ITCT_HDR_MCR_OFF) |
 615                 (1 << ITCT_HDR_VLN_OFF) |
 616                 (port->id << ITCT_HDR_PORT_ID_OFF));
 617         itct->qw0 = cpu_to_le64(qw0);
 618
 619         /* qw1 */
 620         memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
 621         itct->sas_addr = __swab64(itct->sas_addr);
 622
 623         /* qw2 */
 624         if (!dev_is_sata(device))
 625                 itct->qw2 = cpu_to_le64((500ULL << ITCT_HDR_INLT_OFF) |
 626                                         (0x1ULL << ITCT_HDR_BITLT_OFF) |
 627                                         (0x32ULL << ITCT_HDR_MCTLT_OFF) |
 628                                         (0x1ULL << ITCT_HDR_RTOLT_OFF));
 629 }
 630
 631 static void free_device_v2_hw(struct hisi_hba *hisi_hba,
 632                               struct hisi_sas_device *sas_dev)
 633 {
 634         u64 qw0, dev_id = sas_dev->device_id;
 635         struct device *dev = &hisi_hba->pdev->dev;
 636         struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
 637         u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
 638         int i;
 639
 640         /* clear the itct interrupt state */
 641         if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
 642                 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
 643                                  ENT_INT_SRC3_ITC_INT_MSK);
 644
 645         /* clear the itct int*/
 646         for (i = 0; i < 2; i++) {
 647                 /* clear the itct table*/
 648                 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
 649                 reg_val |= ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
 650                 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
 651
 652                 udelay(10);
 653                 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
 654                 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) {
 655                         dev_dbg(dev, "got clear ITCT done interrupt\n");
 656
 657                         /* invalid the itct state*/
 658                         qw0 = cpu_to_le64(itct->qw0);
 659                         qw0 &= ~(1 << ITCT_HDR_VALID_OFF);
 660                         hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
 661                                          ENT_INT_SRC3_ITC_INT_MSK);
 662                         hisi_hba->devices[dev_id].dev_type = SAS_PHY_UNUSED;
 663                         hisi_hba->devices[dev_id].dev_status = HISI_SAS_DEV_NORMAL;
 664
 665                         /* clear the itct */
 666                         hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
 667                         dev_dbg(dev, "clear ITCT ok\n");
 668                         break;
 669                 }
 670         }
 671 }
 672
 673 static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
 674 {
 675         int i, reset_val;
 676         u32 val;
 677         unsigned long end_time;
 678         struct device *dev = &hisi_hba->pdev->dev;
 679
 680         /* The mask needs to be set depending on the number of phys */
 681         if (hisi_hba->n_phy == 9)
 682                 reset_val = 0x1fffff;
 683         else
 684                 reset_val = 0x7ffff;
 685
 686         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
 687
 688         /* Disable all of the PHYs */
 689         for (i = 0; i < hisi_hba->n_phy; i++) {
 690                 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
 691
 692                 phy_cfg &= ~PHY_CTRL_RESET_MSK;
 693                 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
 694         }
 695         udelay(50);
 696
 697         /* Ensure DMA tx & rx idle */
 698         for (i = 0; i < hisi_hba->n_phy; i++) {
 699                 u32 dma_tx_status, dma_rx_status;
 700
 701                 end_time = jiffies + msecs_to_jiffies(1000);
 702
 703                 while (1) {
 704                         dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
 705                                                             DMA_TX_STATUS);
 706                         dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
 707                                                             DMA_RX_STATUS);
 708
 709                         if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
 710                                 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
 711                                 break;
 712
 713                         msleep(20);
 714                         if (time_after(jiffies, end_time))
 715                                 return -EIO;
 716                 }
 717         }
 718
 719         /* Ensure axi bus idle */
 720         end_time = jiffies + msecs_to_jiffies(1000);
 721         while (1) {
 722                 u32 axi_status =
 723                         hisi_sas_read32(hisi_hba, AXI_CFG);
 724
 725                 if (axi_status == 0)
 726                         break;
 727
 728                 msleep(20);
 729                 if (time_after(jiffies, end_time))
 730                         return -EIO;
 731         }
 732
 733         if (ACPI_HANDLE(dev)) {
 734                 acpi_status s;
 735
 736                 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
 737                 if (ACPI_FAILURE(s)) {
 738                         dev_err(dev, "Reset failed\n");
 739                         return -EIO;
 740                 }
 741         } else if (hisi_hba->ctrl) {
 742                 /* reset and disable clock*/
 743                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
 744                                 reset_val);
 745                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
 746                                 reset_val);
 747                 msleep(1);
 748                 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
 749                 if (reset_val != (val & reset_val)) {
 750                         dev_err(dev, "SAS reset fail.\n");
 751                         return -EIO;
 752                 }
 753
 754                 /* De-reset and enable clock*/
 755                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
 756                                 reset_val);
 757                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
 758                                 reset_val);
 759                 msleep(1);
 760                 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
 761                                 &val);
 762                 if (val & reset_val) {
 763                         dev_err(dev, "SAS de-reset fail.\n");
 764                         return -EIO;
 765                 }
 766         } else
 767                 dev_warn(dev, "no reset method\n");
 768
 769         return 0;
 770 }
 771
 772 static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
 773 {
 774         struct device *dev = &hisi_hba->pdev->dev;
 775         int i;
 776
 777         /* Global registers init */
 778
 779         /* Deal with am-max-transmissions quirk */
 780         if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) {
 781                 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
 782                 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
 783                                  0x2020);
 784         } /* Else, use defaults -> do nothing */
 785
 786         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
 787                          (u32)((1ULL << hisi_hba->queue_count) - 1));
 788         hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
 789         hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
 790         hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
 791         hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
 792         hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
 793         hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
 794         hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32);
 795         hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
 796         hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
 797         hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
 798         hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
 799         hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
 800         hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
 801         hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
 802         hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
 803         hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
 804         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
 805         hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
 806         hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
 807         hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
 808         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
 809         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
 810         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffffffe);
 811         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfffff3c0);
 812         for (i = 0; i < hisi_hba->queue_count; i++)
 813                 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
 814
 815         hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
 816         hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
 817
 818         for (i = 0; i < hisi_hba->n_phy; i++) {
 819                 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
 820                 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, 0x30b9908);
 821                 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
 822                 hisi_sas_phy_write32(hisi_hba, i, SL_CONTROL, 0x0);
 823                 hisi_sas_phy_write32(hisi_hba, i, TXID_AUTO, 0x2);
 824                 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x10);
 825                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
 826                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
 827                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
 828                 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
 829                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
 830                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff);
 831                 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x23f801fc);
 832                 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
 833                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
 834                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
 835                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
 836                 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
 837                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
 838                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
 839                 if (hisi_hba->refclk_frequency_mhz == 66)
 840                         hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
 841                 /* else, do nothing -> leave it how you found it */
 842         }
 843
 844         for (i = 0; i < hisi_hba->queue_count; i++) {
 845                 /* Delivery queue */
 846                 hisi_sas_write32(hisi_hba,
 847                                  DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
 848                                  upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
 849
 850                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
 851                                  lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
 852
 853                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
 854                                  HISI_SAS_QUEUE_SLOTS);
 855
 856                 /* Completion queue */
 857                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
 858                                  upper_32_bits(hisi_hba->complete_hdr_dma[i]));
 859
 860                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
 861                                  lower_32_bits(hisi_hba->complete_hdr_dma[i]));
 862
 863                 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
 864                                  HISI_SAS_QUEUE_SLOTS);
 865         }
 866
 867         /* itct */
 868         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
 869                          lower_32_bits(hisi_hba->itct_dma));
 870
 871         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
 872                          upper_32_bits(hisi_hba->itct_dma));
 873
 874         /* iost */
 875         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
 876                          lower_32_bits(hisi_hba->iost_dma));
 877
 878         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
 879                          upper_32_bits(hisi_hba->iost_dma));
 880
 881         /* breakpoint */
 882         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
 883                          lower_32_bits(hisi_hba->breakpoint_dma));
 884
 885         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
 886                          upper_32_bits(hisi_hba->breakpoint_dma));
 887
 888         /* SATA broken msg */
 889         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
 890                          lower_32_bits(hisi_hba->sata_breakpoint_dma));
 891
 892         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
 893                          upper_32_bits(hisi_hba->sata_breakpoint_dma));
 894
 895         /* SATA initial fis */
 896         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
 897                          lower_32_bits(hisi_hba->initial_fis_dma));
 898
 899         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
 900                          upper_32_bits(hisi_hba->initial_fis_dma));
 901 }
 902
 903 static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
 904 {
 905         struct device *dev = &hisi_hba->pdev->dev;
 906         int rc;
 907
 908         rc = reset_hw_v2_hw(hisi_hba);
 909         if (rc) {
 910                 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
 911                 return rc;
 912         }
 913
 914         msleep(100);
 915         init_reg_v2_hw(hisi_hba);
 916
 917         return 0;
 918 }
 919
 920 static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 921 {
 922         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 923
 924         cfg |= PHY_CFG_ENA_MSK;
 925         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 926 }
 927
 928 static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 929 {
 930         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 931
 932         cfg &= ~PHY_CFG_ENA_MSK;
 933         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 934 }
 935
 936 static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 937 {
 938         config_id_frame_v2_hw(hisi_hba, phy_no);
 939         config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
 940         enable_phy_v2_hw(hisi_hba, phy_no);
 941 }
 942
 943 static void stop_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 944 {
 945         disable_phy_v2_hw(hisi_hba, phy_no);
 946 }
 947
 948 static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 949 {
 950         stop_phy_v2_hw(hisi_hba, phy_no);
 951         msleep(100);
 952         start_phy_v2_hw(hisi_hba, phy_no);
 953 }
 954
 955 static void start_phys_v2_hw(unsigned long data)
 956 {
 957         struct hisi_hba *hisi_hba = (struct hisi_hba *)data;
 958         int i;
 959
 960         for (i = 0; i < hisi_hba->n_phy; i++)
 961                 start_phy_v2_hw(hisi_hba, i);
 962 }
 963
 964 static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
 965 {
 966         struct timer_list *timer = &hisi_hba->timer;
 967
 968         setup_timer(timer, start_phys_v2_hw, (unsigned long)hisi_hba);
 969         mod_timer(timer, jiffies + HZ);
 970 }
 971
 972 static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 973 {
 974         u32 sl_control;
 975
 976         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
 977         sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
 978         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
 979         msleep(1);
 980         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
 981         sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
 982         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
 983 }
 984
 985 static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
 986 {
 987         int i, bitmap = 0;
 988         u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
 989         u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
 990
 991         for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
 992                 if (phy_state & 1 << i)
 993                         if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
 994                                 bitmap |= 1 << i;
 995
 996         if (hisi_hba->n_phy == 9) {
 997                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
 998
 999                 if (phy_state & 1 << 8)
1000                         if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1001                              PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
1002                                 bitmap |= 1 << 9;
1003         }
1004
1005         return bitmap;
1006 }
1007
1008 /**
1009  * This function allocates across all queues to load balance.
1010  * Slots are allocated from queues in a round-robin fashion.
1011  *
1012  * The callpath to this function and upto writing the write
1013  * queue pointer should be safe from interruption.
1014  */
1015 static int get_free_slot_v2_hw(struct hisi_hba *hisi_hba, int *q, int *s)
1016 {
1017         struct device *dev = &hisi_hba->pdev->dev;
1018         struct hisi_sas_dq *dq;
1019         u32 r, w;
1020         int queue = hisi_hba->queue;
1021
1022         while (1) {
1023                 dq = &hisi_hba->dq[queue];
1024                 w = dq->wr_point;
1025                 r = hisi_sas_read32_relaxed(hisi_hba,
1026                                             DLVRY_Q_0_RD_PTR + (queue * 0x14));
1027                 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
1028                         queue = (queue + 1) % hisi_hba->queue_count;
1029                         if (queue == hisi_hba->queue) {
1030                                 dev_warn(dev, "could not find free slot\n");
1031                                 return -EAGAIN;
1032                         }
1033                         continue;
1034                 }
1035                 break;
1036         }
1037         hisi_hba->queue = (queue + 1) % hisi_hba->queue_count;
1038         *q = queue;
1039         *s = w;
1040         return 0;
1041 }
1042
1043 static void start_delivery_v2_hw(struct hisi_hba *hisi_hba)
1044 {
1045         int dlvry_queue = hisi_hba->slot_prep->dlvry_queue;
1046         int dlvry_queue_slot = hisi_hba->slot_prep->dlvry_queue_slot;
1047         struct hisi_sas_dq *dq = &hisi_hba->dq[dlvry_queue];
1048
1049         dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
1050         hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
1051                          dq->wr_point);
1052 }
1053
1054 static int prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
1055                               struct hisi_sas_slot *slot,
1056                               struct hisi_sas_cmd_hdr *hdr,
1057                               struct scatterlist *scatter,
1058                               int n_elem)
1059 {
1060         struct device *dev = &hisi_hba->pdev->dev;
1061         struct scatterlist *sg;
1062         int i;
1063
1064         if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
1065                 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
1066                         n_elem);
1067                 return -EINVAL;
1068         }
1069
1070         slot->sge_page = dma_pool_alloc(hisi_hba->sge_page_pool, GFP_ATOMIC,
1071                                         &slot->sge_page_dma);
1072         if (!slot->sge_page)
1073                 return -ENOMEM;
1074
1075         for_each_sg(scatter, sg, n_elem, i) {
1076                 struct hisi_sas_sge *entry = &slot->sge_page->sge[i];
1077
1078                 entry->addr = cpu_to_le64(sg_dma_address(sg));
1079                 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1080                 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1081                 entry->data_off = 0;
1082         }
1083
1084         hdr->prd_table_addr = cpu_to_le64(slot->sge_page_dma);
1085
1086         hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1087
1088         return 0;
1089 }
1090
1091 static int prep_smp_v2_hw(struct hisi_hba *hisi_hba,
1092                           struct hisi_sas_slot *slot)
1093 {
1094         struct sas_task *task = slot->task;
1095         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1096         struct domain_device *device = task->dev;
1097         struct device *dev = &hisi_hba->pdev->dev;
1098         struct hisi_sas_port *port = slot->port;
1099         struct scatterlist *sg_req, *sg_resp;
1100         struct hisi_sas_device *sas_dev = device->lldd_dev;
1101         dma_addr_t req_dma_addr;
1102         unsigned int req_len, resp_len;
1103         int elem, rc;
1104
1105         /*
1106         * DMA-map SMP request, response buffers
1107         */
1108         /* req */
1109         sg_req = &task->smp_task.smp_req;
1110         elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
1111         if (!elem)
1112                 return -ENOMEM;
1113         req_len = sg_dma_len(sg_req);
1114         req_dma_addr = sg_dma_address(sg_req);
1115
1116         /* resp */
1117         sg_resp = &task->smp_task.smp_resp;
1118         elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
1119         if (!elem) {
1120                 rc = -ENOMEM;
1121                 goto err_out_req;
1122         }
1123         resp_len = sg_dma_len(sg_resp);
1124         if ((req_len & 0x3) || (resp_len & 0x3)) {
1125                 rc = -EINVAL;
1126                 goto err_out_resp;
1127         }
1128
1129         /* create header */
1130         /* dw0 */
1131         hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1132                                (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1133                                (2 << CMD_HDR_CMD_OFF)); /* smp */
1134
1135         /* map itct entry */
1136         hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1137                                (1 << CMD_HDR_FRAME_TYPE_OFF) |
1138                                (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1139
1140         /* dw2 */
1141         hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1142                                (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1143                                CMD_HDR_MRFL_OFF));
1144
1145         hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1146
1147         hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1148         hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
1149
1150         return 0;
1151
1152 err_out_resp:
1153         dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
1154                      DMA_FROM_DEVICE);
1155 err_out_req:
1156         dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
1157                      DMA_TO_DEVICE);
1158         return rc;
1159 }
1160
1161 static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
1162                           struct hisi_sas_slot *slot, int is_tmf,
1163                           struct hisi_sas_tmf_task *tmf)
1164 {
1165         struct sas_task *task = slot->task;
1166         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1167         struct domain_device *device = task->dev;
1168         struct hisi_sas_device *sas_dev = device->lldd_dev;
1169         struct hisi_sas_port *port = slot->port;
1170         struct sas_ssp_task *ssp_task = &task->ssp_task;
1171         struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1172         int has_data = 0, rc, priority = is_tmf;
1173         u8 *buf_cmd;
1174         u32 dw1 = 0, dw2 = 0;
1175
1176         hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1177                                (2 << CMD_HDR_TLR_CTRL_OFF) |
1178                                (port->id << CMD_HDR_PORT_OFF) |
1179                                (priority << CMD_HDR_PRIORITY_OFF) |
1180                                (1 << CMD_HDR_CMD_OFF)); /* ssp */
1181
1182         dw1 = 1 << CMD_HDR_VDTL_OFF;
1183         if (is_tmf) {
1184                 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1185                 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1186         } else {
1187                 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1188                 switch (scsi_cmnd->sc_data_direction) {
1189                 case DMA_TO_DEVICE:
1190                         has_data = 1;
1191                         dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1192                         break;
1193                 case DMA_FROM_DEVICE:
1194                         has_data = 1;
1195                         dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1196                         break;
1197                 default:
1198                         dw1 &= ~CMD_HDR_DIR_MSK;
1199                 }
1200         }
1201
1202         /* map itct entry */
1203         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1204         hdr->dw1 = cpu_to_le32(dw1);
1205
1206         dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1207               + 3) / 4) << CMD_HDR_CFL_OFF) |
1208               ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1209               (2 << CMD_HDR_SG_MOD_OFF);
1210         hdr->dw2 = cpu_to_le32(dw2);
1211
1212         hdr->transfer_tags = cpu_to_le32(slot->idx);
1213
1214         if (has_data) {
1215                 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1216                                         slot->n_elem);
1217                 if (rc)
1218                         return rc;
1219         }
1220
1221         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1222         hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma);
1223         hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
1224
1225         buf_cmd = slot->command_table + sizeof(struct ssp_frame_hdr);
1226
1227         memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1228         if (!is_tmf) {
1229                 buf_cmd[9] = task->ssp_task.task_attr |
1230                                 (task->ssp_task.task_prio << 3);
1231                 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1232                                 task->ssp_task.cmd->cmd_len);
1233         } else {
1234                 buf_cmd[10] = tmf->tmf;
1235                 switch (tmf->tmf) {
1236                 case TMF_ABORT_TASK:
1237                 case TMF_QUERY_TASK:
1238                         buf_cmd[12] =
1239                                 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1240                         buf_cmd[13] =
1241                                 tmf->tag_of_task_to_be_managed & 0xff;
1242                         break;
1243                 default:
1244                         break;
1245                 }
1246         }
1247
1248         return 0;
1249 }
1250
1251 static void sata_done_v2_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
1252                             struct hisi_sas_slot *slot)
1253 {
1254         struct task_status_struct *ts = &task->task_status;
1255         struct ata_task_resp *resp = (struct ata_task_resp *)ts->buf;
1256         struct dev_to_host_fis *d2h = slot->status_buffer +
1257                                       sizeof(struct hisi_sas_err_record);
1258
1259         resp->frame_len = sizeof(struct dev_to_host_fis);
1260         memcpy(&resp->ending_fis[0], d2h, sizeof(struct dev_to_host_fis));
1261
1262         ts->buf_valid_size = sizeof(*resp);
1263 }
1264
1265 /* by default, task resp is complete */
1266 static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
1267                            struct sas_task *task,
1268                            struct hisi_sas_slot *slot)
1269 {
1270         struct task_status_struct *ts = &task->task_status;
1271         struct hisi_sas_err_record_v2 *err_record = slot->status_buffer;
1272         u32 trans_tx_fail_type = cpu_to_le32(err_record->trans_tx_fail_type);
1273         u32 trans_rx_fail_type = cpu_to_le32(err_record->trans_rx_fail_type);
1274         u16 dma_tx_err_type = cpu_to_le16(err_record->dma_tx_err_type);
1275         u16 sipc_rx_err_type = cpu_to_le16(err_record->sipc_rx_err_type);
1276         u32 dma_rx_err_type = cpu_to_le32(err_record->dma_rx_err_type);
1277         int error = -1;
1278
1279         if (dma_rx_err_type) {
1280                 error = ffs(dma_rx_err_type)
1281                         - 1 + DMA_RX_ERR_BASE;
1282         } else if (sipc_rx_err_type) {
1283                 error = ffs(sipc_rx_err_type)
1284                         - 1 + SIPC_RX_ERR_BASE;
1285         }  else if (dma_tx_err_type) {
1286                 error = ffs(dma_tx_err_type)
1287                         - 1 + DMA_TX_ERR_BASE;
1288         } else if (trans_rx_fail_type) {
1289                 error = ffs(trans_rx_fail_type)
1290                         - 1 + TRANS_RX_FAIL_BASE;
1291         } else if (trans_tx_fail_type) {
1292                 error = ffs(trans_tx_fail_type)
1293                         - 1 + TRANS_TX_FAIL_BASE;
1294         }
1295
1296         switch (task->task_proto) {
1297         case SAS_PROTOCOL_SSP:
1298         {
1299                 switch (error) {
1300                 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
1301                 {
1302                         ts->stat = SAS_OPEN_REJECT;
1303                         ts->open_rej_reason = SAS_OREJ_NO_DEST;
1304                         break;
1305                 }
1306                 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
1307                 {
1308                         ts->stat = SAS_OPEN_REJECT;
1309                         ts->open_rej_reason = SAS_OREJ_PATH_BLOCKED;
1310                         break;
1311                 }
1312                 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
1313                 {
1314                         ts->stat = SAS_OPEN_REJECT;
1315                         ts->open_rej_reason = SAS_OREJ_EPROTO;
1316                         break;
1317                 }
1318                 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
1319                 {
1320                         ts->stat = SAS_OPEN_REJECT;
1321                         ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1322                         break;
1323                 }
1324                 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
1325                 {
1326                         ts->stat = SAS_OPEN_REJECT;
1327                         ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1328                         break;
1329                 }
1330                 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
1331                 {
1332                         ts->stat = SAS_OPEN_REJECT;
1333                         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1334                         break;
1335                 }
1336                 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
1337                 {
1338                         ts->stat = SAS_OPEN_REJECT;
1339                         ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1340                         break;
1341                 }
1342                 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
1343                 {
1344                         ts->stat = SAS_OPEN_REJECT;
1345                         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1346                         break;
1347                 }
1348                 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
1349                 {
1350                         /* not sure */
1351                         ts->stat = SAS_DEV_NO_RESPONSE;
1352                         break;
1353                 }
1354                 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
1355                 {
1356                         ts->stat = SAS_PHY_DOWN;
1357                         break;
1358                 }
1359                 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
1360                 {
1361                         ts->stat = SAS_OPEN_TO;
1362                         break;
1363                 }
1364                 case DMA_RX_DATA_LEN_OVERFLOW:
1365                 {
1366                         ts->stat = SAS_DATA_OVERRUN;
1367                         ts->residual = 0;
1368                         break;
1369                 }
1370                 case DMA_RX_DATA_LEN_UNDERFLOW:
1371                 case SIPC_RX_DATA_UNDERFLOW_ERR:
1372                 {
1373                         ts->residual = trans_tx_fail_type;
1374                         ts->stat = SAS_DATA_UNDERRUN;
1375                         break;
1376                 }
1377                 case TRANS_TX_ERR_FRAME_TXED:
1378                 {
1379                         /* This will request a retry */
1380                         ts->stat = SAS_QUEUE_FULL;
1381                         slot->abort = 1;
1382                         break;
1383                 }
1384                 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
1385                 case TRANS_TX_ERR_PHY_NOT_ENABLE:
1386                 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
1387                 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
1388                 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
1389                 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
1390                 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
1391                 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
1392                 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
1393                 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
1394                 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
1395                 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
1396                 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
1397                 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
1398                 case TRANS_TX_ERR_WITH_IPTT_CONFLICT:
1399                 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
1400                 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR:
1401                 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
1402                 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
1403                 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
1404                 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
1405                 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
1406                 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
1407                 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
1408                 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
1409                 case TRANS_RX_ERR_WITH_DATA_LEN0:
1410                 case TRANS_RX_ERR_WITH_BAD_HASH:
1411                 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
1412                 case TRANS_RX_SSP_FRM_LEN_ERR:
1413                 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
1414                 case DMA_TX_UNEXP_XFER_ERR:
1415                 case DMA_TX_UNEXP_RETRANS_ERR:
1416                 case DMA_TX_XFER_LEN_OVERFLOW:
1417                 case DMA_TX_XFER_OFFSET_ERR:
1418                 case DMA_RX_DATA_OFFSET_ERR:
1419                 case DMA_RX_UNEXP_NORM_RESP_ERR:
1420                 case DMA_RX_UNEXP_RDFRAME_ERR:
1421                 case DMA_RX_UNKNOWN_FRM_ERR:
1422                 {
1423                         ts->stat = SAS_OPEN_REJECT;
1424                         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1425                         break;
1426                 }
1427                 default:
1428                         break;
1429                 }
1430         }
1431                 break;
1432         case SAS_PROTOCOL_SMP:
1433                 ts->stat = SAM_STAT_CHECK_CONDITION;
1434                 break;
1435
1436         case SAS_PROTOCOL_SATA:
1437         case SAS_PROTOCOL_STP:
1438         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1439         {
1440                 switch (error) {
1441                 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
1442                 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
1443                 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
1444                 {
1445                         ts->resp = SAS_TASK_UNDELIVERED;
1446                         ts->stat = SAS_DEV_NO_RESPONSE;
1447                         break;
1448                 }
1449                 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
1450                 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
1451                 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
1452                 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
1453                 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
1454                 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
1455                 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY:
1456                 {
1457                         ts->stat = SAS_OPEN_REJECT;
1458                         break;
1459                 }
1460                 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
1461                 {
1462                         ts->stat = SAS_OPEN_TO;
1463                         break;
1464                 }
1465                 case DMA_RX_DATA_LEN_OVERFLOW:
1466                 {
1467                         ts->stat = SAS_DATA_OVERRUN;
1468                         break;
1469                 }
1470                 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
1471                 case TRANS_TX_ERR_PHY_NOT_ENABLE:
1472                 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
1473                 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
1474                 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
1475                 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
1476                 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
1477                 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
1478                 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
1479                 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
1480                 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
1481                 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
1482                 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
1483                 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
1484                 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
1485                 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT:
1486                 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
1487                 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
1488                 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR:
1489                 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR:
1490                 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN:
1491                 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP:
1492                 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
1493                 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
1494                 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
1495                 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
1496                 case TRANS_RX_ERR_WITH_DATA_LEN0:
1497                 case TRANS_RX_ERR_WITH_BAD_HASH:
1498                 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
1499                 case TRANS_RX_SSP_FRM_LEN_ERR:
1500                 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD:
1501                 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR:
1502                 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR:
1503                 case SIPC_RX_WRSETUP_LEN_ODD_ERR:
1504                 case SIPC_RX_WRSETUP_LEN_ZERO_ERR:
1505                 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR:
1506                 case SIPC_RX_SATA_UNEXP_FIS_ERR:
1507                 case DMA_RX_SATA_FRAME_TYPE_ERR:
1508                 case DMA_RX_UNEXP_RDFRAME_ERR:
1509                 case DMA_RX_PIO_DATA_LEN_ERR:
1510                 case DMA_RX_RDSETUP_STATUS_ERR:
1511                 case DMA_RX_RDSETUP_STATUS_DRQ_ERR:
1512                 case DMA_RX_RDSETUP_STATUS_BSY_ERR:
1513                 case DMA_RX_RDSETUP_LEN_ODD_ERR:
1514                 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
1515                 case DMA_RX_RDSETUP_LEN_OVER_ERR:
1516                 case DMA_RX_RDSETUP_OFFSET_ERR:
1517                 case DMA_RX_RDSETUP_ACTIVE_ERR:
1518                 case DMA_RX_RDSETUP_ESTATUS_ERR:
1519                 case DMA_RX_UNKNOWN_FRM_ERR:
1520                 {
1521                         ts->stat = SAS_OPEN_REJECT;
1522                         break;
1523                 }
1524                 default:
1525                 {
1526                         ts->stat = SAS_PROTO_RESPONSE;
1527                         break;
1528                 }
1529                 }
1530                 sata_done_v2_hw(hisi_hba, task, slot);
1531         }
1532                 break;
1533         default:
1534                 break;
1535         }
1536 }
1537
1538 static int
1539 slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot,
1540                     int abort)
1541 {
1542         struct sas_task *task = slot->task;
1543         struct hisi_sas_device *sas_dev;
1544         struct device *dev = &hisi_hba->pdev->dev;
1545         struct task_status_struct *ts;
1546         struct domain_device *device;
1547         enum exec_status sts;
1548         struct hisi_sas_complete_v2_hdr *complete_queue =
1549                         hisi_hba->complete_hdr[slot->cmplt_queue];
1550         struct hisi_sas_complete_v2_hdr *complete_hdr =
1551                         &complete_queue[slot->cmplt_queue_slot];
1552
1553         if (unlikely(!task || !task->lldd_task || !task->dev))
1554                 return -EINVAL;
1555
1556         ts = &task->task_status;
1557         device = task->dev;
1558         sas_dev = device->lldd_dev;
1559
1560         task->task_state_flags &=
1561                 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1562         task->task_state_flags |= SAS_TASK_STATE_DONE;
1563
1564         memset(ts, 0, sizeof(*ts));
1565         ts->resp = SAS_TASK_COMPLETE;
1566
1567         if (unlikely(!sas_dev || abort)) {
1568                 if (!sas_dev)
1569                         dev_dbg(dev, "slot complete: port has not device\n");
1570                 ts->stat = SAS_PHY_DOWN;
1571                 goto out;
1572         }
1573
1574         /* Use SAS+TMF status codes */
1575         switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
1576                         >> CMPLT_HDR_ABORT_STAT_OFF) {
1577         case STAT_IO_ABORTED:
1578                 /* this io has been aborted by abort command */
1579                 ts->stat = SAS_ABORTED_TASK;
1580                 goto out;
1581         case STAT_IO_COMPLETE:
1582                 /* internal abort command complete */
1583                 ts->stat = TMF_RESP_FUNC_COMPLETE;
1584                 goto out;
1585         case STAT_IO_NO_DEVICE:
1586                 ts->stat = TMF_RESP_FUNC_COMPLETE;
1587                 goto out;
1588         case STAT_IO_NOT_VALID:
1589                 /* abort single io, controller don't find
1590                  * the io need to abort
1591                  */
1592                 ts->stat = TMF_RESP_FUNC_FAILED;
1593                 goto out;
1594         default:
1595                 break;
1596         }
1597
1598         if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) &&
1599                 (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
1600
1601                 slot_err_v2_hw(hisi_hba, task, slot);
1602                 if (unlikely(slot->abort)) {
1603                         queue_work(hisi_hba->wq, &slot->abort_slot);
1604                         /* immediately return and do not complete */
1605                         return ts->stat;
1606                 }
1607                 goto out;
1608         }
1609
1610         switch (task->task_proto) {
1611         case SAS_PROTOCOL_SSP:
1612         {
1613                 struct ssp_response_iu *iu = slot->status_buffer +
1614                         sizeof(struct hisi_sas_err_record);
1615
1616                 sas_ssp_task_response(dev, task, iu);
1617                 break;
1618         }
1619         case SAS_PROTOCOL_SMP:
1620         {
1621                 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1622                 void *to;
1623
1624                 ts->stat = SAM_STAT_GOOD;
1625                 to = kmap_atomic(sg_page(sg_resp));
1626
1627                 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1628                              DMA_FROM_DEVICE);
1629                 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
1630                              DMA_TO_DEVICE);
1631                 memcpy(to + sg_resp->offset,
1632                        slot->status_buffer +
1633                        sizeof(struct hisi_sas_err_record),
1634                        sg_dma_len(sg_resp));
1635                 kunmap_atomic(to);
1636                 break;
1637         }
1638         case SAS_PROTOCOL_SATA:
1639         case SAS_PROTOCOL_STP:
1640         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1641         {
1642                 ts->stat = SAM_STAT_GOOD;
1643                 sata_done_v2_hw(hisi_hba, task, slot);
1644                 break;
1645         }
1646         default:
1647                 ts->stat = SAM_STAT_CHECK_CONDITION;
1648                 break;
1649         }
1650
1651         if (!slot->port->port_attached) {
1652                 dev_err(dev, "slot complete: port %d has removed\n",
1653                         slot->port->sas_port.id);
1654                 ts->stat = SAS_PHY_DOWN;
1655         }
1656
1657 out:
1658         if (sas_dev && sas_dev->running_req)
1659                 sas_dev->running_req--;
1660
1661         hisi_sas_slot_task_free(hisi_hba, task, slot);
1662         sts = ts->stat;
1663
1664         if (task->task_done)
1665                 task->task_done(task);
1666
1667         return sts;
1668 }
1669
1670 static u8 get_ata_protocol(u8 cmd, int direction)
1671 {
1672         switch (cmd) {
1673         case ATA_CMD_FPDMA_WRITE:
1674         case ATA_CMD_FPDMA_READ:
1675         case ATA_CMD_FPDMA_RECV:
1676         case ATA_CMD_FPDMA_SEND:
1677         case ATA_CMD_NCQ_NON_DATA:
1678         return SATA_PROTOCOL_FPDMA;
1679
1680         case ATA_CMD_ID_ATA:
1681         case ATA_CMD_PMP_READ:
1682         case ATA_CMD_READ_LOG_EXT:
1683         case ATA_CMD_PIO_READ:
1684         case ATA_CMD_PIO_READ_EXT:
1685         case ATA_CMD_PMP_WRITE:
1686         case ATA_CMD_WRITE_LOG_EXT:
1687         case ATA_CMD_PIO_WRITE:
1688         case ATA_CMD_PIO_WRITE_EXT:
1689         return SATA_PROTOCOL_PIO;
1690
1691         case ATA_CMD_READ:
1692         case ATA_CMD_READ_EXT:
1693         case ATA_CMD_READ_LOG_DMA_EXT:
1694         case ATA_CMD_WRITE:
1695         case ATA_CMD_WRITE_EXT:
1696         case ATA_CMD_WRITE_QUEUED:
1697         case ATA_CMD_WRITE_LOG_DMA_EXT:
1698         return SATA_PROTOCOL_DMA;
1699
1700         case ATA_CMD_DOWNLOAD_MICRO:
1701         case ATA_CMD_DEV_RESET:
1702         case ATA_CMD_CHK_POWER:
1703         case ATA_CMD_FLUSH:
1704         case ATA_CMD_FLUSH_EXT:
1705         case ATA_CMD_VERIFY:
1706         case ATA_CMD_VERIFY_EXT:
1707         case ATA_CMD_SET_FEATURES:
1708         case ATA_CMD_STANDBY:
1709         case ATA_CMD_STANDBYNOW1:
1710         return SATA_PROTOCOL_NONDATA;
1711         default:
1712                 if (direction == DMA_NONE)
1713                         return SATA_PROTOCOL_NONDATA;
1714                 return SATA_PROTOCOL_PIO;
1715         }
1716 }
1717
1718 static int get_ncq_tag_v2_hw(struct sas_task *task, u32 *tag)
1719 {
1720         struct ata_queued_cmd *qc = task->uldd_task;
1721
1722         if (qc) {
1723                 if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
1724                         qc->tf.command == ATA_CMD_FPDMA_READ) {
1725                         *tag = qc->tag;
1726                         return 1;
1727                 }
1728         }
1729         return 0;
1730 }
1731
1732 static int prep_ata_v2_hw(struct hisi_hba *hisi_hba,
1733                           struct hisi_sas_slot *slot)
1734 {
1735         struct sas_task *task = slot->task;
1736         struct domain_device *device = task->dev;
1737         struct domain_device *parent_dev = device->parent;
1738         struct hisi_sas_device *sas_dev = device->lldd_dev;
1739         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1740         struct hisi_sas_port *port = device->port->lldd_port;
1741         u8 *buf_cmd;
1742         int has_data = 0, rc = 0, hdr_tag = 0;
1743         u32 dw1 = 0, dw2 = 0;
1744
1745         /* create header */
1746         /* dw0 */
1747         hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1748         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
1749                 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1750         else
1751                 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
1752
1753         /* dw1 */
1754         switch (task->data_dir) {
1755         case DMA_TO_DEVICE:
1756                 has_data = 1;
1757                 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1758                 break;
1759         case DMA_FROM_DEVICE:
1760                 has_data = 1;
1761                 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1762                 break;
1763         default:
1764                 dw1 &= ~CMD_HDR_DIR_MSK;
1765         }
1766
1767         if (0 == task->ata_task.fis.command)
1768                 dw1 |= 1 << CMD_HDR_RESET_OFF;
1769
1770         dw1 |= (get_ata_protocol(task->ata_task.fis.command, task->data_dir))
1771                 << CMD_HDR_FRAME_TYPE_OFF;
1772         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1773         hdr->dw1 = cpu_to_le32(dw1);
1774
1775         /* dw2 */
1776         if (task->ata_task.use_ncq && get_ncq_tag_v2_hw(task, &hdr_tag)) {
1777                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1778                 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1779         }
1780
1781         dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1782                         2 << CMD_HDR_SG_MOD_OFF;
1783         hdr->dw2 = cpu_to_le32(dw2);
1784
1785         /* dw3 */
1786         hdr->transfer_tags = cpu_to_le32(slot->idx);
1787
1788         if (has_data) {
1789                 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1790                                         slot->n_elem);
1791                 if (rc)
1792                         return rc;
1793         }
1794
1795
1796         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1797         hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma);
1798         hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
1799
1800         buf_cmd = slot->command_table;
1801
1802         if (likely(!task->ata_task.device_control_reg_update))
1803                 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1804         /* fill in command FIS */
1805         memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1806
1807         return 0;
1808 }
1809
1810 static int prep_abort_v2_hw(struct hisi_hba *hisi_hba,
1811                 struct hisi_sas_slot *slot,
1812                 int device_id, int abort_flag, int tag_to_abort)
1813 {
1814         struct sas_task *task = slot->task;
1815         struct domain_device *dev = task->dev;
1816         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1817         struct hisi_sas_port *port = slot->port;
1818
1819         /* dw0 */
1820         hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
1821                                (port->id << CMD_HDR_PORT_OFF) |
1822                                ((dev_is_sata(dev) ? 1:0) <<
1823                                 CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
1824                                (abort_flag << CMD_HDR_ABORT_FLAG_OFF));
1825
1826         /* dw1 */
1827         hdr->dw1 = cpu_to_le32(device_id << CMD_HDR_DEV_ID_OFF);
1828
1829         /* dw7 */
1830         hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
1831         hdr->transfer_tags = cpu_to_le32(slot->idx);
1832
1833         return 0;
1834 }
1835
1836 static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
1837 {
1838         int i, res = 0;
1839         u32 context, port_id, link_rate, hard_phy_linkrate;
1840         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1841         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1842         struct device *dev = &hisi_hba->pdev->dev;
1843         u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1844         struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
1845
1846         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1847
1848         /* Check for SATA dev */
1849         context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1850         if (context & (1 << phy_no))
1851                 goto end;
1852
1853         if (phy_no == 8) {
1854                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1855
1856                 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1857                           PORT_STATE_PHY8_PORT_NUM_OFF;
1858                 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
1859                             PORT_STATE_PHY8_CONN_RATE_OFF;
1860         } else {
1861                 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1862                 port_id = (port_id >> (4 * phy_no)) & 0xf;
1863                 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1864                 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1865         }
1866
1867         if (port_id == 0xf) {
1868                 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1869                 res = IRQ_NONE;
1870                 goto end;
1871         }
1872
1873         for (i = 0; i < 6; i++) {
1874                 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1875                                                RX_IDAF_DWORD0 + (i * 4));
1876                 frame_rcvd[i] = __swab32(idaf);
1877         }
1878
1879         sas_phy->linkrate = link_rate;
1880         hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
1881                                                 HARD_PHY_LINKRATE);
1882         phy->maximum_linkrate = hard_phy_linkrate & 0xf;
1883         phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
1884
1885         sas_phy->oob_mode = SAS_OOB_MODE;
1886         memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
1887         dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1888         phy->port_id = port_id;
1889         phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1890         phy->phy_type |= PORT_TYPE_SAS;
1891         phy->phy_attached = 1;
1892         phy->identify.device_type = id->dev_type;
1893         phy->frame_rcvd_size =  sizeof(struct sas_identify_frame);
1894         if (phy->identify.device_type == SAS_END_DEVICE)
1895                 phy->identify.target_port_protocols =
1896                         SAS_PROTOCOL_SSP;
1897         else if (phy->identify.device_type != SAS_PHY_UNUSED)
1898                 phy->identify.target_port_protocols =
1899                         SAS_PROTOCOL_SMP;
1900         queue_work(hisi_hba->wq, &phy->phyup_ws);
1901
1902 end:
1903         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1904                              CHL_INT0_SL_PHY_ENABLE_MSK);
1905         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1906
1907         return res;
1908 }
1909
1910 static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
1911 {
1912         int res = 0;
1913         u32 phy_state, sl_ctrl, txid_auto;
1914
1915         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1916
1917         phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1918         hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
1919
1920         sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1921         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
1922                              sl_ctrl & ~SL_CONTROL_CTA_MSK);
1923
1924         txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1925         hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1926                              txid_auto | TXID_AUTO_CT3_MSK);
1927
1928         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1929         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1930
1931         return res;
1932 }
1933
1934 static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
1935 {
1936         struct hisi_hba *hisi_hba = p;
1937         u32 irq_msk;
1938         int phy_no = 0;
1939         irqreturn_t res = IRQ_HANDLED;
1940
1941         irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
1942                    >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
1943         while (irq_msk) {
1944                 if (irq_msk  & 1) {
1945                         u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1946                                                             CHL_INT0);
1947
1948                         if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1949                                 /* phy up */
1950                                 if (phy_up_v2_hw(phy_no, hisi_hba)) {
1951                                         res = IRQ_NONE;
1952                                         goto end;
1953                                 }
1954
1955                         if (irq_value & CHL_INT0_NOT_RDY_MSK)
1956                                 /* phy down */
1957                                 if (phy_down_v2_hw(phy_no, hisi_hba)) {
1958                                         res = IRQ_NONE;
1959                                         goto end;
1960                                 }
1961                 }
1962                 irq_msk >>= 1;
1963                 phy_no++;
1964         }
1965
1966 end:
1967         return res;
1968 }
1969
1970 static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
1971 {
1972         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1973         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1974         struct sas_ha_struct *sas_ha = &hisi_hba->sha;
1975
1976         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1977         sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1978         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1979                              CHL_INT0_SL_RX_BCST_ACK_MSK);
1980         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1981 }
1982
1983 static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
1984 {
1985         struct hisi_hba *hisi_hba = p;
1986         struct device *dev = &hisi_hba->pdev->dev;
1987         u32 ent_msk, ent_tmp, irq_msk;
1988         int phy_no = 0;
1989
1990         ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1991         ent_tmp = ent_msk;
1992         ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
1993         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
1994
1995         irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
1996                         HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
1997
1998         while (irq_msk) {
1999                 if (irq_msk & (1 << phy_no)) {
2000                         u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
2001                                                              CHL_INT0);
2002                         u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
2003                                                              CHL_INT1);
2004                         u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
2005                                                              CHL_INT2);
2006
2007                         if (irq_value1) {
2008                                 if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK |
2009                                                   CHL_INT1_DMAC_TX_ECC_ERR_MSK))
2010                                         panic("%s: DMAC RX/TX ecc bad error! (0x%x)",
2011                                                 dev_name(dev), irq_value1);
2012
2013                                 hisi_sas_phy_write32(hisi_hba, phy_no,
2014                                                      CHL_INT1, irq_value1);
2015                         }
2016
2017                         if (irq_value2)
2018                                 hisi_sas_phy_write32(hisi_hba, phy_no,
2019                                                      CHL_INT2, irq_value2);
2020
2021
2022                         if (irq_value0) {
2023                                 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
2024                                         phy_bcast_v2_hw(phy_no, hisi_hba);
2025
2026                                 hisi_sas_phy_write32(hisi_hba, phy_no,
2027                                                 CHL_INT0, irq_value0
2028                                                 & (~CHL_INT0_HOTPLUG_TOUT_MSK)
2029                                                 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
2030                                                 & (~CHL_INT0_NOT_RDY_MSK));
2031                         }
2032                 }
2033                 irq_msk &= ~(1 << phy_no);
2034                 phy_no++;
2035         }
2036
2037         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
2038
2039         return IRQ_HANDLED;
2040 }
2041
2042 static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
2043 {
2044         struct hisi_sas_cq *cq = p;
2045         struct hisi_hba *hisi_hba = cq->hisi_hba;
2046         struct hisi_sas_slot *slot;
2047         struct hisi_sas_itct *itct;
2048         struct hisi_sas_complete_v2_hdr *complete_queue;
2049         u32 irq_value, rd_point = cq->rd_point, wr_point, dev_id;
2050         int queue = cq->id;
2051
2052         complete_queue = hisi_hba->complete_hdr[queue];
2053         irq_value = hisi_sas_read32(hisi_hba, OQ_INT_SRC);
2054
2055         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
2056
2057         wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
2058                                    (0x14 * queue));
2059
2060         while (rd_point != wr_point) {
2061                 struct hisi_sas_complete_v2_hdr *complete_hdr;
2062                 int iptt;
2063
2064                 complete_hdr = &complete_queue[rd_point];
2065
2066                 /* Check for NCQ completion */
2067                 if (complete_hdr->act) {
2068                         u32 act_tmp = complete_hdr->act;
2069                         int ncq_tag_count = ffs(act_tmp);
2070
2071                         dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
2072                                  CMPLT_HDR_DEV_ID_OFF;
2073                         itct = &hisi_hba->itct[dev_id];
2074
2075                         /* The NCQ tags are held in the itct header */
2076                         while (ncq_tag_count) {
2077                                 __le64 *ncq_tag = &itct->qw4_15[0];
2078
2079                                 ncq_tag_count -= 1;
2080                                 iptt = (ncq_tag[ncq_tag_count / 5]
2081                                         >> (ncq_tag_count % 5) * 12) & 0xfff;
2082
2083                                 slot = &hisi_hba->slot_info[iptt];
2084                                 slot->cmplt_queue_slot = rd_point;
2085                                 slot->cmplt_queue = queue;
2086                                 slot_complete_v2_hw(hisi_hba, slot, 0);
2087
2088                                 act_tmp &= ~(1 << ncq_tag_count);
2089                                 ncq_tag_count = ffs(act_tmp);
2090                         }
2091                 } else {
2092                         iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
2093                         slot = &hisi_hba->slot_info[iptt];
2094                         slot->cmplt_queue_slot = rd_point;
2095                         slot->cmplt_queue = queue;
2096                         slot_complete_v2_hw(hisi_hba, slot, 0);
2097                 }
2098
2099                 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
2100                         rd_point = 0;
2101         }
2102
2103         /* update rd_point */
2104         cq->rd_point = rd_point;
2105         hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
2106         return IRQ_HANDLED;
2107 }
2108
2109 static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
2110 {
2111         struct hisi_sas_phy *phy = p;
2112         struct hisi_hba *hisi_hba = phy->hisi_hba;
2113         struct asd_sas_phy *sas_phy = &phy->sas_phy;
2114         struct device *dev = &hisi_hba->pdev->dev;
2115         struct  hisi_sas_initial_fis *initial_fis;
2116         struct dev_to_host_fis *fis;
2117         u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
2118         irqreturn_t res = IRQ_HANDLED;
2119         u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
2120         int phy_no, offset;
2121
2122         phy_no = sas_phy->id;
2123         initial_fis = &hisi_hba->initial_fis[phy_no];
2124         fis = &initial_fis->fis;
2125
2126         offset = 4 * (phy_no / 4);
2127         ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset);
2128         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset,
2129                          ent_msk | 1 << ((phy_no % 4) * 8));
2130
2131         ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset);
2132         ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF *
2133                              (phy_no % 4)));
2134         ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
2135         if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
2136                 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
2137                 res = IRQ_NONE;
2138                 goto end;
2139         }
2140
2141         if (unlikely(phy_no == 8)) {
2142                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2143
2144                 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
2145                           PORT_STATE_PHY8_PORT_NUM_OFF;
2146                 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
2147                             PORT_STATE_PHY8_CONN_RATE_OFF;
2148         } else {
2149                 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
2150                 port_id = (port_id >> (4 * phy_no)) & 0xf;
2151                 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
2152                 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
2153         }
2154
2155         if (port_id == 0xf) {
2156                 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
2157                 res = IRQ_NONE;
2158                 goto end;
2159         }
2160
2161         sas_phy->linkrate = link_rate;
2162         hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
2163                                                 HARD_PHY_LINKRATE);
2164         phy->maximum_linkrate = hard_phy_linkrate & 0xf;
2165         phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
2166
2167         sas_phy->oob_mode = SATA_OOB_MODE;
2168         /* Make up some unique SAS address */
2169         attached_sas_addr[0] = 0x50;
2170         attached_sas_addr[7] = phy_no;
2171         memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
2172         memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
2173         dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
2174         phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
2175         phy->port_id = port_id;
2176         phy->phy_type |= PORT_TYPE_SATA;
2177         phy->phy_attached = 1;
2178         phy->identify.device_type = SAS_SATA_DEV;
2179         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
2180         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
2181         queue_work(hisi_hba->wq, &phy->phyup_ws);
2182
2183 end:
2184         hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp);
2185         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk);
2186
2187         return res;
2188 }
2189
2190 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
2191         int_phy_updown_v2_hw,
2192         int_chnl_int_v2_hw,
2193 };
2194
2195 /**
2196  * There is a limitation in the hip06 chipset that we need
2197  * to map in all mbigen interrupts, even if they are not used.
2198  */
2199 static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
2200 {
2201         struct platform_device *pdev = hisi_hba->pdev;
2202         struct device *dev = &pdev->dev;
2203         int i, irq, rc, irq_map[128];
2204
2205
2206         for (i = 0; i < 128; i++)
2207                 irq_map[i] = platform_get_irq(pdev, i);
2208
2209         for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
2210                 int idx = i;
2211
2212                 irq = irq_map[idx + 1]; /* Phy up/down is irq1 */
2213                 if (!irq) {
2214                         dev_err(dev, "irq init: fail map phy interrupt %d\n",
2215                                 idx);
2216                         return -ENOENT;
2217                 }
2218
2219                 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
2220                                       DRV_NAME " phy", hisi_hba);
2221                 if (rc) {
2222                         dev_err(dev, "irq init: could not request "
2223                                 "phy interrupt %d, rc=%d\n",
2224                                 irq, rc);
2225                         return -ENOENT;
2226                 }
2227         }
2228
2229         for (i = 0; i < hisi_hba->n_phy; i++) {
2230                 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
2231                 int idx = i + 72; /* First SATA interrupt is irq72 */
2232
2233                 irq = irq_map[idx];
2234                 if (!irq) {
2235                         dev_err(dev, "irq init: fail map phy interrupt %d\n",
2236                                 idx);
2237                         return -ENOENT;
2238                 }
2239
2240                 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
2241                                       DRV_NAME " sata", phy);
2242                 if (rc) {
2243                         dev_err(dev, "irq init: could not request "
2244                                 "sata interrupt %d, rc=%d\n",
2245                                 irq, rc);
2246                         return -ENOENT;
2247                 }
2248         }
2249
2250         for (i = 0; i < hisi_hba->queue_count; i++) {
2251                 int idx = i + 96; /* First cq interrupt is irq96 */
2252
2253                 irq = irq_map[idx];
2254                 if (!irq) {
2255                         dev_err(dev,
2256                                 "irq init: could not map cq interrupt %d\n",
2257                                 idx);
2258                         return -ENOENT;
2259                 }
2260                 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0,
2261                                       DRV_NAME " cq", &hisi_hba->cq[i]);
2262                 if (rc) {
2263                         dev_err(dev,
2264                                 "irq init: could not request cq interrupt %d, rc=%d\n",
2265                                 irq, rc);
2266                         return -ENOENT;
2267                 }
2268         }
2269
2270         return 0;
2271 }
2272
2273 static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
2274 {
2275         int rc;
2276
2277         rc = hw_init_v2_hw(hisi_hba);
2278         if (rc)
2279                 return rc;
2280
2281         rc = interrupt_init_v2_hw(hisi_hba);
2282         if (rc)
2283                 return rc;
2284
2285         phys_init_v2_hw(hisi_hba);
2286
2287         return 0;
2288 }
2289
2290 static const struct hisi_sas_hw hisi_sas_v2_hw = {
2291         .hw_init = hisi_sas_v2_init,
2292         .setup_itct = setup_itct_v2_hw,
2293         .slot_index_alloc = slot_index_alloc_quirk_v2_hw,
2294         .alloc_dev = alloc_dev_quirk_v2_hw,
2295         .sl_notify = sl_notify_v2_hw,
2296         .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
2297         .free_device = free_device_v2_hw,
2298         .prep_smp = prep_smp_v2_hw,
2299         .prep_ssp = prep_ssp_v2_hw,
2300         .prep_stp = prep_ata_v2_hw,
2301         .prep_abort = prep_abort_v2_hw,
2302         .get_free_slot = get_free_slot_v2_hw,
2303         .start_delivery = start_delivery_v2_hw,
2304         .slot_complete = slot_complete_v2_hw,
2305         .phy_enable = enable_phy_v2_hw,
2306         .phy_disable = disable_phy_v2_hw,
2307         .phy_hard_reset = phy_hard_reset_v2_hw,
2308         .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
2309         .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
2310 };
2311
2312 static int hisi_sas_v2_probe(struct platform_device *pdev)
2313 {
2314         return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
2315 }
2316
2317 static int hisi_sas_v2_remove(struct platform_device *pdev)
2318 {
2319         return hisi_sas_remove(pdev);
2320 }
2321
2322 static const struct of_device_id sas_v2_of_match[] = {
2323         { .compatible = "hisilicon,hip06-sas-v2",},
2324         { .compatible = "hisilicon,hip07-sas-v2",},
2325         {},
2326 };
2327 MODULE_DEVICE_TABLE(of, sas_v2_of_match);
2328
2329 static const struct acpi_device_id sas_v2_acpi_match[] = {
2330         { "HISI0162", 0 },
2331         { }
2332 };
2333
2334 MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match);
2335
2336 static struct platform_driver hisi_sas_v2_driver = {
2337         .probe = hisi_sas_v2_probe,
2338         .remove = hisi_sas_v2_remove,
2339         .driver = {
2340                 .name = DRV_NAME,
2341                 .of_match_table = sas_v2_of_match,
2342                 .acpi_match_table = ACPI_PTR(sas_v2_acpi_match),
2343         },
2344 };
2345
2346 module_platform_driver(hisi_sas_v2_driver);
2347
2348 MODULE_LICENSE("GPL");
2349 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
2350 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
2351 MODULE_ALIAS("platform:" DRV_NAME);