drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

   1 /*
   2  * Copyright (c) 2016 Linaro Ltd.
   3  * Copyright (c) 2016 Hisilicon Limited.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  */
  11
  12 #include "hisi_sas.h"
  13 #define DRV_NAME "hisi_sas_v2_hw"
  14
  15 /* global registers need init*/
  16 #define DLVRY_QUEUE_ENABLE              0x0
  17 #define IOST_BASE_ADDR_LO               0x8
  18 #define IOST_BASE_ADDR_HI               0xc
  19 #define ITCT_BASE_ADDR_LO               0x10
  20 #define ITCT_BASE_ADDR_HI               0x14
  21 #define IO_BROKEN_MSG_ADDR_LO           0x18
  22 #define IO_BROKEN_MSG_ADDR_HI           0x1c
  23 #define PHY_CONTEXT                     0x20
  24 #define PHY_STATE                       0x24
  25 #define PHY_PORT_NUM_MA                 0x28
  26 #define PORT_STATE                      0x2c
  27 #define PORT_STATE_PHY8_PORT_NUM_OFF    16
  28 #define PORT_STATE_PHY8_PORT_NUM_MSK    (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
  29 #define PORT_STATE_PHY8_CONN_RATE_OFF   20
  30 #define PORT_STATE_PHY8_CONN_RATE_MSK   (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
  31 #define PHY_CONN_RATE                   0x30
  32 #define HGC_TRANS_TASK_CNT_LIMIT        0x38
  33 #define AXI_AHB_CLK_CFG                 0x3c
  34 #define ITCT_CLR                        0x44
  35 #define ITCT_CLR_EN_OFF                 16
  36 #define ITCT_CLR_EN_MSK                 (0x1 << ITCT_CLR_EN_OFF)
  37 #define ITCT_DEV_OFF                    0
  38 #define ITCT_DEV_MSK                    (0x7ff << ITCT_DEV_OFF)
  39 #define AXI_USER1                       0x48
  40 #define AXI_USER2                       0x4c
  41 #define IO_SATA_BROKEN_MSG_ADDR_LO      0x58
  42 #define IO_SATA_BROKEN_MSG_ADDR_HI      0x5c
  43 #define SATA_INITI_D2H_STORE_ADDR_LO    0x60
  44 #define SATA_INITI_D2H_STORE_ADDR_HI    0x64
  45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
  46 #define HGC_SAS_TXFAIL_RETRY_CTRL       0x88
  47 #define HGC_GET_ITV_TIME                0x90
  48 #define DEVICE_MSG_WORK_MODE            0x94
  49 #define OPENA_WT_CONTI_TIME             0x9c
  50 #define I_T_NEXUS_LOSS_TIME             0xa0
  51 #define MAX_CON_TIME_LIMIT_TIME         0xa4
  52 #define BUS_INACTIVE_LIMIT_TIME         0xa8
  53 #define REJECT_TO_OPEN_LIMIT_TIME       0xac
  54 #define CFG_AGING_TIME                  0xbc
  55 #define HGC_DFX_CFG2                    0xc0
  56 #define HGC_IOMB_PROC1_STATUS   0x104
  57 #define CFG_1US_TIMER_TRSH              0xcc
  58 #define HGC_INVLD_DQE_INFO              0x148
  59 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF   9
  60 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK   (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
  61 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF   18
  62 #define INT_COAL_EN                     0x19c
  63 #define OQ_INT_COAL_TIME                0x1a0
  64 #define OQ_INT_COAL_CNT                 0x1a4
  65 #define ENT_INT_COAL_TIME               0x1a8
  66 #define ENT_INT_COAL_CNT                0x1ac
  67 #define OQ_INT_SRC                      0x1b0
  68 #define OQ_INT_SRC_MSK                  0x1b4
  69 #define ENT_INT_SRC1                    0x1b8
  70 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF    0
  71 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
  72 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF    8
  73 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
  74 #define ENT_INT_SRC2                    0x1bc
  75 #define ENT_INT_SRC3                    0x1c0
  76 #define ENT_INT_SRC3_ITC_INT_OFF        15
  77 #define ENT_INT_SRC3_ITC_INT_MSK        (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
  78 #define ENT_INT_SRC_MSK1                0x1c4
  79 #define ENT_INT_SRC_MSK2                0x1c8
  80 #define ENT_INT_SRC_MSK3                0x1cc
  81 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF  31
  82 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK  (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
  83 #define SAS_ECC_INTR_MSK                0x1ec
  84 #define HGC_ERR_STAT_EN                 0x238
  85 #define DLVRY_Q_0_BASE_ADDR_LO          0x260
  86 #define DLVRY_Q_0_BASE_ADDR_HI          0x264
  87 #define DLVRY_Q_0_DEPTH                 0x268
  88 #define DLVRY_Q_0_WR_PTR                0x26c
  89 #define DLVRY_Q_0_RD_PTR                0x270
  90 #define HYPER_STREAM_ID_EN_CFG          0xc80
  91 #define OQ0_INT_SRC_MSK                 0xc90
  92 #define COMPL_Q_0_BASE_ADDR_LO          0x4e0
  93 #define COMPL_Q_0_BASE_ADDR_HI          0x4e4
  94 #define COMPL_Q_0_DEPTH                 0x4e8
  95 #define COMPL_Q_0_WR_PTR                0x4ec
  96 #define COMPL_Q_0_RD_PTR                0x4f0
  97
  98 /* phy registers need init */
  99 #define PORT_BASE                       (0x2000)
 100
 101 #define PHY_CFG                         (PORT_BASE + 0x0)
 102 #define HARD_PHY_LINKRATE               (PORT_BASE + 0x4)
 103 #define PHY_CFG_ENA_OFF                 0
 104 #define PHY_CFG_ENA_MSK                 (0x1 << PHY_CFG_ENA_OFF)
 105 #define PHY_CFG_DC_OPT_OFF              2
 106 #define PHY_CFG_DC_OPT_MSK              (0x1 << PHY_CFG_DC_OPT_OFF)
 107 #define PROG_PHY_LINK_RATE              (PORT_BASE + 0x8)
 108 #define PROG_PHY_LINK_RATE_MAX_OFF      0
 109 #define PROG_PHY_LINK_RATE_MAX_MSK      (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
 110 #define PHY_CTRL                        (PORT_BASE + 0x14)
 111 #define PHY_CTRL_RESET_OFF              0
 112 #define PHY_CTRL_RESET_MSK              (0x1 << PHY_CTRL_RESET_OFF)
 113 #define SAS_PHY_CTRL                    (PORT_BASE + 0x20)
 114 #define SL_CFG                          (PORT_BASE + 0x84)
 115 #define PHY_PCN                         (PORT_BASE + 0x44)
 116 #define SL_TOUT_CFG                     (PORT_BASE + 0x8c)
 117 #define SL_CONTROL                      (PORT_BASE + 0x94)
 118 #define SL_CONTROL_NOTIFY_EN_OFF        0
 119 #define SL_CONTROL_NOTIFY_EN_MSK        (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
 120 #define TX_ID_DWORD0                    (PORT_BASE + 0x9c)
 121 #define TX_ID_DWORD1                    (PORT_BASE + 0xa0)
 122 #define TX_ID_DWORD2                    (PORT_BASE + 0xa4)
 123 #define TX_ID_DWORD3                    (PORT_BASE + 0xa8)
 124 #define TX_ID_DWORD4                    (PORT_BASE + 0xaC)
 125 #define TX_ID_DWORD5                    (PORT_BASE + 0xb0)
 126 #define TX_ID_DWORD6                    (PORT_BASE + 0xb4)
 127 #define RX_IDAF_DWORD0                  (PORT_BASE + 0xc4)
 128 #define RX_IDAF_DWORD1                  (PORT_BASE + 0xc8)
 129 #define RX_IDAF_DWORD2                  (PORT_BASE + 0xcc)
 130 #define RX_IDAF_DWORD3                  (PORT_BASE + 0xd0)
 131 #define RX_IDAF_DWORD4                  (PORT_BASE + 0xd4)
 132 #define RX_IDAF_DWORD5                  (PORT_BASE + 0xd8)
 133 #define RX_IDAF_DWORD6                  (PORT_BASE + 0xdc)
 134 #define RXOP_CHECK_CFG_H                (PORT_BASE + 0xfc)
 135 #define DONE_RECEIVED_TIME              (PORT_BASE + 0x11c)
 136 #define CHL_INT0                        (PORT_BASE + 0x1b4)
 137 #define CHL_INT0_HOTPLUG_TOUT_OFF       0
 138 #define CHL_INT0_HOTPLUG_TOUT_MSK       (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
 139 #define CHL_INT0_SL_RX_BCST_ACK_OFF     1
 140 #define CHL_INT0_SL_RX_BCST_ACK_MSK     (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
 141 #define CHL_INT0_SL_PHY_ENABLE_OFF      2
 142 #define CHL_INT0_SL_PHY_ENABLE_MSK      (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
 143 #define CHL_INT0_NOT_RDY_OFF            4
 144 #define CHL_INT0_NOT_RDY_MSK            (0x1 << CHL_INT0_NOT_RDY_OFF)
 145 #define CHL_INT0_PHY_RDY_OFF            5
 146 #define CHL_INT0_PHY_RDY_MSK            (0x1 << CHL_INT0_PHY_RDY_OFF)
 147 #define CHL_INT1                        (PORT_BASE + 0x1b8)
 148 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF    15
 149 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
 150 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF    17
 151 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
 152 #define CHL_INT2                        (PORT_BASE + 0x1bc)
 153 #define CHL_INT0_MSK                    (PORT_BASE + 0x1c0)
 154 #define CHL_INT1_MSK                    (PORT_BASE + 0x1c4)
 155 #define CHL_INT2_MSK                    (PORT_BASE + 0x1c8)
 156 #define CHL_INT_COAL_EN                 (PORT_BASE + 0x1d0)
 157 #define PHY_CTRL_RDY_MSK                (PORT_BASE + 0x2b0)
 158 #define PHYCTRL_NOT_RDY_MSK             (PORT_BASE + 0x2b4)
 159 #define PHYCTRL_DWS_RESET_MSK           (PORT_BASE + 0x2b8)
 160 #define PHYCTRL_PHY_ENA_MSK             (PORT_BASE + 0x2bc)
 161 #define SL_RX_BCAST_CHK_MSK             (PORT_BASE + 0x2c0)
 162 #define PHYCTRL_OOB_RESTART_MSK         (PORT_BASE + 0x2c4)
 163 #define DMA_TX_STATUS                   (PORT_BASE + 0x2d0)
 164 #define DMA_TX_STATUS_BUSY_OFF          0
 165 #define DMA_TX_STATUS_BUSY_MSK          (0x1 << DMA_TX_STATUS_BUSY_OFF)
 166 #define DMA_RX_STATUS                   (PORT_BASE + 0x2e8)
 167 #define DMA_RX_STATUS_BUSY_OFF          0
 168 #define DMA_RX_STATUS_BUSY_MSK          (0x1 << DMA_RX_STATUS_BUSY_OFF)
 169
 170 #define AXI_CFG                         (0x5100)
 171 #define AM_CFG_MAX_TRANS                (0x5010)
 172 #define AM_CFG_SINGLE_PORT_MAX_TRANS    (0x5014)
 173
 174 /* HW dma structures */
 175 /* Delivery queue header */
 176 /* dw0 */
 177 #define CMD_HDR_ABORT_FLAG_OFF          0
 178 #define CMD_HDR_ABORT_FLAG_MSK          (0x3 << CMD_HDR_ABORT_FLAG_OFF)
 179 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF   2
 180 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK   (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
 181 #define CMD_HDR_RESP_REPORT_OFF         5
 182 #define CMD_HDR_RESP_REPORT_MSK         (0x1 << CMD_HDR_RESP_REPORT_OFF)
 183 #define CMD_HDR_TLR_CTRL_OFF            6
 184 #define CMD_HDR_TLR_CTRL_MSK            (0x3 << CMD_HDR_TLR_CTRL_OFF)
 185 #define CMD_HDR_PORT_OFF                18
 186 #define CMD_HDR_PORT_MSK                (0xf << CMD_HDR_PORT_OFF)
 187 #define CMD_HDR_PRIORITY_OFF            27
 188 #define CMD_HDR_PRIORITY_MSK            (0x1 << CMD_HDR_PRIORITY_OFF)
 189 #define CMD_HDR_CMD_OFF                 29
 190 #define CMD_HDR_CMD_MSK                 (0x7 << CMD_HDR_CMD_OFF)
 191 /* dw1 */
 192 #define CMD_HDR_DIR_OFF                 5
 193 #define CMD_HDR_DIR_MSK                 (0x3 << CMD_HDR_DIR_OFF)
 194 #define CMD_HDR_RESET_OFF               7
 195 #define CMD_HDR_RESET_MSK               (0x1 << CMD_HDR_RESET_OFF)
 196 #define CMD_HDR_VDTL_OFF                10
 197 #define CMD_HDR_VDTL_MSK                (0x1 << CMD_HDR_VDTL_OFF)
 198 #define CMD_HDR_FRAME_TYPE_OFF          11
 199 #define CMD_HDR_FRAME_TYPE_MSK          (0x1f << CMD_HDR_FRAME_TYPE_OFF)
 200 #define CMD_HDR_DEV_ID_OFF              16
 201 #define CMD_HDR_DEV_ID_MSK              (0xffff << CMD_HDR_DEV_ID_OFF)
 202 /* dw2 */
 203 #define CMD_HDR_CFL_OFF                 0
 204 #define CMD_HDR_CFL_MSK                 (0x1ff << CMD_HDR_CFL_OFF)
 205 #define CMD_HDR_NCQ_TAG_OFF             10
 206 #define CMD_HDR_NCQ_TAG_MSK             (0x1f << CMD_HDR_NCQ_TAG_OFF)
 207 #define CMD_HDR_MRFL_OFF                15
 208 #define CMD_HDR_MRFL_MSK                (0x1ff << CMD_HDR_MRFL_OFF)
 209 #define CMD_HDR_SG_MOD_OFF              24
 210 #define CMD_HDR_SG_MOD_MSK              (0x3 << CMD_HDR_SG_MOD_OFF)
 211 #define CMD_HDR_FIRST_BURST_OFF         26
 212 #define CMD_HDR_FIRST_BURST_MSK         (0x1 << CMD_HDR_SG_MOD_OFF)
 213 /* dw3 */
 214 #define CMD_HDR_IPTT_OFF                0
 215 #define CMD_HDR_IPTT_MSK                (0xffff << CMD_HDR_IPTT_OFF)
 216 /* dw6 */
 217 #define CMD_HDR_DIF_SGL_LEN_OFF         0
 218 #define CMD_HDR_DIF_SGL_LEN_MSK         (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
 219 #define CMD_HDR_DATA_SGL_LEN_OFF        16
 220 #define CMD_HDR_DATA_SGL_LEN_MSK        (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
 221 #define CMD_HDR_ABORT_IPTT_OFF          16
 222 #define CMD_HDR_ABORT_IPTT_MSK          (0xffff << CMD_HDR_ABORT_IPTT_OFF)
 223
 224 /* Completion header */
 225 /* dw0 */
 226 #define CMPLT_HDR_RSPNS_XFRD_OFF        10
 227 #define CMPLT_HDR_RSPNS_XFRD_MSK        (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
 228 #define CMPLT_HDR_ERX_OFF               12
 229 #define CMPLT_HDR_ERX_MSK               (0x1 << CMPLT_HDR_ERX_OFF)
 230 #define CMPLT_HDR_ABORT_STAT_OFF        13
 231 #define CMPLT_HDR_ABORT_STAT_MSK        (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
 232 /* abort_stat */
 233 #define STAT_IO_NOT_VALID               0x1
 234 #define STAT_IO_NO_DEVICE               0x2
 235 #define STAT_IO_COMPLETE                0x3
 236 #define STAT_IO_ABORTED                 0x4
 237 /* dw1 */
 238 #define CMPLT_HDR_IPTT_OFF              0
 239 #define CMPLT_HDR_IPTT_MSK              (0xffff << CMPLT_HDR_IPTT_OFF)
 240 #define CMPLT_HDR_DEV_ID_OFF            16
 241 #define CMPLT_HDR_DEV_ID_MSK            (0xffff << CMPLT_HDR_DEV_ID_OFF)
 242
 243 /* ITCT header */
 244 /* qw0 */
 245 #define ITCT_HDR_DEV_TYPE_OFF           0
 246 #define ITCT_HDR_DEV_TYPE_MSK           (0x3 << ITCT_HDR_DEV_TYPE_OFF)
 247 #define ITCT_HDR_VALID_OFF              2
 248 #define ITCT_HDR_VALID_MSK              (0x1 << ITCT_HDR_VALID_OFF)
 249 #define ITCT_HDR_MCR_OFF                5
 250 #define ITCT_HDR_MCR_MSK                (0xf << ITCT_HDR_MCR_OFF)
 251 #define ITCT_HDR_VLN_OFF                9
 252 #define ITCT_HDR_VLN_MSK                (0xf << ITCT_HDR_VLN_OFF)
 253 #define ITCT_HDR_PORT_ID_OFF            28
 254 #define ITCT_HDR_PORT_ID_MSK            (0xf << ITCT_HDR_PORT_ID_OFF)
 255 /* qw2 */
 256 #define ITCT_HDR_INLT_OFF               0
 257 #define ITCT_HDR_INLT_MSK               (0xffffULL << ITCT_HDR_INLT_OFF)
 258 #define ITCT_HDR_BITLT_OFF              16
 259 #define ITCT_HDR_BITLT_MSK              (0xffffULL << ITCT_HDR_BITLT_OFF)
 260 #define ITCT_HDR_MCTLT_OFF              32
 261 #define ITCT_HDR_MCTLT_MSK              (0xffffULL << ITCT_HDR_MCTLT_OFF)
 262 #define ITCT_HDR_RTOLT_OFF              48
 263 #define ITCT_HDR_RTOLT_MSK              (0xffffULL << ITCT_HDR_RTOLT_OFF)
 264
 265 struct hisi_sas_complete_v2_hdr {
 266         __le32 dw0;
 267         __le32 dw1;
 268         __le32 act;
 269         __le32 dw3;
 270 };
 271
 272 struct hisi_sas_err_record_v2 {
 273         /* dw0 */
 274         __le32 trans_tx_fail_type;
 275
 276         /* dw1 */
 277         __le32 trans_rx_fail_type;
 278
 279         /* dw2 */
 280         __le16 dma_tx_err_type;
 281         __le16 sipc_rx_err_type;
 282
 283         /* dw3 */
 284         __le32 dma_rx_err_type;
 285 };
 286
 287 enum {
 288         HISI_SAS_PHY_PHY_UPDOWN,
 289         HISI_SAS_PHY_CHNL_INT,
 290         HISI_SAS_PHY_INT_NR
 291 };
 292
 293 enum {
 294         TRANS_TX_FAIL_BASE = 0x0, /* dw0 */
 295         TRANS_RX_FAIL_BASE = 0x100, /* dw1 */
 296         DMA_TX_ERR_BASE = 0x200, /* dw2 bit 15-0 */
 297         SIPC_RX_ERR_BASE = 0x300, /* dw2 bit 31-16*/
 298         DMA_RX_ERR_BASE = 0x400, /* dw3 */
 299
 300         /* trans tx*/
 301         TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */
 302         TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */
 303         TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */
 304         TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */
 305         TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */
 306         RESERVED0, /* 0x5 */
 307         TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */
 308         TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */
 309         TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */
 310         TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */
 311         TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */
 312         TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */
 313         TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */
 314         TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */
 315         TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */
 316         TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */
 317         TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */
 318         TRANS_TX_ERR_FRAME_TXED, /* 0x11 */
 319         TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */
 320         TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */
 321         TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */
 322         TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */
 323         TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/
 324         TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */
 325         TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */
 326         TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */
 327         TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/
 328         TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/
 329         /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
 330         TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */
 331         /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
 332         TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */
 333         TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */
 334         /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
 335         TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */
 336
 337         /* trans rx */
 338         TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x100 */
 339         TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x101 for sata/stp */
 340         TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x102 for ssp/smp */
 341         /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x102 <] for sata/stp */
 342         TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x103 for sata/stp */
 343         TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x104 for sata/stp */
 344         TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x105 for smp */
 345         /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x105 <] for sata/stp */
 346         TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x106 for sata/stp*/
 347         TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x107 */
 348         TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x108 */
 349         TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x109 */
 350         TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x10a */
 351         RESERVED1, /* 0x10b */
 352         TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x10c */
 353         TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x10d */
 354         TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x10e */
 355         TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x10f */
 356         TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x110 for ssp/smp */
 357         TRANS_RX_ERR_WITH_BAD_HASH, /* 0x111 for ssp */
 358         /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x111 <] for sata/stp */
 359         TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x112 for ssp*/
 360         /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x112 <] for sata/stp */
 361         TRANS_RX_SSP_FRM_LEN_ERR, /* 0x113 for ssp */
 362         /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x113 <] for sata */
 363         RESERVED2, /* 0x114 */
 364         RESERVED3, /* 0x115 */
 365         RESERVED4, /* 0x116 */
 366         RESERVED5, /* 0x117 */
 367         TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x118 */
 368         TRANS_RX_SMP_FRM_LEN_ERR, /* 0x119 */
 369         TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x11a */
 370         RESERVED6, /* 0x11b */
 371         RESERVED7, /* 0x11c */
 372         RESERVED8, /* 0x11d */
 373         RESERVED9, /* 0x11e */
 374         TRANS_RX_R_ERR, /* 0x11f */
 375
 376         /* dma tx */
 377         DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x200 */
 378         DMA_TX_DIF_APP_ERR, /* 0x201 */
 379         DMA_TX_DIF_RPP_ERR, /* 0x202 */
 380         DMA_TX_DATA_SGL_OVERFLOW, /* 0x203 */
 381         DMA_TX_DIF_SGL_OVERFLOW, /* 0x204 */
 382         DMA_TX_UNEXP_XFER_ERR, /* 0x205 */
 383         DMA_TX_UNEXP_RETRANS_ERR, /* 0x206 */
 384         DMA_TX_XFER_LEN_OVERFLOW, /* 0x207 */
 385         DMA_TX_XFER_OFFSET_ERR, /* 0x208 */
 386         DMA_TX_RAM_ECC_ERR, /* 0x209 */
 387         DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x20a */
 388
 389         /* sipc rx */
 390         SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x300 */
 391         SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x301 */
 392         SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x302 */
 393         SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x303 */
 394         SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x304 */
 395         SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x305 */
 396         SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x306 */
 397         SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x307 */
 398         SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x308 */
 399         SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x309 */
 400         SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x30a */
 401
 402         /* dma rx */
 403         DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x400 */
 404         DMA_RX_DIF_APP_ERR, /* 0x401 */
 405         DMA_RX_DIF_RPP_ERR, /* 0x402 */
 406         DMA_RX_DATA_SGL_OVERFLOW, /* 0x403 */
 407         DMA_RX_DIF_SGL_OVERFLOW, /* 0x404 */
 408         DMA_RX_DATA_LEN_OVERFLOW, /* 0x405 */
 409         DMA_RX_DATA_LEN_UNDERFLOW, /* 0x406 */
 410         DMA_RX_DATA_OFFSET_ERR, /* 0x407 */
 411         RESERVED10, /* 0x408 */
 412         DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x409 */
 413         DMA_RX_RESP_BUF_OVERFLOW, /* 0x40a */
 414         DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x40b */
 415         DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x40c */
 416         DMA_RX_UNEXP_RDFRAME_ERR, /* 0x40d */
 417         DMA_RX_PIO_DATA_LEN_ERR, /* 0x40e */
 418         DMA_RX_RDSETUP_STATUS_ERR, /* 0x40f */
 419         DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x410 */
 420         DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x411 */
 421         DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x412 */
 422         DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x413 */
 423         DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x414 */
 424         DMA_RX_RDSETUP_OFFSET_ERR, /* 0x415 */
 425         DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x416 */
 426         DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x417 */
 427         DMA_RX_RAM_ECC_ERR, /* 0x418 */
 428         DMA_RX_UNKNOWN_FRM_ERR, /* 0x419 */
 429 };
 430
 431 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
 432
 433 #define DIR_NO_DATA 0
 434 #define DIR_TO_INI 1
 435 #define DIR_TO_DEVICE 2
 436 #define DIR_RESERVED 3
 437
 438 #define SATA_PROTOCOL_NONDATA           0x1
 439 #define SATA_PROTOCOL_PIO               0x2
 440 #define SATA_PROTOCOL_DMA               0x4
 441 #define SATA_PROTOCOL_FPDMA             0x8
 442 #define SATA_PROTOCOL_ATAPI             0x10
 443
 444 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
 445 {
 446         void __iomem *regs = hisi_hba->regs + off;
 447
 448         return readl(regs);
 449 }
 450
 451 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
 452 {
 453         void __iomem *regs = hisi_hba->regs + off;
 454
 455         return readl_relaxed(regs);
 456 }
 457
 458 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
 459 {
 460         void __iomem *regs = hisi_hba->regs + off;
 461
 462         writel(val, regs);
 463 }
 464
 465 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
 466                                  u32 off, u32 val)
 467 {
 468         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 469
 470         writel(val, regs);
 471 }
 472
 473 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
 474                                       int phy_no, u32 off)
 475 {
 476         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 477
 478         return readl(regs);
 479 }
 480
 481 /* This function needs to be protected from pre-emption. */
 482 static int
 483 slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba, int *slot_idx,
 484                        struct domain_device *device)
 485 {
 486         unsigned int index = 0;
 487         void *bitmap = hisi_hba->slot_index_tags;
 488         int sata_dev = dev_is_sata(device);
 489
 490         while (1) {
 491                 index = find_next_zero_bit(bitmap, hisi_hba->slot_index_count,
 492                                            index);
 493                 if (index >= hisi_hba->slot_index_count)
 494                         return -SAS_QUEUE_FULL;
 495                 /*
 496                  * SAS IPTT bit0 should be 1
 497                  */
 498                 if (sata_dev || (index & 1))
 499                         break;
 500                 index++;
 501         }
 502
 503         set_bit(index, bitmap);
 504         *slot_idx = index;
 505         return 0;
 506 }
 507
 508 static struct
 509 hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device)
 510 {
 511         struct hisi_hba *hisi_hba = device->port->ha->lldd_ha;
 512         struct hisi_sas_device *sas_dev = NULL;
 513         int i, sata_dev = dev_is_sata(device);
 514
 515         spin_lock(&hisi_hba->lock);
 516         for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
 517                 /*
 518                  * SATA device id bit0 should be 0
 519                  */
 520                 if (sata_dev && (i & 1))
 521                         continue;
 522                 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) {
 523                         hisi_hba->devices[i].device_id = i;
 524                         sas_dev = &hisi_hba->devices[i];
 525                         sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
 526                         sas_dev->dev_type = device->dev_type;
 527                         sas_dev->hisi_hba = hisi_hba;
 528                         sas_dev->sas_device = device;
 529                         break;
 530                 }
 531         }
 532         spin_unlock(&hisi_hba->lock);
 533
 534         return sas_dev;
 535 }
 536
 537 static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 538 {
 539         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 540
 541         cfg &= ~PHY_CFG_DC_OPT_MSK;
 542         cfg |= 1 << PHY_CFG_DC_OPT_OFF;
 543         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 544 }
 545
 546 static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 547 {
 548         struct sas_identify_frame identify_frame;
 549         u32 *identify_buffer;
 550
 551         memset(&identify_frame, 0, sizeof(identify_frame));
 552         identify_frame.dev_type = SAS_END_DEVICE;
 553         identify_frame.frame_type = 0;
 554         identify_frame._un1 = 1;
 555         identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
 556         identify_frame.target_bits = SAS_PROTOCOL_NONE;
 557         memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 558         memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 559         identify_frame.phy_id = phy_no;
 560         identify_buffer = (u32 *)(&identify_frame);
 561
 562         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
 563                         __swab32(identify_buffer[0]));
 564         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
 565                         __swab32(identify_buffer[1]));
 566         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
 567                         __swab32(identify_buffer[2]));
 568         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
 569                         __swab32(identify_buffer[3]));
 570         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
 571                         __swab32(identify_buffer[4]));
 572         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
 573                         __swab32(identify_buffer[5]));
 574 }
 575
 576 static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
 577                              struct hisi_sas_device *sas_dev)
 578 {
 579         struct domain_device *device = sas_dev->sas_device;
 580         struct device *dev = &hisi_hba->pdev->dev;
 581         u64 qw0, device_id = sas_dev->device_id;
 582         struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
 583         struct domain_device *parent_dev = device->parent;
 584         struct hisi_sas_port *port = device->port->lldd_port;
 585
 586         memset(itct, 0, sizeof(*itct));
 587
 588         /* qw0 */
 589         qw0 = 0;
 590         switch (sas_dev->dev_type) {
 591         case SAS_END_DEVICE:
 592         case SAS_EDGE_EXPANDER_DEVICE:
 593         case SAS_FANOUT_EXPANDER_DEVICE:
 594                 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
 595                 break;
 596         case SAS_SATA_DEV:
 597         case SAS_SATA_PENDING:
 598                 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
 599                         qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
 600                 else
 601                         qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
 602                 break;
 603         default:
 604                 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
 605                          sas_dev->dev_type);
 606         }
 607
 608         qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
 609                 (device->linkrate << ITCT_HDR_MCR_OFF) |
 610                 (1 << ITCT_HDR_VLN_OFF) |
 611                 (port->id << ITCT_HDR_PORT_ID_OFF));
 612         itct->qw0 = cpu_to_le64(qw0);
 613
 614         /* qw1 */
 615         memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
 616         itct->sas_addr = __swab64(itct->sas_addr);
 617
 618         /* qw2 */
 619         if (!dev_is_sata(device))
 620                 itct->qw2 = cpu_to_le64((500ULL << ITCT_HDR_INLT_OFF) |
 621                                         (0x1ULL << ITCT_HDR_BITLT_OFF) |
 622                                         (0x32ULL << ITCT_HDR_MCTLT_OFF) |
 623                                         (0x1ULL << ITCT_HDR_RTOLT_OFF));
 624 }
 625
 626 static void free_device_v2_hw(struct hisi_hba *hisi_hba,
 627                               struct hisi_sas_device *sas_dev)
 628 {
 629         u64 qw0, dev_id = sas_dev->device_id;
 630         struct device *dev = &hisi_hba->pdev->dev;
 631         struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
 632         u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
 633         int i;
 634
 635         /* clear the itct interrupt state */
 636         if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
 637                 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
 638                                  ENT_INT_SRC3_ITC_INT_MSK);
 639
 640         /* clear the itct int*/
 641         for (i = 0; i < 2; i++) {
 642                 /* clear the itct table*/
 643                 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
 644                 reg_val |= ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
 645                 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
 646
 647                 udelay(10);
 648                 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
 649                 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) {
 650                         dev_dbg(dev, "got clear ITCT done interrupt\n");
 651
 652                         /* invalid the itct state*/
 653                         qw0 = cpu_to_le64(itct->qw0);
 654                         qw0 &= ~(1 << ITCT_HDR_VALID_OFF);
 655                         hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
 656                                          ENT_INT_SRC3_ITC_INT_MSK);
 657                         hisi_hba->devices[dev_id].dev_type = SAS_PHY_UNUSED;
 658                         hisi_hba->devices[dev_id].dev_status = HISI_SAS_DEV_NORMAL;
 659
 660                         /* clear the itct */
 661                         hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
 662                         dev_dbg(dev, "clear ITCT ok\n");
 663                         break;
 664                 }
 665         }
 666 }
 667
 668 static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
 669 {
 670         int i, reset_val;
 671         u32 val;
 672         unsigned long end_time;
 673         struct device *dev = &hisi_hba->pdev->dev;
 674
 675         /* The mask needs to be set depending on the number of phys */
 676         if (hisi_hba->n_phy == 9)
 677                 reset_val = 0x1fffff;
 678         else
 679                 reset_val = 0x7ffff;
 680
 681         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
 682
 683         /* Disable all of the PHYs */
 684         for (i = 0; i < hisi_hba->n_phy; i++) {
 685                 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
 686
 687                 phy_cfg &= ~PHY_CTRL_RESET_MSK;
 688                 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
 689         }
 690         udelay(50);
 691
 692         /* Ensure DMA tx & rx idle */
 693         for (i = 0; i < hisi_hba->n_phy; i++) {
 694                 u32 dma_tx_status, dma_rx_status;
 695
 696                 end_time = jiffies + msecs_to_jiffies(1000);
 697
 698                 while (1) {
 699                         dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
 700                                                             DMA_TX_STATUS);
 701                         dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
 702                                                             DMA_RX_STATUS);
 703
 704                         if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
 705                                 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
 706                                 break;
 707
 708                         msleep(20);
 709                         if (time_after(jiffies, end_time))
 710                                 return -EIO;
 711                 }
 712         }
 713
 714         /* Ensure axi bus idle */
 715         end_time = jiffies + msecs_to_jiffies(1000);
 716         while (1) {
 717                 u32 axi_status =
 718                         hisi_sas_read32(hisi_hba, AXI_CFG);
 719
 720                 if (axi_status == 0)
 721                         break;
 722
 723                 msleep(20);
 724                 if (time_after(jiffies, end_time))
 725                         return -EIO;
 726         }
 727
 728         if (ACPI_HANDLE(dev)) {
 729                 acpi_status s;
 730
 731                 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
 732                 if (ACPI_FAILURE(s)) {
 733                         dev_err(dev, "Reset failed\n");
 734                         return -EIO;
 735                 }
 736         } else if (hisi_hba->ctrl) {
 737                 /* reset and disable clock*/
 738                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
 739                                 reset_val);
 740                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
 741                                 reset_val);
 742                 msleep(1);
 743                 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
 744                 if (reset_val != (val & reset_val)) {
 745                         dev_err(dev, "SAS reset fail.\n");
 746                         return -EIO;
 747                 }
 748
 749                 /* De-reset and enable clock*/
 750                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
 751                                 reset_val);
 752                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
 753                                 reset_val);
 754                 msleep(1);
 755                 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
 756                                 &val);
 757                 if (val & reset_val) {
 758                         dev_err(dev, "SAS de-reset fail.\n");
 759                         return -EIO;
 760                 }
 761         } else
 762                 dev_warn(dev, "no reset method\n");
 763
 764         return 0;
 765 }
 766
 767 static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
 768 {
 769         struct device *dev = &hisi_hba->pdev->dev;
 770         int i;
 771
 772         /* Global registers init */
 773
 774         /* Deal with am-max-transmissions quirk */
 775         if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) {
 776                 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
 777                 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
 778                                  0x2020);
 779         } /* Else, use defaults -> do nothing */
 780
 781         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
 782                          (u32)((1ULL << hisi_hba->queue_count) - 1));
 783         hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
 784         hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
 785         hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
 786         hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
 787         hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
 788         hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
 789         hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32);
 790         hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
 791         hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
 792         hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
 793         hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
 794         hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
 795         hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
 796         hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
 797         hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
 798         hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
 799         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
 800         hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
 801         hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
 802         hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
 803         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
 804         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
 805         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffffffe);
 806         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfffff3c0);
 807         for (i = 0; i < hisi_hba->queue_count; i++)
 808                 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
 809
 810         hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
 811         hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
 812
 813         for (i = 0; i < hisi_hba->n_phy; i++) {
 814                 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
 815                 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, 0x30b9908);
 816                 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
 817                 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x10);
 818                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
 819                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
 820                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
 821                 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
 822                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
 823                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff);
 824                 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x23f801fc);
 825                 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
 826                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
 827                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
 828                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
 829                 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
 830                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
 831                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
 832                 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
 833         }
 834
 835         for (i = 0; i < hisi_hba->queue_count; i++) {
 836                 /* Delivery queue */
 837                 hisi_sas_write32(hisi_hba,
 838                                  DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
 839                                  upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
 840
 841                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
 842                                  lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
 843
 844                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
 845                                  HISI_SAS_QUEUE_SLOTS);
 846
 847                 /* Completion queue */
 848                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
 849                                  upper_32_bits(hisi_hba->complete_hdr_dma[i]));
 850
 851                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
 852                                  lower_32_bits(hisi_hba->complete_hdr_dma[i]));
 853
 854                 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
 855                                  HISI_SAS_QUEUE_SLOTS);
 856         }
 857
 858         /* itct */
 859         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
 860                          lower_32_bits(hisi_hba->itct_dma));
 861
 862         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
 863                          upper_32_bits(hisi_hba->itct_dma));
 864
 865         /* iost */
 866         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
 867                          lower_32_bits(hisi_hba->iost_dma));
 868
 869         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
 870                          upper_32_bits(hisi_hba->iost_dma));
 871
 872         /* breakpoint */
 873         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
 874                          lower_32_bits(hisi_hba->breakpoint_dma));
 875
 876         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
 877                          upper_32_bits(hisi_hba->breakpoint_dma));
 878
 879         /* SATA broken msg */
 880         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
 881                          lower_32_bits(hisi_hba->sata_breakpoint_dma));
 882
 883         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
 884                          upper_32_bits(hisi_hba->sata_breakpoint_dma));
 885
 886         /* SATA initial fis */
 887         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
 888                          lower_32_bits(hisi_hba->initial_fis_dma));
 889
 890         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
 891                          upper_32_bits(hisi_hba->initial_fis_dma));
 892 }
 893
 894 static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
 895 {
 896         struct device *dev = &hisi_hba->pdev->dev;
 897         int rc;
 898
 899         rc = reset_hw_v2_hw(hisi_hba);
 900         if (rc) {
 901                 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
 902                 return rc;
 903         }
 904
 905         msleep(100);
 906         init_reg_v2_hw(hisi_hba);
 907
 908         return 0;
 909 }
 910
 911 static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 912 {
 913         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 914
 915         cfg |= PHY_CFG_ENA_MSK;
 916         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 917 }
 918
 919 static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 920 {
 921         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 922
 923         cfg &= ~PHY_CFG_ENA_MSK;
 924         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 925 }
 926
 927 static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 928 {
 929         config_id_frame_v2_hw(hisi_hba, phy_no);
 930         config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
 931         enable_phy_v2_hw(hisi_hba, phy_no);
 932 }
 933
 934 static void stop_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 935 {
 936         disable_phy_v2_hw(hisi_hba, phy_no);
 937 }
 938
 939 static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 940 {
 941         stop_phy_v2_hw(hisi_hba, phy_no);
 942         msleep(100);
 943         start_phy_v2_hw(hisi_hba, phy_no);
 944 }
 945
 946 static void start_phys_v2_hw(unsigned long data)
 947 {
 948         struct hisi_hba *hisi_hba = (struct hisi_hba *)data;
 949         int i;
 950
 951         for (i = 0; i < hisi_hba->n_phy; i++)
 952                 start_phy_v2_hw(hisi_hba, i);
 953 }
 954
 955 static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
 956 {
 957         struct timer_list *timer = &hisi_hba->timer;
 958
 959         setup_timer(timer, start_phys_v2_hw, (unsigned long)hisi_hba);
 960         mod_timer(timer, jiffies + HZ);
 961 }
 962
 963 static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 964 {
 965         u32 sl_control;
 966
 967         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
 968         sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
 969         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
 970         msleep(1);
 971         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
 972         sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
 973         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
 974 }
 975
 976 static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
 977 {
 978         int i, bitmap = 0;
 979         u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
 980         u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
 981
 982         for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
 983                 if (phy_state & 1 << i)
 984                         if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
 985                                 bitmap |= 1 << i;
 986
 987         if (hisi_hba->n_phy == 9) {
 988                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
 989
 990                 if (phy_state & 1 << 8)
 991                         if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
 992                              PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
 993                                 bitmap |= 1 << 9;
 994         }
 995
 996         return bitmap;
 997 }
 998
 999 /**
1000  * This function allocates across all queues to load balance.
1001  * Slots are allocated from queues in a round-robin fashion.
1002  *
1003  * The callpath to this function and upto writing the write
1004  * queue pointer should be safe from interruption.
1005  */
1006 static int get_free_slot_v2_hw(struct hisi_hba *hisi_hba, int *q, int *s)
1007 {
1008         struct device *dev = &hisi_hba->pdev->dev;
1009         struct hisi_sas_dq *dq;
1010         u32 r, w;
1011         int queue = hisi_hba->queue;
1012
1013         while (1) {
1014                 dq = &hisi_hba->dq[queue];
1015                 w = dq->wr_point;
1016                 r = hisi_sas_read32_relaxed(hisi_hba,
1017                                             DLVRY_Q_0_RD_PTR + (queue * 0x14));
1018                 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
1019                         queue = (queue + 1) % hisi_hba->queue_count;
1020                         if (queue == hisi_hba->queue) {
1021                                 dev_warn(dev, "could not find free slot\n");
1022                                 return -EAGAIN;
1023                         }
1024                         continue;
1025                 }
1026                 break;
1027         }
1028         hisi_hba->queue = (queue + 1) % hisi_hba->queue_count;
1029         *q = queue;
1030         *s = w;
1031         return 0;
1032 }
1033
1034 static void start_delivery_v2_hw(struct hisi_hba *hisi_hba)
1035 {
1036         int dlvry_queue = hisi_hba->slot_prep->dlvry_queue;
1037         int dlvry_queue_slot = hisi_hba->slot_prep->dlvry_queue_slot;
1038         struct hisi_sas_dq *dq = &hisi_hba->dq[dlvry_queue];
1039
1040         dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
1041         hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
1042                          dq->wr_point);
1043 }
1044
1045 static int prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
1046                               struct hisi_sas_slot *slot,
1047                               struct hisi_sas_cmd_hdr *hdr,
1048                               struct scatterlist *scatter,
1049                               int n_elem)
1050 {
1051         struct device *dev = &hisi_hba->pdev->dev;
1052         struct scatterlist *sg;
1053         int i;
1054
1055         if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
1056                 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
1057                         n_elem);
1058                 return -EINVAL;
1059         }
1060
1061         slot->sge_page = dma_pool_alloc(hisi_hba->sge_page_pool, GFP_ATOMIC,
1062                                         &slot->sge_page_dma);
1063         if (!slot->sge_page)
1064                 return -ENOMEM;
1065
1066         for_each_sg(scatter, sg, n_elem, i) {
1067                 struct hisi_sas_sge *entry = &slot->sge_page->sge[i];
1068
1069                 entry->addr = cpu_to_le64(sg_dma_address(sg));
1070                 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1071                 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1072                 entry->data_off = 0;
1073         }
1074
1075         hdr->prd_table_addr = cpu_to_le64(slot->sge_page_dma);
1076
1077         hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1078
1079         return 0;
1080 }
1081
1082 static int prep_smp_v2_hw(struct hisi_hba *hisi_hba,
1083                           struct hisi_sas_slot *slot)
1084 {
1085         struct sas_task *task = slot->task;
1086         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1087         struct domain_device *device = task->dev;
1088         struct device *dev = &hisi_hba->pdev->dev;
1089         struct hisi_sas_port *port = slot->port;
1090         struct scatterlist *sg_req, *sg_resp;
1091         struct hisi_sas_device *sas_dev = device->lldd_dev;
1092         dma_addr_t req_dma_addr;
1093         unsigned int req_len, resp_len;
1094         int elem, rc;
1095
1096         /*
1097         * DMA-map SMP request, response buffers
1098         */
1099         /* req */
1100         sg_req = &task->smp_task.smp_req;
1101         elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
1102         if (!elem)
1103                 return -ENOMEM;
1104         req_len = sg_dma_len(sg_req);
1105         req_dma_addr = sg_dma_address(sg_req);
1106
1107         /* resp */
1108         sg_resp = &task->smp_task.smp_resp;
1109         elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
1110         if (!elem) {
1111                 rc = -ENOMEM;
1112                 goto err_out_req;
1113         }
1114         resp_len = sg_dma_len(sg_resp);
1115         if ((req_len & 0x3) || (resp_len & 0x3)) {
1116                 rc = -EINVAL;
1117                 goto err_out_resp;
1118         }
1119
1120         /* create header */
1121         /* dw0 */
1122         hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1123                                (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1124                                (2 << CMD_HDR_CMD_OFF)); /* smp */
1125
1126         /* map itct entry */
1127         hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1128                                (1 << CMD_HDR_FRAME_TYPE_OFF) |
1129                                (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1130
1131         /* dw2 */
1132         hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1133                                (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1134                                CMD_HDR_MRFL_OFF));
1135
1136         hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1137
1138         hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1139         hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
1140
1141         return 0;
1142
1143 err_out_resp:
1144         dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
1145                      DMA_FROM_DEVICE);
1146 err_out_req:
1147         dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
1148                      DMA_TO_DEVICE);
1149         return rc;
1150 }
1151
1152 static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
1153                           struct hisi_sas_slot *slot, int is_tmf,
1154                           struct hisi_sas_tmf_task *tmf)
1155 {
1156         struct sas_task *task = slot->task;
1157         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1158         struct domain_device *device = task->dev;
1159         struct hisi_sas_device *sas_dev = device->lldd_dev;
1160         struct hisi_sas_port *port = slot->port;
1161         struct sas_ssp_task *ssp_task = &task->ssp_task;
1162         struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1163         int has_data = 0, rc, priority = is_tmf;
1164         u8 *buf_cmd;
1165         u32 dw1 = 0, dw2 = 0;
1166
1167         hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1168                                (2 << CMD_HDR_TLR_CTRL_OFF) |
1169                                (port->id << CMD_HDR_PORT_OFF) |
1170                                (priority << CMD_HDR_PRIORITY_OFF) |
1171                                (1 << CMD_HDR_CMD_OFF)); /* ssp */
1172
1173         dw1 = 1 << CMD_HDR_VDTL_OFF;
1174         if (is_tmf) {
1175                 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1176                 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1177         } else {
1178                 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1179                 switch (scsi_cmnd->sc_data_direction) {
1180                 case DMA_TO_DEVICE:
1181                         has_data = 1;
1182                         dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1183                         break;
1184                 case DMA_FROM_DEVICE:
1185                         has_data = 1;
1186                         dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1187                         break;
1188                 default:
1189                         dw1 &= ~CMD_HDR_DIR_MSK;
1190                 }
1191         }
1192
1193         /* map itct entry */
1194         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1195         hdr->dw1 = cpu_to_le32(dw1);
1196
1197         dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1198               + 3) / 4) << CMD_HDR_CFL_OFF) |
1199               ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1200               (2 << CMD_HDR_SG_MOD_OFF);
1201         hdr->dw2 = cpu_to_le32(dw2);
1202
1203         hdr->transfer_tags = cpu_to_le32(slot->idx);
1204
1205         if (has_data) {
1206                 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1207                                         slot->n_elem);
1208                 if (rc)
1209                         return rc;
1210         }
1211
1212         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1213         hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma);
1214         hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
1215
1216         buf_cmd = slot->command_table + sizeof(struct ssp_frame_hdr);
1217
1218         memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1219         if (!is_tmf) {
1220                 buf_cmd[9] = task->ssp_task.task_attr |
1221                                 (task->ssp_task.task_prio << 3);
1222                 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1223                                 task->ssp_task.cmd->cmd_len);
1224         } else {
1225                 buf_cmd[10] = tmf->tmf;
1226                 switch (tmf->tmf) {
1227                 case TMF_ABORT_TASK:
1228                 case TMF_QUERY_TASK:
1229                         buf_cmd[12] =
1230                                 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1231                         buf_cmd[13] =
1232                                 tmf->tag_of_task_to_be_managed & 0xff;
1233                         break;
1234                 default:
1235                         break;
1236                 }
1237         }
1238
1239         return 0;
1240 }
1241
1242 static void sata_done_v2_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
1243                             struct hisi_sas_slot *slot)
1244 {
1245         struct task_status_struct *ts = &task->task_status;
1246         struct ata_task_resp *resp = (struct ata_task_resp *)ts->buf;
1247         struct dev_to_host_fis *d2h = slot->status_buffer +
1248                                       sizeof(struct hisi_sas_err_record);
1249
1250         resp->frame_len = sizeof(struct dev_to_host_fis);
1251         memcpy(&resp->ending_fis[0], d2h, sizeof(struct dev_to_host_fis));
1252
1253         ts->buf_valid_size = sizeof(*resp);
1254 }
1255
1256 /* by default, task resp is complete */
1257 static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
1258                            struct sas_task *task,
1259                            struct hisi_sas_slot *slot)
1260 {
1261         struct task_status_struct *ts = &task->task_status;
1262         struct hisi_sas_err_record_v2 *err_record = slot->status_buffer;
1263         u32 trans_tx_fail_type = cpu_to_le32(err_record->trans_tx_fail_type);
1264         u32 trans_rx_fail_type = cpu_to_le32(err_record->trans_rx_fail_type);
1265         u16 dma_tx_err_type = cpu_to_le16(err_record->dma_tx_err_type);
1266         u16 sipc_rx_err_type = cpu_to_le16(err_record->sipc_rx_err_type);
1267         u32 dma_rx_err_type = cpu_to_le32(err_record->dma_rx_err_type);
1268         int error = -1;
1269
1270         if (dma_rx_err_type) {
1271                 error = ffs(dma_rx_err_type)
1272                         - 1 + DMA_RX_ERR_BASE;
1273         } else if (sipc_rx_err_type) {
1274                 error = ffs(sipc_rx_err_type)
1275                         - 1 + SIPC_RX_ERR_BASE;
1276         }  else if (dma_tx_err_type) {
1277                 error = ffs(dma_tx_err_type)
1278                         - 1 + DMA_TX_ERR_BASE;
1279         } else if (trans_rx_fail_type) {
1280                 error = ffs(trans_rx_fail_type)
1281                         - 1 + TRANS_RX_FAIL_BASE;
1282         } else if (trans_tx_fail_type) {
1283                 error = ffs(trans_tx_fail_type)
1284                         - 1 + TRANS_TX_FAIL_BASE;
1285         }
1286
1287         switch (task->task_proto) {
1288         case SAS_PROTOCOL_SSP:
1289         {
1290                 switch (error) {
1291                 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
1292                 {
1293                         ts->stat = SAS_OPEN_REJECT;
1294                         ts->open_rej_reason = SAS_OREJ_NO_DEST;
1295                         break;
1296                 }
1297                 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
1298                 {
1299                         ts->stat = SAS_OPEN_REJECT;
1300                         ts->open_rej_reason = SAS_OREJ_PATH_BLOCKED;
1301                         break;
1302                 }
1303                 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
1304                 {
1305                         ts->stat = SAS_OPEN_REJECT;
1306                         ts->open_rej_reason = SAS_OREJ_EPROTO;
1307                         break;
1308                 }
1309                 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
1310                 {
1311                         ts->stat = SAS_OPEN_REJECT;
1312                         ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1313                         break;
1314                 }
1315                 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
1316                 {
1317                         ts->stat = SAS_OPEN_REJECT;
1318                         ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1319                         break;
1320                 }
1321                 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
1322                 {
1323                         ts->stat = SAS_OPEN_REJECT;
1324                         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1325                         break;
1326                 }
1327                 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
1328                 {
1329                         ts->stat = SAS_OPEN_REJECT;
1330                         ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1331                         break;
1332                 }
1333                 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
1334                 {
1335                         ts->stat = SAS_OPEN_REJECT;
1336                         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1337                         break;
1338                 }
1339                 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
1340                 {
1341                         /* not sure */
1342                         ts->stat = SAS_DEV_NO_RESPONSE;
1343                         break;
1344                 }
1345                 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
1346                 {
1347                         ts->stat = SAS_PHY_DOWN;
1348                         break;
1349                 }
1350                 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
1351                 {
1352                         ts->stat = SAS_OPEN_TO;
1353                         break;
1354                 }
1355                 case DMA_RX_DATA_LEN_OVERFLOW:
1356                 {
1357                         ts->stat = SAS_DATA_OVERRUN;
1358                         ts->residual = 0;
1359                         break;
1360                 }
1361                 case DMA_RX_DATA_LEN_UNDERFLOW:
1362                 case SIPC_RX_DATA_UNDERFLOW_ERR:
1363                 {
1364                         ts->residual = trans_tx_fail_type;
1365                         ts->stat = SAS_DATA_UNDERRUN;
1366                         break;
1367                 }
1368                 case TRANS_TX_ERR_FRAME_TXED:
1369                 {
1370                         /* This will request a retry */
1371                         ts->stat = SAS_QUEUE_FULL;
1372                         slot->abort = 1;
1373                         break;
1374                 }
1375                 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
1376                 case TRANS_TX_ERR_PHY_NOT_ENABLE:
1377                 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
1378                 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
1379                 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
1380                 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
1381                 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
1382                 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
1383                 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
1384                 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
1385                 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
1386                 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
1387                 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
1388                 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
1389                 case TRANS_TX_ERR_WITH_IPTT_CONFLICT:
1390                 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
1391                 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR:
1392                 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
1393                 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
1394                 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
1395                 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
1396                 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
1397                 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
1398                 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
1399                 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
1400                 case TRANS_RX_ERR_WITH_DATA_LEN0:
1401                 case TRANS_RX_ERR_WITH_BAD_HASH:
1402                 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
1403                 case TRANS_RX_SSP_FRM_LEN_ERR:
1404                 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
1405                 case DMA_TX_UNEXP_XFER_ERR:
1406                 case DMA_TX_UNEXP_RETRANS_ERR:
1407                 case DMA_TX_XFER_LEN_OVERFLOW:
1408                 case DMA_TX_XFER_OFFSET_ERR:
1409                 case DMA_RX_DATA_OFFSET_ERR:
1410                 case DMA_RX_UNEXP_NORM_RESP_ERR:
1411                 case DMA_RX_UNEXP_RDFRAME_ERR:
1412                 case DMA_RX_UNKNOWN_FRM_ERR:
1413                 {
1414                         ts->stat = SAS_OPEN_REJECT;
1415                         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1416                         break;
1417                 }
1418                 default:
1419                         break;
1420                 }
1421         }
1422                 break;
1423         case SAS_PROTOCOL_SMP:
1424                 ts->stat = SAM_STAT_CHECK_CONDITION;
1425                 break;
1426
1427         case SAS_PROTOCOL_SATA:
1428         case SAS_PROTOCOL_STP:
1429         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1430         {
1431                 switch (error) {
1432                 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
1433                 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
1434                 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
1435                 {
1436                         ts->resp = SAS_TASK_UNDELIVERED;
1437                         ts->stat = SAS_DEV_NO_RESPONSE;
1438                         break;
1439                 }
1440                 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
1441                 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
1442                 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
1443                 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
1444                 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
1445                 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
1446                 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY:
1447                 {
1448                         ts->stat = SAS_OPEN_REJECT;
1449                         break;
1450                 }
1451                 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
1452                 {
1453                         ts->stat = SAS_OPEN_TO;
1454                         break;
1455                 }
1456                 case DMA_RX_DATA_LEN_OVERFLOW:
1457                 {
1458                         ts->stat = SAS_DATA_OVERRUN;
1459                         break;
1460                 }
1461                 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
1462                 case TRANS_TX_ERR_PHY_NOT_ENABLE:
1463                 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
1464                 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
1465                 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
1466                 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
1467                 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
1468                 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
1469                 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
1470                 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
1471                 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
1472                 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
1473                 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
1474                 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
1475                 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
1476                 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT:
1477                 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
1478                 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
1479                 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR:
1480                 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR:
1481                 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN:
1482                 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP:
1483                 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
1484                 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
1485                 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
1486                 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
1487                 case TRANS_RX_ERR_WITH_DATA_LEN0:
1488                 case TRANS_RX_ERR_WITH_BAD_HASH:
1489                 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
1490                 case TRANS_RX_SSP_FRM_LEN_ERR:
1491                 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD:
1492                 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR:
1493                 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR:
1494                 case SIPC_RX_WRSETUP_LEN_ODD_ERR:
1495                 case SIPC_RX_WRSETUP_LEN_ZERO_ERR:
1496                 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR:
1497                 case SIPC_RX_SATA_UNEXP_FIS_ERR:
1498                 case DMA_RX_SATA_FRAME_TYPE_ERR:
1499                 case DMA_RX_UNEXP_RDFRAME_ERR:
1500                 case DMA_RX_PIO_DATA_LEN_ERR:
1501                 case DMA_RX_RDSETUP_STATUS_ERR:
1502                 case DMA_RX_RDSETUP_STATUS_DRQ_ERR:
1503                 case DMA_RX_RDSETUP_STATUS_BSY_ERR:
1504                 case DMA_RX_RDSETUP_LEN_ODD_ERR:
1505                 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
1506                 case DMA_RX_RDSETUP_LEN_OVER_ERR:
1507                 case DMA_RX_RDSETUP_OFFSET_ERR:
1508                 case DMA_RX_RDSETUP_ACTIVE_ERR:
1509                 case DMA_RX_RDSETUP_ESTATUS_ERR:
1510                 case DMA_RX_UNKNOWN_FRM_ERR:
1511                 {
1512                         ts->stat = SAS_OPEN_REJECT;
1513                         break;
1514                 }
1515                 default:
1516                 {
1517                         ts->stat = SAS_PROTO_RESPONSE;
1518                         break;
1519                 }
1520                 }
1521                 sata_done_v2_hw(hisi_hba, task, slot);
1522         }
1523                 break;
1524         default:
1525                 break;
1526         }
1527 }
1528
1529 static int
1530 slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot,
1531                     int abort)
1532 {
1533         struct sas_task *task = slot->task;
1534         struct hisi_sas_device *sas_dev;
1535         struct device *dev = &hisi_hba->pdev->dev;
1536         struct task_status_struct *ts;
1537         struct domain_device *device;
1538         enum exec_status sts;
1539         struct hisi_sas_complete_v2_hdr *complete_queue =
1540                         hisi_hba->complete_hdr[slot->cmplt_queue];
1541         struct hisi_sas_complete_v2_hdr *complete_hdr =
1542                         &complete_queue[slot->cmplt_queue_slot];
1543
1544         if (unlikely(!task || !task->lldd_task || !task->dev))
1545                 return -EINVAL;
1546
1547         ts = &task->task_status;
1548         device = task->dev;
1549         sas_dev = device->lldd_dev;
1550
1551         task->task_state_flags &=
1552                 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1553         task->task_state_flags |= SAS_TASK_STATE_DONE;
1554
1555         memset(ts, 0, sizeof(*ts));
1556         ts->resp = SAS_TASK_COMPLETE;
1557
1558         if (unlikely(!sas_dev || abort)) {
1559                 if (!sas_dev)
1560                         dev_dbg(dev, "slot complete: port has not device\n");
1561                 ts->stat = SAS_PHY_DOWN;
1562                 goto out;
1563         }
1564
1565         /* Use SAS+TMF status codes */
1566         switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
1567                         >> CMPLT_HDR_ABORT_STAT_OFF) {
1568         case STAT_IO_ABORTED:
1569                 /* this io has been aborted by abort command */
1570                 ts->stat = SAS_ABORTED_TASK;
1571                 goto out;
1572         case STAT_IO_COMPLETE:
1573                 /* internal abort command complete */
1574                 ts->stat = TMF_RESP_FUNC_COMPLETE;
1575                 goto out;
1576         case STAT_IO_NO_DEVICE:
1577                 ts->stat = TMF_RESP_FUNC_COMPLETE;
1578                 goto out;
1579         case STAT_IO_NOT_VALID:
1580                 /* abort single io, controller don't find
1581                  * the io need to abort
1582                  */
1583                 ts->stat = TMF_RESP_FUNC_FAILED;
1584                 goto out;
1585         default:
1586                 break;
1587         }
1588
1589         if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) &&
1590                 (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
1591
1592                 slot_err_v2_hw(hisi_hba, task, slot);
1593                 if (unlikely(slot->abort)) {
1594                         queue_work(hisi_hba->wq, &slot->abort_slot);
1595                         /* immediately return and do not complete */
1596                         return ts->stat;
1597                 }
1598                 goto out;
1599         }
1600
1601         switch (task->task_proto) {
1602         case SAS_PROTOCOL_SSP:
1603         {
1604                 struct ssp_response_iu *iu = slot->status_buffer +
1605                         sizeof(struct hisi_sas_err_record);
1606
1607                 sas_ssp_task_response(dev, task, iu);
1608                 break;
1609         }
1610         case SAS_PROTOCOL_SMP:
1611         {
1612                 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1613                 void *to;
1614
1615                 ts->stat = SAM_STAT_GOOD;
1616                 to = kmap_atomic(sg_page(sg_resp));
1617
1618                 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1619                              DMA_FROM_DEVICE);
1620                 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
1621                              DMA_TO_DEVICE);
1622                 memcpy(to + sg_resp->offset,
1623                        slot->status_buffer +
1624                        sizeof(struct hisi_sas_err_record),
1625                        sg_dma_len(sg_resp));
1626                 kunmap_atomic(to);
1627                 break;
1628         }
1629         case SAS_PROTOCOL_SATA:
1630         case SAS_PROTOCOL_STP:
1631         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1632         {
1633                 ts->stat = SAM_STAT_GOOD;
1634                 sata_done_v2_hw(hisi_hba, task, slot);
1635                 break;
1636         }
1637         default:
1638                 ts->stat = SAM_STAT_CHECK_CONDITION;
1639                 break;
1640         }
1641
1642         if (!slot->port->port_attached) {
1643                 dev_err(dev, "slot complete: port %d has removed\n",
1644                         slot->port->sas_port.id);
1645                 ts->stat = SAS_PHY_DOWN;
1646         }
1647
1648 out:
1649         if (sas_dev && sas_dev->running_req)
1650                 sas_dev->running_req--;
1651
1652         hisi_sas_slot_task_free(hisi_hba, task, slot);
1653         sts = ts->stat;
1654
1655         if (task->task_done)
1656                 task->task_done(task);
1657
1658         return sts;
1659 }
1660
1661 static u8 get_ata_protocol(u8 cmd, int direction)
1662 {
1663         switch (cmd) {
1664         case ATA_CMD_FPDMA_WRITE:
1665         case ATA_CMD_FPDMA_READ:
1666         case ATA_CMD_FPDMA_RECV:
1667         case ATA_CMD_FPDMA_SEND:
1668         case ATA_CMD_NCQ_NON_DATA:
1669         return SATA_PROTOCOL_FPDMA;
1670
1671         case ATA_CMD_ID_ATA:
1672         case ATA_CMD_PMP_READ:
1673         case ATA_CMD_READ_LOG_EXT:
1674         case ATA_CMD_PIO_READ:
1675         case ATA_CMD_PIO_READ_EXT:
1676         case ATA_CMD_PMP_WRITE:
1677         case ATA_CMD_WRITE_LOG_EXT:
1678         case ATA_CMD_PIO_WRITE:
1679         case ATA_CMD_PIO_WRITE_EXT:
1680         return SATA_PROTOCOL_PIO;
1681
1682         case ATA_CMD_READ:
1683         case ATA_CMD_READ_EXT:
1684         case ATA_CMD_READ_LOG_DMA_EXT:
1685         case ATA_CMD_WRITE:
1686         case ATA_CMD_WRITE_EXT:
1687         case ATA_CMD_WRITE_QUEUED:
1688         case ATA_CMD_WRITE_LOG_DMA_EXT:
1689         return SATA_PROTOCOL_DMA;
1690
1691         case ATA_CMD_DOWNLOAD_MICRO:
1692         case ATA_CMD_DEV_RESET:
1693         case ATA_CMD_CHK_POWER:
1694         case ATA_CMD_FLUSH:
1695         case ATA_CMD_FLUSH_EXT:
1696         case ATA_CMD_VERIFY:
1697         case ATA_CMD_VERIFY_EXT:
1698         case ATA_CMD_SET_FEATURES:
1699         case ATA_CMD_STANDBY:
1700         case ATA_CMD_STANDBYNOW1:
1701         return SATA_PROTOCOL_NONDATA;
1702         default:
1703                 if (direction == DMA_NONE)
1704                         return SATA_PROTOCOL_NONDATA;
1705                 return SATA_PROTOCOL_PIO;
1706         }
1707 }
1708
1709 static int get_ncq_tag_v2_hw(struct sas_task *task, u32 *tag)
1710 {
1711         struct ata_queued_cmd *qc = task->uldd_task;
1712
1713         if (qc) {
1714                 if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
1715                         qc->tf.command == ATA_CMD_FPDMA_READ) {
1716                         *tag = qc->tag;
1717                         return 1;
1718                 }
1719         }
1720         return 0;
1721 }
1722
1723 static int prep_ata_v2_hw(struct hisi_hba *hisi_hba,
1724                           struct hisi_sas_slot *slot)
1725 {
1726         struct sas_task *task = slot->task;
1727         struct domain_device *device = task->dev;
1728         struct domain_device *parent_dev = device->parent;
1729         struct hisi_sas_device *sas_dev = device->lldd_dev;
1730         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1731         struct hisi_sas_port *port = device->port->lldd_port;
1732         u8 *buf_cmd;
1733         int has_data = 0, rc = 0, hdr_tag = 0;
1734         u32 dw1 = 0, dw2 = 0;
1735
1736         /* create header */
1737         /* dw0 */
1738         hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1739         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
1740                 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1741         else
1742                 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
1743
1744         /* dw1 */
1745         switch (task->data_dir) {
1746         case DMA_TO_DEVICE:
1747                 has_data = 1;
1748                 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1749                 break;
1750         case DMA_FROM_DEVICE:
1751                 has_data = 1;
1752                 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1753                 break;
1754         default:
1755                 dw1 &= ~CMD_HDR_DIR_MSK;
1756         }
1757
1758         if (0 == task->ata_task.fis.command)
1759                 dw1 |= 1 << CMD_HDR_RESET_OFF;
1760
1761         dw1 |= (get_ata_protocol(task->ata_task.fis.command, task->data_dir))
1762                 << CMD_HDR_FRAME_TYPE_OFF;
1763         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1764         hdr->dw1 = cpu_to_le32(dw1);
1765
1766         /* dw2 */
1767         if (task->ata_task.use_ncq && get_ncq_tag_v2_hw(task, &hdr_tag)) {
1768                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1769                 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1770         }
1771
1772         dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1773                         2 << CMD_HDR_SG_MOD_OFF;
1774         hdr->dw2 = cpu_to_le32(dw2);
1775
1776         /* dw3 */
1777         hdr->transfer_tags = cpu_to_le32(slot->idx);
1778
1779         if (has_data) {
1780                 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1781                                         slot->n_elem);
1782                 if (rc)
1783                         return rc;
1784         }
1785
1786
1787         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1788         hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma);
1789         hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
1790
1791         buf_cmd = slot->command_table;
1792
1793         if (likely(!task->ata_task.device_control_reg_update))
1794                 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1795         /* fill in command FIS */
1796         memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1797
1798         return 0;
1799 }
1800
1801 static int prep_abort_v2_hw(struct hisi_hba *hisi_hba,
1802                 struct hisi_sas_slot *slot,
1803                 int device_id, int abort_flag, int tag_to_abort)
1804 {
1805         struct sas_task *task = slot->task;
1806         struct domain_device *dev = task->dev;
1807         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1808         struct hisi_sas_port *port = slot->port;
1809
1810         /* dw0 */
1811         hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
1812                                (port->id << CMD_HDR_PORT_OFF) |
1813                                ((dev_is_sata(dev) ? 1:0) <<
1814                                 CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
1815                                (abort_flag << CMD_HDR_ABORT_FLAG_OFF));
1816
1817         /* dw1 */
1818         hdr->dw1 = cpu_to_le32(device_id << CMD_HDR_DEV_ID_OFF);
1819
1820         /* dw7 */
1821         hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
1822         hdr->transfer_tags = cpu_to_le32(slot->idx);
1823
1824         return 0;
1825 }
1826
1827 static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
1828 {
1829         int i, res = 0;
1830         u32 context, port_id, link_rate, hard_phy_linkrate;
1831         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1832         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1833         struct device *dev = &hisi_hba->pdev->dev;
1834         u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1835         struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
1836
1837         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1838
1839         /* Check for SATA dev */
1840         context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1841         if (context & (1 << phy_no))
1842                 goto end;
1843
1844         if (phy_no == 8) {
1845                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1846
1847                 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1848                           PORT_STATE_PHY8_PORT_NUM_OFF;
1849                 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
1850                             PORT_STATE_PHY8_CONN_RATE_OFF;
1851         } else {
1852                 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1853                 port_id = (port_id >> (4 * phy_no)) & 0xf;
1854                 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1855                 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1856         }
1857
1858         if (port_id == 0xf) {
1859                 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1860                 res = IRQ_NONE;
1861                 goto end;
1862         }
1863
1864         for (i = 0; i < 6; i++) {
1865                 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1866                                                RX_IDAF_DWORD0 + (i * 4));
1867                 frame_rcvd[i] = __swab32(idaf);
1868         }
1869
1870         sas_phy->linkrate = link_rate;
1871         hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
1872                                                 HARD_PHY_LINKRATE);
1873         phy->maximum_linkrate = hard_phy_linkrate & 0xf;
1874         phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
1875
1876         sas_phy->oob_mode = SAS_OOB_MODE;
1877         memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
1878         dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1879         phy->port_id = port_id;
1880         phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1881         phy->phy_type |= PORT_TYPE_SAS;
1882         phy->phy_attached = 1;
1883         phy->identify.device_type = id->dev_type;
1884         phy->frame_rcvd_size =  sizeof(struct sas_identify_frame);
1885         if (phy->identify.device_type == SAS_END_DEVICE)
1886                 phy->identify.target_port_protocols =
1887                         SAS_PROTOCOL_SSP;
1888         else if (phy->identify.device_type != SAS_PHY_UNUSED)
1889                 phy->identify.target_port_protocols =
1890                         SAS_PROTOCOL_SMP;
1891         queue_work(hisi_hba->wq, &phy->phyup_ws);
1892
1893 end:
1894         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1895                              CHL_INT0_SL_PHY_ENABLE_MSK);
1896         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1897
1898         return res;
1899 }
1900
1901 static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
1902 {
1903         int res = 0;
1904         u32 phy_cfg, phy_state;
1905
1906         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1907
1908         phy_cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1909
1910         phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1911
1912         hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
1913
1914         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1915         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1916
1917         return res;
1918 }
1919
1920 static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
1921 {
1922         struct hisi_hba *hisi_hba = p;
1923         u32 irq_msk;
1924         int phy_no = 0;
1925         irqreturn_t res = IRQ_HANDLED;
1926
1927         irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
1928                    >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
1929         while (irq_msk) {
1930                 if (irq_msk  & 1) {
1931                         u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1932                                                             CHL_INT0);
1933
1934                         if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1935                                 /* phy up */
1936                                 if (phy_up_v2_hw(phy_no, hisi_hba)) {
1937                                         res = IRQ_NONE;
1938                                         goto end;
1939                                 }
1940
1941                         if (irq_value & CHL_INT0_NOT_RDY_MSK)
1942                                 /* phy down */
1943                                 if (phy_down_v2_hw(phy_no, hisi_hba)) {
1944                                         res = IRQ_NONE;
1945                                         goto end;
1946                                 }
1947                 }
1948                 irq_msk >>= 1;
1949                 phy_no++;
1950         }
1951
1952 end:
1953         return res;
1954 }
1955
1956 static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
1957 {
1958         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1959         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1960         struct sas_ha_struct *sas_ha = &hisi_hba->sha;
1961
1962         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1963         sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1964         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1965                              CHL_INT0_SL_RX_BCST_ACK_MSK);
1966         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1967 }
1968
1969 static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
1970 {
1971         struct hisi_hba *hisi_hba = p;
1972         struct device *dev = &hisi_hba->pdev->dev;
1973         u32 ent_msk, ent_tmp, irq_msk;
1974         int phy_no = 0;
1975
1976         ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1977         ent_tmp = ent_msk;
1978         ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
1979         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
1980
1981         irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
1982                         HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
1983
1984         while (irq_msk) {
1985                 if (irq_msk & (1 << phy_no)) {
1986                         u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
1987                                                              CHL_INT0);
1988                         u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1989                                                              CHL_INT1);
1990                         u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
1991                                                              CHL_INT2);
1992
1993                         if (irq_value1) {
1994                                 if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK |
1995                                                   CHL_INT1_DMAC_TX_ECC_ERR_MSK))
1996                                         panic("%s: DMAC RX/TX ecc bad error! (0x%x)",
1997                                                 dev_name(dev), irq_value1);
1998
1999                                 hisi_sas_phy_write32(hisi_hba, phy_no,
2000                                                      CHL_INT1, irq_value1);
2001                         }
2002
2003                         if (irq_value2)
2004                                 hisi_sas_phy_write32(hisi_hba, phy_no,
2005                                                      CHL_INT2, irq_value2);
2006
2007
2008                         if (irq_value0) {
2009                                 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
2010                                         phy_bcast_v2_hw(phy_no, hisi_hba);
2011
2012                                 hisi_sas_phy_write32(hisi_hba, phy_no,
2013                                                 CHL_INT0, irq_value0
2014                                                 & (~CHL_INT0_HOTPLUG_TOUT_MSK)
2015                                                 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
2016                                                 & (~CHL_INT0_NOT_RDY_MSK));
2017                         }
2018                 }
2019                 irq_msk &= ~(1 << phy_no);
2020                 phy_no++;
2021         }
2022
2023         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
2024
2025         return IRQ_HANDLED;
2026 }
2027
2028 static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
2029 {
2030         struct hisi_sas_cq *cq = p;
2031         struct hisi_hba *hisi_hba = cq->hisi_hba;
2032         struct hisi_sas_slot *slot;
2033         struct hisi_sas_itct *itct;
2034         struct hisi_sas_complete_v2_hdr *complete_queue;
2035         u32 irq_value, rd_point = cq->rd_point, wr_point, dev_id;
2036         int queue = cq->id;
2037
2038         complete_queue = hisi_hba->complete_hdr[queue];
2039         irq_value = hisi_sas_read32(hisi_hba, OQ_INT_SRC);
2040
2041         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
2042
2043         wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
2044                                    (0x14 * queue));
2045
2046         while (rd_point != wr_point) {
2047                 struct hisi_sas_complete_v2_hdr *complete_hdr;
2048                 int iptt;
2049
2050                 complete_hdr = &complete_queue[rd_point];
2051
2052                 /* Check for NCQ completion */
2053                 if (complete_hdr->act) {
2054                         u32 act_tmp = complete_hdr->act;
2055                         int ncq_tag_count = ffs(act_tmp);
2056
2057                         dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
2058                                  CMPLT_HDR_DEV_ID_OFF;
2059                         itct = &hisi_hba->itct[dev_id];
2060
2061                         /* The NCQ tags are held in the itct header */
2062                         while (ncq_tag_count) {
2063                                 __le64 *ncq_tag = &itct->qw4_15[0];
2064
2065                                 ncq_tag_count -= 1;
2066                                 iptt = (ncq_tag[ncq_tag_count / 5]
2067                                         >> (ncq_tag_count % 5) * 12) & 0xfff;
2068
2069                                 slot = &hisi_hba->slot_info[iptt];
2070                                 slot->cmplt_queue_slot = rd_point;
2071                                 slot->cmplt_queue = queue;
2072                                 slot_complete_v2_hw(hisi_hba, slot, 0);
2073
2074                                 act_tmp &= ~(1 << ncq_tag_count);
2075                                 ncq_tag_count = ffs(act_tmp);
2076                         }
2077                 } else {
2078                         iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
2079                         slot = &hisi_hba->slot_info[iptt];
2080                         slot->cmplt_queue_slot = rd_point;
2081                         slot->cmplt_queue = queue;
2082                         slot_complete_v2_hw(hisi_hba, slot, 0);
2083                 }
2084
2085                 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
2086                         rd_point = 0;
2087         }
2088
2089         /* update rd_point */
2090         cq->rd_point = rd_point;
2091         hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
2092         return IRQ_HANDLED;
2093 }
2094
2095 static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
2096 {
2097         struct hisi_sas_phy *phy = p;
2098         struct hisi_hba *hisi_hba = phy->hisi_hba;
2099         struct asd_sas_phy *sas_phy = &phy->sas_phy;
2100         struct device *dev = &hisi_hba->pdev->dev;
2101         struct  hisi_sas_initial_fis *initial_fis;
2102         struct dev_to_host_fis *fis;
2103         u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
2104         irqreturn_t res = IRQ_HANDLED;
2105         u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
2106         int phy_no, offset;
2107
2108         phy_no = sas_phy->id;
2109         initial_fis = &hisi_hba->initial_fis[phy_no];
2110         fis = &initial_fis->fis;
2111
2112         offset = 4 * (phy_no / 4);
2113         ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset);
2114         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset,
2115                          ent_msk | 1 << ((phy_no % 4) * 8));
2116
2117         ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset);
2118         ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF *
2119                              (phy_no % 4)));
2120         ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
2121         if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
2122                 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
2123                 res = IRQ_NONE;
2124                 goto end;
2125         }
2126
2127         if (unlikely(phy_no == 8)) {
2128                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2129
2130                 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
2131                           PORT_STATE_PHY8_PORT_NUM_OFF;
2132                 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
2133                             PORT_STATE_PHY8_CONN_RATE_OFF;
2134         } else {
2135                 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
2136                 port_id = (port_id >> (4 * phy_no)) & 0xf;
2137                 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
2138                 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
2139         }
2140
2141         if (port_id == 0xf) {
2142                 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
2143                 res = IRQ_NONE;
2144                 goto end;
2145         }
2146
2147         sas_phy->linkrate = link_rate;
2148         hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
2149                                                 HARD_PHY_LINKRATE);
2150         phy->maximum_linkrate = hard_phy_linkrate & 0xf;
2151         phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
2152
2153         sas_phy->oob_mode = SATA_OOB_MODE;
2154         /* Make up some unique SAS address */
2155         attached_sas_addr[0] = 0x50;
2156         attached_sas_addr[7] = phy_no;
2157         memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
2158         memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
2159         dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
2160         phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
2161         phy->port_id = port_id;
2162         phy->phy_type |= PORT_TYPE_SATA;
2163         phy->phy_attached = 1;
2164         phy->identify.device_type = SAS_SATA_DEV;
2165         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
2166         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
2167         queue_work(hisi_hba->wq, &phy->phyup_ws);
2168
2169 end:
2170         hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp);
2171         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk);
2172
2173         return res;
2174 }
2175
2176 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
2177         int_phy_updown_v2_hw,
2178         int_chnl_int_v2_hw,
2179 };
2180
2181 /**
2182  * There is a limitation in the hip06 chipset that we need
2183  * to map in all mbigen interrupts, even if they are not used.
2184  */
2185 static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
2186 {
2187         struct platform_device *pdev = hisi_hba->pdev;
2188         struct device *dev = &pdev->dev;
2189         int i, irq, rc, irq_map[128];
2190
2191
2192         for (i = 0; i < 128; i++)
2193                 irq_map[i] = platform_get_irq(pdev, i);
2194
2195         for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
2196                 int idx = i;
2197
2198                 irq = irq_map[idx + 1]; /* Phy up/down is irq1 */
2199                 if (!irq) {
2200                         dev_err(dev, "irq init: fail map phy interrupt %d\n",
2201                                 idx);
2202                         return -ENOENT;
2203                 }
2204
2205                 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
2206                                       DRV_NAME " phy", hisi_hba);
2207                 if (rc) {
2208                         dev_err(dev, "irq init: could not request "
2209                                 "phy interrupt %d, rc=%d\n",
2210                                 irq, rc);
2211                         return -ENOENT;
2212                 }
2213         }
2214
2215         for (i = 0; i < hisi_hba->n_phy; i++) {
2216                 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
2217                 int idx = i + 72; /* First SATA interrupt is irq72 */
2218
2219                 irq = irq_map[idx];
2220                 if (!irq) {
2221                         dev_err(dev, "irq init: fail map phy interrupt %d\n",
2222                                 idx);
2223                         return -ENOENT;
2224                 }
2225
2226                 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
2227                                       DRV_NAME " sata", phy);
2228                 if (rc) {
2229                         dev_err(dev, "irq init: could not request "
2230                                 "sata interrupt %d, rc=%d\n",
2231                                 irq, rc);
2232                         return -ENOENT;
2233                 }
2234         }
2235
2236         for (i = 0; i < hisi_hba->queue_count; i++) {
2237                 int idx = i + 96; /* First cq interrupt is irq96 */
2238
2239                 irq = irq_map[idx];
2240                 if (!irq) {
2241                         dev_err(dev,
2242                                 "irq init: could not map cq interrupt %d\n",
2243                                 idx);
2244                         return -ENOENT;
2245                 }
2246                 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0,
2247                                       DRV_NAME " cq", &hisi_hba->cq[i]);
2248                 if (rc) {
2249                         dev_err(dev,
2250                                 "irq init: could not request cq interrupt %d, rc=%d\n",
2251                                 irq, rc);
2252                         return -ENOENT;
2253                 }
2254         }
2255
2256         return 0;
2257 }
2258
2259 static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
2260 {
2261         int rc;
2262
2263         rc = hw_init_v2_hw(hisi_hba);
2264         if (rc)
2265                 return rc;
2266
2267         rc = interrupt_init_v2_hw(hisi_hba);
2268         if (rc)
2269                 return rc;
2270
2271         phys_init_v2_hw(hisi_hba);
2272
2273         return 0;
2274 }
2275
2276 static const struct hisi_sas_hw hisi_sas_v2_hw = {
2277         .hw_init = hisi_sas_v2_init,
2278         .setup_itct = setup_itct_v2_hw,
2279         .slot_index_alloc = slot_index_alloc_quirk_v2_hw,
2280         .alloc_dev = alloc_dev_quirk_v2_hw,
2281         .sl_notify = sl_notify_v2_hw,
2282         .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
2283         .free_device = free_device_v2_hw,
2284         .prep_smp = prep_smp_v2_hw,
2285         .prep_ssp = prep_ssp_v2_hw,
2286         .prep_stp = prep_ata_v2_hw,
2287         .prep_abort = prep_abort_v2_hw,
2288         .get_free_slot = get_free_slot_v2_hw,
2289         .start_delivery = start_delivery_v2_hw,
2290         .slot_complete = slot_complete_v2_hw,
2291         .phy_enable = enable_phy_v2_hw,
2292         .phy_disable = disable_phy_v2_hw,
2293         .phy_hard_reset = phy_hard_reset_v2_hw,
2294         .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
2295         .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
2296 };
2297
2298 static int hisi_sas_v2_probe(struct platform_device *pdev)
2299 {
2300         return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
2301 }
2302
2303 static int hisi_sas_v2_remove(struct platform_device *pdev)
2304 {
2305         return hisi_sas_remove(pdev);
2306 }
2307
2308 static const struct of_device_id sas_v2_of_match[] = {
2309         { .compatible = "hisilicon,hip06-sas-v2",},
2310         {},
2311 };
2312 MODULE_DEVICE_TABLE(of, sas_v2_of_match);
2313
2314 static const struct acpi_device_id sas_v2_acpi_match[] = {
2315         { "HISI0162", 0 },
2316         { }
2317 };
2318
2319 MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match);
2320
2321 static struct platform_driver hisi_sas_v2_driver = {
2322         .probe = hisi_sas_v2_probe,
2323         .remove = hisi_sas_v2_remove,
2324         .driver = {
2325                 .name = DRV_NAME,
2326                 .of_match_table = sas_v2_of_match,
2327                 .acpi_match_table = ACPI_PTR(sas_v2_acpi_match),
2328         },
2329 };
2330
2331 module_platform_driver(hisi_sas_v2_driver);
2332
2333 MODULE_LICENSE("GPL");
2334 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
2335 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
2336 MODULE_ALIAS("platform:" DRV_NAME);