drivers/scsi/lpfc/lpfc_hw4.h

   1 /*******************************************************************
   2  * This file is part of the Emulex Linux Device Driver for         *
   3  * Fibre Channel Host Bus Adapters.                                *
   4  * Copyright (C) 2017-2019 Broadcom. All Rights Reserved. The term *
   5  * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries.  *
   6  * Copyright (C) 2009-2016 Emulex.  All rights reserved.           *
   7  * EMULEX and SLI are trademarks of Emulex.                        *
   8  * www.broadcom.com                                                *
   9  *                                                                 *
  10  * This program is free software; you can redistribute it and/or   *
  11  * modify it under the terms of version 2 of the GNU General       *
  12  * Public License as published by the Free Software Foundation.    *
  13  * This program is distributed in the hope that it will be useful. *
  14  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  15  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  16  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  17  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  18  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  19  * more details, a copy of which can be found in the file COPYING  *
  20  * included with this package.                                     *
  21  *******************************************************************/
  22
  23 /* Macros to deal with bit fields. Each bit field must have 3 #defines
  24  * associated with it (_SHIFT, _MASK, and _WORD).
  25  * EG. For a bit field that is in the 7th bit of the "field4" field of a
  26  * structure and is 2 bits in size the following #defines must exist:
  27  *      struct temp {
  28  *              uint32_t        field1;
  29  *              uint32_t        field2;
  30  *              uint32_t        field3;
  31  *              uint32_t        field4;
  32  *      #define example_bit_field_SHIFT         7
  33  *      #define example_bit_field_MASK          0x03
  34  *      #define example_bit_field_WORD          field4
  35  *              uint32_t        field5;
  36  *      };
  37  * Then the macros below may be used to get or set the value of that field.
  38  * EG. To get the value of the bit field from the above example:
  39  *      struct temp t1;
  40  *      value = bf_get(example_bit_field, &t1);
  41  * And then to set that bit field:
  42  *      bf_set(example_bit_field, &t1, 2);
  43  * Or clear that bit field:
  44  *      bf_set(example_bit_field, &t1, 0);
  45  */
  46 #define bf_get_be32(name, ptr) \
  47         ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
  48 #define bf_get_le32(name, ptr) \
  49         ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
  50 #define bf_get(name, ptr) \
  51         (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK)
  52 #define bf_set_le32(name, ptr, value) \
  53         ((ptr)->name##_WORD = cpu_to_le32(((((value) & \
  54         name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \
  55         ~(name##_MASK << name##_SHIFT)))))
  56 #define bf_set(name, ptr, value) \
  57         ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \
  58                  ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT))))
  59
  60 struct dma_address {
  61         uint32_t addr_lo;
  62         uint32_t addr_hi;
  63 };
  64
  65 struct lpfc_sli_intf {
  66         uint32_t word0;
  67 #define lpfc_sli_intf_valid_SHIFT               29
  68 #define lpfc_sli_intf_valid_MASK                0x00000007
  69 #define lpfc_sli_intf_valid_WORD                word0
  70 #define LPFC_SLI_INTF_VALID             6
  71 #define lpfc_sli_intf_sli_hint2_SHIFT           24
  72 #define lpfc_sli_intf_sli_hint2_MASK            0x0000001F
  73 #define lpfc_sli_intf_sli_hint2_WORD            word0
  74 #define LPFC_SLI_INTF_SLI_HINT2_NONE    0
  75 #define lpfc_sli_intf_sli_hint1_SHIFT           16
  76 #define lpfc_sli_intf_sli_hint1_MASK            0x000000FF
  77 #define lpfc_sli_intf_sli_hint1_WORD            word0
  78 #define LPFC_SLI_INTF_SLI_HINT1_NONE    0
  79 #define LPFC_SLI_INTF_SLI_HINT1_1       1
  80 #define LPFC_SLI_INTF_SLI_HINT1_2       2
  81 #define lpfc_sli_intf_if_type_SHIFT             12
  82 #define lpfc_sli_intf_if_type_MASK              0x0000000F
  83 #define lpfc_sli_intf_if_type_WORD              word0
  84 #define LPFC_SLI_INTF_IF_TYPE_0         0
  85 #define LPFC_SLI_INTF_IF_TYPE_1         1
  86 #define LPFC_SLI_INTF_IF_TYPE_2         2
  87 #define LPFC_SLI_INTF_IF_TYPE_6         6
  88 #define lpfc_sli_intf_sli_family_SHIFT          8
  89 #define lpfc_sli_intf_sli_family_MASK           0x0000000F
  90 #define lpfc_sli_intf_sli_family_WORD           word0
  91 #define LPFC_SLI_INTF_FAMILY_BE2        0x0
  92 #define LPFC_SLI_INTF_FAMILY_BE3        0x1
  93 #define LPFC_SLI_INTF_FAMILY_LNCR_A0    0xa
  94 #define LPFC_SLI_INTF_FAMILY_LNCR_B0    0xb
  95 #define lpfc_sli_intf_slirev_SHIFT              4
  96 #define lpfc_sli_intf_slirev_MASK               0x0000000F
  97 #define lpfc_sli_intf_slirev_WORD               word0
  98 #define LPFC_SLI_INTF_REV_SLI3          3
  99 #define LPFC_SLI_INTF_REV_SLI4          4
 100 #define lpfc_sli_intf_func_type_SHIFT           0
 101 #define lpfc_sli_intf_func_type_MASK            0x00000001
 102 #define lpfc_sli_intf_func_type_WORD            word0
 103 #define LPFC_SLI_INTF_IF_TYPE_PHYS      0
 104 #define LPFC_SLI_INTF_IF_TYPE_VIRT      1
 105 };
 106
 107 #define LPFC_SLI4_MBX_EMBED     true
 108 #define LPFC_SLI4_MBX_NEMBED    false
 109
 110 #define LPFC_SLI4_MB_WORD_COUNT         64
 111 #define LPFC_MAX_MQ_PAGE                8
 112 #define LPFC_MAX_WQ_PAGE_V0             4
 113 #define LPFC_MAX_WQ_PAGE                8
 114 #define LPFC_MAX_RQ_PAGE                8
 115 #define LPFC_MAX_CQ_PAGE                4
 116 #define LPFC_MAX_EQ_PAGE                8
 117
 118 #define LPFC_VIR_FUNC_MAX       32 /* Maximum number of virtual functions */
 119 #define LPFC_PCI_FUNC_MAX        5 /* Maximum number of PCI functions */
 120 #define LPFC_VFR_PAGE_SIZE      0x1000 /* 4KB BAR2 per-VF register page size */
 121
 122 /* Define SLI4 Alignment requirements. */
 123 #define LPFC_ALIGN_16_BYTE      16
 124 #define LPFC_ALIGN_64_BYTE      64
 125
 126 /* Define SLI4 specific definitions. */
 127 #define LPFC_MQ_CQE_BYTE_OFFSET 256
 128 #define LPFC_MBX_CMD_HDR_LENGTH 16
 129 #define LPFC_MBX_ERROR_RANGE    0x4000
 130 #define LPFC_BMBX_BIT1_ADDR_HI  0x2
 131 #define LPFC_BMBX_BIT1_ADDR_LO  0
 132 #define LPFC_RPI_HDR_COUNT      64
 133 #define LPFC_HDR_TEMPLATE_SIZE  4096
 134 #define LPFC_RPI_ALLOC_ERROR    0xFFFF
 135 #define LPFC_FCF_RECORD_WD_CNT  132
 136 #define LPFC_ENTIRE_FCF_DATABASE 0
 137 #define LPFC_DFLT_FCF_INDEX      0
 138
 139 /* Virtual function numbers */
 140 #define LPFC_VF0                0
 141 #define LPFC_VF1                1
 142 #define LPFC_VF2                2
 143 #define LPFC_VF3                3
 144 #define LPFC_VF4                4
 145 #define LPFC_VF5                5
 146 #define LPFC_VF6                6
 147 #define LPFC_VF7                7
 148 #define LPFC_VF8                8
 149 #define LPFC_VF9                9
 150 #define LPFC_VF10               10
 151 #define LPFC_VF11               11
 152 #define LPFC_VF12               12
 153 #define LPFC_VF13               13
 154 #define LPFC_VF14               14
 155 #define LPFC_VF15               15
 156 #define LPFC_VF16               16
 157 #define LPFC_VF17               17
 158 #define LPFC_VF18               18
 159 #define LPFC_VF19               19
 160 #define LPFC_VF20               20
 161 #define LPFC_VF21               21
 162 #define LPFC_VF22               22
 163 #define LPFC_VF23               23
 164 #define LPFC_VF24               24
 165 #define LPFC_VF25               25
 166 #define LPFC_VF26               26
 167 #define LPFC_VF27               27
 168 #define LPFC_VF28               28
 169 #define LPFC_VF29               29
 170 #define LPFC_VF30               30
 171 #define LPFC_VF31               31
 172
 173 /* PCI function numbers */
 174 #define LPFC_PCI_FUNC0          0
 175 #define LPFC_PCI_FUNC1          1
 176 #define LPFC_PCI_FUNC2          2
 177 #define LPFC_PCI_FUNC3          3
 178 #define LPFC_PCI_FUNC4          4
 179
 180 /* SLI4 interface type-2 PDEV_CTL register */
 181 #define LPFC_CTL_PDEV_CTL_OFFSET        0x414
 182 #define LPFC_CTL_PDEV_CTL_DRST          0x00000001
 183 #define LPFC_CTL_PDEV_CTL_FRST          0x00000002
 184 #define LPFC_CTL_PDEV_CTL_DD            0x00000004
 185 #define LPFC_CTL_PDEV_CTL_LC            0x00000008
 186 #define LPFC_CTL_PDEV_CTL_FRL_ALL       0x00
 187 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE   0x10
 188 #define LPFC_CTL_PDEV_CTL_FRL_NIC       0x20
 189 #define LPFC_CTL_PDEV_CTL_DDL_RAS       0x1000000
 190
 191 #define LPFC_FW_DUMP_REQUEST    (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST)
 192
 193 /* Active interrupt test count */
 194 #define LPFC_ACT_INTR_CNT       4
 195
 196 /* Algrithmns for scheduling FCP commands to WQs */
 197 #define LPFC_FCP_SCHED_BY_HDWQ          0
 198 #define LPFC_FCP_SCHED_BY_CPU           1
 199
 200 /* Algrithmns for NameServer Query after RSCN */
 201 #define LPFC_NS_QUERY_GID_FT    0
 202 #define LPFC_NS_QUERY_GID_PT    1
 203
 204 /* Delay Multiplier constant */
 205 #define LPFC_DMULT_CONST       651042
 206 #define LPFC_DMULT_MAX         1023
 207
 208 /* Configuration of Interrupts / sec for entire HBA port */
 209 #define LPFC_MIN_IMAX          5000
 210 #define LPFC_MAX_IMAX          5000000
 211 #define LPFC_DEF_IMAX          0
 212
 213 #define LPFC_MAX_AUTO_EQ_DELAY 120
 214 #define LPFC_EQ_DELAY_STEP     15
 215 #define LPFC_EQD_ISR_TRIGGER   20000
 216 /* 1s intervals */
 217 #define LPFC_EQ_DELAY_MSECS    1000
 218
 219 #define LPFC_MIN_CPU_MAP       0
 220 #define LPFC_MAX_CPU_MAP       1
 221 #define LPFC_HBA_CPU_MAP       1
 222
 223 /* PORT_CAPABILITIES constants. */
 224 #define LPFC_MAX_SUPPORTED_PAGES        8
 225
 226 struct ulp_bde64 {
 227         union ULP_BDE_TUS {
 228                 uint32_t w;
 229                 struct {
 230 #ifdef __BIG_ENDIAN_BITFIELD
 231                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
 232                                                    VALUE !! */
 233                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
 234 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 235                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
 236                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
 237                                                    VALUE !! */
 238 #endif
 239 #define BUFF_TYPE_BDE_64    0x00        /* BDE (Host_resident) */
 240 #define BUFF_TYPE_BDE_IMMED 0x01        /* Immediate Data BDE */
 241 #define BUFF_TYPE_BDE_64P   0x02        /* BDE (Port-resident) */
 242 #define BUFF_TYPE_BDE_64I   0x08        /* Input BDE (Host-resident) */
 243 #define BUFF_TYPE_BDE_64IP  0x0A        /* Input BDE (Port-resident) */
 244 #define BUFF_TYPE_BLP_64    0x40        /* BLP (Host-resident) */
 245 #define BUFF_TYPE_BLP_64P   0x42        /* BLP (Port-resident) */
 246                 } f;
 247         } tus;
 248         uint32_t addrLow;
 249         uint32_t addrHigh;
 250 };
 251
 252 /* Maximun size of immediate data that can fit into a 128 byte WQE */
 253 #define LPFC_MAX_BDE_IMM_SIZE   64
 254
 255 struct lpfc_sli4_flags {
 256         uint32_t word0;
 257 #define lpfc_idx_rsrc_rdy_SHIFT         0
 258 #define lpfc_idx_rsrc_rdy_MASK          0x00000001
 259 #define lpfc_idx_rsrc_rdy_WORD          word0
 260 #define LPFC_IDX_RSRC_RDY               1
 261 #define lpfc_rpi_rsrc_rdy_SHIFT         1
 262 #define lpfc_rpi_rsrc_rdy_MASK          0x00000001
 263 #define lpfc_rpi_rsrc_rdy_WORD          word0
 264 #define LPFC_RPI_RSRC_RDY               1
 265 #define lpfc_vpi_rsrc_rdy_SHIFT         2
 266 #define lpfc_vpi_rsrc_rdy_MASK          0x00000001
 267 #define lpfc_vpi_rsrc_rdy_WORD          word0
 268 #define LPFC_VPI_RSRC_RDY               1
 269 #define lpfc_vfi_rsrc_rdy_SHIFT         3
 270 #define lpfc_vfi_rsrc_rdy_MASK          0x00000001
 271 #define lpfc_vfi_rsrc_rdy_WORD          word0
 272 #define LPFC_VFI_RSRC_RDY               1
 273 };
 274
 275 struct sli4_bls_rsp {
 276         uint32_t word0_rsvd;      /* Word0 must be reserved */
 277         uint32_t word1;
 278 #define lpfc_abts_orig_SHIFT      0
 279 #define lpfc_abts_orig_MASK       0x00000001
 280 #define lpfc_abts_orig_WORD       word1
 281 #define LPFC_ABTS_UNSOL_RSP       1
 282 #define LPFC_ABTS_UNSOL_INT       0
 283         uint32_t word2;
 284 #define lpfc_abts_rxid_SHIFT      0
 285 #define lpfc_abts_rxid_MASK       0x0000FFFF
 286 #define lpfc_abts_rxid_WORD       word2
 287 #define lpfc_abts_oxid_SHIFT      16
 288 #define lpfc_abts_oxid_MASK       0x0000FFFF
 289 #define lpfc_abts_oxid_WORD       word2
 290         uint32_t word3;
 291 #define lpfc_vndr_code_SHIFT    0
 292 #define lpfc_vndr_code_MASK     0x000000FF
 293 #define lpfc_vndr_code_WORD     word3
 294 #define lpfc_rsn_expln_SHIFT    8
 295 #define lpfc_rsn_expln_MASK     0x000000FF
 296 #define lpfc_rsn_expln_WORD     word3
 297 #define lpfc_rsn_code_SHIFT     16
 298 #define lpfc_rsn_code_MASK      0x000000FF
 299 #define lpfc_rsn_code_WORD      word3
 300
 301         uint32_t word4;
 302         uint32_t word5_rsvd;    /* Word5 must be reserved */
 303 };
 304
 305 /* event queue entry structure */
 306 struct lpfc_eqe {
 307         uint32_t word0;
 308 #define lpfc_eqe_resource_id_SHIFT      16
 309 #define lpfc_eqe_resource_id_MASK       0x0000FFFF
 310 #define lpfc_eqe_resource_id_WORD       word0
 311 #define lpfc_eqe_minor_code_SHIFT       4
 312 #define lpfc_eqe_minor_code_MASK        0x00000FFF
 313 #define lpfc_eqe_minor_code_WORD        word0
 314 #define lpfc_eqe_major_code_SHIFT       1
 315 #define lpfc_eqe_major_code_MASK        0x00000007
 316 #define lpfc_eqe_major_code_WORD        word0
 317 #define lpfc_eqe_valid_SHIFT            0
 318 #define lpfc_eqe_valid_MASK             0x00000001
 319 #define lpfc_eqe_valid_WORD             word0
 320 };
 321
 322 /* completion queue entry structure (common fields for all cqe types) */
 323 struct lpfc_cqe {
 324         uint32_t reserved0;
 325         uint32_t reserved1;
 326         uint32_t reserved2;
 327         uint32_t word3;
 328 #define lpfc_cqe_valid_SHIFT            31
 329 #define lpfc_cqe_valid_MASK             0x00000001
 330 #define lpfc_cqe_valid_WORD             word3
 331 #define lpfc_cqe_code_SHIFT             16
 332 #define lpfc_cqe_code_MASK              0x000000FF
 333 #define lpfc_cqe_code_WORD              word3
 334 };
 335
 336 /* Completion Queue Entry Status Codes */
 337 #define CQE_STATUS_SUCCESS              0x0
 338 #define CQE_STATUS_FCP_RSP_FAILURE      0x1
 339 #define CQE_STATUS_REMOTE_STOP          0x2
 340 #define CQE_STATUS_LOCAL_REJECT         0x3
 341 #define CQE_STATUS_NPORT_RJT            0x4
 342 #define CQE_STATUS_FABRIC_RJT           0x5
 343 #define CQE_STATUS_NPORT_BSY            0x6
 344 #define CQE_STATUS_FABRIC_BSY           0x7
 345 #define CQE_STATUS_INTERMED_RSP         0x8
 346 #define CQE_STATUS_LS_RJT               0x9
 347 #define CQE_STATUS_CMD_REJECT           0xb
 348 #define CQE_STATUS_FCP_TGT_LENCHECK     0xc
 349 #define CQE_STATUS_NEED_BUFF_ENTRY      0xf
 350 #define CQE_STATUS_DI_ERROR             0x16
 351
 352 /* Used when mapping CQE status to IOCB */
 353 #define LPFC_IOCB_STATUS_MASK           0xf
 354
 355 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */
 356 #define CQE_HW_STATUS_NO_ERR            0x0
 357 #define CQE_HW_STATUS_UNDERRUN          0x1
 358 #define CQE_HW_STATUS_OVERRUN           0x2
 359
 360 /* Completion Queue Entry Codes */
 361 #define CQE_CODE_COMPL_WQE              0x1
 362 #define CQE_CODE_RELEASE_WQE            0x2
 363 #define CQE_CODE_RECEIVE                0x4
 364 #define CQE_CODE_XRI_ABORTED            0x5
 365 #define CQE_CODE_RECEIVE_V1             0x9
 366 #define CQE_CODE_NVME_ERSP              0xd
 367
 368 /*
 369  * Define mask value for xri_aborted and wcqe completed CQE extended status.
 370  * Currently, extended status is limited to 9 bits (0x0 -> 0x103) .
 371  */
 372 #define WCQE_PARAM_MASK         0x1FF
 373
 374 /* completion queue entry for wqe completions */
 375 struct lpfc_wcqe_complete {
 376         uint32_t word0;
 377 #define lpfc_wcqe_c_request_tag_SHIFT   16
 378 #define lpfc_wcqe_c_request_tag_MASK    0x0000FFFF
 379 #define lpfc_wcqe_c_request_tag_WORD    word0
 380 #define lpfc_wcqe_c_status_SHIFT        8
 381 #define lpfc_wcqe_c_status_MASK         0x000000FF
 382 #define lpfc_wcqe_c_status_WORD         word0
 383 #define lpfc_wcqe_c_hw_status_SHIFT     0
 384 #define lpfc_wcqe_c_hw_status_MASK      0x000000FF
 385 #define lpfc_wcqe_c_hw_status_WORD      word0
 386 #define lpfc_wcqe_c_ersp0_SHIFT         0
 387 #define lpfc_wcqe_c_ersp0_MASK          0x0000FFFF
 388 #define lpfc_wcqe_c_ersp0_WORD          word0
 389         uint32_t total_data_placed;
 390         uint32_t parameter;
 391 #define lpfc_wcqe_c_bg_edir_SHIFT       5
 392 #define lpfc_wcqe_c_bg_edir_MASK        0x00000001
 393 #define lpfc_wcqe_c_bg_edir_WORD        parameter
 394 #define lpfc_wcqe_c_bg_tdpv_SHIFT       3
 395 #define lpfc_wcqe_c_bg_tdpv_MASK        0x00000001
 396 #define lpfc_wcqe_c_bg_tdpv_WORD        parameter
 397 #define lpfc_wcqe_c_bg_re_SHIFT         2
 398 #define lpfc_wcqe_c_bg_re_MASK          0x00000001
 399 #define lpfc_wcqe_c_bg_re_WORD          parameter
 400 #define lpfc_wcqe_c_bg_ae_SHIFT         1
 401 #define lpfc_wcqe_c_bg_ae_MASK          0x00000001
 402 #define lpfc_wcqe_c_bg_ae_WORD          parameter
 403 #define lpfc_wcqe_c_bg_ge_SHIFT         0
 404 #define lpfc_wcqe_c_bg_ge_MASK          0x00000001
 405 #define lpfc_wcqe_c_bg_ge_WORD          parameter
 406         uint32_t word3;
 407 #define lpfc_wcqe_c_valid_SHIFT         lpfc_cqe_valid_SHIFT
 408 #define lpfc_wcqe_c_valid_MASK          lpfc_cqe_valid_MASK
 409 #define lpfc_wcqe_c_valid_WORD          lpfc_cqe_valid_WORD
 410 #define lpfc_wcqe_c_xb_SHIFT            28
 411 #define lpfc_wcqe_c_xb_MASK             0x00000001
 412 #define lpfc_wcqe_c_xb_WORD             word3
 413 #define lpfc_wcqe_c_pv_SHIFT            27
 414 #define lpfc_wcqe_c_pv_MASK             0x00000001
 415 #define lpfc_wcqe_c_pv_WORD             word3
 416 #define lpfc_wcqe_c_priority_SHIFT      24
 417 #define lpfc_wcqe_c_priority_MASK       0x00000007
 418 #define lpfc_wcqe_c_priority_WORD       word3
 419 #define lpfc_wcqe_c_code_SHIFT          lpfc_cqe_code_SHIFT
 420 #define lpfc_wcqe_c_code_MASK           lpfc_cqe_code_MASK
 421 #define lpfc_wcqe_c_code_WORD           lpfc_cqe_code_WORD
 422 #define lpfc_wcqe_c_sqhead_SHIFT        0
 423 #define lpfc_wcqe_c_sqhead_MASK         0x0000FFFF
 424 #define lpfc_wcqe_c_sqhead_WORD         word3
 425 };
 426
 427 /* completion queue entry for wqe release */
 428 struct lpfc_wcqe_release {
 429         uint32_t reserved0;
 430         uint32_t reserved1;
 431         uint32_t word2;
 432 #define lpfc_wcqe_r_wq_id_SHIFT         16
 433 #define lpfc_wcqe_r_wq_id_MASK          0x0000FFFF
 434 #define lpfc_wcqe_r_wq_id_WORD          word2
 435 #define lpfc_wcqe_r_wqe_index_SHIFT     0
 436 #define lpfc_wcqe_r_wqe_index_MASK      0x0000FFFF
 437 #define lpfc_wcqe_r_wqe_index_WORD      word2
 438         uint32_t word3;
 439 #define lpfc_wcqe_r_valid_SHIFT         lpfc_cqe_valid_SHIFT
 440 #define lpfc_wcqe_r_valid_MASK          lpfc_cqe_valid_MASK
 441 #define lpfc_wcqe_r_valid_WORD          lpfc_cqe_valid_WORD
 442 #define lpfc_wcqe_r_code_SHIFT          lpfc_cqe_code_SHIFT
 443 #define lpfc_wcqe_r_code_MASK           lpfc_cqe_code_MASK
 444 #define lpfc_wcqe_r_code_WORD           lpfc_cqe_code_WORD
 445 };
 446
 447 struct sli4_wcqe_xri_aborted {
 448         uint32_t word0;
 449 #define lpfc_wcqe_xa_status_SHIFT               8
 450 #define lpfc_wcqe_xa_status_MASK                0x000000FF
 451 #define lpfc_wcqe_xa_status_WORD                word0
 452         uint32_t parameter;
 453         uint32_t word2;
 454 #define lpfc_wcqe_xa_remote_xid_SHIFT   16
 455 #define lpfc_wcqe_xa_remote_xid_MASK    0x0000FFFF
 456 #define lpfc_wcqe_xa_remote_xid_WORD    word2
 457 #define lpfc_wcqe_xa_xri_SHIFT          0
 458 #define lpfc_wcqe_xa_xri_MASK           0x0000FFFF
 459 #define lpfc_wcqe_xa_xri_WORD           word2
 460         uint32_t word3;
 461 #define lpfc_wcqe_xa_valid_SHIFT        lpfc_cqe_valid_SHIFT
 462 #define lpfc_wcqe_xa_valid_MASK         lpfc_cqe_valid_MASK
 463 #define lpfc_wcqe_xa_valid_WORD         lpfc_cqe_valid_WORD
 464 #define lpfc_wcqe_xa_ia_SHIFT           30
 465 #define lpfc_wcqe_xa_ia_MASK            0x00000001
 466 #define lpfc_wcqe_xa_ia_WORD            word3
 467 #define CQE_XRI_ABORTED_IA_REMOTE       0
 468 #define CQE_XRI_ABORTED_IA_LOCAL        1
 469 #define lpfc_wcqe_xa_br_SHIFT           29
 470 #define lpfc_wcqe_xa_br_MASK            0x00000001
 471 #define lpfc_wcqe_xa_br_WORD            word3
 472 #define CQE_XRI_ABORTED_BR_BA_ACC       0
 473 #define CQE_XRI_ABORTED_BR_BA_RJT       1
 474 #define lpfc_wcqe_xa_eo_SHIFT           28
 475 #define lpfc_wcqe_xa_eo_MASK            0x00000001
 476 #define lpfc_wcqe_xa_eo_WORD            word3
 477 #define CQE_XRI_ABORTED_EO_REMOTE       0
 478 #define CQE_XRI_ABORTED_EO_LOCAL        1
 479 #define lpfc_wcqe_xa_code_SHIFT         lpfc_cqe_code_SHIFT
 480 #define lpfc_wcqe_xa_code_MASK          lpfc_cqe_code_MASK
 481 #define lpfc_wcqe_xa_code_WORD          lpfc_cqe_code_WORD
 482 };
 483
 484 /* completion queue entry structure for rqe completion */
 485 struct lpfc_rcqe {
 486         uint32_t word0;
 487 #define lpfc_rcqe_bindex_SHIFT          16
 488 #define lpfc_rcqe_bindex_MASK           0x0000FFF
 489 #define lpfc_rcqe_bindex_WORD           word0
 490 #define lpfc_rcqe_status_SHIFT          8
 491 #define lpfc_rcqe_status_MASK           0x000000FF
 492 #define lpfc_rcqe_status_WORD           word0
 493 #define FC_STATUS_RQ_SUCCESS            0x10 /* Async receive successful */
 494 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED   0x11 /* payload truncated */
 495 #define FC_STATUS_INSUFF_BUF_NEED_BUF   0x12 /* Insufficient buffers */
 496 #define FC_STATUS_INSUFF_BUF_FRM_DISC   0x13 /* Frame Discard */
 497         uint32_t word1;
 498 #define lpfc_rcqe_fcf_id_v1_SHIFT       0
 499 #define lpfc_rcqe_fcf_id_v1_MASK        0x0000003F
 500 #define lpfc_rcqe_fcf_id_v1_WORD        word1
 501         uint32_t word2;
 502 #define lpfc_rcqe_length_SHIFT          16
 503 #define lpfc_rcqe_length_MASK           0x0000FFFF
 504 #define lpfc_rcqe_length_WORD           word2
 505 #define lpfc_rcqe_rq_id_SHIFT           6
 506 #define lpfc_rcqe_rq_id_MASK            0x000003FF
 507 #define lpfc_rcqe_rq_id_WORD            word2
 508 #define lpfc_rcqe_fcf_id_SHIFT          0
 509 #define lpfc_rcqe_fcf_id_MASK           0x0000003F
 510 #define lpfc_rcqe_fcf_id_WORD           word2
 511 #define lpfc_rcqe_rq_id_v1_SHIFT        0
 512 #define lpfc_rcqe_rq_id_v1_MASK         0x0000FFFF
 513 #define lpfc_rcqe_rq_id_v1_WORD         word2
 514         uint32_t word3;
 515 #define lpfc_rcqe_valid_SHIFT           lpfc_cqe_valid_SHIFT
 516 #define lpfc_rcqe_valid_MASK            lpfc_cqe_valid_MASK
 517 #define lpfc_rcqe_valid_WORD            lpfc_cqe_valid_WORD
 518 #define lpfc_rcqe_port_SHIFT            30
 519 #define lpfc_rcqe_port_MASK             0x00000001
 520 #define lpfc_rcqe_port_WORD             word3
 521 #define lpfc_rcqe_hdr_length_SHIFT      24
 522 #define lpfc_rcqe_hdr_length_MASK       0x0000001F
 523 #define lpfc_rcqe_hdr_length_WORD       word3
 524 #define lpfc_rcqe_code_SHIFT            lpfc_cqe_code_SHIFT
 525 #define lpfc_rcqe_code_MASK             lpfc_cqe_code_MASK
 526 #define lpfc_rcqe_code_WORD             lpfc_cqe_code_WORD
 527 #define lpfc_rcqe_eof_SHIFT             8
 528 #define lpfc_rcqe_eof_MASK              0x000000FF
 529 #define lpfc_rcqe_eof_WORD              word3
 530 #define FCOE_EOFn       0x41
 531 #define FCOE_EOFt       0x42
 532 #define FCOE_EOFni      0x49
 533 #define FCOE_EOFa       0x50
 534 #define lpfc_rcqe_sof_SHIFT             0
 535 #define lpfc_rcqe_sof_MASK              0x000000FF
 536 #define lpfc_rcqe_sof_WORD              word3
 537 #define FCOE_SOFi2      0x2d
 538 #define FCOE_SOFi3      0x2e
 539 #define FCOE_SOFn2      0x35
 540 #define FCOE_SOFn3      0x36
 541 };
 542
 543 struct lpfc_rqe {
 544         uint32_t address_hi;
 545         uint32_t address_lo;
 546 };
 547
 548 /* buffer descriptors */
 549 struct lpfc_bde4 {
 550         uint32_t addr_hi;
 551         uint32_t addr_lo;
 552         uint32_t word2;
 553 #define lpfc_bde4_last_SHIFT            31
 554 #define lpfc_bde4_last_MASK             0x00000001
 555 #define lpfc_bde4_last_WORD             word2
 556 #define lpfc_bde4_sge_offset_SHIFT      0
 557 #define lpfc_bde4_sge_offset_MASK       0x000003FF
 558 #define lpfc_bde4_sge_offset_WORD       word2
 559         uint32_t word3;
 560 #define lpfc_bde4_length_SHIFT          0
 561 #define lpfc_bde4_length_MASK           0x000000FF
 562 #define lpfc_bde4_length_WORD           word3
 563 };
 564
 565 struct lpfc_register {
 566         uint32_t word0;
 567 };
 568
 569 #define LPFC_PORT_SEM_UE_RECOVERABLE    0xE000
 570 #define LPFC_PORT_SEM_MASK              0xF000
 571 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */
 572 #define LPFC_UERR_STATUS_HI             0x00A4
 573 #define LPFC_UERR_STATUS_LO             0x00A0
 574 #define LPFC_UE_MASK_HI                 0x00AC
 575 #define LPFC_UE_MASK_LO                 0x00A8
 576
 577 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */
 578 #define LPFC_SLI_INTF                   0x0058
 579 #define LPFC_SLI_ASIC_VER               0x009C
 580
 581 #define LPFC_CTL_PORT_SEM_OFFSET        0x400
 582 #define lpfc_port_smphr_perr_SHIFT      31
 583 #define lpfc_port_smphr_perr_MASK       0x1
 584 #define lpfc_port_smphr_perr_WORD       word0
 585 #define lpfc_port_smphr_sfi_SHIFT       30
 586 #define lpfc_port_smphr_sfi_MASK        0x1
 587 #define lpfc_port_smphr_sfi_WORD        word0
 588 #define lpfc_port_smphr_nip_SHIFT       29
 589 #define lpfc_port_smphr_nip_MASK        0x1
 590 #define lpfc_port_smphr_nip_WORD        word0
 591 #define lpfc_port_smphr_ipc_SHIFT       28
 592 #define lpfc_port_smphr_ipc_MASK        0x1
 593 #define lpfc_port_smphr_ipc_WORD        word0
 594 #define lpfc_port_smphr_scr1_SHIFT      27
 595 #define lpfc_port_smphr_scr1_MASK       0x1
 596 #define lpfc_port_smphr_scr1_WORD       word0
 597 #define lpfc_port_smphr_scr2_SHIFT      26
 598 #define lpfc_port_smphr_scr2_MASK       0x1
 599 #define lpfc_port_smphr_scr2_WORD       word0
 600 #define lpfc_port_smphr_host_scratch_SHIFT      16
 601 #define lpfc_port_smphr_host_scratch_MASK       0xFF
 602 #define lpfc_port_smphr_host_scratch_WORD       word0
 603 #define lpfc_port_smphr_port_status_SHIFT       0
 604 #define lpfc_port_smphr_port_status_MASK        0xFFFF
 605 #define lpfc_port_smphr_port_status_WORD        word0
 606
 607 #define LPFC_POST_STAGE_POWER_ON_RESET                  0x0000
 608 #define LPFC_POST_STAGE_AWAITING_HOST_RDY               0x0001
 609 #define LPFC_POST_STAGE_HOST_RDY                        0x0002
 610 #define LPFC_POST_STAGE_BE_RESET                        0x0003
 611 #define LPFC_POST_STAGE_SEEPROM_CS_START                0x0100
 612 #define LPFC_POST_STAGE_SEEPROM_CS_DONE                 0x0101
 613 #define LPFC_POST_STAGE_DDR_CONFIG_START                0x0200
 614 #define LPFC_POST_STAGE_DDR_CONFIG_DONE                 0x0201
 615 #define LPFC_POST_STAGE_DDR_CALIBRATE_START             0x0300
 616 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE              0x0301
 617 #define LPFC_POST_STAGE_DDR_TEST_START                  0x0400
 618 #define LPFC_POST_STAGE_DDR_TEST_DONE                   0x0401
 619 #define LPFC_POST_STAGE_REDBOOT_INIT_START              0x0600
 620 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE               0x0601
 621 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START             0x0700
 622 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE              0x0701
 623 #define LPFC_POST_STAGE_ARMFW_START                     0x0800
 624 #define LPFC_POST_STAGE_DHCP_QUERY_START                0x0900
 625 #define LPFC_POST_STAGE_DHCP_QUERY_DONE                 0x0901
 626 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START     0x0A00
 627 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE      0x0A01
 628 #define LPFC_POST_STAGE_RC_OPTION_SET                   0x0B00
 629 #define LPFC_POST_STAGE_SWITCH_LINK                     0x0B01
 630 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE               0x0B02
 631 #define LPFC_POST_STAGE_PERFROM_TFTP                    0x0B03
 632 #define LPFC_POST_STAGE_PARSE_XML                       0x0B04
 633 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE                  0x0B05
 634 #define LPFC_POST_STAGE_FLASH_IMAGE                     0x0B06
 635 #define LPFC_POST_STAGE_RC_DONE                         0x0B07
 636 #define LPFC_POST_STAGE_REBOOT_SYSTEM                   0x0B08
 637 #define LPFC_POST_STAGE_MAC_ADDRESS                     0x0C00
 638 #define LPFC_POST_STAGE_PORT_READY                      0xC000
 639 #define LPFC_POST_STAGE_PORT_UE                         0xF000
 640
 641 #define LPFC_CTL_PORT_STA_OFFSET        0x404
 642 #define lpfc_sliport_status_err_SHIFT   31
 643 #define lpfc_sliport_status_err_MASK    0x1
 644 #define lpfc_sliport_status_err_WORD    word0
 645 #define lpfc_sliport_status_end_SHIFT   30
 646 #define lpfc_sliport_status_end_MASK    0x1
 647 #define lpfc_sliport_status_end_WORD    word0
 648 #define lpfc_sliport_status_oti_SHIFT   29
 649 #define lpfc_sliport_status_oti_MASK    0x1
 650 #define lpfc_sliport_status_oti_WORD    word0
 651 #define lpfc_sliport_status_rn_SHIFT    24
 652 #define lpfc_sliport_status_rn_MASK     0x1
 653 #define lpfc_sliport_status_rn_WORD     word0
 654 #define lpfc_sliport_status_rdy_SHIFT   23
 655 #define lpfc_sliport_status_rdy_MASK    0x1
 656 #define lpfc_sliport_status_rdy_WORD    word0
 657 #define MAX_IF_TYPE_2_RESETS            6
 658
 659 #define LPFC_CTL_PORT_CTL_OFFSET        0x408
 660 #define lpfc_sliport_ctrl_end_SHIFT     30
 661 #define lpfc_sliport_ctrl_end_MASK      0x1
 662 #define lpfc_sliport_ctrl_end_WORD      word0
 663 #define LPFC_SLIPORT_LITTLE_ENDIAN 0
 664 #define LPFC_SLIPORT_BIG_ENDIAN    1
 665 #define lpfc_sliport_ctrl_ip_SHIFT      27
 666 #define lpfc_sliport_ctrl_ip_MASK       0x1
 667 #define lpfc_sliport_ctrl_ip_WORD       word0
 668 #define LPFC_SLIPORT_INIT_PORT  1
 669
 670 #define LPFC_CTL_PORT_ER1_OFFSET        0x40C
 671 #define LPFC_CTL_PORT_ER2_OFFSET        0x410
 672
 673 #define LPFC_CTL_PORT_EQ_DELAY_OFFSET   0x418
 674 #define lpfc_sliport_eqdelay_delay_SHIFT 16
 675 #define lpfc_sliport_eqdelay_delay_MASK 0xffff
 676 #define lpfc_sliport_eqdelay_delay_WORD word0
 677 #define lpfc_sliport_eqdelay_id_SHIFT   0
 678 #define lpfc_sliport_eqdelay_id_MASK    0xfff
 679 #define lpfc_sliport_eqdelay_id_WORD    word0
 680 #define LPFC_SEC_TO_USEC                1000000
 681
 682 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically
 683  * reside in BAR 2.
 684  */
 685 #define LPFC_SLIPORT_IF0_SMPHR  0x00AC
 686
 687 #define LPFC_IMR_MASK_ALL       0xFFFFFFFF
 688 #define LPFC_ISCR_CLEAR_ALL     0xFFFFFFFF
 689
 690 #define LPFC_HST_ISR0           0x0C18
 691 #define LPFC_HST_ISR1           0x0C1C
 692 #define LPFC_HST_ISR2           0x0C20
 693 #define LPFC_HST_ISR3           0x0C24
 694 #define LPFC_HST_ISR4           0x0C28
 695
 696 #define LPFC_HST_IMR0           0x0C48
 697 #define LPFC_HST_IMR1           0x0C4C
 698 #define LPFC_HST_IMR2           0x0C50
 699 #define LPFC_HST_IMR3           0x0C54
 700 #define LPFC_HST_IMR4           0x0C58
 701
 702 #define LPFC_HST_ISCR0          0x0C78
 703 #define LPFC_HST_ISCR1          0x0C7C
 704 #define LPFC_HST_ISCR2          0x0C80
 705 #define LPFC_HST_ISCR3          0x0C84
 706 #define LPFC_HST_ISCR4          0x0C88
 707
 708 #define LPFC_SLI4_INTR0                 BIT0
 709 #define LPFC_SLI4_INTR1                 BIT1
 710 #define LPFC_SLI4_INTR2                 BIT2
 711 #define LPFC_SLI4_INTR3                 BIT3
 712 #define LPFC_SLI4_INTR4                 BIT4
 713 #define LPFC_SLI4_INTR5                 BIT5
 714 #define LPFC_SLI4_INTR6                 BIT6
 715 #define LPFC_SLI4_INTR7                 BIT7
 716 #define LPFC_SLI4_INTR8                 BIT8
 717 #define LPFC_SLI4_INTR9                 BIT9
 718 #define LPFC_SLI4_INTR10                BIT10
 719 #define LPFC_SLI4_INTR11                BIT11
 720 #define LPFC_SLI4_INTR12                BIT12
 721 #define LPFC_SLI4_INTR13                BIT13
 722 #define LPFC_SLI4_INTR14                BIT14
 723 #define LPFC_SLI4_INTR15                BIT15
 724 #define LPFC_SLI4_INTR16                BIT16
 725 #define LPFC_SLI4_INTR17                BIT17
 726 #define LPFC_SLI4_INTR18                BIT18
 727 #define LPFC_SLI4_INTR19                BIT19
 728 #define LPFC_SLI4_INTR20                BIT20
 729 #define LPFC_SLI4_INTR21                BIT21
 730 #define LPFC_SLI4_INTR22                BIT22
 731 #define LPFC_SLI4_INTR23                BIT23
 732 #define LPFC_SLI4_INTR24                BIT24
 733 #define LPFC_SLI4_INTR25                BIT25
 734 #define LPFC_SLI4_INTR26                BIT26
 735 #define LPFC_SLI4_INTR27                BIT27
 736 #define LPFC_SLI4_INTR28                BIT28
 737 #define LPFC_SLI4_INTR29                BIT29
 738 #define LPFC_SLI4_INTR30                BIT30
 739 #define LPFC_SLI4_INTR31                BIT31
 740
 741 /*
 742  * The Doorbell registers defined here exist in different BAR
 743  * register sets depending on the UCNA Port's reported if_type
 744  * value.  For UCNA ports running SLI4 and if_type 0, they reside in
 745  * BAR4.  For UCNA ports running SLI4 and if_type 2, they reside in
 746  * BAR0.  For FC ports running SLI4 and if_type 6, they reside in
 747  * BAR2. The offsets and base address are different,  so the driver
 748  * has to compute the register addresses accordingly
 749  */
 750 #define LPFC_ULP0_RQ_DOORBELL           0x00A0
 751 #define LPFC_ULP1_RQ_DOORBELL           0x00C0
 752 #define LPFC_IF6_RQ_DOORBELL            0x0080
 753 #define lpfc_rq_db_list_fm_num_posted_SHIFT     24
 754 #define lpfc_rq_db_list_fm_num_posted_MASK      0x00FF
 755 #define lpfc_rq_db_list_fm_num_posted_WORD      word0
 756 #define lpfc_rq_db_list_fm_index_SHIFT          16
 757 #define lpfc_rq_db_list_fm_index_MASK           0x00FF
 758 #define lpfc_rq_db_list_fm_index_WORD           word0
 759 #define lpfc_rq_db_list_fm_id_SHIFT             0
 760 #define lpfc_rq_db_list_fm_id_MASK              0xFFFF
 761 #define lpfc_rq_db_list_fm_id_WORD              word0
 762 #define lpfc_rq_db_ring_fm_num_posted_SHIFT     16
 763 #define lpfc_rq_db_ring_fm_num_posted_MASK      0x3FFF
 764 #define lpfc_rq_db_ring_fm_num_posted_WORD      word0
 765 #define lpfc_rq_db_ring_fm_id_SHIFT             0
 766 #define lpfc_rq_db_ring_fm_id_MASK              0xFFFF
 767 #define lpfc_rq_db_ring_fm_id_WORD              word0
 768
 769 #define LPFC_ULP0_WQ_DOORBELL           0x0040
 770 #define LPFC_ULP1_WQ_DOORBELL           0x0060
 771 #define lpfc_wq_db_list_fm_num_posted_SHIFT     24
 772 #define lpfc_wq_db_list_fm_num_posted_MASK      0x00FF
 773 #define lpfc_wq_db_list_fm_num_posted_WORD      word0
 774 #define lpfc_wq_db_list_fm_index_SHIFT          16
 775 #define lpfc_wq_db_list_fm_index_MASK           0x00FF
 776 #define lpfc_wq_db_list_fm_index_WORD           word0
 777 #define lpfc_wq_db_list_fm_id_SHIFT             0
 778 #define lpfc_wq_db_list_fm_id_MASK              0xFFFF
 779 #define lpfc_wq_db_list_fm_id_WORD              word0
 780 #define lpfc_wq_db_ring_fm_num_posted_SHIFT     16
 781 #define lpfc_wq_db_ring_fm_num_posted_MASK      0x3FFF
 782 #define lpfc_wq_db_ring_fm_num_posted_WORD      word0
 783 #define lpfc_wq_db_ring_fm_id_SHIFT             0
 784 #define lpfc_wq_db_ring_fm_id_MASK              0xFFFF
 785 #define lpfc_wq_db_ring_fm_id_WORD              word0
 786
 787 #define LPFC_IF6_WQ_DOORBELL            0x0040
 788 #define lpfc_if6_wq_db_list_fm_num_posted_SHIFT 24
 789 #define lpfc_if6_wq_db_list_fm_num_posted_MASK  0x00FF
 790 #define lpfc_if6_wq_db_list_fm_num_posted_WORD  word0
 791 #define lpfc_if6_wq_db_list_fm_dpp_SHIFT        23
 792 #define lpfc_if6_wq_db_list_fm_dpp_MASK         0x0001
 793 #define lpfc_if6_wq_db_list_fm_dpp_WORD         word0
 794 #define lpfc_if6_wq_db_list_fm_dpp_id_SHIFT     16
 795 #define lpfc_if6_wq_db_list_fm_dpp_id_MASK      0x001F
 796 #define lpfc_if6_wq_db_list_fm_dpp_id_WORD      word0
 797 #define lpfc_if6_wq_db_list_fm_id_SHIFT         0
 798 #define lpfc_if6_wq_db_list_fm_id_MASK          0xFFFF
 799 #define lpfc_if6_wq_db_list_fm_id_WORD          word0
 800
 801 #define LPFC_EQCQ_DOORBELL              0x0120
 802 #define lpfc_eqcq_doorbell_se_SHIFT             31
 803 #define lpfc_eqcq_doorbell_se_MASK              0x0001
 804 #define lpfc_eqcq_doorbell_se_WORD              word0
 805 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF    0
 806 #define LPFC_EQCQ_SOLICIT_ENABLE_ON     1
 807 #define lpfc_eqcq_doorbell_arm_SHIFT            29
 808 #define lpfc_eqcq_doorbell_arm_MASK             0x0001
 809 #define lpfc_eqcq_doorbell_arm_WORD             word0
 810 #define lpfc_eqcq_doorbell_num_released_SHIFT   16
 811 #define lpfc_eqcq_doorbell_num_released_MASK    0x1FFF
 812 #define lpfc_eqcq_doorbell_num_released_WORD    word0
 813 #define lpfc_eqcq_doorbell_qt_SHIFT             10
 814 #define lpfc_eqcq_doorbell_qt_MASK              0x0001
 815 #define lpfc_eqcq_doorbell_qt_WORD              word0
 816 #define LPFC_QUEUE_TYPE_COMPLETION      0
 817 #define LPFC_QUEUE_TYPE_EVENT           1
 818 #define lpfc_eqcq_doorbell_eqci_SHIFT           9
 819 #define lpfc_eqcq_doorbell_eqci_MASK            0x0001
 820 #define lpfc_eqcq_doorbell_eqci_WORD            word0
 821 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT        0
 822 #define lpfc_eqcq_doorbell_cqid_lo_MASK         0x03FF
 823 #define lpfc_eqcq_doorbell_cqid_lo_WORD         word0
 824 #define lpfc_eqcq_doorbell_cqid_hi_SHIFT        11
 825 #define lpfc_eqcq_doorbell_cqid_hi_MASK         0x001F
 826 #define lpfc_eqcq_doorbell_cqid_hi_WORD         word0
 827 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT        0
 828 #define lpfc_eqcq_doorbell_eqid_lo_MASK         0x01FF
 829 #define lpfc_eqcq_doorbell_eqid_lo_WORD         word0
 830 #define lpfc_eqcq_doorbell_eqid_hi_SHIFT        11
 831 #define lpfc_eqcq_doorbell_eqid_hi_MASK         0x001F
 832 #define lpfc_eqcq_doorbell_eqid_hi_WORD         word0
 833 #define LPFC_CQID_HI_FIELD_SHIFT                10
 834 #define LPFC_EQID_HI_FIELD_SHIFT                9
 835
 836 #define LPFC_IF6_CQ_DOORBELL                    0x00C0
 837 #define lpfc_if6_cq_doorbell_se_SHIFT           31
 838 #define lpfc_if6_cq_doorbell_se_MASK            0x0001
 839 #define lpfc_if6_cq_doorbell_se_WORD            word0
 840 #define LPFC_IF6_CQ_SOLICIT_ENABLE_OFF          0
 841 #define LPFC_IF6_CQ_SOLICIT_ENABLE_ON           1
 842 #define lpfc_if6_cq_doorbell_arm_SHIFT          29
 843 #define lpfc_if6_cq_doorbell_arm_MASK           0x0001
 844 #define lpfc_if6_cq_doorbell_arm_WORD           word0
 845 #define lpfc_if6_cq_doorbell_num_released_SHIFT 16
 846 #define lpfc_if6_cq_doorbell_num_released_MASK  0x1FFF
 847 #define lpfc_if6_cq_doorbell_num_released_WORD  word0
 848 #define lpfc_if6_cq_doorbell_cqid_SHIFT         0
 849 #define lpfc_if6_cq_doorbell_cqid_MASK          0xFFFF
 850 #define lpfc_if6_cq_doorbell_cqid_WORD          word0
 851
 852 #define LPFC_IF6_EQ_DOORBELL                    0x0120
 853 #define lpfc_if6_eq_doorbell_io_SHIFT           31
 854 #define lpfc_if6_eq_doorbell_io_MASK            0x0001
 855 #define lpfc_if6_eq_doorbell_io_WORD            word0
 856 #define LPFC_IF6_EQ_INTR_OVERRIDE_OFF           0
 857 #define LPFC_IF6_EQ_INTR_OVERRIDE_ON            1
 858 #define lpfc_if6_eq_doorbell_arm_SHIFT          29
 859 #define lpfc_if6_eq_doorbell_arm_MASK           0x0001
 860 #define lpfc_if6_eq_doorbell_arm_WORD           word0
 861 #define lpfc_if6_eq_doorbell_num_released_SHIFT 16
 862 #define lpfc_if6_eq_doorbell_num_released_MASK  0x1FFF
 863 #define lpfc_if6_eq_doorbell_num_released_WORD  word0
 864 #define lpfc_if6_eq_doorbell_eqid_SHIFT         0
 865 #define lpfc_if6_eq_doorbell_eqid_MASK          0x0FFF
 866 #define lpfc_if6_eq_doorbell_eqid_WORD          word0
 867
 868 #define LPFC_BMBX                       0x0160
 869 #define lpfc_bmbx_addr_SHIFT            2
 870 #define lpfc_bmbx_addr_MASK             0x3FFFFFFF
 871 #define lpfc_bmbx_addr_WORD             word0
 872 #define lpfc_bmbx_hi_SHIFT              1
 873 #define lpfc_bmbx_hi_MASK               0x0001
 874 #define lpfc_bmbx_hi_WORD               word0
 875 #define lpfc_bmbx_rdy_SHIFT             0
 876 #define lpfc_bmbx_rdy_MASK              0x0001
 877 #define lpfc_bmbx_rdy_WORD              word0
 878
 879 #define LPFC_MQ_DOORBELL                        0x0140
 880 #define LPFC_IF6_MQ_DOORBELL                    0x0160
 881 #define lpfc_mq_doorbell_num_posted_SHIFT       16
 882 #define lpfc_mq_doorbell_num_posted_MASK        0x3FFF
 883 #define lpfc_mq_doorbell_num_posted_WORD        word0
 884 #define lpfc_mq_doorbell_id_SHIFT               0
 885 #define lpfc_mq_doorbell_id_MASK                0xFFFF
 886 #define lpfc_mq_doorbell_id_WORD                word0
 887
 888 struct lpfc_sli4_cfg_mhdr {
 889         uint32_t word1;
 890 #define lpfc_mbox_hdr_emb_SHIFT         0
 891 #define lpfc_mbox_hdr_emb_MASK          0x00000001
 892 #define lpfc_mbox_hdr_emb_WORD          word1
 893 #define lpfc_mbox_hdr_sge_cnt_SHIFT     3
 894 #define lpfc_mbox_hdr_sge_cnt_MASK      0x0000001F
 895 #define lpfc_mbox_hdr_sge_cnt_WORD      word1
 896         uint32_t payload_length;
 897         uint32_t tag_lo;
 898         uint32_t tag_hi;
 899         uint32_t reserved5;
 900 };
 901
 902 union lpfc_sli4_cfg_shdr {
 903         struct {
 904                 uint32_t word6;
 905 #define lpfc_mbox_hdr_opcode_SHIFT      0
 906 #define lpfc_mbox_hdr_opcode_MASK       0x000000FF
 907 #define lpfc_mbox_hdr_opcode_WORD       word6
 908 #define lpfc_mbox_hdr_subsystem_SHIFT   8
 909 #define lpfc_mbox_hdr_subsystem_MASK    0x000000FF
 910 #define lpfc_mbox_hdr_subsystem_WORD    word6
 911 #define lpfc_mbox_hdr_port_number_SHIFT 16
 912 #define lpfc_mbox_hdr_port_number_MASK  0x000000FF
 913 #define lpfc_mbox_hdr_port_number_WORD  word6
 914 #define lpfc_mbox_hdr_domain_SHIFT      24
 915 #define lpfc_mbox_hdr_domain_MASK       0x000000FF
 916 #define lpfc_mbox_hdr_domain_WORD       word6
 917                 uint32_t timeout;
 918                 uint32_t request_length;
 919                 uint32_t word9;
 920 #define lpfc_mbox_hdr_version_SHIFT     0
 921 #define lpfc_mbox_hdr_version_MASK      0x000000FF
 922 #define lpfc_mbox_hdr_version_WORD      word9
 923 #define lpfc_mbox_hdr_pf_num_SHIFT      16
 924 #define lpfc_mbox_hdr_pf_num_MASK       0x000000FF
 925 #define lpfc_mbox_hdr_pf_num_WORD       word9
 926 #define lpfc_mbox_hdr_vh_num_SHIFT      24
 927 #define lpfc_mbox_hdr_vh_num_MASK       0x000000FF
 928 #define lpfc_mbox_hdr_vh_num_WORD       word9
 929 #define LPFC_Q_CREATE_VERSION_2 2
 930 #define LPFC_Q_CREATE_VERSION_1 1
 931 #define LPFC_Q_CREATE_VERSION_0 0
 932 #define LPFC_OPCODE_VERSION_0   0
 933 #define LPFC_OPCODE_VERSION_1   1
 934         } request;
 935         struct {
 936                 uint32_t word6;
 937 #define lpfc_mbox_hdr_opcode_SHIFT              0
 938 #define lpfc_mbox_hdr_opcode_MASK               0x000000FF
 939 #define lpfc_mbox_hdr_opcode_WORD               word6
 940 #define lpfc_mbox_hdr_subsystem_SHIFT           8
 941 #define lpfc_mbox_hdr_subsystem_MASK            0x000000FF
 942 #define lpfc_mbox_hdr_subsystem_WORD            word6
 943 #define lpfc_mbox_hdr_domain_SHIFT              24
 944 #define lpfc_mbox_hdr_domain_MASK               0x000000FF
 945 #define lpfc_mbox_hdr_domain_WORD               word6
 946                 uint32_t word7;
 947 #define lpfc_mbox_hdr_status_SHIFT              0
 948 #define lpfc_mbox_hdr_status_MASK               0x000000FF
 949 #define lpfc_mbox_hdr_status_WORD               word7
 950 #define lpfc_mbox_hdr_add_status_SHIFT          8
 951 #define lpfc_mbox_hdr_add_status_MASK           0x000000FF
 952 #define lpfc_mbox_hdr_add_status_WORD           word7
 953                 uint32_t response_length;
 954                 uint32_t actual_response_length;
 955         } response;
 956 };
 957
 958 /* Mailbox Header structures.
 959  * struct mbox_header is defined for first generation SLI4_CFG mailbox
 960  * calls deployed for BE-based ports.
 961  *
 962  * struct sli4_mbox_header is defined for second generation SLI4
 963  * ports that don't deploy the SLI4_CFG mechanism.
 964  */
 965 struct mbox_header {
 966         struct lpfc_sli4_cfg_mhdr cfg_mhdr;
 967         union  lpfc_sli4_cfg_shdr cfg_shdr;
 968 };
 969
 970 #define LPFC_EXTENT_LOCAL               0
 971 #define LPFC_TIMEOUT_DEFAULT            0
 972 #define LPFC_EXTENT_VERSION_DEFAULT     0
 973
 974 /* Subsystem Definitions */
 975 #define LPFC_MBOX_SUBSYSTEM_NA          0x0
 976 #define LPFC_MBOX_SUBSYSTEM_COMMON      0x1
 977 #define LPFC_MBOX_SUBSYSTEM_LOWLEVEL    0xB
 978 #define LPFC_MBOX_SUBSYSTEM_FCOE        0xC
 979
 980 /* Device Specific Definitions */
 981
 982 /* The HOST ENDIAN defines are in Big Endian format. */
 983 #define HOST_ENDIAN_LOW_WORD0   0xFF3412FF
 984 #define HOST_ENDIAN_HIGH_WORD1  0xFF7856FF
 985
 986 /* Common Opcodes */
 987 #define LPFC_MBOX_OPCODE_NA                             0x00
 988 #define LPFC_MBOX_OPCODE_CQ_CREATE                      0x0C
 989 #define LPFC_MBOX_OPCODE_EQ_CREATE                      0x0D
 990 #define LPFC_MBOX_OPCODE_MQ_CREATE                      0x15
 991 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES            0x20
 992 #define LPFC_MBOX_OPCODE_NOP                            0x21
 993 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY                0x29
 994 #define LPFC_MBOX_OPCODE_MQ_DESTROY                     0x35
 995 #define LPFC_MBOX_OPCODE_CQ_DESTROY                     0x36
 996 #define LPFC_MBOX_OPCODE_EQ_DESTROY                     0x37
 997 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG                   0x3A
 998 #define LPFC_MBOX_OPCODE_FUNCTION_RESET                 0x3D
 999 #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG       0x3E
1000 #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG                0x43
1001 #define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG              0x45
1002 #define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG              0x46
1003 #define LPFC_MBOX_OPCODE_GET_PORT_NAME                  0x4D
1004 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT                  0x5A
1005 #define LPFC_MBOX_OPCODE_GET_VPD_DATA                   0x5B
1006 #define LPFC_MBOX_OPCODE_SET_HOST_DATA                  0x5D
1007 #define LPFC_MBOX_OPCODE_SEND_ACTIVATION                0x73
1008 #define LPFC_MBOX_OPCODE_RESET_LICENSES                 0x74
1009 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO           0x9A
1010 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT          0x9B
1011 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT              0x9C
1012 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT            0x9D
1013 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG            0xA0
1014 #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES         0xA1
1015 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG             0xA4
1016 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG             0xA5
1017 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST               0xA6
1018 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE                0xA8
1019 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG     0xA9
1020 #define LPFC_MBOX_OPCODE_READ_OBJECT                    0xAB
1021 #define LPFC_MBOX_OPCODE_WRITE_OBJECT                   0xAC
1022 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST               0xAD
1023 #define LPFC_MBOX_OPCODE_DELETE_OBJECT                  0xAE
1024 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS            0xB5
1025 #define LPFC_MBOX_OPCODE_SET_FEATURES                   0xBF
1026
1027 /* FCoE Opcodes */
1028 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE                 0x01
1029 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY                0x02
1030 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES            0x03
1031 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES          0x04
1032 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE                 0x05
1033 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY                0x06
1034 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE            0x08
1035 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF                   0x09
1036 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF                0x0A
1037 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE         0x0B
1038 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF            0x10
1039 #define LPFC_MBOX_OPCODE_FCOE_CQ_CREATE_SET             0x1D
1040 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS       0x21
1041 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE           0x22
1042 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK        0x23
1043 #define LPFC_MBOX_OPCODE_FCOE_FC_SET_TRUNK_MODE         0x42
1044
1045 /* Low level Opcodes */
1046 #define LPFC_MBOX_OPCODE_SET_DIAG_LOG_OPTION            0x37
1047
1048 /* Mailbox command structures */
1049 struct eq_context {
1050         uint32_t word0;
1051 #define lpfc_eq_context_size_SHIFT      31
1052 #define lpfc_eq_context_size_MASK       0x00000001
1053 #define lpfc_eq_context_size_WORD       word0
1054 #define LPFC_EQE_SIZE_4                 0x0
1055 #define LPFC_EQE_SIZE_16                0x1
1056 #define lpfc_eq_context_valid_SHIFT     29
1057 #define lpfc_eq_context_valid_MASK      0x00000001
1058 #define lpfc_eq_context_valid_WORD      word0
1059 #define lpfc_eq_context_autovalid_SHIFT 28
1060 #define lpfc_eq_context_autovalid_MASK  0x00000001
1061 #define lpfc_eq_context_autovalid_WORD  word0
1062         uint32_t word1;
1063 #define lpfc_eq_context_count_SHIFT     26
1064 #define lpfc_eq_context_count_MASK      0x00000003
1065 #define lpfc_eq_context_count_WORD      word1
1066 #define LPFC_EQ_CNT_256         0x0
1067 #define LPFC_EQ_CNT_512         0x1
1068 #define LPFC_EQ_CNT_1024        0x2
1069 #define LPFC_EQ_CNT_2048        0x3
1070 #define LPFC_EQ_CNT_4096        0x4
1071         uint32_t word2;
1072 #define lpfc_eq_context_delay_multi_SHIFT       13
1073 #define lpfc_eq_context_delay_multi_MASK        0x000003FF
1074 #define lpfc_eq_context_delay_multi_WORD        word2
1075         uint32_t reserved3;
1076 };
1077
1078 struct eq_delay_info {
1079         uint32_t eq_id;
1080         uint32_t phase;
1081         uint32_t delay_multi;
1082 };
1083 #define LPFC_MAX_EQ_DELAY_EQID_CNT      8
1084
1085 struct sgl_page_pairs {
1086         uint32_t sgl_pg0_addr_lo;
1087         uint32_t sgl_pg0_addr_hi;
1088         uint32_t sgl_pg1_addr_lo;
1089         uint32_t sgl_pg1_addr_hi;
1090 };
1091
1092 struct lpfc_mbx_post_sgl_pages {
1093         struct mbox_header header;
1094         uint32_t word0;
1095 #define lpfc_post_sgl_pages_xri_SHIFT   0
1096 #define lpfc_post_sgl_pages_xri_MASK    0x0000FFFF
1097 #define lpfc_post_sgl_pages_xri_WORD    word0
1098 #define lpfc_post_sgl_pages_xricnt_SHIFT        16
1099 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF
1100 #define lpfc_post_sgl_pages_xricnt_WORD word0
1101         struct sgl_page_pairs  sgl_pg_pairs[1];
1102 };
1103
1104 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */
1105 struct lpfc_mbx_post_uembed_sgl_page1 {
1106         union  lpfc_sli4_cfg_shdr cfg_shdr;
1107         uint32_t word0;
1108         struct sgl_page_pairs sgl_pg_pairs;
1109 };
1110
1111 struct lpfc_mbx_sge {
1112         uint32_t pa_lo;
1113         uint32_t pa_hi;
1114         uint32_t length;
1115 };
1116
1117 struct lpfc_mbx_nembed_cmd {
1118         struct lpfc_sli4_cfg_mhdr cfg_mhdr;
1119 #define LPFC_SLI4_MBX_SGE_MAX_PAGES     19
1120         struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES];
1121 };
1122
1123 struct lpfc_mbx_nembed_sge_virt {
1124         void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES];
1125 };
1126
1127 struct lpfc_mbx_eq_create {
1128         struct mbox_header header;
1129         union {
1130                 struct {
1131                         uint32_t word0;
1132 #define lpfc_mbx_eq_create_num_pages_SHIFT      0
1133 #define lpfc_mbx_eq_create_num_pages_MASK       0x0000FFFF
1134 #define lpfc_mbx_eq_create_num_pages_WORD       word0
1135                         struct eq_context context;
1136                         struct dma_address page[LPFC_MAX_EQ_PAGE];
1137                 } request;
1138                 struct {
1139                         uint32_t word0;
1140 #define lpfc_mbx_eq_create_q_id_SHIFT   0
1141 #define lpfc_mbx_eq_create_q_id_MASK    0x0000FFFF
1142 #define lpfc_mbx_eq_create_q_id_WORD    word0
1143                 } response;
1144         } u;
1145 };
1146
1147 struct lpfc_mbx_modify_eq_delay {
1148         struct mbox_header header;
1149         union {
1150                 struct {
1151                         uint32_t num_eq;
1152                         struct eq_delay_info eq[LPFC_MAX_EQ_DELAY_EQID_CNT];
1153                 } request;
1154                 struct {
1155                         uint32_t word0;
1156                 } response;
1157         } u;
1158 };
1159
1160 struct lpfc_mbx_eq_destroy {
1161         struct mbox_header header;
1162         union {
1163                 struct {
1164                         uint32_t word0;
1165 #define lpfc_mbx_eq_destroy_q_id_SHIFT  0
1166 #define lpfc_mbx_eq_destroy_q_id_MASK   0x0000FFFF
1167 #define lpfc_mbx_eq_destroy_q_id_WORD   word0
1168                 } request;
1169                 struct {
1170                         uint32_t word0;
1171                 } response;
1172         } u;
1173 };
1174
1175 struct lpfc_mbx_nop {
1176         struct mbox_header header;
1177         uint32_t context[2];
1178 };
1179
1180
1181
1182 struct lpfc_mbx_set_ras_fwlog {
1183         struct mbox_header header;
1184         union {
1185                 struct {
1186                         uint32_t word4;
1187 #define lpfc_fwlog_enable_SHIFT         0
1188 #define lpfc_fwlog_enable_MASK          0x00000001
1189 #define lpfc_fwlog_enable_WORD          word4
1190 #define lpfc_fwlog_loglvl_SHIFT         8
1191 #define lpfc_fwlog_loglvl_MASK          0x0000000F
1192 #define lpfc_fwlog_loglvl_WORD          word4
1193 #define lpfc_fwlog_ra_SHIFT             15
1194 #define lpfc_fwlog_ra_WORD              0x00000008
1195 #define lpfc_fwlog_buffcnt_SHIFT        16
1196 #define lpfc_fwlog_buffcnt_MASK         0x000000FF
1197 #define lpfc_fwlog_buffcnt_WORD         word4
1198 #define lpfc_fwlog_buffsz_SHIFT         24
1199 #define lpfc_fwlog_buffsz_MASK          0x000000FF
1200 #define lpfc_fwlog_buffsz_WORD          word4
1201                         uint32_t word5;
1202 #define lpfc_fwlog_acqe_SHIFT           0
1203 #define lpfc_fwlog_acqe_MASK            0x0000FFFF
1204 #define lpfc_fwlog_acqe_WORD            word5
1205 #define lpfc_fwlog_cqid_SHIFT           16
1206 #define lpfc_fwlog_cqid_MASK            0x0000FFFF
1207 #define lpfc_fwlog_cqid_WORD            word5
1208 #define LPFC_MAX_FWLOG_PAGE     16
1209                         struct dma_address lwpd;
1210                         struct dma_address buff_fwlog[LPFC_MAX_FWLOG_PAGE];
1211                 } request;
1212                 struct {
1213                         uint32_t word0;
1214                 } response;
1215         } u;
1216 };
1217
1218
1219 struct cq_context {
1220         uint32_t word0;
1221 #define lpfc_cq_context_event_SHIFT     31
1222 #define lpfc_cq_context_event_MASK      0x00000001
1223 #define lpfc_cq_context_event_WORD      word0
1224 #define lpfc_cq_context_valid_SHIFT     29
1225 #define lpfc_cq_context_valid_MASK      0x00000001
1226 #define lpfc_cq_context_valid_WORD      word0
1227 #define lpfc_cq_context_count_SHIFT     27
1228 #define lpfc_cq_context_count_MASK      0x00000003
1229 #define lpfc_cq_context_count_WORD      word0
1230 #define LPFC_CQ_CNT_256         0x0
1231 #define LPFC_CQ_CNT_512         0x1
1232 #define LPFC_CQ_CNT_1024        0x2
1233 #define LPFC_CQ_CNT_WORD7       0x3
1234 #define lpfc_cq_context_autovalid_SHIFT 15
1235 #define lpfc_cq_context_autovalid_MASK  0x00000001
1236 #define lpfc_cq_context_autovalid_WORD  word0
1237         uint32_t word1;
1238 #define lpfc_cq_eq_id_SHIFT             22      /* Version 0 Only */
1239 #define lpfc_cq_eq_id_MASK              0x000000FF
1240 #define lpfc_cq_eq_id_WORD              word1
1241 #define lpfc_cq_eq_id_2_SHIFT           0       /* Version 2 Only */
1242 #define lpfc_cq_eq_id_2_MASK            0x0000FFFF
1243 #define lpfc_cq_eq_id_2_WORD            word1
1244         uint32_t lpfc_cq_context_count;         /* Version 2 Only */
1245         uint32_t reserved1;
1246 };
1247
1248 struct lpfc_mbx_cq_create {
1249         struct mbox_header header;
1250         union {
1251                 struct {
1252                         uint32_t word0;
1253 #define lpfc_mbx_cq_create_page_size_SHIFT      16      /* Version 2 Only */
1254 #define lpfc_mbx_cq_create_page_size_MASK       0x000000FF
1255 #define lpfc_mbx_cq_create_page_size_WORD       word0
1256 #define lpfc_mbx_cq_create_num_pages_SHIFT      0
1257 #define lpfc_mbx_cq_create_num_pages_MASK       0x0000FFFF
1258 #define lpfc_mbx_cq_create_num_pages_WORD       word0
1259                         struct cq_context context;
1260                         struct dma_address page[LPFC_MAX_CQ_PAGE];
1261                 } request;
1262                 struct {
1263                         uint32_t word0;
1264 #define lpfc_mbx_cq_create_q_id_SHIFT   0
1265 #define lpfc_mbx_cq_create_q_id_MASK    0x0000FFFF
1266 #define lpfc_mbx_cq_create_q_id_WORD    word0
1267                 } response;
1268         } u;
1269 };
1270
1271 struct lpfc_mbx_cq_create_set {
1272         union  lpfc_sli4_cfg_shdr cfg_shdr;
1273         union {
1274                 struct {
1275                         uint32_t word0;
1276 #define lpfc_mbx_cq_create_set_page_size_SHIFT  16      /* Version 2 Only */
1277 #define lpfc_mbx_cq_create_set_page_size_MASK   0x000000FF
1278 #define lpfc_mbx_cq_create_set_page_size_WORD   word0
1279 #define lpfc_mbx_cq_create_set_num_pages_SHIFT  0
1280 #define lpfc_mbx_cq_create_set_num_pages_MASK   0x0000FFFF
1281 #define lpfc_mbx_cq_create_set_num_pages_WORD   word0
1282                         uint32_t word1;
1283 #define lpfc_mbx_cq_create_set_evt_SHIFT        31
1284 #define lpfc_mbx_cq_create_set_evt_MASK         0x00000001
1285 #define lpfc_mbx_cq_create_set_evt_WORD         word1
1286 #define lpfc_mbx_cq_create_set_valid_SHIFT      29
1287 #define lpfc_mbx_cq_create_set_valid_MASK       0x00000001
1288 #define lpfc_mbx_cq_create_set_valid_WORD       word1
1289 #define lpfc_mbx_cq_create_set_cqe_cnt_SHIFT    27
1290 #define lpfc_mbx_cq_create_set_cqe_cnt_MASK     0x00000003
1291 #define lpfc_mbx_cq_create_set_cqe_cnt_WORD     word1
1292 #define lpfc_mbx_cq_create_set_cqe_size_SHIFT   25
1293 #define lpfc_mbx_cq_create_set_cqe_size_MASK    0x00000003
1294 #define lpfc_mbx_cq_create_set_cqe_size_WORD    word1
1295 #define lpfc_mbx_cq_create_set_autovalid_SHIFT  15
1296 #define lpfc_mbx_cq_create_set_autovalid_MASK   0x0000001
1297 #define lpfc_mbx_cq_create_set_autovalid_WORD   word1
1298 #define lpfc_mbx_cq_create_set_nodelay_SHIFT    14
1299 #define lpfc_mbx_cq_create_set_nodelay_MASK     0x00000001
1300 #define lpfc_mbx_cq_create_set_nodelay_WORD     word1
1301 #define lpfc_mbx_cq_create_set_clswm_SHIFT      12
1302 #define lpfc_mbx_cq_create_set_clswm_MASK       0x00000003
1303 #define lpfc_mbx_cq_create_set_clswm_WORD       word1
1304                         uint32_t word2;
1305 #define lpfc_mbx_cq_create_set_arm_SHIFT        31
1306 #define lpfc_mbx_cq_create_set_arm_MASK         0x00000001
1307 #define lpfc_mbx_cq_create_set_arm_WORD         word2
1308 #define lpfc_mbx_cq_create_set_cq_cnt_SHIFT     16
1309 #define lpfc_mbx_cq_create_set_cq_cnt_MASK      0x00007FFF
1310 #define lpfc_mbx_cq_create_set_cq_cnt_WORD      word2
1311 #define lpfc_mbx_cq_create_set_num_cq_SHIFT     0
1312 #define lpfc_mbx_cq_create_set_num_cq_MASK      0x0000FFFF
1313 #define lpfc_mbx_cq_create_set_num_cq_WORD      word2
1314                         uint32_t word3;
1315 #define lpfc_mbx_cq_create_set_eq_id1_SHIFT     16
1316 #define lpfc_mbx_cq_create_set_eq_id1_MASK      0x0000FFFF
1317 #define lpfc_mbx_cq_create_set_eq_id1_WORD      word3
1318 #define lpfc_mbx_cq_create_set_eq_id0_SHIFT     0
1319 #define lpfc_mbx_cq_create_set_eq_id0_MASK      0x0000FFFF
1320 #define lpfc_mbx_cq_create_set_eq_id0_WORD      word3
1321                         uint32_t word4;
1322 #define lpfc_mbx_cq_create_set_eq_id3_SHIFT     16
1323 #define lpfc_mbx_cq_create_set_eq_id3_MASK      0x0000FFFF
1324 #define lpfc_mbx_cq_create_set_eq_id3_WORD      word4
1325 #define lpfc_mbx_cq_create_set_eq_id2_SHIFT     0
1326 #define lpfc_mbx_cq_create_set_eq_id2_MASK      0x0000FFFF
1327 #define lpfc_mbx_cq_create_set_eq_id2_WORD      word4
1328                         uint32_t word5;
1329 #define lpfc_mbx_cq_create_set_eq_id5_SHIFT     16
1330 #define lpfc_mbx_cq_create_set_eq_id5_MASK      0x0000FFFF
1331 #define lpfc_mbx_cq_create_set_eq_id5_WORD      word5
1332 #define lpfc_mbx_cq_create_set_eq_id4_SHIFT     0
1333 #define lpfc_mbx_cq_create_set_eq_id4_MASK      0x0000FFFF
1334 #define lpfc_mbx_cq_create_set_eq_id4_WORD      word5
1335                         uint32_t word6;
1336 #define lpfc_mbx_cq_create_set_eq_id7_SHIFT     16
1337 #define lpfc_mbx_cq_create_set_eq_id7_MASK      0x0000FFFF
1338 #define lpfc_mbx_cq_create_set_eq_id7_WORD      word6
1339 #define lpfc_mbx_cq_create_set_eq_id6_SHIFT     0
1340 #define lpfc_mbx_cq_create_set_eq_id6_MASK      0x0000FFFF
1341 #define lpfc_mbx_cq_create_set_eq_id6_WORD      word6
1342                         uint32_t word7;
1343 #define lpfc_mbx_cq_create_set_eq_id9_SHIFT     16
1344 #define lpfc_mbx_cq_create_set_eq_id9_MASK      0x0000FFFF
1345 #define lpfc_mbx_cq_create_set_eq_id9_WORD      word7
1346 #define lpfc_mbx_cq_create_set_eq_id8_SHIFT     0
1347 #define lpfc_mbx_cq_create_set_eq_id8_MASK      0x0000FFFF
1348 #define lpfc_mbx_cq_create_set_eq_id8_WORD      word7
1349                         uint32_t word8;
1350 #define lpfc_mbx_cq_create_set_eq_id11_SHIFT    16
1351 #define lpfc_mbx_cq_create_set_eq_id11_MASK     0x0000FFFF
1352 #define lpfc_mbx_cq_create_set_eq_id11_WORD     word8
1353 #define lpfc_mbx_cq_create_set_eq_id10_SHIFT    0
1354 #define lpfc_mbx_cq_create_set_eq_id10_MASK     0x0000FFFF
1355 #define lpfc_mbx_cq_create_set_eq_id10_WORD     word8
1356                         uint32_t word9;
1357 #define lpfc_mbx_cq_create_set_eq_id13_SHIFT    16
1358 #define lpfc_mbx_cq_create_set_eq_id13_MASK     0x0000FFFF
1359 #define lpfc_mbx_cq_create_set_eq_id13_WORD     word9
1360 #define lpfc_mbx_cq_create_set_eq_id12_SHIFT    0
1361 #define lpfc_mbx_cq_create_set_eq_id12_MASK     0x0000FFFF
1362 #define lpfc_mbx_cq_create_set_eq_id12_WORD     word9
1363                         uint32_t word10;
1364 #define lpfc_mbx_cq_create_set_eq_id15_SHIFT    16
1365 #define lpfc_mbx_cq_create_set_eq_id15_MASK     0x0000FFFF
1366 #define lpfc_mbx_cq_create_set_eq_id15_WORD     word10
1367 #define lpfc_mbx_cq_create_set_eq_id14_SHIFT    0
1368 #define lpfc_mbx_cq_create_set_eq_id14_MASK     0x0000FFFF
1369 #define lpfc_mbx_cq_create_set_eq_id14_WORD     word10
1370                         struct dma_address page[1];
1371                 } request;
1372                 struct {
1373                         uint32_t word0;
1374 #define lpfc_mbx_cq_create_set_num_alloc_SHIFT  16
1375 #define lpfc_mbx_cq_create_set_num_alloc_MASK   0x0000FFFF
1376 #define lpfc_mbx_cq_create_set_num_alloc_WORD   word0
1377 #define lpfc_mbx_cq_create_set_base_id_SHIFT    0
1378 #define lpfc_mbx_cq_create_set_base_id_MASK     0x0000FFFF
1379 #define lpfc_mbx_cq_create_set_base_id_WORD     word0
1380                 } response;
1381         } u;
1382 };
1383
1384 struct lpfc_mbx_cq_destroy {
1385         struct mbox_header header;
1386         union {
1387                 struct {
1388                         uint32_t word0;
1389 #define lpfc_mbx_cq_destroy_q_id_SHIFT  0
1390 #define lpfc_mbx_cq_destroy_q_id_MASK   0x0000FFFF
1391 #define lpfc_mbx_cq_destroy_q_id_WORD   word0
1392                 } request;
1393                 struct {
1394                         uint32_t word0;
1395                 } response;
1396         } u;
1397 };
1398
1399 struct wq_context {
1400         uint32_t reserved0;
1401         uint32_t reserved1;
1402         uint32_t reserved2;
1403         uint32_t reserved3;
1404 };
1405
1406 struct lpfc_mbx_wq_create {
1407         struct mbox_header header;
1408         union {
1409                 struct {        /* Version 0 Request */
1410                         uint32_t word0;
1411 #define lpfc_mbx_wq_create_num_pages_SHIFT      0
1412 #define lpfc_mbx_wq_create_num_pages_MASK       0x000000FF
1413 #define lpfc_mbx_wq_create_num_pages_WORD       word0
1414 #define lpfc_mbx_wq_create_dua_SHIFT            8
1415 #define lpfc_mbx_wq_create_dua_MASK             0x00000001
1416 #define lpfc_mbx_wq_create_dua_WORD             word0
1417 #define lpfc_mbx_wq_create_cq_id_SHIFT          16
1418 #define lpfc_mbx_wq_create_cq_id_MASK           0x0000FFFF
1419 #define lpfc_mbx_wq_create_cq_id_WORD           word0
1420                         struct dma_address page[LPFC_MAX_WQ_PAGE_V0];
1421                         uint32_t word9;
1422 #define lpfc_mbx_wq_create_bua_SHIFT            0
1423 #define lpfc_mbx_wq_create_bua_MASK             0x00000001
1424 #define lpfc_mbx_wq_create_bua_WORD             word9
1425 #define lpfc_mbx_wq_create_ulp_num_SHIFT        8
1426 #define lpfc_mbx_wq_create_ulp_num_MASK         0x000000FF
1427 #define lpfc_mbx_wq_create_ulp_num_WORD         word9
1428                 } request;
1429                 struct {        /* Version 1 Request */
1430                         uint32_t word0; /* Word 0 is the same as in v0 */
1431                         uint32_t word1;
1432 #define lpfc_mbx_wq_create_page_size_SHIFT      0
1433 #define lpfc_mbx_wq_create_page_size_MASK       0x000000FF
1434 #define lpfc_mbx_wq_create_page_size_WORD       word1
1435 #define LPFC_WQ_PAGE_SIZE_4096  0x1
1436 #define lpfc_mbx_wq_create_dpp_req_SHIFT        15
1437 #define lpfc_mbx_wq_create_dpp_req_MASK         0x00000001
1438 #define lpfc_mbx_wq_create_dpp_req_WORD         word1
1439 #define lpfc_mbx_wq_create_doe_SHIFT            14
1440 #define lpfc_mbx_wq_create_doe_MASK             0x00000001
1441 #define lpfc_mbx_wq_create_doe_WORD             word1
1442 #define lpfc_mbx_wq_create_toe_SHIFT            13
1443 #define lpfc_mbx_wq_create_toe_MASK             0x00000001
1444 #define lpfc_mbx_wq_create_toe_WORD             word1
1445 #define lpfc_mbx_wq_create_wqe_size_SHIFT       8
1446 #define lpfc_mbx_wq_create_wqe_size_MASK        0x0000000F
1447 #define lpfc_mbx_wq_create_wqe_size_WORD        word1
1448 #define LPFC_WQ_WQE_SIZE_64     0x5
1449 #define LPFC_WQ_WQE_SIZE_128    0x6
1450 #define lpfc_mbx_wq_create_wqe_count_SHIFT      16
1451 #define lpfc_mbx_wq_create_wqe_count_MASK       0x0000FFFF
1452 #define lpfc_mbx_wq_create_wqe_count_WORD       word1
1453                         uint32_t word2;
1454                         struct dma_address page[LPFC_MAX_WQ_PAGE-1];
1455                 } request_1;
1456                 struct {
1457                         uint32_t word0;
1458 #define lpfc_mbx_wq_create_q_id_SHIFT   0
1459 #define lpfc_mbx_wq_create_q_id_MASK    0x0000FFFF
1460 #define lpfc_mbx_wq_create_q_id_WORD    word0
1461                         uint32_t doorbell_offset;
1462                         uint32_t word2;
1463 #define lpfc_mbx_wq_create_bar_set_SHIFT        0
1464 #define lpfc_mbx_wq_create_bar_set_MASK         0x0000FFFF
1465 #define lpfc_mbx_wq_create_bar_set_WORD         word2
1466 #define WQ_PCI_BAR_0_AND_1      0x00
1467 #define WQ_PCI_BAR_2_AND_3      0x01
1468 #define WQ_PCI_BAR_4_AND_5      0x02
1469 #define lpfc_mbx_wq_create_db_format_SHIFT      16
1470 #define lpfc_mbx_wq_create_db_format_MASK       0x0000FFFF
1471 #define lpfc_mbx_wq_create_db_format_WORD       word2
1472                 } response;
1473                 struct {
1474                         uint32_t word0;
1475 #define lpfc_mbx_wq_create_dpp_rsp_SHIFT        31
1476 #define lpfc_mbx_wq_create_dpp_rsp_MASK         0x00000001
1477 #define lpfc_mbx_wq_create_dpp_rsp_WORD         word0
1478 #define lpfc_mbx_wq_create_v1_q_id_SHIFT        0
1479 #define lpfc_mbx_wq_create_v1_q_id_MASK         0x0000FFFF
1480 #define lpfc_mbx_wq_create_v1_q_id_WORD         word0
1481                         uint32_t word1;
1482 #define lpfc_mbx_wq_create_v1_bar_set_SHIFT     0
1483 #define lpfc_mbx_wq_create_v1_bar_set_MASK      0x0000000F
1484 #define lpfc_mbx_wq_create_v1_bar_set_WORD      word1
1485                         uint32_t doorbell_offset;
1486                         uint32_t word3;
1487 #define lpfc_mbx_wq_create_dpp_id_SHIFT         16
1488 #define lpfc_mbx_wq_create_dpp_id_MASK          0x0000001F
1489 #define lpfc_mbx_wq_create_dpp_id_WORD          word3
1490 #define lpfc_mbx_wq_create_dpp_bar_SHIFT        0
1491 #define lpfc_mbx_wq_create_dpp_bar_MASK         0x0000000F
1492 #define lpfc_mbx_wq_create_dpp_bar_WORD         word3
1493                         uint32_t dpp_offset;
1494                 } response_1;
1495         } u;
1496 };
1497
1498 struct lpfc_mbx_wq_destroy {
1499         struct mbox_header header;
1500         union {
1501                 struct {
1502                         uint32_t word0;
1503 #define lpfc_mbx_wq_destroy_q_id_SHIFT  0
1504 #define lpfc_mbx_wq_destroy_q_id_MASK   0x0000FFFF
1505 #define lpfc_mbx_wq_destroy_q_id_WORD   word0
1506                 } request;
1507                 struct {
1508                         uint32_t word0;
1509                 } response;
1510         } u;
1511 };
1512
1513 #define LPFC_HDR_BUF_SIZE 128
1514 #define LPFC_DATA_BUF_SIZE 2048
1515 #define LPFC_NVMET_DATA_BUF_SIZE 128
1516 struct rq_context {
1517         uint32_t word0;
1518 #define lpfc_rq_context_rqe_count_SHIFT 16      /* Version 0 Only */
1519 #define lpfc_rq_context_rqe_count_MASK  0x0000000F
1520 #define lpfc_rq_context_rqe_count_WORD  word0
1521 #define LPFC_RQ_RING_SIZE_512           9       /* 512 entries */
1522 #define LPFC_RQ_RING_SIZE_1024          10      /* 1024 entries */
1523 #define LPFC_RQ_RING_SIZE_2048          11      /* 2048 entries */
1524 #define LPFC_RQ_RING_SIZE_4096          12      /* 4096 entries */
1525 #define lpfc_rq_context_rqe_count_1_SHIFT       16      /* Version 1-2 Only */
1526 #define lpfc_rq_context_rqe_count_1_MASK        0x0000FFFF
1527 #define lpfc_rq_context_rqe_count_1_WORD        word0
1528 #define lpfc_rq_context_rqe_size_SHIFT  8               /* Version 1-2 Only */
1529 #define lpfc_rq_context_rqe_size_MASK   0x0000000F
1530 #define lpfc_rq_context_rqe_size_WORD   word0
1531 #define LPFC_RQE_SIZE_8         2
1532 #define LPFC_RQE_SIZE_16        3
1533 #define LPFC_RQE_SIZE_32        4
1534 #define LPFC_RQE_SIZE_64        5
1535 #define LPFC_RQE_SIZE_128       6
1536 #define lpfc_rq_context_page_size_SHIFT 0               /* Version 1 Only */
1537 #define lpfc_rq_context_page_size_MASK  0x000000FF
1538 #define lpfc_rq_context_page_size_WORD  word0
1539 #define LPFC_RQ_PAGE_SIZE_4096  0x1
1540         uint32_t word1;
1541 #define lpfc_rq_context_data_size_SHIFT 16              /* Version 2 Only */
1542 #define lpfc_rq_context_data_size_MASK  0x0000FFFF
1543 #define lpfc_rq_context_data_size_WORD  word1
1544 #define lpfc_rq_context_hdr_size_SHIFT  0               /* Version 2 Only */
1545 #define lpfc_rq_context_hdr_size_MASK   0x0000FFFF
1546 #define lpfc_rq_context_hdr_size_WORD   word1
1547         uint32_t word2;
1548 #define lpfc_rq_context_cq_id_SHIFT     16
1549 #define lpfc_rq_context_cq_id_MASK      0x000003FF
1550 #define lpfc_rq_context_cq_id_WORD      word2
1551 #define lpfc_rq_context_buf_size_SHIFT  0
1552 #define lpfc_rq_context_buf_size_MASK   0x0000FFFF
1553 #define lpfc_rq_context_buf_size_WORD   word2
1554 #define lpfc_rq_context_base_cq_SHIFT   0               /* Version 2 Only */
1555 #define lpfc_rq_context_base_cq_MASK    0x0000FFFF
1556 #define lpfc_rq_context_base_cq_WORD    word2
1557         uint32_t buffer_size;                           /* Version 1 Only */
1558 };
1559
1560 struct lpfc_mbx_rq_create {
1561         struct mbox_header header;
1562         union {
1563                 struct {
1564                         uint32_t word0;
1565 #define lpfc_mbx_rq_create_num_pages_SHIFT      0
1566 #define lpfc_mbx_rq_create_num_pages_MASK       0x0000FFFF
1567 #define lpfc_mbx_rq_create_num_pages_WORD       word0
1568 #define lpfc_mbx_rq_create_dua_SHIFT            16
1569 #define lpfc_mbx_rq_create_dua_MASK             0x00000001
1570 #define lpfc_mbx_rq_create_dua_WORD             word0
1571 #define lpfc_mbx_rq_create_bqu_SHIFT            17
1572 #define lpfc_mbx_rq_create_bqu_MASK             0x00000001
1573 #define lpfc_mbx_rq_create_bqu_WORD             word0
1574 #define lpfc_mbx_rq_create_ulp_num_SHIFT        24
1575 #define lpfc_mbx_rq_create_ulp_num_MASK         0x000000FF
1576 #define lpfc_mbx_rq_create_ulp_num_WORD         word0
1577                         struct rq_context context;
1578                         struct dma_address page[LPFC_MAX_RQ_PAGE];
1579                 } request;
1580                 struct {
1581                         uint32_t word0;
1582 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT       16
1583 #define lpfc_mbx_rq_create_q_cnt_v2_MASK        0x0000FFFF
1584 #define lpfc_mbx_rq_create_q_cnt_v2_WORD        word0
1585 #define lpfc_mbx_rq_create_q_id_SHIFT           0
1586 #define lpfc_mbx_rq_create_q_id_MASK            0x0000FFFF
1587 #define lpfc_mbx_rq_create_q_id_WORD            word0
1588                         uint32_t doorbell_offset;
1589                         uint32_t word2;
1590 #define lpfc_mbx_rq_create_bar_set_SHIFT        0
1591 #define lpfc_mbx_rq_create_bar_set_MASK         0x0000FFFF
1592 #define lpfc_mbx_rq_create_bar_set_WORD         word2
1593 #define lpfc_mbx_rq_create_db_format_SHIFT      16
1594 #define lpfc_mbx_rq_create_db_format_MASK       0x0000FFFF
1595 #define lpfc_mbx_rq_create_db_format_WORD       word2
1596                 } response;
1597         } u;
1598 };
1599
1600 struct lpfc_mbx_rq_create_v2 {
1601         union  lpfc_sli4_cfg_shdr cfg_shdr;
1602         union {
1603                 struct {
1604                         uint32_t word0;
1605 #define lpfc_mbx_rq_create_num_pages_SHIFT      0
1606 #define lpfc_mbx_rq_create_num_pages_MASK       0x0000FFFF
1607 #define lpfc_mbx_rq_create_num_pages_WORD       word0
1608 #define lpfc_mbx_rq_create_rq_cnt_SHIFT         16
1609 #define lpfc_mbx_rq_create_rq_cnt_MASK          0x000000FF
1610 #define lpfc_mbx_rq_create_rq_cnt_WORD          word0
1611 #define lpfc_mbx_rq_create_dua_SHIFT            16
1612 #define lpfc_mbx_rq_create_dua_MASK             0x00000001
1613 #define lpfc_mbx_rq_create_dua_WORD             word0
1614 #define lpfc_mbx_rq_create_bqu_SHIFT            17
1615 #define lpfc_mbx_rq_create_bqu_MASK             0x00000001
1616 #define lpfc_mbx_rq_create_bqu_WORD             word0
1617 #define lpfc_mbx_rq_create_ulp_num_SHIFT        24
1618 #define lpfc_mbx_rq_create_ulp_num_MASK         0x000000FF
1619 #define lpfc_mbx_rq_create_ulp_num_WORD         word0
1620 #define lpfc_mbx_rq_create_dim_SHIFT            29
1621 #define lpfc_mbx_rq_create_dim_MASK             0x00000001
1622 #define lpfc_mbx_rq_create_dim_WORD             word0
1623 #define lpfc_mbx_rq_create_dfd_SHIFT            30
1624 #define lpfc_mbx_rq_create_dfd_MASK             0x00000001
1625 #define lpfc_mbx_rq_create_dfd_WORD             word0
1626 #define lpfc_mbx_rq_create_dnb_SHIFT            31
1627 #define lpfc_mbx_rq_create_dnb_MASK             0x00000001
1628 #define lpfc_mbx_rq_create_dnb_WORD             word0
1629                         struct rq_context context;
1630                         struct dma_address page[1];
1631                 } request;
1632                 struct {
1633                         uint32_t word0;
1634 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT       16
1635 #define lpfc_mbx_rq_create_q_cnt_v2_MASK        0x0000FFFF
1636 #define lpfc_mbx_rq_create_q_cnt_v2_WORD        word0
1637 #define lpfc_mbx_rq_create_q_id_SHIFT           0
1638 #define lpfc_mbx_rq_create_q_id_MASK            0x0000FFFF
1639 #define lpfc_mbx_rq_create_q_id_WORD            word0
1640                         uint32_t doorbell_offset;
1641                         uint32_t word2;
1642 #define lpfc_mbx_rq_create_bar_set_SHIFT        0
1643 #define lpfc_mbx_rq_create_bar_set_MASK         0x0000FFFF
1644 #define lpfc_mbx_rq_create_bar_set_WORD         word2
1645 #define lpfc_mbx_rq_create_db_format_SHIFT      16
1646 #define lpfc_mbx_rq_create_db_format_MASK       0x0000FFFF
1647 #define lpfc_mbx_rq_create_db_format_WORD       word2
1648                 } response;
1649         } u;
1650 };
1651
1652 struct lpfc_mbx_rq_destroy {
1653         struct mbox_header header;
1654         union {
1655                 struct {
1656                         uint32_t word0;
1657 #define lpfc_mbx_rq_destroy_q_id_SHIFT  0
1658 #define lpfc_mbx_rq_destroy_q_id_MASK   0x0000FFFF
1659 #define lpfc_mbx_rq_destroy_q_id_WORD   word0
1660                 } request;
1661                 struct {
1662                         uint32_t word0;
1663                 } response;
1664         } u;
1665 };
1666
1667 struct mq_context {
1668         uint32_t word0;
1669 #define lpfc_mq_context_cq_id_SHIFT     22      /* Version 0 Only */
1670 #define lpfc_mq_context_cq_id_MASK      0x000003FF
1671 #define lpfc_mq_context_cq_id_WORD      word0
1672 #define lpfc_mq_context_ring_size_SHIFT 16
1673 #define lpfc_mq_context_ring_size_MASK  0x0000000F
1674 #define lpfc_mq_context_ring_size_WORD  word0
1675 #define LPFC_MQ_RING_SIZE_16            0x5
1676 #define LPFC_MQ_RING_SIZE_32            0x6
1677 #define LPFC_MQ_RING_SIZE_64            0x7
1678 #define LPFC_MQ_RING_SIZE_128           0x8
1679         uint32_t word1;
1680 #define lpfc_mq_context_valid_SHIFT     31
1681 #define lpfc_mq_context_valid_MASK      0x00000001
1682 #define lpfc_mq_context_valid_WORD      word1
1683         uint32_t reserved2;
1684         uint32_t reserved3;
1685 };
1686
1687 struct lpfc_mbx_mq_create {
1688         struct mbox_header header;
1689         union {
1690                 struct {
1691                         uint32_t word0;
1692 #define lpfc_mbx_mq_create_num_pages_SHIFT      0
1693 #define lpfc_mbx_mq_create_num_pages_MASK       0x0000FFFF
1694 #define lpfc_mbx_mq_create_num_pages_WORD       word0
1695                         struct mq_context context;
1696                         struct dma_address page[LPFC_MAX_MQ_PAGE];
1697                 } request;
1698                 struct {
1699                         uint32_t word0;
1700 #define lpfc_mbx_mq_create_q_id_SHIFT   0
1701 #define lpfc_mbx_mq_create_q_id_MASK    0x0000FFFF
1702 #define lpfc_mbx_mq_create_q_id_WORD    word0
1703                 } response;
1704         } u;
1705 };
1706
1707 struct lpfc_mbx_mq_create_ext {
1708         struct mbox_header header;
1709         union {
1710                 struct {
1711                         uint32_t word0;
1712 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT  0
1713 #define lpfc_mbx_mq_create_ext_num_pages_MASK   0x0000FFFF
1714 #define lpfc_mbx_mq_create_ext_num_pages_WORD   word0
1715 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT      16      /* Version 1 Only */
1716 #define lpfc_mbx_mq_create_ext_cq_id_MASK       0x0000FFFF
1717 #define lpfc_mbx_mq_create_ext_cq_id_WORD       word0
1718                         uint32_t async_evt_bmap;
1719 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT     LPFC_TRAILER_CODE_LINK
1720 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK      0x00000001
1721 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD      async_evt_bmap
1722 #define LPFC_EVT_CODE_LINK_NO_LINK      0x0
1723 #define LPFC_EVT_CODE_LINK_10_MBIT      0x1
1724 #define LPFC_EVT_CODE_LINK_100_MBIT     0x2
1725 #define LPFC_EVT_CODE_LINK_1_GBIT       0x3
1726 #define LPFC_EVT_CODE_LINK_10_GBIT      0x4
1727 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT      LPFC_TRAILER_CODE_FCOE
1728 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK       0x00000001
1729 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD       async_evt_bmap
1730 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT   LPFC_TRAILER_CODE_GRP5
1731 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK    0x00000001
1732 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD    async_evt_bmap
1733 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT       LPFC_TRAILER_CODE_FC
1734 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK        0x00000001
1735 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD        async_evt_bmap
1736 #define LPFC_EVT_CODE_FC_NO_LINK        0x0
1737 #define LPFC_EVT_CODE_FC_1_GBAUD        0x1
1738 #define LPFC_EVT_CODE_FC_2_GBAUD        0x2
1739 #define LPFC_EVT_CODE_FC_4_GBAUD        0x4
1740 #define LPFC_EVT_CODE_FC_8_GBAUD        0x8
1741 #define LPFC_EVT_CODE_FC_10_GBAUD       0xA
1742 #define LPFC_EVT_CODE_FC_16_GBAUD       0x10
1743 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT      LPFC_TRAILER_CODE_SLI
1744 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK       0x00000001
1745 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD       async_evt_bmap
1746                         struct mq_context context;
1747                         struct dma_address page[LPFC_MAX_MQ_PAGE];
1748                 } request;
1749                 struct {
1750                         uint32_t word0;
1751 #define lpfc_mbx_mq_create_q_id_SHIFT   0
1752 #define lpfc_mbx_mq_create_q_id_MASK    0x0000FFFF
1753 #define lpfc_mbx_mq_create_q_id_WORD    word0
1754                 } response;
1755         } u;
1756 #define LPFC_ASYNC_EVENT_LINK_STATE     0x2
1757 #define LPFC_ASYNC_EVENT_FCF_STATE      0x4
1758 #define LPFC_ASYNC_EVENT_GROUP5         0x20
1759 };
1760
1761 struct lpfc_mbx_mq_destroy {
1762         struct mbox_header header;
1763         union {
1764                 struct {
1765                         uint32_t word0;
1766 #define lpfc_mbx_mq_destroy_q_id_SHIFT  0
1767 #define lpfc_mbx_mq_destroy_q_id_MASK   0x0000FFFF
1768 #define lpfc_mbx_mq_destroy_q_id_WORD   word0
1769                 } request;
1770                 struct {
1771                         uint32_t word0;
1772                 } response;
1773         } u;
1774 };
1775
1776 /* Start Gen 2 SLI4 Mailbox definitions: */
1777
1778 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */
1779 #define LPFC_RSC_TYPE_FCOE_VFI  0x20
1780 #define LPFC_RSC_TYPE_FCOE_VPI  0x21
1781 #define LPFC_RSC_TYPE_FCOE_RPI  0x22
1782 #define LPFC_RSC_TYPE_FCOE_XRI  0x23
1783
1784 struct lpfc_mbx_get_rsrc_extent_info {
1785         struct mbox_header header;
1786         union {
1787                 struct {
1788                         uint32_t word4;
1789 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT        0
1790 #define lpfc_mbx_get_rsrc_extent_info_type_MASK         0x0000FFFF
1791 #define lpfc_mbx_get_rsrc_extent_info_type_WORD         word4
1792                 } req;
1793                 struct {
1794                         uint32_t word4;
1795 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT         0
1796 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK          0x0000FFFF
1797 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD          word4
1798 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT        16
1799 #define lpfc_mbx_get_rsrc_extent_info_size_MASK         0x0000FFFF
1800 #define lpfc_mbx_get_rsrc_extent_info_size_WORD         word4
1801                 } rsp;
1802         } u;
1803 };
1804
1805 struct lpfc_mbx_query_fw_config {
1806         struct mbox_header header;
1807         struct {
1808                 uint32_t config_number;
1809 #define LPFC_FC_FCOE            0x00000007
1810                 uint32_t asic_revision;
1811                 uint32_t physical_port;
1812                 uint32_t function_mode;
1813 #define LPFC_FCOE_INI_MODE      0x00000040
1814 #define LPFC_FCOE_TGT_MODE      0x00000080
1815 #define LPFC_DUA_MODE           0x00000800
1816                 uint32_t ulp0_mode;
1817 #define LPFC_ULP_FCOE_INIT_MODE 0x00000040
1818 #define LPFC_ULP_FCOE_TGT_MODE  0x00000080
1819                 uint32_t ulp0_nap_words[12];
1820                 uint32_t ulp1_mode;
1821                 uint32_t ulp1_nap_words[12];
1822                 uint32_t function_capabilities;
1823                 uint32_t cqid_base;
1824                 uint32_t cqid_tot;
1825                 uint32_t eqid_base;
1826                 uint32_t eqid_tot;
1827                 uint32_t ulp0_nap2_words[2];
1828                 uint32_t ulp1_nap2_words[2];
1829         } rsp;
1830 };
1831
1832 struct lpfc_mbx_set_beacon_config {
1833         struct mbox_header header;
1834         uint32_t word4;
1835 #define lpfc_mbx_set_beacon_port_num_SHIFT              0
1836 #define lpfc_mbx_set_beacon_port_num_MASK               0x0000003F
1837 #define lpfc_mbx_set_beacon_port_num_WORD               word4
1838 #define lpfc_mbx_set_beacon_port_type_SHIFT             6
1839 #define lpfc_mbx_set_beacon_port_type_MASK              0x00000003
1840 #define lpfc_mbx_set_beacon_port_type_WORD              word4
1841 #define lpfc_mbx_set_beacon_state_SHIFT                 8
1842 #define lpfc_mbx_set_beacon_state_MASK                  0x000000FF
1843 #define lpfc_mbx_set_beacon_state_WORD                  word4
1844 #define lpfc_mbx_set_beacon_duration_SHIFT              16
1845 #define lpfc_mbx_set_beacon_duration_MASK               0x000000FF
1846 #define lpfc_mbx_set_beacon_duration_WORD               word4
1847
1848 /* COMMON_SET_BEACON_CONFIG_V1 */
1849 #define lpfc_mbx_set_beacon_duration_v1_SHIFT           16
1850 #define lpfc_mbx_set_beacon_duration_v1_MASK            0x0000FFFF
1851 #define lpfc_mbx_set_beacon_duration_v1_WORD            word4
1852         uint32_t word5;  /* RESERVED  */
1853 };
1854
1855 struct lpfc_id_range {
1856         uint32_t word5;
1857 #define lpfc_mbx_rsrc_id_word4_0_SHIFT  0
1858 #define lpfc_mbx_rsrc_id_word4_0_MASK   0x0000FFFF
1859 #define lpfc_mbx_rsrc_id_word4_0_WORD   word5
1860 #define lpfc_mbx_rsrc_id_word4_1_SHIFT  16
1861 #define lpfc_mbx_rsrc_id_word4_1_MASK   0x0000FFFF
1862 #define lpfc_mbx_rsrc_id_word4_1_WORD   word5
1863 };
1864
1865 struct lpfc_mbx_set_link_diag_state {
1866         struct mbox_header header;
1867         union {
1868                 struct {
1869                         uint32_t word0;
1870 #define lpfc_mbx_set_diag_state_diag_SHIFT      0
1871 #define lpfc_mbx_set_diag_state_diag_MASK       0x00000001
1872 #define lpfc_mbx_set_diag_state_diag_WORD       word0
1873 #define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT    2
1874 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK     0x00000001
1875 #define lpfc_mbx_set_diag_state_diag_bit_valid_WORD     word0
1876 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE        0
1877 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE           1
1878 #define lpfc_mbx_set_diag_state_link_num_SHIFT  16
1879 #define lpfc_mbx_set_diag_state_link_num_MASK   0x0000003F
1880 #define lpfc_mbx_set_diag_state_link_num_WORD   word0
1881 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22
1882 #define lpfc_mbx_set_diag_state_link_type_MASK  0x00000003
1883 #define lpfc_mbx_set_diag_state_link_type_WORD  word0
1884                 } req;
1885                 struct {
1886                         uint32_t word0;
1887                 } rsp;
1888         } u;
1889 };
1890
1891 struct lpfc_mbx_set_link_diag_loopback {
1892         struct mbox_header header;
1893         union {
1894                 struct {
1895                         uint32_t word0;
1896 #define lpfc_mbx_set_diag_lpbk_type_SHIFT               0
1897 #define lpfc_mbx_set_diag_lpbk_type_MASK                0x00000003
1898 #define lpfc_mbx_set_diag_lpbk_type_WORD                word0
1899 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE                 0x0
1900 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL                0x1
1901 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES                  0x2
1902 #define LPFC_DIAG_LOOPBACK_TYPE_EXTERNAL_TRUNKED        0x3
1903 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT           16
1904 #define lpfc_mbx_set_diag_lpbk_link_num_MASK            0x0000003F
1905 #define lpfc_mbx_set_diag_lpbk_link_num_WORD            word0
1906 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT          22
1907 #define lpfc_mbx_set_diag_lpbk_link_type_MASK           0x00000003
1908 #define lpfc_mbx_set_diag_lpbk_link_type_WORD           word0
1909                 } req;
1910                 struct {
1911                         uint32_t word0;
1912                 } rsp;
1913         } u;
1914 };
1915
1916 struct lpfc_mbx_run_link_diag_test {
1917         struct mbox_header header;
1918         union {
1919                 struct {
1920                         uint32_t word0;
1921 #define lpfc_mbx_run_diag_test_link_num_SHIFT   16
1922 #define lpfc_mbx_run_diag_test_link_num_MASK    0x0000003F
1923 #define lpfc_mbx_run_diag_test_link_num_WORD    word0
1924 #define lpfc_mbx_run_diag_test_link_type_SHIFT  22
1925 #define lpfc_mbx_run_diag_test_link_type_MASK   0x00000003
1926 #define lpfc_mbx_run_diag_test_link_type_WORD   word0
1927                         uint32_t word1;
1928 #define lpfc_mbx_run_diag_test_test_id_SHIFT    0
1929 #define lpfc_mbx_run_diag_test_test_id_MASK     0x0000FFFF
1930 #define lpfc_mbx_run_diag_test_test_id_WORD     word1
1931 #define lpfc_mbx_run_diag_test_loops_SHIFT      16
1932 #define lpfc_mbx_run_diag_test_loops_MASK       0x0000FFFF
1933 #define lpfc_mbx_run_diag_test_loops_WORD       word1
1934                         uint32_t word2;
1935 #define lpfc_mbx_run_diag_test_test_ver_SHIFT   0
1936 #define lpfc_mbx_run_diag_test_test_ver_MASK    0x0000FFFF
1937 #define lpfc_mbx_run_diag_test_test_ver_WORD    word2
1938 #define lpfc_mbx_run_diag_test_err_act_SHIFT    16
1939 #define lpfc_mbx_run_diag_test_err_act_MASK     0x000000FF
1940 #define lpfc_mbx_run_diag_test_err_act_WORD     word2
1941                 } req;
1942                 struct {
1943                         uint32_t word0;
1944                 } rsp;
1945         } u;
1946 };
1947
1948 /*
1949  * struct lpfc_mbx_alloc_rsrc_extents:
1950  * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires
1951  * 6 words of header + 4 words of shared subcommand header +
1952  * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total.
1953  *
1954  * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes
1955  * for extents payload.
1956  *
1957  * 212/2 (bytes per extent) = 106 extents.
1958  * 106/2 (extents per word) = 53 words.
1959  * lpfc_id_range id is statically size to 53.
1960  *
1961  * This mailbox definition is used for ALLOC or GET_ALLOCATED
1962  * extent ranges.  For ALLOC, the type and cnt are required.
1963  * For GET_ALLOCATED, only the type is required.
1964  */
1965 struct lpfc_mbx_alloc_rsrc_extents {
1966         struct mbox_header header;
1967         union {
1968                 struct {
1969                         uint32_t word4;
1970 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT  0
1971 #define lpfc_mbx_alloc_rsrc_extents_type_MASK   0x0000FFFF
1972 #define lpfc_mbx_alloc_rsrc_extents_type_WORD   word4
1973 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT   16
1974 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK    0x0000FFFF
1975 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD    word4
1976                 } req;
1977                 struct {
1978                         uint32_t word4;
1979 #define lpfc_mbx_rsrc_cnt_SHIFT 0
1980 #define lpfc_mbx_rsrc_cnt_MASK  0x0000FFFF
1981 #define lpfc_mbx_rsrc_cnt_WORD  word4
1982                         struct lpfc_id_range id[53];
1983                 } rsp;
1984         } u;
1985 };
1986
1987 /*
1988  * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this
1989  * structure shares the same SHIFT/MASK/WORD defines provided in the
1990  * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in
1991  * the structures defined above.  This non-embedded structure provides for the
1992  * maximum number of extents supported by the port.
1993  */
1994 struct lpfc_mbx_nembed_rsrc_extent {
1995         union  lpfc_sli4_cfg_shdr cfg_shdr;
1996         uint32_t word4;
1997         struct lpfc_id_range id;
1998 };
1999
2000 struct lpfc_mbx_dealloc_rsrc_extents {
2001         struct mbox_header header;
2002         struct {
2003                 uint32_t word4;
2004 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT        0
2005 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK         0x0000FFFF
2006 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD         word4
2007         } req;
2008
2009 };
2010
2011 /* Start SLI4 FCoE specific mbox structures. */
2012
2013 struct lpfc_mbx_post_hdr_tmpl {
2014         struct mbox_header header;
2015         uint32_t word10;
2016 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT  0
2017 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK   0x0000FFFF
2018 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD   word10
2019 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT   16
2020 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK    0x0000FFFF
2021 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD    word10
2022         uint32_t rpi_paddr_lo;
2023         uint32_t rpi_paddr_hi;
2024 };
2025
2026 struct sli4_sge {       /* SLI-4 */
2027         uint32_t addr_hi;
2028         uint32_t addr_lo;
2029
2030         uint32_t word2;
2031 #define lpfc_sli4_sge_offset_SHIFT      0
2032 #define lpfc_sli4_sge_offset_MASK       0x07FFFFFF
2033 #define lpfc_sli4_sge_offset_WORD       word2
2034 #define lpfc_sli4_sge_type_SHIFT        27
2035 #define lpfc_sli4_sge_type_MASK         0x0000000F
2036 #define lpfc_sli4_sge_type_WORD         word2
2037 #define LPFC_SGE_TYPE_DATA              0x0
2038 #define LPFC_SGE_TYPE_DIF               0x4
2039 #define LPFC_SGE_TYPE_LSP               0x5
2040 #define LPFC_SGE_TYPE_PEDIF             0x6
2041 #define LPFC_SGE_TYPE_PESEED            0x7
2042 #define LPFC_SGE_TYPE_DISEED            0x8
2043 #define LPFC_SGE_TYPE_ENC               0x9
2044 #define LPFC_SGE_TYPE_ATM               0xA
2045 #define LPFC_SGE_TYPE_SKIP              0xC
2046 #define lpfc_sli4_sge_last_SHIFT        31 /* Last SEG in the SGL sets it */
2047 #define lpfc_sli4_sge_last_MASK         0x00000001
2048 #define lpfc_sli4_sge_last_WORD         word2
2049         uint32_t sge_len;
2050 };
2051
2052 struct sli4_hybrid_sgl {
2053         struct list_head list_node;
2054         struct sli4_sge *dma_sgl;
2055         dma_addr_t dma_phys_sgl;
2056 };
2057
2058 struct fcp_cmd_rsp_buf {
2059         struct list_head list_node;
2060
2061         /* for storing cmd/rsp dma alloc'ed virt_addr */
2062         struct fcp_cmnd *fcp_cmnd;
2063         struct fcp_rsp *fcp_rsp;
2064
2065         /* for storing this cmd/rsp's dma mapped phys addr from per CPU pool */
2066         dma_addr_t fcp_cmd_rsp_dma_handle;
2067 };
2068
2069 struct sli4_sge_diseed {        /* SLI-4 */
2070         uint32_t ref_tag;
2071         uint32_t ref_tag_tran;
2072
2073         uint32_t word2;
2074 #define lpfc_sli4_sge_dif_apptran_SHIFT 0
2075 #define lpfc_sli4_sge_dif_apptran_MASK  0x0000FFFF
2076 #define lpfc_sli4_sge_dif_apptran_WORD  word2
2077 #define lpfc_sli4_sge_dif_af_SHIFT      24
2078 #define lpfc_sli4_sge_dif_af_MASK       0x00000001
2079 #define lpfc_sli4_sge_dif_af_WORD       word2
2080 #define lpfc_sli4_sge_dif_na_SHIFT      25
2081 #define lpfc_sli4_sge_dif_na_MASK       0x00000001
2082 #define lpfc_sli4_sge_dif_na_WORD       word2
2083 #define lpfc_sli4_sge_dif_hi_SHIFT      26
2084 #define lpfc_sli4_sge_dif_hi_MASK       0x00000001
2085 #define lpfc_sli4_sge_dif_hi_WORD       word2
2086 #define lpfc_sli4_sge_dif_type_SHIFT    27
2087 #define lpfc_sli4_sge_dif_type_MASK     0x0000000F
2088 #define lpfc_sli4_sge_dif_type_WORD     word2
2089 #define lpfc_sli4_sge_dif_last_SHIFT    31 /* Last SEG in the SGL sets it */
2090 #define lpfc_sli4_sge_dif_last_MASK     0x00000001
2091 #define lpfc_sli4_sge_dif_last_WORD     word2
2092         uint32_t word3;
2093 #define lpfc_sli4_sge_dif_apptag_SHIFT  0
2094 #define lpfc_sli4_sge_dif_apptag_MASK   0x0000FFFF
2095 #define lpfc_sli4_sge_dif_apptag_WORD   word3
2096 #define lpfc_sli4_sge_dif_bs_SHIFT      16
2097 #define lpfc_sli4_sge_dif_bs_MASK       0x00000007
2098 #define lpfc_sli4_sge_dif_bs_WORD       word3
2099 #define lpfc_sli4_sge_dif_ai_SHIFT      19
2100 #define lpfc_sli4_sge_dif_ai_MASK       0x00000001
2101 #define lpfc_sli4_sge_dif_ai_WORD       word3
2102 #define lpfc_sli4_sge_dif_me_SHIFT      20
2103 #define lpfc_sli4_sge_dif_me_MASK       0x00000001
2104 #define lpfc_sli4_sge_dif_me_WORD       word3
2105 #define lpfc_sli4_sge_dif_re_SHIFT      21
2106 #define lpfc_sli4_sge_dif_re_MASK       0x00000001
2107 #define lpfc_sli4_sge_dif_re_WORD       word3
2108 #define lpfc_sli4_sge_dif_ce_SHIFT      22
2109 #define lpfc_sli4_sge_dif_ce_MASK       0x00000001
2110 #define lpfc_sli4_sge_dif_ce_WORD       word3
2111 #define lpfc_sli4_sge_dif_nr_SHIFT      23
2112 #define lpfc_sli4_sge_dif_nr_MASK       0x00000001
2113 #define lpfc_sli4_sge_dif_nr_WORD       word3
2114 #define lpfc_sli4_sge_dif_oprx_SHIFT    24
2115 #define lpfc_sli4_sge_dif_oprx_MASK     0x0000000F
2116 #define lpfc_sli4_sge_dif_oprx_WORD     word3
2117 #define lpfc_sli4_sge_dif_optx_SHIFT    28
2118 #define lpfc_sli4_sge_dif_optx_MASK     0x0000000F
2119 #define lpfc_sli4_sge_dif_optx_WORD     word3
2120 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */
2121 };
2122
2123 struct fcf_record {
2124         uint32_t max_rcv_size;
2125         uint32_t fka_adv_period;
2126         uint32_t fip_priority;
2127         uint32_t word3;
2128 #define lpfc_fcf_record_mac_0_SHIFT             0
2129 #define lpfc_fcf_record_mac_0_MASK              0x000000FF
2130 #define lpfc_fcf_record_mac_0_WORD              word3
2131 #define lpfc_fcf_record_mac_1_SHIFT             8
2132 #define lpfc_fcf_record_mac_1_MASK              0x000000FF
2133 #define lpfc_fcf_record_mac_1_WORD              word3
2134 #define lpfc_fcf_record_mac_2_SHIFT             16
2135 #define lpfc_fcf_record_mac_2_MASK              0x000000FF
2136 #define lpfc_fcf_record_mac_2_WORD              word3
2137 #define lpfc_fcf_record_mac_3_SHIFT             24
2138 #define lpfc_fcf_record_mac_3_MASK              0x000000FF
2139 #define lpfc_fcf_record_mac_3_WORD              word3
2140         uint32_t word4;
2141 #define lpfc_fcf_record_mac_4_SHIFT             0
2142 #define lpfc_fcf_record_mac_4_MASK              0x000000FF
2143 #define lpfc_fcf_record_mac_4_WORD              word4
2144 #define lpfc_fcf_record_mac_5_SHIFT             8
2145 #define lpfc_fcf_record_mac_5_MASK              0x000000FF
2146 #define lpfc_fcf_record_mac_5_WORD              word4
2147 #define lpfc_fcf_record_fcf_avail_SHIFT         16
2148 #define lpfc_fcf_record_fcf_avail_MASK          0x000000FF
2149 #define lpfc_fcf_record_fcf_avail_WORD          word4
2150 #define lpfc_fcf_record_mac_addr_prov_SHIFT     24
2151 #define lpfc_fcf_record_mac_addr_prov_MASK      0x000000FF
2152 #define lpfc_fcf_record_mac_addr_prov_WORD      word4
2153 #define LPFC_FCF_FPMA           1       /* Fabric Provided MAC Address */
2154 #define LPFC_FCF_SPMA           2       /* Server Provided MAC Address */
2155         uint32_t word5;
2156 #define lpfc_fcf_record_fab_name_0_SHIFT        0
2157 #define lpfc_fcf_record_fab_name_0_MASK         0x000000FF
2158 #define lpfc_fcf_record_fab_name_0_WORD         word5
2159 #define lpfc_fcf_record_fab_name_1_SHIFT        8
2160 #define lpfc_fcf_record_fab_name_1_MASK         0x000000FF
2161 #define lpfc_fcf_record_fab_name_1_WORD         word5
2162 #define lpfc_fcf_record_fab_name_2_SHIFT        16
2163 #define lpfc_fcf_record_fab_name_2_MASK         0x000000FF
2164 #define lpfc_fcf_record_fab_name_2_WORD         word5
2165 #define lpfc_fcf_record_fab_name_3_SHIFT        24
2166 #define lpfc_fcf_record_fab_name_3_MASK         0x000000FF
2167 #define lpfc_fcf_record_fab_name_3_WORD         word5
2168         uint32_t word6;
2169 #define lpfc_fcf_record_fab_name_4_SHIFT        0
2170 #define lpfc_fcf_record_fab_name_4_MASK         0x000000FF
2171 #define lpfc_fcf_record_fab_name_4_WORD         word6
2172 #define lpfc_fcf_record_fab_name_5_SHIFT        8
2173 #define lpfc_fcf_record_fab_name_5_MASK         0x000000FF
2174 #define lpfc_fcf_record_fab_name_5_WORD         word6
2175 #define lpfc_fcf_record_fab_name_6_SHIFT        16
2176 #define lpfc_fcf_record_fab_name_6_MASK         0x000000FF
2177 #define lpfc_fcf_record_fab_name_6_WORD         word6
2178 #define lpfc_fcf_record_fab_name_7_SHIFT        24
2179 #define lpfc_fcf_record_fab_name_7_MASK         0x000000FF
2180 #define lpfc_fcf_record_fab_name_7_WORD         word6
2181         uint32_t word7;
2182 #define lpfc_fcf_record_fc_map_0_SHIFT          0
2183 #define lpfc_fcf_record_fc_map_0_MASK           0x000000FF
2184 #define lpfc_fcf_record_fc_map_0_WORD           word7
2185 #define lpfc_fcf_record_fc_map_1_SHIFT          8
2186 #define lpfc_fcf_record_fc_map_1_MASK           0x000000FF
2187 #define lpfc_fcf_record_fc_map_1_WORD           word7
2188 #define lpfc_fcf_record_fc_map_2_SHIFT          16
2189 #define lpfc_fcf_record_fc_map_2_MASK           0x000000FF
2190 #define lpfc_fcf_record_fc_map_2_WORD           word7
2191 #define lpfc_fcf_record_fcf_valid_SHIFT         24
2192 #define lpfc_fcf_record_fcf_valid_MASK          0x00000001
2193 #define lpfc_fcf_record_fcf_valid_WORD          word7
2194 #define lpfc_fcf_record_fcf_fc_SHIFT            25
2195 #define lpfc_fcf_record_fcf_fc_MASK             0x00000001
2196 #define lpfc_fcf_record_fcf_fc_WORD             word7
2197 #define lpfc_fcf_record_fcf_sol_SHIFT           31
2198 #define lpfc_fcf_record_fcf_sol_MASK            0x00000001
2199 #define lpfc_fcf_record_fcf_sol_WORD            word7
2200         uint32_t word8;
2201 #define lpfc_fcf_record_fcf_index_SHIFT         0
2202 #define lpfc_fcf_record_fcf_index_MASK          0x0000FFFF
2203 #define lpfc_fcf_record_fcf_index_WORD          word8
2204 #define lpfc_fcf_record_fcf_state_SHIFT         16
2205 #define lpfc_fcf_record_fcf_state_MASK          0x0000FFFF
2206 #define lpfc_fcf_record_fcf_state_WORD          word8
2207         uint8_t vlan_bitmap[512];
2208         uint32_t word137;
2209 #define lpfc_fcf_record_switch_name_0_SHIFT     0
2210 #define lpfc_fcf_record_switch_name_0_MASK      0x000000FF
2211 #define lpfc_fcf_record_switch_name_0_WORD      word137
2212 #define lpfc_fcf_record_switch_name_1_SHIFT     8
2213 #define lpfc_fcf_record_switch_name_1_MASK      0x000000FF
2214 #define lpfc_fcf_record_switch_name_1_WORD      word137
2215 #define lpfc_fcf_record_switch_name_2_SHIFT     16
2216 #define lpfc_fcf_record_switch_name_2_MASK      0x000000FF
2217 #define lpfc_fcf_record_switch_name_2_WORD      word137
2218 #define lpfc_fcf_record_switch_name_3_SHIFT     24
2219 #define lpfc_fcf_record_switch_name_3_MASK      0x000000FF
2220 #define lpfc_fcf_record_switch_name_3_WORD      word137
2221         uint32_t word138;
2222 #define lpfc_fcf_record_switch_name_4_SHIFT     0
2223 #define lpfc_fcf_record_switch_name_4_MASK      0x000000FF
2224 #define lpfc_fcf_record_switch_name_4_WORD      word138
2225 #define lpfc_fcf_record_switch_name_5_SHIFT     8
2226 #define lpfc_fcf_record_switch_name_5_MASK      0x000000FF
2227 #define lpfc_fcf_record_switch_name_5_WORD      word138
2228 #define lpfc_fcf_record_switch_name_6_SHIFT     16
2229 #define lpfc_fcf_record_switch_name_6_MASK      0x000000FF
2230 #define lpfc_fcf_record_switch_name_6_WORD      word138
2231 #define lpfc_fcf_record_switch_name_7_SHIFT     24
2232 #define lpfc_fcf_record_switch_name_7_MASK      0x000000FF
2233 #define lpfc_fcf_record_switch_name_7_WORD      word138
2234 };
2235
2236 struct lpfc_mbx_read_fcf_tbl {
2237         union lpfc_sli4_cfg_shdr cfg_shdr;
2238         union {
2239                 struct {
2240                         uint32_t word10;
2241 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT        0
2242 #define lpfc_mbx_read_fcf_tbl_indx_MASK         0x0000FFFF
2243 #define lpfc_mbx_read_fcf_tbl_indx_WORD         word10
2244                 } request;
2245                 struct {
2246                         uint32_t eventag;
2247                 } response;
2248         } u;
2249         uint32_t word11;
2250 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT   0
2251 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK    0x0000FFFF
2252 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD    word11
2253 };
2254
2255 struct lpfc_mbx_add_fcf_tbl_entry {
2256         union lpfc_sli4_cfg_shdr cfg_shdr;
2257         uint32_t word10;
2258 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT        0
2259 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK         0x0000FFFF
2260 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD         word10
2261         struct lpfc_mbx_sge fcf_sge;
2262 };
2263
2264 struct lpfc_mbx_del_fcf_tbl_entry {
2265         struct mbox_header header;
2266         uint32_t word10;
2267 #define lpfc_mbx_del_fcf_tbl_count_SHIFT        0
2268 #define lpfc_mbx_del_fcf_tbl_count_MASK         0x0000FFFF
2269 #define lpfc_mbx_del_fcf_tbl_count_WORD         word10
2270 #define lpfc_mbx_del_fcf_tbl_index_SHIFT        16
2271 #define lpfc_mbx_del_fcf_tbl_index_MASK         0x0000FFFF
2272 #define lpfc_mbx_del_fcf_tbl_index_WORD         word10
2273 };
2274
2275 struct lpfc_mbx_redisc_fcf_tbl {
2276         struct mbox_header header;
2277         uint32_t word10;
2278 #define lpfc_mbx_redisc_fcf_count_SHIFT         0
2279 #define lpfc_mbx_redisc_fcf_count_MASK          0x0000FFFF
2280 #define lpfc_mbx_redisc_fcf_count_WORD          word10
2281         uint32_t resvd;
2282         uint32_t word12;
2283 #define lpfc_mbx_redisc_fcf_index_SHIFT         0
2284 #define lpfc_mbx_redisc_fcf_index_MASK          0x0000FFFF
2285 #define lpfc_mbx_redisc_fcf_index_WORD          word12
2286 };
2287
2288 /* Status field for embedded SLI_CONFIG mailbox command */
2289 #define STATUS_SUCCESS                                  0x0
2290 #define STATUS_FAILED                                   0x1
2291 #define STATUS_ILLEGAL_REQUEST                          0x2
2292 #define STATUS_ILLEGAL_FIELD                            0x3
2293 #define STATUS_INSUFFICIENT_BUFFER                      0x4
2294 #define STATUS_UNAUTHORIZED_REQUEST                     0x5
2295 #define STATUS_FLASHROM_SAVE_FAILED                     0x17
2296 #define STATUS_FLASHROM_RESTORE_FAILED                  0x18
2297 #define STATUS_ICCBINDEX_ALLOC_FAILED                   0x1a
2298 #define STATUS_IOCTLHANDLE_ALLOC_FAILED                 0x1b
2299 #define STATUS_INVALID_PHY_ADDR_FROM_OSM                0x1c
2300 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM            0x1d
2301 #define STATUS_ASSERT_FAILED                            0x1e
2302 #define STATUS_INVALID_SESSION                          0x1f
2303 #define STATUS_INVALID_CONNECTION                       0x20
2304 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT               0x21
2305 #define STATUS_BTL_NO_FREE_SLOT_PATH                    0x24
2306 #define STATUS_BTL_NO_FREE_SLOT_TGTID                   0x25
2307 #define STATUS_OSM_DEVSLOT_NOT_FOUND                    0x26
2308 #define STATUS_FLASHROM_READ_FAILED                     0x27
2309 #define STATUS_POLL_IOCTL_TIMEOUT                       0x28
2310 #define STATUS_ERROR_ACITMAIN                           0x2a
2311 #define STATUS_REBOOT_REQUIRED                          0x2c
2312 #define STATUS_FCF_IN_USE                               0x3a
2313 #define STATUS_FCF_TABLE_EMPTY                          0x43
2314
2315 /*
2316  * Additional status field for embedded SLI_CONFIG mailbox
2317  * command.
2318  */
2319 #define ADD_STATUS_OPERATION_ALREADY_ACTIVE             0x67
2320 #define ADD_STATUS_FW_NOT_SUPPORTED                     0xEB
2321 #define ADD_STATUS_INVALID_REQUEST                      0x4B
2322 #define ADD_STATUS_FW_DOWNLOAD_HW_DISABLED              0x58
2323
2324 struct lpfc_mbx_sli4_config {
2325         struct mbox_header header;
2326 };
2327
2328 struct lpfc_mbx_init_vfi {
2329         uint32_t word1;
2330 #define lpfc_init_vfi_vr_SHIFT          31
2331 #define lpfc_init_vfi_vr_MASK           0x00000001
2332 #define lpfc_init_vfi_vr_WORD           word1
2333 #define lpfc_init_vfi_vt_SHIFT          30
2334 #define lpfc_init_vfi_vt_MASK           0x00000001
2335 #define lpfc_init_vfi_vt_WORD           word1
2336 #define lpfc_init_vfi_vf_SHIFT          29
2337 #define lpfc_init_vfi_vf_MASK           0x00000001
2338 #define lpfc_init_vfi_vf_WORD           word1
2339 #define lpfc_init_vfi_vp_SHIFT          28
2340 #define lpfc_init_vfi_vp_MASK           0x00000001
2341 #define lpfc_init_vfi_vp_WORD           word1
2342 #define lpfc_init_vfi_vfi_SHIFT         0
2343 #define lpfc_init_vfi_vfi_MASK          0x0000FFFF
2344 #define lpfc_init_vfi_vfi_WORD          word1
2345         uint32_t word2;
2346 #define lpfc_init_vfi_vpi_SHIFT         16
2347 #define lpfc_init_vfi_vpi_MASK          0x0000FFFF
2348 #define lpfc_init_vfi_vpi_WORD          word2
2349 #define lpfc_init_vfi_fcfi_SHIFT        0
2350 #define lpfc_init_vfi_fcfi_MASK         0x0000FFFF
2351 #define lpfc_init_vfi_fcfi_WORD         word2
2352         uint32_t word3;
2353 #define lpfc_init_vfi_pri_SHIFT         13
2354 #define lpfc_init_vfi_pri_MASK          0x00000007
2355 #define lpfc_init_vfi_pri_WORD          word3
2356 #define lpfc_init_vfi_vf_id_SHIFT       1
2357 #define lpfc_init_vfi_vf_id_MASK        0x00000FFF
2358 #define lpfc_init_vfi_vf_id_WORD        word3
2359         uint32_t word4;
2360 #define lpfc_init_vfi_hop_count_SHIFT   24
2361 #define lpfc_init_vfi_hop_count_MASK    0x000000FF
2362 #define lpfc_init_vfi_hop_count_WORD    word4
2363 };
2364 #define MBX_VFI_IN_USE                  0x9F02
2365
2366
2367 struct lpfc_mbx_reg_vfi {
2368         uint32_t word1;
2369 #define lpfc_reg_vfi_upd_SHIFT          29
2370 #define lpfc_reg_vfi_upd_MASK           0x00000001
2371 #define lpfc_reg_vfi_upd_WORD           word1
2372 #define lpfc_reg_vfi_vp_SHIFT           28
2373 #define lpfc_reg_vfi_vp_MASK            0x00000001
2374 #define lpfc_reg_vfi_vp_WORD            word1
2375 #define lpfc_reg_vfi_vfi_SHIFT          0
2376 #define lpfc_reg_vfi_vfi_MASK           0x0000FFFF
2377 #define lpfc_reg_vfi_vfi_WORD           word1
2378         uint32_t word2;
2379 #define lpfc_reg_vfi_vpi_SHIFT          16
2380 #define lpfc_reg_vfi_vpi_MASK           0x0000FFFF
2381 #define lpfc_reg_vfi_vpi_WORD           word2
2382 #define lpfc_reg_vfi_fcfi_SHIFT         0
2383 #define lpfc_reg_vfi_fcfi_MASK          0x0000FFFF
2384 #define lpfc_reg_vfi_fcfi_WORD          word2
2385         uint32_t wwn[2];
2386         struct ulp_bde64 bde;
2387         uint32_t e_d_tov;
2388         uint32_t r_a_tov;
2389         uint32_t word10;
2390 #define lpfc_reg_vfi_nport_id_SHIFT     0
2391 #define lpfc_reg_vfi_nport_id_MASK      0x00FFFFFF
2392 #define lpfc_reg_vfi_nport_id_WORD      word10
2393 #define lpfc_reg_vfi_bbcr_SHIFT         27
2394 #define lpfc_reg_vfi_bbcr_MASK          0x00000001
2395 #define lpfc_reg_vfi_bbcr_WORD          word10
2396 #define lpfc_reg_vfi_bbscn_SHIFT        28
2397 #define lpfc_reg_vfi_bbscn_MASK         0x0000000F
2398 #define lpfc_reg_vfi_bbscn_WORD         word10
2399 };
2400
2401 struct lpfc_mbx_init_vpi {
2402         uint32_t word1;
2403 #define lpfc_init_vpi_vfi_SHIFT         16
2404 #define lpfc_init_vpi_vfi_MASK          0x0000FFFF
2405 #define lpfc_init_vpi_vfi_WORD          word1
2406 #define lpfc_init_vpi_vpi_SHIFT         0
2407 #define lpfc_init_vpi_vpi_MASK          0x0000FFFF
2408 #define lpfc_init_vpi_vpi_WORD          word1
2409 };
2410
2411 struct lpfc_mbx_read_vpi {
2412         uint32_t word1_rsvd;
2413         uint32_t word2;
2414 #define lpfc_mbx_read_vpi_vnportid_SHIFT        0
2415 #define lpfc_mbx_read_vpi_vnportid_MASK         0x00FFFFFF
2416 #define lpfc_mbx_read_vpi_vnportid_WORD         word2
2417         uint32_t word3_rsvd;
2418         uint32_t word4;
2419 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT        0
2420 #define lpfc_mbx_read_vpi_acq_alpa_MASK         0x000000FF
2421 #define lpfc_mbx_read_vpi_acq_alpa_WORD         word4
2422 #define lpfc_mbx_read_vpi_pb_SHIFT              15
2423 #define lpfc_mbx_read_vpi_pb_MASK               0x00000001
2424 #define lpfc_mbx_read_vpi_pb_WORD               word4
2425 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT       16
2426 #define lpfc_mbx_read_vpi_spec_alpa_MASK        0x000000FF
2427 #define lpfc_mbx_read_vpi_spec_alpa_WORD        word4
2428 #define lpfc_mbx_read_vpi_ns_SHIFT              30
2429 #define lpfc_mbx_read_vpi_ns_MASK               0x00000001
2430 #define lpfc_mbx_read_vpi_ns_WORD               word4
2431 #define lpfc_mbx_read_vpi_hl_SHIFT              31
2432 #define lpfc_mbx_read_vpi_hl_MASK               0x00000001
2433 #define lpfc_mbx_read_vpi_hl_WORD               word4
2434         uint32_t word5_rsvd;
2435         uint32_t word6;
2436 #define lpfc_mbx_read_vpi_vpi_SHIFT             0
2437 #define lpfc_mbx_read_vpi_vpi_MASK              0x0000FFFF
2438 #define lpfc_mbx_read_vpi_vpi_WORD              word6
2439         uint32_t word7;
2440 #define lpfc_mbx_read_vpi_mac_0_SHIFT           0
2441 #define lpfc_mbx_read_vpi_mac_0_MASK            0x000000FF
2442 #define lpfc_mbx_read_vpi_mac_0_WORD            word7
2443 #define lpfc_mbx_read_vpi_mac_1_SHIFT           8
2444 #define lpfc_mbx_read_vpi_mac_1_MASK            0x000000FF
2445 #define lpfc_mbx_read_vpi_mac_1_WORD            word7
2446 #define lpfc_mbx_read_vpi_mac_2_SHIFT           16
2447 #define lpfc_mbx_read_vpi_mac_2_MASK            0x000000FF
2448 #define lpfc_mbx_read_vpi_mac_2_WORD            word7
2449 #define lpfc_mbx_read_vpi_mac_3_SHIFT           24
2450 #define lpfc_mbx_read_vpi_mac_3_MASK            0x000000FF
2451 #define lpfc_mbx_read_vpi_mac_3_WORD            word7
2452         uint32_t word8;
2453 #define lpfc_mbx_read_vpi_mac_4_SHIFT           0
2454 #define lpfc_mbx_read_vpi_mac_4_MASK            0x000000FF
2455 #define lpfc_mbx_read_vpi_mac_4_WORD            word8
2456 #define lpfc_mbx_read_vpi_mac_5_SHIFT           8
2457 #define lpfc_mbx_read_vpi_mac_5_MASK            0x000000FF
2458 #define lpfc_mbx_read_vpi_mac_5_WORD            word8
2459 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT        16
2460 #define lpfc_mbx_read_vpi_vlan_tag_MASK         0x00000FFF
2461 #define lpfc_mbx_read_vpi_vlan_tag_WORD         word8
2462 #define lpfc_mbx_read_vpi_vv_SHIFT              28
2463 #define lpfc_mbx_read_vpi_vv_MASK               0x0000001
2464 #define lpfc_mbx_read_vpi_vv_WORD               word8
2465 };
2466
2467 struct lpfc_mbx_unreg_vfi {
2468         uint32_t word1_rsvd;
2469         uint32_t word2;
2470 #define lpfc_unreg_vfi_vfi_SHIFT        0
2471 #define lpfc_unreg_vfi_vfi_MASK         0x0000FFFF
2472 #define lpfc_unreg_vfi_vfi_WORD         word2
2473 };
2474
2475 struct lpfc_mbx_resume_rpi {
2476         uint32_t word1;
2477 #define lpfc_resume_rpi_index_SHIFT     0
2478 #define lpfc_resume_rpi_index_MASK      0x0000FFFF
2479 #define lpfc_resume_rpi_index_WORD      word1
2480 #define lpfc_resume_rpi_ii_SHIFT        30
2481 #define lpfc_resume_rpi_ii_MASK         0x00000003
2482 #define lpfc_resume_rpi_ii_WORD         word1
2483 #define RESUME_INDEX_RPI                0
2484 #define RESUME_INDEX_VPI                1
2485 #define RESUME_INDEX_VFI                2
2486 #define RESUME_INDEX_FCFI               3
2487         uint32_t event_tag;
2488 };
2489
2490 #define REG_FCF_INVALID_QID     0xFFFF
2491 struct lpfc_mbx_reg_fcfi {
2492         uint32_t word1;
2493 #define lpfc_reg_fcfi_info_index_SHIFT  0
2494 #define lpfc_reg_fcfi_info_index_MASK   0x0000FFFF
2495 #define lpfc_reg_fcfi_info_index_WORD   word1
2496 #define lpfc_reg_fcfi_fcfi_SHIFT        16
2497 #define lpfc_reg_fcfi_fcfi_MASK         0x0000FFFF
2498 #define lpfc_reg_fcfi_fcfi_WORD         word1
2499         uint32_t word2;
2500 #define lpfc_reg_fcfi_rq_id1_SHIFT      0
2501 #define lpfc_reg_fcfi_rq_id1_MASK       0x0000FFFF
2502 #define lpfc_reg_fcfi_rq_id1_WORD       word2
2503 #define lpfc_reg_fcfi_rq_id0_SHIFT      16
2504 #define lpfc_reg_fcfi_rq_id0_MASK       0x0000FFFF
2505 #define lpfc_reg_fcfi_rq_id0_WORD       word2
2506         uint32_t word3;
2507 #define lpfc_reg_fcfi_rq_id3_SHIFT      0
2508 #define lpfc_reg_fcfi_rq_id3_MASK       0x0000FFFF
2509 #define lpfc_reg_fcfi_rq_id3_WORD       word3
2510 #define lpfc_reg_fcfi_rq_id2_SHIFT      16
2511 #define lpfc_reg_fcfi_rq_id2_MASK       0x0000FFFF
2512 #define lpfc_reg_fcfi_rq_id2_WORD       word3
2513         uint32_t word4;
2514 #define lpfc_reg_fcfi_type_match0_SHIFT 24
2515 #define lpfc_reg_fcfi_type_match0_MASK  0x000000FF
2516 #define lpfc_reg_fcfi_type_match0_WORD  word4
2517 #define lpfc_reg_fcfi_type_mask0_SHIFT  16
2518 #define lpfc_reg_fcfi_type_mask0_MASK   0x000000FF
2519 #define lpfc_reg_fcfi_type_mask0_WORD   word4
2520 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8
2521 #define lpfc_reg_fcfi_rctl_match0_MASK  0x000000FF
2522 #define lpfc_reg_fcfi_rctl_match0_WORD  word4
2523 #define lpfc_reg_fcfi_rctl_mask0_SHIFT  0
2524 #define lpfc_reg_fcfi_rctl_mask0_MASK   0x000000FF
2525 #define lpfc_reg_fcfi_rctl_mask0_WORD   word4
2526         uint32_t word5;
2527 #define lpfc_reg_fcfi_type_match1_SHIFT 24
2528 #define lpfc_reg_fcfi_type_match1_MASK  0x000000FF
2529 #define lpfc_reg_fcfi_type_match1_WORD  word5
2530 #define lpfc_reg_fcfi_type_mask1_SHIFT  16
2531 #define lpfc_reg_fcfi_type_mask1_MASK   0x000000FF
2532 #define lpfc_reg_fcfi_type_mask1_WORD   word5
2533 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8
2534 #define lpfc_reg_fcfi_rctl_match1_MASK  0x000000FF
2535 #define lpfc_reg_fcfi_rctl_match1_WORD  word5
2536 #define lpfc_reg_fcfi_rctl_mask1_SHIFT  0
2537 #define lpfc_reg_fcfi_rctl_mask1_MASK   0x000000FF
2538 #define lpfc_reg_fcfi_rctl_mask1_WORD   word5
2539         uint32_t word6;
2540 #define lpfc_reg_fcfi_type_match2_SHIFT 24
2541 #define lpfc_reg_fcfi_type_match2_MASK  0x000000FF
2542 #define lpfc_reg_fcfi_type_match2_WORD  word6
2543 #define lpfc_reg_fcfi_type_mask2_SHIFT  16
2544 #define lpfc_reg_fcfi_type_mask2_MASK   0x000000FF
2545 #define lpfc_reg_fcfi_type_mask2_WORD   word6
2546 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8
2547 #define lpfc_reg_fcfi_rctl_match2_MASK  0x000000FF
2548 #define lpfc_reg_fcfi_rctl_match2_WORD  word6
2549 #define lpfc_reg_fcfi_rctl_mask2_SHIFT  0
2550 #define lpfc_reg_fcfi_rctl_mask2_MASK   0x000000FF
2551 #define lpfc_reg_fcfi_rctl_mask2_WORD   word6
2552         uint32_t word7;
2553 #define lpfc_reg_fcfi_type_match3_SHIFT 24
2554 #define lpfc_reg_fcfi_type_match3_MASK  0x000000FF
2555 #define lpfc_reg_fcfi_type_match3_WORD  word7
2556 #define lpfc_reg_fcfi_type_mask3_SHIFT  16
2557 #define lpfc_reg_fcfi_type_mask3_MASK   0x000000FF
2558 #define lpfc_reg_fcfi_type_mask3_WORD   word7
2559 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8
2560 #define lpfc_reg_fcfi_rctl_match3_MASK  0x000000FF
2561 #define lpfc_reg_fcfi_rctl_match3_WORD  word7
2562 #define lpfc_reg_fcfi_rctl_mask3_SHIFT  0
2563 #define lpfc_reg_fcfi_rctl_mask3_MASK   0x000000FF
2564 #define lpfc_reg_fcfi_rctl_mask3_WORD   word7
2565         uint32_t word8;
2566 #define lpfc_reg_fcfi_mam_SHIFT         13
2567 #define lpfc_reg_fcfi_mam_MASK          0x00000003
2568 #define lpfc_reg_fcfi_mam_WORD          word8
2569 #define LPFC_MAM_BOTH           0       /* Both SPMA and FPMA */
2570 #define LPFC_MAM_SPMA           1       /* Server Provided MAC Address */
2571 #define LPFC_MAM_FPMA           2       /* Fabric Provided MAC Address */
2572 #define lpfc_reg_fcfi_vv_SHIFT          12
2573 #define lpfc_reg_fcfi_vv_MASK           0x00000001
2574 #define lpfc_reg_fcfi_vv_WORD           word8
2575 #define lpfc_reg_fcfi_vlan_tag_SHIFT    0
2576 #define lpfc_reg_fcfi_vlan_tag_MASK     0x00000FFF
2577 #define lpfc_reg_fcfi_vlan_tag_WORD     word8
2578 };
2579
2580 struct lpfc_mbx_reg_fcfi_mrq {
2581         uint32_t word1;
2582 #define lpfc_reg_fcfi_mrq_info_index_SHIFT      0
2583 #define lpfc_reg_fcfi_mrq_info_index_MASK       0x0000FFFF
2584 #define lpfc_reg_fcfi_mrq_info_index_WORD       word1
2585 #define lpfc_reg_fcfi_mrq_fcfi_SHIFT            16
2586 #define lpfc_reg_fcfi_mrq_fcfi_MASK             0x0000FFFF
2587 #define lpfc_reg_fcfi_mrq_fcfi_WORD             word1
2588         uint32_t word2;
2589 #define lpfc_reg_fcfi_mrq_rq_id1_SHIFT          0
2590 #define lpfc_reg_fcfi_mrq_rq_id1_MASK           0x0000FFFF
2591 #define lpfc_reg_fcfi_mrq_rq_id1_WORD           word2
2592 #define lpfc_reg_fcfi_mrq_rq_id0_SHIFT          16
2593 #define lpfc_reg_fcfi_mrq_rq_id0_MASK           0x0000FFFF
2594 #define lpfc_reg_fcfi_mrq_rq_id0_WORD           word2
2595         uint32_t word3;
2596 #define lpfc_reg_fcfi_mrq_rq_id3_SHIFT          0
2597 #define lpfc_reg_fcfi_mrq_rq_id3_MASK           0x0000FFFF
2598 #define lpfc_reg_fcfi_mrq_rq_id3_WORD           word3
2599 #define lpfc_reg_fcfi_mrq_rq_id2_SHIFT          16
2600 #define lpfc_reg_fcfi_mrq_rq_id2_MASK           0x0000FFFF
2601 #define lpfc_reg_fcfi_mrq_rq_id2_WORD           word3
2602         uint32_t word4;
2603 #define lpfc_reg_fcfi_mrq_type_match0_SHIFT     24
2604 #define lpfc_reg_fcfi_mrq_type_match0_MASK      0x000000FF
2605 #define lpfc_reg_fcfi_mrq_type_match0_WORD      word4
2606 #define lpfc_reg_fcfi_mrq_type_mask0_SHIFT      16
2607 #define lpfc_reg_fcfi_mrq_type_mask0_MASK       0x000000FF
2608 #define lpfc_reg_fcfi_mrq_type_mask0_WORD       word4
2609 #define lpfc_reg_fcfi_mrq_rctl_match0_SHIFT     8
2610 #define lpfc_reg_fcfi_mrq_rctl_match0_MASK      0x000000FF
2611 #define lpfc_reg_fcfi_mrq_rctl_match0_WORD      word4
2612 #define lpfc_reg_fcfi_mrq_rctl_mask0_SHIFT      0
2613 #define lpfc_reg_fcfi_mrq_rctl_mask0_MASK       0x000000FF
2614 #define lpfc_reg_fcfi_mrq_rctl_mask0_WORD       word4
2615         uint32_t word5;
2616 #define lpfc_reg_fcfi_mrq_type_match1_SHIFT     24
2617 #define lpfc_reg_fcfi_mrq_type_match1_MASK      0x000000FF
2618 #define lpfc_reg_fcfi_mrq_type_match1_WORD      word5
2619 #define lpfc_reg_fcfi_mrq_type_mask1_SHIFT      16
2620 #define lpfc_reg_fcfi_mrq_type_mask1_MASK       0x000000FF
2621 #define lpfc_reg_fcfi_mrq_type_mask1_WORD       word5
2622 #define lpfc_reg_fcfi_mrq_rctl_match1_SHIFT     8
2623 #define lpfc_reg_fcfi_mrq_rctl_match1_MASK      0x000000FF
2624 #define lpfc_reg_fcfi_mrq_rctl_match1_WORD      word5
2625 #define lpfc_reg_fcfi_mrq_rctl_mask1_SHIFT      0
2626 #define lpfc_reg_fcfi_mrq_rctl_mask1_MASK       0x000000FF
2627 #define lpfc_reg_fcfi_mrq_rctl_mask1_WORD       word5
2628         uint32_t word6;
2629 #define lpfc_reg_fcfi_mrq_type_match2_SHIFT     24
2630 #define lpfc_reg_fcfi_mrq_type_match2_MASK      0x000000FF
2631 #define lpfc_reg_fcfi_mrq_type_match2_WORD      word6
2632 #define lpfc_reg_fcfi_mrq_type_mask2_SHIFT      16
2633 #define lpfc_reg_fcfi_mrq_type_mask2_MASK       0x000000FF
2634 #define lpfc_reg_fcfi_mrq_type_mask2_WORD       word6
2635 #define lpfc_reg_fcfi_mrq_rctl_match2_SHIFT     8
2636 #define lpfc_reg_fcfi_mrq_rctl_match2_MASK      0x000000FF
2637 #define lpfc_reg_fcfi_mrq_rctl_match2_WORD      word6
2638 #define lpfc_reg_fcfi_mrq_rctl_mask2_SHIFT      0
2639 #define lpfc_reg_fcfi_mrq_rctl_mask2_MASK       0x000000FF
2640 #define lpfc_reg_fcfi_mrq_rctl_mask2_WORD       word6
2641         uint32_t word7;
2642 #define lpfc_reg_fcfi_mrq_type_match3_SHIFT     24
2643 #define lpfc_reg_fcfi_mrq_type_match3_MASK      0x000000FF
2644 #define lpfc_reg_fcfi_mrq_type_match3_WORD      word7
2645 #define lpfc_reg_fcfi_mrq_type_mask3_SHIFT      16
2646 #define lpfc_reg_fcfi_mrq_type_mask3_MASK       0x000000FF
2647 #define lpfc_reg_fcfi_mrq_type_mask3_WORD       word7
2648 #define lpfc_reg_fcfi_mrq_rctl_match3_SHIFT     8
2649 #define lpfc_reg_fcfi_mrq_rctl_match3_MASK      0x000000FF
2650 #define lpfc_reg_fcfi_mrq_rctl_match3_WORD      word7
2651 #define lpfc_reg_fcfi_mrq_rctl_mask3_SHIFT      0
2652 #define lpfc_reg_fcfi_mrq_rctl_mask3_MASK       0x000000FF
2653 #define lpfc_reg_fcfi_mrq_rctl_mask3_WORD       word7
2654         uint32_t word8;
2655 #define lpfc_reg_fcfi_mrq_ptc7_SHIFT            31
2656 #define lpfc_reg_fcfi_mrq_ptc7_MASK             0x00000001
2657 #define lpfc_reg_fcfi_mrq_ptc7_WORD             word8
2658 #define lpfc_reg_fcfi_mrq_ptc6_SHIFT            30
2659 #define lpfc_reg_fcfi_mrq_ptc6_MASK             0x00000001
2660 #define lpfc_reg_fcfi_mrq_ptc6_WORD             word8
2661 #define lpfc_reg_fcfi_mrq_ptc5_SHIFT            29
2662 #define lpfc_reg_fcfi_mrq_ptc5_MASK             0x00000001
2663 #define lpfc_reg_fcfi_mrq_ptc5_WORD             word8
2664 #define lpfc_reg_fcfi_mrq_ptc4_SHIFT            28
2665 #define lpfc_reg_fcfi_mrq_ptc4_MASK             0x00000001
2666 #define lpfc_reg_fcfi_mrq_ptc4_WORD             word8
2667 #define lpfc_reg_fcfi_mrq_ptc3_SHIFT            27
2668 #define lpfc_reg_fcfi_mrq_ptc3_MASK             0x00000001
2669 #define lpfc_reg_fcfi_mrq_ptc3_WORD             word8
2670 #define lpfc_reg_fcfi_mrq_ptc2_SHIFT            26
2671 #define lpfc_reg_fcfi_mrq_ptc2_MASK             0x00000001
2672 #define lpfc_reg_fcfi_mrq_ptc2_WORD             word8
2673 #define lpfc_reg_fcfi_mrq_ptc1_SHIFT            25
2674 #define lpfc_reg_fcfi_mrq_ptc1_MASK             0x00000001
2675 #define lpfc_reg_fcfi_mrq_ptc1_WORD             word8
2676 #define lpfc_reg_fcfi_mrq_ptc0_SHIFT            24
2677 #define lpfc_reg_fcfi_mrq_ptc0_MASK             0x00000001
2678 #define lpfc_reg_fcfi_mrq_ptc0_WORD             word8
2679 #define lpfc_reg_fcfi_mrq_pt7_SHIFT             23
2680 #define lpfc_reg_fcfi_mrq_pt7_MASK              0x00000001
2681 #define lpfc_reg_fcfi_mrq_pt7_WORD              word8
2682 #define lpfc_reg_fcfi_mrq_pt6_SHIFT             22
2683 #define lpfc_reg_fcfi_mrq_pt6_MASK              0x00000001
2684 #define lpfc_reg_fcfi_mrq_pt6_WORD              word8
2685 #define lpfc_reg_fcfi_mrq_pt5_SHIFT             21
2686 #define lpfc_reg_fcfi_mrq_pt5_MASK              0x00000001
2687 #define lpfc_reg_fcfi_mrq_pt5_WORD              word8
2688 #define lpfc_reg_fcfi_mrq_pt4_SHIFT             20
2689 #define lpfc_reg_fcfi_mrq_pt4_MASK              0x00000001
2690 #define lpfc_reg_fcfi_mrq_pt4_WORD              word8
2691 #define lpfc_reg_fcfi_mrq_pt3_SHIFT             19
2692 #define lpfc_reg_fcfi_mrq_pt3_MASK              0x00000001
2693 #define lpfc_reg_fcfi_mrq_pt3_WORD              word8
2694 #define lpfc_reg_fcfi_mrq_pt2_SHIFT             18
2695 #define lpfc_reg_fcfi_mrq_pt2_MASK              0x00000001
2696 #define lpfc_reg_fcfi_mrq_pt2_WORD              word8
2697 #define lpfc_reg_fcfi_mrq_pt1_SHIFT             17
2698 #define lpfc_reg_fcfi_mrq_pt1_MASK              0x00000001
2699 #define lpfc_reg_fcfi_mrq_pt1_WORD              word8
2700 #define lpfc_reg_fcfi_mrq_pt0_SHIFT             16
2701 #define lpfc_reg_fcfi_mrq_pt0_MASK              0x00000001
2702 #define lpfc_reg_fcfi_mrq_pt0_WORD              word8
2703 #define lpfc_reg_fcfi_mrq_xmv_SHIFT             15
2704 #define lpfc_reg_fcfi_mrq_xmv_MASK              0x00000001
2705 #define lpfc_reg_fcfi_mrq_xmv_WORD              word8
2706 #define lpfc_reg_fcfi_mrq_mode_SHIFT            13
2707 #define lpfc_reg_fcfi_mrq_mode_MASK             0x00000001
2708 #define lpfc_reg_fcfi_mrq_mode_WORD             word8
2709 #define lpfc_reg_fcfi_mrq_vv_SHIFT              12
2710 #define lpfc_reg_fcfi_mrq_vv_MASK               0x00000001
2711 #define lpfc_reg_fcfi_mrq_vv_WORD               word8
2712 #define lpfc_reg_fcfi_mrq_vlan_tag_SHIFT        0
2713 #define lpfc_reg_fcfi_mrq_vlan_tag_MASK         0x00000FFF
2714 #define lpfc_reg_fcfi_mrq_vlan_tag_WORD         word8
2715         uint32_t word9;
2716 #define lpfc_reg_fcfi_mrq_policy_SHIFT          12
2717 #define lpfc_reg_fcfi_mrq_policy_MASK           0x0000000F
2718 #define lpfc_reg_fcfi_mrq_policy_WORD           word9
2719 #define lpfc_reg_fcfi_mrq_filter_SHIFT          8
2720 #define lpfc_reg_fcfi_mrq_filter_MASK           0x0000000F
2721 #define lpfc_reg_fcfi_mrq_filter_WORD           word9
2722 #define lpfc_reg_fcfi_mrq_npairs_SHIFT          0
2723 #define lpfc_reg_fcfi_mrq_npairs_MASK           0x000000FF
2724 #define lpfc_reg_fcfi_mrq_npairs_WORD           word9
2725         uint32_t word10;
2726         uint32_t word11;
2727         uint32_t word12;
2728         uint32_t word13;
2729         uint32_t word14;
2730         uint32_t word15;
2731         uint32_t word16;
2732 };
2733
2734 struct lpfc_mbx_unreg_fcfi {
2735         uint32_t word1_rsv;
2736         uint32_t word2;
2737 #define lpfc_unreg_fcfi_SHIFT           0
2738 #define lpfc_unreg_fcfi_MASK            0x0000FFFF
2739 #define lpfc_unreg_fcfi_WORD            word2
2740 };
2741
2742 struct lpfc_mbx_read_rev {
2743         uint32_t word1;
2744 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT           16
2745 #define lpfc_mbx_rd_rev_sli_lvl_MASK            0x0000000F
2746 #define lpfc_mbx_rd_rev_sli_lvl_WORD            word1
2747 #define lpfc_mbx_rd_rev_fcoe_SHIFT              20
2748 #define lpfc_mbx_rd_rev_fcoe_MASK               0x00000001
2749 #define lpfc_mbx_rd_rev_fcoe_WORD               word1
2750 #define lpfc_mbx_rd_rev_cee_ver_SHIFT           21
2751 #define lpfc_mbx_rd_rev_cee_ver_MASK            0x00000003
2752 #define lpfc_mbx_rd_rev_cee_ver_WORD            word1
2753 #define LPFC_PREDCBX_CEE_MODE   0
2754 #define LPFC_DCBX_CEE_MODE      1
2755 #define lpfc_mbx_rd_rev_vpd_SHIFT               29
2756 #define lpfc_mbx_rd_rev_vpd_MASK                0x00000001
2757 #define lpfc_mbx_rd_rev_vpd_WORD                word1
2758         uint32_t first_hw_rev;
2759 #define LPFC_G7_ASIC_1                          0xd
2760         uint32_t second_hw_rev;
2761         uint32_t word4_rsvd;
2762         uint32_t third_hw_rev;
2763         uint32_t word6;
2764 #define lpfc_mbx_rd_rev_fcph_low_SHIFT          0
2765 #define lpfc_mbx_rd_rev_fcph_low_MASK           0x000000FF
2766 #define lpfc_mbx_rd_rev_fcph_low_WORD           word6
2767 #define lpfc_mbx_rd_rev_fcph_high_SHIFT         8
2768 #define lpfc_mbx_rd_rev_fcph_high_MASK          0x000000FF
2769 #define lpfc_mbx_rd_rev_fcph_high_WORD          word6
2770 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT       16
2771 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK        0x000000FF
2772 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD        word6
2773 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT      24
2774 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK       0x000000FF
2775 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD       word6
2776         uint32_t word7_rsvd;
2777         uint32_t fw_id_rev;
2778         uint8_t  fw_name[16];
2779         uint32_t ulp_fw_id_rev;
2780         uint8_t  ulp_fw_name[16];
2781         uint32_t word18_47_rsvd[30];
2782         uint32_t word48;
2783 #define lpfc_mbx_rd_rev_avail_len_SHIFT         0
2784 #define lpfc_mbx_rd_rev_avail_len_MASK          0x00FFFFFF
2785 #define lpfc_mbx_rd_rev_avail_len_WORD          word48
2786         uint32_t vpd_paddr_low;
2787         uint32_t vpd_paddr_high;
2788         uint32_t avail_vpd_len;
2789         uint32_t rsvd_52_63[12];
2790 };
2791
2792 struct lpfc_mbx_read_config {
2793         uint32_t word1;
2794 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT     31
2795 #define lpfc_mbx_rd_conf_extnts_inuse_MASK      0x00000001
2796 #define lpfc_mbx_rd_conf_extnts_inuse_WORD      word1
2797         uint32_t word2;
2798 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT         0
2799 #define lpfc_mbx_rd_conf_lnk_numb_MASK          0x0000003F
2800 #define lpfc_mbx_rd_conf_lnk_numb_WORD          word2
2801 #define lpfc_mbx_rd_conf_lnk_type_SHIFT         6
2802 #define lpfc_mbx_rd_conf_lnk_type_MASK          0x00000003
2803 #define lpfc_mbx_rd_conf_lnk_type_WORD          word2
2804 #define LPFC_LNK_TYPE_GE        0
2805 #define LPFC_LNK_TYPE_FC        1
2806 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT          8
2807 #define lpfc_mbx_rd_conf_lnk_ldv_MASK           0x00000001
2808 #define lpfc_mbx_rd_conf_lnk_ldv_WORD           word2
2809 #define lpfc_mbx_rd_conf_trunk_SHIFT            12
2810 #define lpfc_mbx_rd_conf_trunk_MASK             0x0000000F
2811 #define lpfc_mbx_rd_conf_trunk_WORD             word2
2812 #define lpfc_mbx_rd_conf_pt_SHIFT               20
2813 #define lpfc_mbx_rd_conf_pt_MASK                0x00000003
2814 #define lpfc_mbx_rd_conf_pt_WORD                word2
2815 #define lpfc_mbx_rd_conf_tf_SHIFT               22
2816 #define lpfc_mbx_rd_conf_tf_MASK                0x00000001
2817 #define lpfc_mbx_rd_conf_tf_WORD                word2
2818 #define lpfc_mbx_rd_conf_ptv_SHIFT              23
2819 #define lpfc_mbx_rd_conf_ptv_MASK               0x00000001
2820 #define lpfc_mbx_rd_conf_ptv_WORD               word2
2821 #define lpfc_mbx_rd_conf_topology_SHIFT         24
2822 #define lpfc_mbx_rd_conf_topology_MASK          0x000000FF
2823 #define lpfc_mbx_rd_conf_topology_WORD          word2
2824         uint32_t rsvd_3;
2825         uint32_t word4;
2826 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT          0
2827 #define lpfc_mbx_rd_conf_e_d_tov_MASK           0x0000FFFF
2828 #define lpfc_mbx_rd_conf_e_d_tov_WORD           word4
2829         uint32_t rsvd_5;
2830         uint32_t word6;
2831 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT          0
2832 #define lpfc_mbx_rd_conf_r_a_tov_MASK           0x0000FFFF
2833 #define lpfc_mbx_rd_conf_r_a_tov_WORD           word6
2834 #define lpfc_mbx_rd_conf_link_speed_SHIFT       16
2835 #define lpfc_mbx_rd_conf_link_speed_MASK        0x0000FFFF
2836 #define lpfc_mbx_rd_conf_link_speed_WORD        word6
2837         uint32_t rsvd_7;
2838         uint32_t word8;
2839 #define lpfc_mbx_rd_conf_bbscn_min_SHIFT        0
2840 #define lpfc_mbx_rd_conf_bbscn_min_MASK         0x0000000F
2841 #define lpfc_mbx_rd_conf_bbscn_min_WORD         word8
2842 #define lpfc_mbx_rd_conf_bbscn_max_SHIFT        4
2843 #define lpfc_mbx_rd_conf_bbscn_max_MASK         0x0000000F
2844 #define lpfc_mbx_rd_conf_bbscn_max_WORD         word8
2845 #define lpfc_mbx_rd_conf_bbscn_def_SHIFT        8
2846 #define lpfc_mbx_rd_conf_bbscn_def_MASK         0x0000000F
2847 #define lpfc_mbx_rd_conf_bbscn_def_WORD         word8
2848         uint32_t word9;
2849 #define lpfc_mbx_rd_conf_lmt_SHIFT              0
2850 #define lpfc_mbx_rd_conf_lmt_MASK               0x0000FFFF
2851 #define lpfc_mbx_rd_conf_lmt_WORD               word9
2852         uint32_t rsvd_10;
2853         uint32_t rsvd_11;
2854         uint32_t word12;
2855 #define lpfc_mbx_rd_conf_xri_base_SHIFT         0
2856 #define lpfc_mbx_rd_conf_xri_base_MASK          0x0000FFFF
2857 #define lpfc_mbx_rd_conf_xri_base_WORD          word12
2858 #define lpfc_mbx_rd_conf_xri_count_SHIFT        16
2859 #define lpfc_mbx_rd_conf_xri_count_MASK         0x0000FFFF
2860 #define lpfc_mbx_rd_conf_xri_count_WORD         word12
2861         uint32_t word13;
2862 #define lpfc_mbx_rd_conf_rpi_base_SHIFT         0
2863 #define lpfc_mbx_rd_conf_rpi_base_MASK          0x0000FFFF
2864 #define lpfc_mbx_rd_conf_rpi_base_WORD          word13
2865 #define lpfc_mbx_rd_conf_rpi_count_SHIFT        16
2866 #define lpfc_mbx_rd_conf_rpi_count_MASK         0x0000FFFF
2867 #define lpfc_mbx_rd_conf_rpi_count_WORD         word13
2868         uint32_t word14;
2869 #define lpfc_mbx_rd_conf_vpi_base_SHIFT         0
2870 #define lpfc_mbx_rd_conf_vpi_base_MASK          0x0000FFFF
2871 #define lpfc_mbx_rd_conf_vpi_base_WORD          word14
2872 #define lpfc_mbx_rd_conf_vpi_count_SHIFT        16
2873 #define lpfc_mbx_rd_conf_vpi_count_MASK         0x0000FFFF
2874 #define lpfc_mbx_rd_conf_vpi_count_WORD         word14
2875         uint32_t word15;
2876 #define lpfc_mbx_rd_conf_vfi_base_SHIFT         0
2877 #define lpfc_mbx_rd_conf_vfi_base_MASK          0x0000FFFF
2878 #define lpfc_mbx_rd_conf_vfi_base_WORD          word15
2879 #define lpfc_mbx_rd_conf_vfi_count_SHIFT        16
2880 #define lpfc_mbx_rd_conf_vfi_count_MASK         0x0000FFFF
2881 #define lpfc_mbx_rd_conf_vfi_count_WORD         word15
2882         uint32_t word16;
2883 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT       16
2884 #define lpfc_mbx_rd_conf_fcfi_count_MASK        0x0000FFFF
2885 #define lpfc_mbx_rd_conf_fcfi_count_WORD        word16
2886         uint32_t word17;
2887 #define lpfc_mbx_rd_conf_rq_count_SHIFT         0
2888 #define lpfc_mbx_rd_conf_rq_count_MASK          0x0000FFFF
2889 #define lpfc_mbx_rd_conf_rq_count_WORD          word17
2890 #define lpfc_mbx_rd_conf_eq_count_SHIFT         16
2891 #define lpfc_mbx_rd_conf_eq_count_MASK          0x0000FFFF
2892 #define lpfc_mbx_rd_conf_eq_count_WORD          word17
2893         uint32_t word18;
2894 #define lpfc_mbx_rd_conf_wq_count_SHIFT         0
2895 #define lpfc_mbx_rd_conf_wq_count_MASK          0x0000FFFF
2896 #define lpfc_mbx_rd_conf_wq_count_WORD          word18
2897 #define lpfc_mbx_rd_conf_cq_count_SHIFT         16
2898 #define lpfc_mbx_rd_conf_cq_count_MASK          0x0000FFFF
2899 #define lpfc_mbx_rd_conf_cq_count_WORD          word18
2900 };
2901
2902 struct lpfc_mbx_request_features {
2903         uint32_t word1;
2904 #define lpfc_mbx_rq_ftr_qry_SHIFT               0
2905 #define lpfc_mbx_rq_ftr_qry_MASK                0x00000001
2906 #define lpfc_mbx_rq_ftr_qry_WORD                word1
2907         uint32_t word2;
2908 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT           0
2909 #define lpfc_mbx_rq_ftr_rq_iaab_MASK            0x00000001
2910 #define lpfc_mbx_rq_ftr_rq_iaab_WORD            word2
2911 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT           1
2912 #define lpfc_mbx_rq_ftr_rq_npiv_MASK            0x00000001
2913 #define lpfc_mbx_rq_ftr_rq_npiv_WORD            word2
2914 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT            2
2915 #define lpfc_mbx_rq_ftr_rq_dif_MASK             0x00000001
2916 #define lpfc_mbx_rq_ftr_rq_dif_WORD             word2
2917 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT             3
2918 #define lpfc_mbx_rq_ftr_rq_vf_MASK              0x00000001
2919 #define lpfc_mbx_rq_ftr_rq_vf_WORD              word2
2920 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT           4
2921 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK            0x00000001
2922 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD            word2
2923 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT           5
2924 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK            0x00000001
2925 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD            word2
2926 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT           6
2927 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK            0x00000001
2928 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD            word2
2929 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT           7
2930 #define lpfc_mbx_rq_ftr_rq_ifip_MASK            0x00000001
2931 #define lpfc_mbx_rq_ftr_rq_ifip_WORD            word2
2932 #define lpfc_mbx_rq_ftr_rq_iaar_SHIFT           9
2933 #define lpfc_mbx_rq_ftr_rq_iaar_MASK            0x00000001
2934 #define lpfc_mbx_rq_ftr_rq_iaar_WORD            word2
2935 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT          11
2936 #define lpfc_mbx_rq_ftr_rq_perfh_MASK           0x00000001
2937 #define lpfc_mbx_rq_ftr_rq_perfh_WORD           word2
2938 #define lpfc_mbx_rq_ftr_rq_mrqp_SHIFT           16
2939 #define lpfc_mbx_rq_ftr_rq_mrqp_MASK            0x00000001
2940 #define lpfc_mbx_rq_ftr_rq_mrqp_WORD            word2
2941         uint32_t word3;
2942 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT          0
2943 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK           0x00000001
2944 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD           word3
2945 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT          1
2946 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK           0x00000001
2947 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD           word3
2948 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT           2
2949 #define lpfc_mbx_rq_ftr_rsp_dif_MASK            0x00000001
2950 #define lpfc_mbx_rq_ftr_rsp_dif_WORD            word3
2951 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT            3
2952 #define lpfc_mbx_rq_ftr_rsp_vf__MASK            0x00000001
2953 #define lpfc_mbx_rq_ftr_rsp_vf_WORD             word3
2954 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT          4
2955 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK           0x00000001
2956 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD           word3
2957 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT          5
2958 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK           0x00000001
2959 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD           word3
2960 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT          6
2961 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK           0x00000001
2962 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD           word3
2963 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT          7
2964 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK           0x00000001
2965 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD           word3
2966 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT         11
2967 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK          0x00000001
2968 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD          word3
2969 #define lpfc_mbx_rq_ftr_rsp_mrqp_SHIFT          16
2970 #define lpfc_mbx_rq_ftr_rsp_mrqp_MASK           0x00000001
2971 #define lpfc_mbx_rq_ftr_rsp_mrqp_WORD           word3
2972 };
2973
2974 struct lpfc_mbx_supp_pages {
2975         uint32_t word1;
2976 #define qs_SHIFT                                0
2977 #define qs_MASK                                 0x00000001
2978 #define qs_WORD                                 word1
2979 #define wr_SHIFT                                1
2980 #define wr_MASK                                 0x00000001
2981 #define wr_WORD                                 word1
2982 #define pf_SHIFT                                8
2983 #define pf_MASK                                 0x000000ff
2984 #define pf_WORD                                 word1
2985 #define cpn_SHIFT                               16
2986 #define cpn_MASK                                0x000000ff
2987 #define cpn_WORD                                word1
2988         uint32_t word2;
2989 #define list_offset_SHIFT                       0
2990 #define list_offset_MASK                        0x000000ff
2991 #define list_offset_WORD                        word2
2992 #define next_offset_SHIFT                       8
2993 #define next_offset_MASK                        0x000000ff
2994 #define next_offset_WORD                        word2
2995 #define elem_cnt_SHIFT                          16
2996 #define elem_cnt_MASK                           0x000000ff
2997 #define elem_cnt_WORD                           word2
2998         uint32_t word3;
2999 #define pn_0_SHIFT                              24
3000 #define pn_0_MASK                               0x000000ff
3001 #define pn_0_WORD                               word3
3002 #define pn_1_SHIFT                              16
3003 #define pn_1_MASK                               0x000000ff
3004 #define pn_1_WORD                               word3
3005 #define pn_2_SHIFT                              8
3006 #define pn_2_MASK                               0x000000ff
3007 #define pn_2_WORD                               word3
3008 #define pn_3_SHIFT                              0
3009 #define pn_3_MASK                               0x000000ff
3010 #define pn_3_WORD                               word3
3011         uint32_t word4;
3012 #define pn_4_SHIFT                              24
3013 #define pn_4_MASK                               0x000000ff
3014 #define pn_4_WORD                               word4
3015 #define pn_5_SHIFT                              16
3016 #define pn_5_MASK                               0x000000ff
3017 #define pn_5_WORD                               word4
3018 #define pn_6_SHIFT                              8
3019 #define pn_6_MASK                               0x000000ff
3020 #define pn_6_WORD                               word4
3021 #define pn_7_SHIFT                              0
3022 #define pn_7_MASK                               0x000000ff
3023 #define pn_7_WORD                               word4
3024         uint32_t rsvd[27];
3025 #define LPFC_SUPP_PAGES                 0
3026 #define LPFC_BLOCK_GUARD_PROFILES       1
3027 #define LPFC_SLI4_PARAMETERS            2
3028 };
3029
3030 struct lpfc_mbx_memory_dump_type3 {
3031         uint32_t word1;
3032 #define lpfc_mbx_memory_dump_type3_type_SHIFT    0
3033 #define lpfc_mbx_memory_dump_type3_type_MASK     0x0000000f
3034 #define lpfc_mbx_memory_dump_type3_type_WORD     word1
3035 #define lpfc_mbx_memory_dump_type3_link_SHIFT    24
3036 #define lpfc_mbx_memory_dump_type3_link_MASK     0x000000ff
3037 #define lpfc_mbx_memory_dump_type3_link_WORD     word1
3038         uint32_t word2;
3039 #define lpfc_mbx_memory_dump_type3_page_no_SHIFT  0
3040 #define lpfc_mbx_memory_dump_type3_page_no_MASK   0x0000ffff
3041 #define lpfc_mbx_memory_dump_type3_page_no_WORD   word2
3042 #define lpfc_mbx_memory_dump_type3_offset_SHIFT   16
3043 #define lpfc_mbx_memory_dump_type3_offset_MASK    0x0000ffff
3044 #define lpfc_mbx_memory_dump_type3_offset_WORD    word2
3045         uint32_t word3;
3046 #define lpfc_mbx_memory_dump_type3_length_SHIFT  0
3047 #define lpfc_mbx_memory_dump_type3_length_MASK   0x00ffffff
3048 #define lpfc_mbx_memory_dump_type3_length_WORD   word3
3049         uint32_t addr_lo;
3050         uint32_t addr_hi;
3051         uint32_t return_len;
3052 };
3053
3054 #define DMP_PAGE_A0             0xa0
3055 #define DMP_PAGE_A2             0xa2
3056 #define DMP_SFF_PAGE_A0_SIZE    256
3057 #define DMP_SFF_PAGE_A2_SIZE    256
3058
3059 #define SFP_WAVELENGTH_LC1310   1310
3060 #define SFP_WAVELENGTH_LL1550   1550
3061
3062
3063 /*
3064  *  * SFF-8472 TABLE 3.4
3065  *   */
3066 #define  SFF_PG0_CONNECTOR_UNKNOWN    0x00   /* Unknown  */
3067 #define  SFF_PG0_CONNECTOR_SC         0x01   /* SC       */
3068 #define  SFF_PG0_CONNECTOR_FC_COPPER1 0x02   /* FC style 1 copper connector */
3069 #define  SFF_PG0_CONNECTOR_FC_COPPER2 0x03   /* FC style 2 copper connector */
3070 #define  SFF_PG0_CONNECTOR_BNC        0x04   /* BNC / TNC */
3071 #define  SFF_PG0_CONNECTOR__FC_COAX   0x05   /* FC coaxial headers */
3072 #define  SFF_PG0_CONNECTOR_FIBERJACK  0x06   /* FiberJack */
3073 #define  SFF_PG0_CONNECTOR_LC         0x07   /* LC        */
3074 #define  SFF_PG0_CONNECTOR_MT         0x08   /* MT - RJ   */
3075 #define  SFF_PG0_CONNECTOR_MU         0x09   /* MU        */
3076 #define  SFF_PG0_CONNECTOR_SF         0x0A   /* SG        */
3077 #define  SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */
3078 #define  SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */
3079 #define  SFF_PG0_CONNECTOR_HSSDC_II   0x20   /* HSSDC II */
3080 #define  SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */
3081 #define  SFF_PG0_CONNECTOR_RJ45       0x22  /* RJ45 */
3082
3083 /* SFF-8472 Table 3.1 Diagnostics: Data Fields Address/Page A0 */
3084
3085 #define SSF_IDENTIFIER                  0
3086 #define SSF_EXT_IDENTIFIER              1
3087 #define SSF_CONNECTOR                   2
3088 #define SSF_TRANSCEIVER_CODE_B0         3
3089 #define SSF_TRANSCEIVER_CODE_B1         4
3090 #define SSF_TRANSCEIVER_CODE_B2         5
3091 #define SSF_TRANSCEIVER_CODE_B3         6
3092 #define SSF_TRANSCEIVER_CODE_B4         7
3093 #define SSF_TRANSCEIVER_CODE_B5         8
3094 #define SSF_TRANSCEIVER_CODE_B6         9
3095 #define SSF_TRANSCEIVER_CODE_B7         10
3096 #define SSF_ENCODING                    11
3097 #define SSF_BR_NOMINAL                  12
3098 #define SSF_RATE_IDENTIFIER             13
3099 #define SSF_LENGTH_9UM_KM               14
3100 #define SSF_LENGTH_9UM                  15
3101 #define SSF_LENGTH_50UM_OM2             16
3102 #define SSF_LENGTH_62UM_OM1             17
3103 #define SFF_LENGTH_COPPER               18
3104 #define SSF_LENGTH_50UM_OM3             19
3105 #define SSF_VENDOR_NAME                 20
3106 #define SSF_VENDOR_OUI                  36
3107 #define SSF_VENDOR_PN                   40
3108 #define SSF_VENDOR_REV                  56
3109 #define SSF_WAVELENGTH_B1               60
3110 #define SSF_WAVELENGTH_B0               61
3111 #define SSF_CC_BASE                     63
3112 #define SSF_OPTIONS_B1                  64
3113 #define SSF_OPTIONS_B0                  65
3114 #define SSF_BR_MAX                      66
3115 #define SSF_BR_MIN                      67
3116 #define SSF_VENDOR_SN                   68
3117 #define SSF_DATE_CODE                   84
3118 #define SSF_MONITORING_TYPEDIAGNOSTIC   92
3119 #define SSF_ENHANCED_OPTIONS            93
3120 #define SFF_8472_COMPLIANCE             94
3121 #define SSF_CC_EXT                      95
3122 #define SSF_A0_VENDOR_SPECIFIC          96
3123
3124 /* SFF-8472 Table 3.1a Diagnostics: Data Fields Address/Page A2 */
3125
3126 #define SSF_TEMP_HIGH_ALARM             0
3127 #define SSF_TEMP_LOW_ALARM              2
3128 #define SSF_TEMP_HIGH_WARNING           4
3129 #define SSF_TEMP_LOW_WARNING            6
3130 #define SSF_VOLTAGE_HIGH_ALARM          8
3131 #define SSF_VOLTAGE_LOW_ALARM           10
3132 #define SSF_VOLTAGE_HIGH_WARNING        12
3133 #define SSF_VOLTAGE_LOW_WARNING         14
3134 #define SSF_BIAS_HIGH_ALARM             16
3135 #define SSF_BIAS_LOW_ALARM              18
3136 #define SSF_BIAS_HIGH_WARNING           20
3137 #define SSF_BIAS_LOW_WARNING            22
3138 #define SSF_TXPOWER_HIGH_ALARM          24
3139 #define SSF_TXPOWER_LOW_ALARM           26
3140 #define SSF_TXPOWER_HIGH_WARNING        28
3141 #define SSF_TXPOWER_LOW_WARNING         30
3142 #define SSF_RXPOWER_HIGH_ALARM          32
3143 #define SSF_RXPOWER_LOW_ALARM           34
3144 #define SSF_RXPOWER_HIGH_WARNING        36
3145 #define SSF_RXPOWER_LOW_WARNING         38
3146 #define SSF_EXT_CAL_CONSTANTS           56
3147 #define SSF_CC_DMI                      95
3148 #define SFF_TEMPERATURE_B1              96
3149 #define SFF_TEMPERATURE_B0              97
3150 #define SFF_VCC_B1                      98
3151 #define SFF_VCC_B0                      99
3152 #define SFF_TX_BIAS_CURRENT_B1          100
3153 #define SFF_TX_BIAS_CURRENT_B0          101
3154 #define SFF_TXPOWER_B1                  102
3155 #define SFF_TXPOWER_B0                  103
3156 #define SFF_RXPOWER_B1                  104
3157 #define SFF_RXPOWER_B0                  105
3158 #define SSF_STATUS_CONTROL              110
3159 #define SSF_ALARM_FLAGS                 112
3160 #define SSF_WARNING_FLAGS               116
3161 #define SSF_EXT_TATUS_CONTROL_B1        118
3162 #define SSF_EXT_TATUS_CONTROL_B0        119
3163 #define SSF_A2_VENDOR_SPECIFIC          120
3164 #define SSF_USER_EEPROM                 128
3165 #define SSF_VENDOR_CONTROL              148
3166
3167
3168 /*
3169  * Tranceiver codes Fibre Channel SFF-8472
3170  * Table 3.5.
3171  */
3172
3173 struct sff_trasnceiver_codes_byte0 {
3174         uint8_t inifiband:4;
3175         uint8_t teng_ethernet:4;
3176 };
3177
3178 struct sff_trasnceiver_codes_byte1 {
3179         uint8_t  sonet:6;
3180         uint8_t  escon:2;
3181 };
3182
3183 struct sff_trasnceiver_codes_byte2 {
3184         uint8_t  soNet:8;
3185 };
3186
3187 struct sff_trasnceiver_codes_byte3 {
3188         uint8_t ethernet:8;
3189 };
3190
3191 struct sff_trasnceiver_codes_byte4 {
3192         uint8_t fc_el_lo:1;
3193         uint8_t fc_lw_laser:1;
3194         uint8_t fc_sw_laser:1;
3195         uint8_t fc_md_distance:1;
3196         uint8_t fc_lg_distance:1;
3197         uint8_t fc_int_distance:1;
3198         uint8_t fc_short_distance:1;
3199         uint8_t fc_vld_distance:1;
3200 };
3201
3202 struct sff_trasnceiver_codes_byte5 {
3203         uint8_t reserved1:1;
3204         uint8_t reserved2:1;
3205         uint8_t fc_sfp_active:1;  /* Active cable   */
3206         uint8_t fc_sfp_passive:1; /* Passive cable  */
3207         uint8_t fc_lw_laser:1;     /* Longwave laser */
3208         uint8_t fc_sw_laser_sl:1;
3209         uint8_t fc_sw_laser_sn:1;
3210         uint8_t fc_el_hi:1;        /* Electrical enclosure high bit */
3211 };
3212
3213 struct sff_trasnceiver_codes_byte6 {
3214         uint8_t fc_tm_sm:1;      /* Single Mode */
3215         uint8_t reserved:1;
3216         uint8_t fc_tm_m6:1;       /* Multimode, 62.5um (M6) */
3217         uint8_t fc_tm_tv:1;      /* Video Coax (TV) */
3218         uint8_t fc_tm_mi:1;      /* Miniature Coax (MI) */
3219         uint8_t fc_tm_tp:1;      /* Twisted Pair (TP) */
3220         uint8_t fc_tm_tw:1;      /* Twin Axial Pair  */
3221 };
3222
3223 struct sff_trasnceiver_codes_byte7 {
3224         uint8_t fc_sp_100MB:1;   /*  100 MB/sec */
3225         uint8_t reserve:1;
3226         uint8_t fc_sp_200mb:1;   /*  200 MB/sec */
3227         uint8_t fc_sp_3200MB:1;  /* 3200 MB/sec */
3228         uint8_t fc_sp_400MB:1;   /*  400 MB/sec */
3229         uint8_t fc_sp_1600MB:1;  /* 1600 MB/sec */
3230         uint8_t fc_sp_800MB:1;   /*  800 MB/sec */
3231         uint8_t fc_sp_1200MB:1;  /* 1200 MB/sec */
3232 };
3233
3234 /* User writable non-volatile memory, SFF-8472 Table 3.20 */
3235 struct user_eeprom {
3236         uint8_t vendor_name[16];
3237         uint8_t vendor_oui[3];
3238         uint8_t vendor_pn[816];
3239         uint8_t vendor_rev[4];
3240         uint8_t vendor_sn[16];
3241         uint8_t datecode[6];
3242         uint8_t lot_code[2];
3243         uint8_t reserved191[57];
3244 };
3245
3246 struct lpfc_mbx_pc_sli4_params {
3247         uint32_t word1;
3248 #define qs_SHIFT                                0
3249 #define qs_MASK                                 0x00000001
3250 #define qs_WORD                                 word1
3251 #define wr_SHIFT                                1
3252 #define wr_MASK                                 0x00000001
3253 #define wr_WORD                                 word1
3254 #define pf_SHIFT                                8
3255 #define pf_MASK                                 0x000000ff
3256 #define pf_WORD                                 word1
3257 #define cpn_SHIFT                               16
3258 #define cpn_MASK                                0x000000ff
3259 #define cpn_WORD                                word1
3260         uint32_t word2;
3261 #define if_type_SHIFT                           0
3262 #define if_type_MASK                            0x00000007
3263 #define if_type_WORD                            word2
3264 #define sli_rev_SHIFT                           4
3265 #define sli_rev_MASK                            0x0000000f
3266 #define sli_rev_WORD                            word2
3267 #define sli_family_SHIFT                        8
3268 #define sli_family_MASK                         0x000000ff
3269 #define sli_family_WORD                         word2
3270 #define featurelevel_1_SHIFT                    16
3271 #define featurelevel_1_MASK                     0x000000ff
3272 #define featurelevel_1_WORD                     word2
3273 #define featurelevel_2_SHIFT                    24
3274 #define featurelevel_2_MASK                     0x0000001f
3275 #define featurelevel_2_WORD                     word2
3276         uint32_t word3;
3277 #define fcoe_SHIFT                              0
3278 #define fcoe_MASK                               0x00000001
3279 #define fcoe_WORD                               word3
3280 #define fc_SHIFT                                1
3281 #define fc_MASK                                 0x00000001
3282 #define fc_WORD                                 word3
3283 #define nic_SHIFT                               2
3284 #define nic_MASK                                0x00000001
3285 #define nic_WORD                                word3
3286 #define iscsi_SHIFT                             3
3287 #define iscsi_MASK                              0x00000001
3288 #define iscsi_WORD                              word3
3289 #define rdma_SHIFT                              4
3290 #define rdma_MASK                               0x00000001
3291 #define rdma_WORD                               word3
3292         uint32_t sge_supp_len;
3293 #define SLI4_PAGE_SIZE 4096
3294         uint32_t word5;
3295 #define if_page_sz_SHIFT                        0
3296 #define if_page_sz_MASK                         0x0000ffff
3297 #define if_page_sz_WORD                         word5
3298 #define loopbk_scope_SHIFT                      24
3299 #define loopbk_scope_MASK                       0x0000000f
3300 #define loopbk_scope_WORD                       word5
3301 #define rq_db_window_SHIFT                      28
3302 #define rq_db_window_MASK                       0x0000000f
3303 #define rq_db_window_WORD                       word5
3304         uint32_t word6;
3305 #define eq_pages_SHIFT                          0
3306 #define eq_pages_MASK                           0x0000000f
3307 #define eq_pages_WORD                           word6
3308 #define eqe_size_SHIFT                          8
3309 #define eqe_size_MASK                           0x000000ff
3310 #define eqe_size_WORD                           word6
3311         uint32_t word7;
3312 #define cq_pages_SHIFT                          0
3313 #define cq_pages_MASK                           0x0000000f
3314 #define cq_pages_WORD                           word7
3315 #define cqe_size_SHIFT                          8
3316 #define cqe_size_MASK                           0x000000ff
3317 #define cqe_size_WORD                           word7
3318         uint32_t word8;
3319 #define mq_pages_SHIFT                          0
3320 #define mq_pages_MASK                           0x0000000f
3321 #define mq_pages_WORD                           word8
3322 #define mqe_size_SHIFT                          8
3323 #define mqe_size_MASK                           0x000000ff
3324 #define mqe_size_WORD                           word8
3325 #define mq_elem_cnt_SHIFT                       16
3326 #define mq_elem_cnt_MASK                        0x000000ff
3327 #define mq_elem_cnt_WORD                        word8
3328         uint32_t word9;
3329 #define wq_pages_SHIFT                          0
3330 #define wq_pages_MASK                           0x0000ffff
3331 #define wq_pages_WORD                           word9
3332 #define wqe_size_SHIFT                          8
3333 #define wqe_size_MASK                           0x000000ff
3334 #define wqe_size_WORD                           word9
3335         uint32_t word10;
3336 #define rq_pages_SHIFT                          0
3337 #define rq_pages_MASK                           0x0000ffff
3338 #define rq_pages_WORD                           word10
3339 #define rqe_size_SHIFT                          8
3340 #define rqe_size_MASK                           0x000000ff
3341 #define rqe_size_WORD                           word10
3342         uint32_t word11;
3343 #define hdr_pages_SHIFT                         0
3344 #define hdr_pages_MASK                          0x0000000f
3345 #define hdr_pages_WORD                          word11
3346 #define hdr_size_SHIFT                          8
3347 #define hdr_size_MASK                           0x0000000f
3348 #define hdr_size_WORD                           word11
3349 #define hdr_pp_align_SHIFT                      16
3350 #define hdr_pp_align_MASK                       0x0000ffff
3351 #define hdr_pp_align_WORD                       word11
3352         uint32_t word12;
3353 #define sgl_pages_SHIFT                         0
3354 #define sgl_pages_MASK                          0x0000000f
3355 #define sgl_pages_WORD                          word12
3356 #define sgl_pp_align_SHIFT                      16
3357 #define sgl_pp_align_MASK                       0x0000ffff
3358 #define sgl_pp_align_WORD                       word12
3359         uint32_t rsvd_13_63[51];
3360 };
3361 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \
3362                                &(~((SLI4_PAGE_SIZE)-1)))
3363
3364 struct lpfc_sli4_parameters {
3365         uint32_t word0;
3366 #define cfg_prot_type_SHIFT                     0
3367 #define cfg_prot_type_MASK                      0x000000FF
3368 #define cfg_prot_type_WORD                      word0
3369         uint32_t word1;
3370 #define cfg_ft_SHIFT                            0
3371 #define cfg_ft_MASK                             0x00000001
3372 #define cfg_ft_WORD                             word1
3373 #define cfg_sli_rev_SHIFT                       4
3374 #define cfg_sli_rev_MASK                        0x0000000f
3375 #define cfg_sli_rev_WORD                        word1
3376 #define cfg_sli_family_SHIFT                    8
3377 #define cfg_sli_family_MASK                     0x0000000f
3378 #define cfg_sli_family_WORD                     word1
3379 #define cfg_if_type_SHIFT                       12
3380 #define cfg_if_type_MASK                        0x0000000f
3381 #define cfg_if_type_WORD                        word1
3382 #define cfg_sli_hint_1_SHIFT                    16
3383 #define cfg_sli_hint_1_MASK                     0x000000ff
3384 #define cfg_sli_hint_1_WORD                     word1
3385 #define cfg_sli_hint_2_SHIFT                    24
3386 #define cfg_sli_hint_2_MASK                     0x0000001f
3387 #define cfg_sli_hint_2_WORD                     word1
3388         uint32_t word2;
3389 #define cfg_eqav_SHIFT                          31
3390 #define cfg_eqav_MASK                           0x00000001
3391 #define cfg_eqav_WORD                           word2
3392         uint32_t word3;
3393         uint32_t word4;
3394 #define cfg_cqv_SHIFT                           14
3395 #define cfg_cqv_MASK                            0x00000003
3396 #define cfg_cqv_WORD                            word4
3397 #define cfg_cqpsize_SHIFT                       16
3398 #define cfg_cqpsize_MASK                        0x000000ff
3399 #define cfg_cqpsize_WORD                        word4
3400 #define cfg_cqav_SHIFT                          31
3401 #define cfg_cqav_MASK                           0x00000001
3402 #define cfg_cqav_WORD                           word4
3403         uint32_t word5;
3404         uint32_t word6;
3405 #define cfg_mqv_SHIFT                           14
3406 #define cfg_mqv_MASK                            0x00000003
3407 #define cfg_mqv_WORD                            word6
3408         uint32_t word7;
3409         uint32_t word8;
3410 #define cfg_wqpcnt_SHIFT                        0
3411 #define cfg_wqpcnt_MASK                         0x0000000f
3412 #define cfg_wqpcnt_WORD                         word8
3413 #define cfg_wqsize_SHIFT                        8
3414 #define cfg_wqsize_MASK                         0x0000000f
3415 #define cfg_wqsize_WORD                         word8
3416 #define cfg_wqv_SHIFT                           14
3417 #define cfg_wqv_MASK                            0x00000003
3418 #define cfg_wqv_WORD                            word8
3419 #define cfg_wqpsize_SHIFT                       16
3420 #define cfg_wqpsize_MASK                        0x000000ff
3421 #define cfg_wqpsize_WORD                        word8
3422         uint32_t word9;
3423         uint32_t word10;
3424 #define cfg_rqv_SHIFT                           14
3425 #define cfg_rqv_MASK                            0x00000003
3426 #define cfg_rqv_WORD                            word10
3427         uint32_t word11;
3428 #define cfg_rq_db_window_SHIFT                  28
3429 #define cfg_rq_db_window_MASK                   0x0000000f
3430 #define cfg_rq_db_window_WORD                   word11
3431         uint32_t word12;
3432 #define cfg_fcoe_SHIFT                          0
3433 #define cfg_fcoe_MASK                           0x00000001
3434 #define cfg_fcoe_WORD                           word12
3435 #define cfg_ext_SHIFT                           1
3436 #define cfg_ext_MASK                            0x00000001
3437 #define cfg_ext_WORD                            word12
3438 #define cfg_hdrr_SHIFT                          2
3439 #define cfg_hdrr_MASK                           0x00000001
3440 #define cfg_hdrr_WORD                           word12
3441 #define cfg_phwq_SHIFT                          15
3442 #define cfg_phwq_MASK                           0x00000001
3443 #define cfg_phwq_WORD                           word12
3444 #define cfg_oas_SHIFT                           25
3445 #define cfg_oas_MASK                            0x00000001
3446 #define cfg_oas_WORD                            word12
3447 #define cfg_loopbk_scope_SHIFT                  28
3448 #define cfg_loopbk_scope_MASK                   0x0000000f
3449 #define cfg_loopbk_scope_WORD                   word12
3450         uint32_t sge_supp_len;
3451         uint32_t word14;
3452 #define cfg_sgl_page_cnt_SHIFT                  0
3453 #define cfg_sgl_page_cnt_MASK                   0x0000000f
3454 #define cfg_sgl_page_cnt_WORD                   word14
3455 #define cfg_sgl_page_size_SHIFT                 8
3456 #define cfg_sgl_page_size_MASK                  0x000000ff
3457 #define cfg_sgl_page_size_WORD                  word14
3458 #define cfg_sgl_pp_align_SHIFT                  16
3459 #define cfg_sgl_pp_align_MASK                   0x000000ff
3460 #define cfg_sgl_pp_align_WORD                   word14
3461         uint32_t word15;
3462         uint32_t word16;
3463         uint32_t word17;
3464         uint32_t word18;
3465         uint32_t word19;
3466 #define cfg_ext_embed_cb_SHIFT                  0
3467 #define cfg_ext_embed_cb_MASK                   0x00000001
3468 #define cfg_ext_embed_cb_WORD                   word19
3469 #define cfg_mds_diags_SHIFT                     1
3470 #define cfg_mds_diags_MASK                      0x00000001
3471 #define cfg_mds_diags_WORD                      word19
3472 #define cfg_nvme_SHIFT                          3
3473 #define cfg_nvme_MASK                           0x00000001
3474 #define cfg_nvme_WORD                           word19
3475 #define cfg_xib_SHIFT                           4
3476 #define cfg_xib_MASK                            0x00000001
3477 #define cfg_xib_WORD                            word19
3478 #define cfg_xpsgl_SHIFT                         6
3479 #define cfg_xpsgl_MASK                          0x00000001
3480 #define cfg_xpsgl_WORD                          word19
3481 #define cfg_eqdr_SHIFT                          8
3482 #define cfg_eqdr_MASK                           0x00000001
3483 #define cfg_eqdr_WORD                           word19
3484 #define cfg_nosr_SHIFT                          9
3485 #define cfg_nosr_MASK                           0x00000001
3486 #define cfg_nosr_WORD                           word19
3487
3488 #define cfg_bv1s_SHIFT                          10
3489 #define cfg_bv1s_MASK                           0x00000001
3490 #define cfg_bv1s_WORD                           word19
3491 #define cfg_pvl_SHIFT                           13
3492 #define cfg_pvl_MASK                            0x00000001
3493 #define cfg_pvl_WORD                            word19
3494
3495 #define cfg_nsler_SHIFT                         12
3496 #define cfg_nsler_MASK                          0x00000001
3497 #define cfg_nsler_WORD                          word19
3498
3499         uint32_t word20;
3500 #define cfg_max_tow_xri_SHIFT                   0
3501 #define cfg_max_tow_xri_MASK                    0x0000ffff
3502 #define cfg_max_tow_xri_WORD                    word20
3503
3504         uint32_t word21;                        /* RESERVED */
3505         uint32_t word22;                        /* RESERVED */
3506         uint32_t word23;                        /* RESERVED */
3507
3508         uint32_t word24;
3509 #define cfg_frag_field_offset_SHIFT             0
3510 #define cfg_frag_field_offset_MASK              0x0000ffff
3511 #define cfg_frag_field_offset_WORD              word24
3512
3513 #define cfg_frag_field_size_SHIFT               16
3514 #define cfg_frag_field_size_MASK                0x0000ffff
3515 #define cfg_frag_field_size_WORD                word24
3516
3517         uint32_t word25;
3518 #define cfg_sgl_field_offset_SHIFT              0
3519 #define cfg_sgl_field_offset_MASK               0x0000ffff
3520 #define cfg_sgl_field_offset_WORD               word25
3521
3522 #define cfg_sgl_field_size_SHIFT                16
3523 #define cfg_sgl_field_size_MASK                 0x0000ffff
3524 #define cfg_sgl_field_size_WORD                 word25
3525
3526         uint32_t word26;        /* Chain SGE initial value LOW  */
3527         uint32_t word27;        /* Chain SGE initial value HIGH */
3528 #define LPFC_NODELAY_MAX_IO                     32
3529 };
3530
3531 #define LPFC_SET_UE_RECOVERY            0x10
3532 #define LPFC_SET_MDS_DIAGS              0x11
3533 #define LPFC_SET_DUAL_DUMP              0x1e
3534 struct lpfc_mbx_set_feature {
3535         struct mbox_header header;
3536         uint32_t feature;
3537         uint32_t param_len;
3538         uint32_t word6;
3539 #define lpfc_mbx_set_feature_UER_SHIFT  0
3540 #define lpfc_mbx_set_feature_UER_MASK   0x00000001
3541 #define lpfc_mbx_set_feature_UER_WORD   word6
3542 #define lpfc_mbx_set_feature_mds_SHIFT  0
3543 #define lpfc_mbx_set_feature_mds_MASK   0x00000001
3544 #define lpfc_mbx_set_feature_mds_WORD   word6
3545 #define lpfc_mbx_set_feature_mds_deep_loopbk_SHIFT  1
3546 #define lpfc_mbx_set_feature_mds_deep_loopbk_MASK   0x00000001
3547 #define lpfc_mbx_set_feature_mds_deep_loopbk_WORD   word6
3548 #define lpfc_mbx_set_feature_dd_SHIFT           0
3549 #define lpfc_mbx_set_feature_dd_MASK            0x00000001
3550 #define lpfc_mbx_set_feature_dd_WORD            word6
3551 #define lpfc_mbx_set_feature_ddquery_SHIFT      1
3552 #define lpfc_mbx_set_feature_ddquery_MASK       0x00000001
3553 #define lpfc_mbx_set_feature_ddquery_WORD       word6
3554 #define LPFC_DISABLE_DUAL_DUMP          0
3555 #define LPFC_ENABLE_DUAL_DUMP           1
3556 #define LPFC_QUERY_OP_DUAL_DUMP         2
3557         uint32_t word7;
3558 #define lpfc_mbx_set_feature_UERP_SHIFT 0
3559 #define lpfc_mbx_set_feature_UERP_MASK  0x0000ffff
3560 #define lpfc_mbx_set_feature_UERP_WORD  word7
3561 #define lpfc_mbx_set_feature_UESR_SHIFT 16
3562 #define lpfc_mbx_set_feature_UESR_MASK  0x0000ffff
3563 #define lpfc_mbx_set_feature_UESR_WORD  word7
3564 };
3565
3566
3567 #define LPFC_SET_HOST_OS_DRIVER_VERSION    0x2
3568 struct lpfc_mbx_set_host_data {
3569 #define LPFC_HOST_OS_DRIVER_VERSION_SIZE   48
3570         struct mbox_header header;
3571         uint32_t param_id;
3572         uint32_t param_len;
3573         uint8_t  data[LPFC_HOST_OS_DRIVER_VERSION_SIZE];
3574 };
3575
3576 struct lpfc_mbx_set_trunk_mode {
3577         struct mbox_header header;
3578         uint32_t word0;
3579 #define lpfc_mbx_set_trunk_mode_WORD      word0
3580 #define lpfc_mbx_set_trunk_mode_SHIFT     0
3581 #define lpfc_mbx_set_trunk_mode_MASK      0xFF
3582         uint32_t word1;
3583         uint32_t word2;
3584 };
3585
3586 struct lpfc_mbx_get_sli4_parameters {
3587         struct mbox_header header;
3588         struct lpfc_sli4_parameters sli4_parameters;
3589 };
3590
3591 struct lpfc_rscr_desc_generic {
3592 #define LPFC_RSRC_DESC_WSIZE                    22
3593         uint32_t desc[LPFC_RSRC_DESC_WSIZE];
3594 };
3595
3596 struct lpfc_rsrc_desc_pcie {
3597         uint32_t word0;
3598 #define lpfc_rsrc_desc_pcie_type_SHIFT          0
3599 #define lpfc_rsrc_desc_pcie_type_MASK           0x000000ff
3600 #define lpfc_rsrc_desc_pcie_type_WORD           word0
3601 #define LPFC_RSRC_DESC_TYPE_PCIE                0x40
3602 #define lpfc_rsrc_desc_pcie_length_SHIFT        8
3603 #define lpfc_rsrc_desc_pcie_length_MASK         0x000000ff
3604 #define lpfc_rsrc_desc_pcie_length_WORD         word0
3605         uint32_t word1;
3606 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT         0
3607 #define lpfc_rsrc_desc_pcie_pfnum_MASK          0x000000ff
3608 #define lpfc_rsrc_desc_pcie_pfnum_WORD          word1
3609         uint32_t reserved;
3610         uint32_t word3;
3611 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT     0
3612 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK      0x000000ff
3613 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD      word3
3614 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT        8
3615 #define lpfc_rsrc_desc_pcie_pf_sta_MASK         0x000000ff
3616 #define lpfc_rsrc_desc_pcie_pf_sta_WORD         word3
3617 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT       16
3618 #define lpfc_rsrc_desc_pcie_pf_type_MASK        0x000000ff
3619 #define lpfc_rsrc_desc_pcie_pf_type_WORD        word3
3620         uint32_t word4;
3621 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT     0
3622 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK      0x0000ffff
3623 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD      word4
3624 };
3625
3626 struct lpfc_rsrc_desc_fcfcoe {
3627         uint32_t word0;
3628 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT        0
3629 #define lpfc_rsrc_desc_fcfcoe_type_MASK         0x000000ff
3630 #define lpfc_rsrc_desc_fcfcoe_type_WORD         word0
3631 #define LPFC_RSRC_DESC_TYPE_FCFCOE              0x43
3632 #define lpfc_rsrc_desc_fcfcoe_length_SHIFT      8
3633 #define lpfc_rsrc_desc_fcfcoe_length_MASK       0x000000ff
3634 #define lpfc_rsrc_desc_fcfcoe_length_WORD       word0
3635 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD      0
3636 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH    72
3637 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH    88
3638         uint32_t word1;
3639 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT       0
3640 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK        0x000000ff
3641 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD        word1
3642 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT       16
3643 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK        0x000007ff
3644 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD        word1
3645         uint32_t word2;
3646 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT     0
3647 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK      0x0000ffff
3648 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD      word2
3649 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT     16
3650 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK      0x0000ffff
3651 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD      word2
3652         uint32_t word3;
3653 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT      0
3654 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK       0x0000ffff
3655 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD       word3
3656 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT      16
3657 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK       0x0000ffff
3658 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD       word3
3659         uint32_t word4;
3660 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT      0
3661 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK       0x0000ffff
3662 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD       word4
3663 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT     16
3664 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK      0x0000ffff
3665 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD      word4
3666         uint32_t word5;
3667 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT    0
3668 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK     0x0000ffff
3669 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD     word5
3670 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT     16
3671 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK      0x0000ffff
3672 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD      word5
3673         uint32_t word6;
3674         uint32_t word7;
3675         uint32_t word8;
3676         uint32_t word9;
3677         uint32_t word10;
3678         uint32_t word11;
3679         uint32_t word12;
3680         uint32_t word13;
3681 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT      0
3682 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK       0x0000003f
3683 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD       word13
3684 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT      6
3685 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK       0x00000003
3686 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD       word13
3687 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT         8
3688 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK          0x00000001
3689 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD          word13
3690 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT         9
3691 #define lpfc_rsrc_desc_fcfcoe_lld_MASK          0x00000001
3692 #define lpfc_rsrc_desc_fcfcoe_lld_WORD          word13
3693 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT      16
3694 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK       0x0000ffff
3695 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD       word13
3696 /* extended FC/FCoE Resource Descriptor when length = 88 bytes */
3697         uint32_t bw_min;
3698         uint32_t bw_max;
3699         uint32_t iops_min;
3700         uint32_t iops_max;
3701         uint32_t reserved[4];
3702 };
3703
3704 struct lpfc_func_cfg {
3705 #define LPFC_RSRC_DESC_MAX_NUM                  2
3706         uint32_t rsrc_desc_count;
3707         struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM];
3708 };
3709
3710 struct lpfc_mbx_get_func_cfg {
3711         struct mbox_header header;
3712 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE       0x0
3713 #define LPFC_CFG_TYPE_FACTURY_DEFAULT           0x1
3714 #define LPFC_CFG_TYPE_CURRENT_ACTIVE            0x2
3715         struct lpfc_func_cfg func_cfg;
3716 };
3717
3718 struct lpfc_prof_cfg {
3719 #define LPFC_RSRC_DESC_MAX_NUM                  2
3720         uint32_t rsrc_desc_count;
3721         struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM];
3722 };
3723
3724 struct lpfc_mbx_get_prof_cfg {
3725         struct mbox_header header;
3726 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE       0x0
3727 #define LPFC_CFG_TYPE_FACTURY_DEFAULT           0x1
3728 #define LPFC_CFG_TYPE_CURRENT_ACTIVE            0x2
3729         union {
3730                 struct {
3731                         uint32_t word10;
3732 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT     0
3733 #define lpfc_mbx_get_prof_cfg_prof_id_MASK      0x000000ff
3734 #define lpfc_mbx_get_prof_cfg_prof_id_WORD      word10
3735 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT     8
3736 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK      0x00000003
3737 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD      word10
3738                 } request;
3739                 struct {
3740                         struct lpfc_prof_cfg prof_cfg;
3741                 } response;
3742         } u;
3743 };
3744
3745 struct lpfc_controller_attribute {
3746         uint32_t version_string[8];
3747         uint32_t manufacturer_name[8];
3748         uint32_t supported_modes;
3749         uint32_t word17;
3750 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT       0
3751 #define lpfc_cntl_attr_eprom_ver_lo_MASK        0x000000ff
3752 #define lpfc_cntl_attr_eprom_ver_lo_WORD        word17
3753 #define lpfc_cntl_attr_eprom_ver_hi_SHIFT       8
3754 #define lpfc_cntl_attr_eprom_ver_hi_MASK        0x000000ff
3755 #define lpfc_cntl_attr_eprom_ver_hi_WORD        word17
3756         uint32_t mbx_da_struct_ver;
3757         uint32_t ep_fw_da_struct_ver;
3758         uint32_t ncsi_ver_str[3];
3759         uint32_t dflt_ext_timeout;
3760         uint32_t model_number[8];
3761         uint32_t description[16];
3762         uint32_t serial_number[8];
3763         uint32_t ip_ver_str[8];
3764         uint32_t fw_ver_str[8];
3765         uint32_t bios_ver_str[8];
3766         uint32_t redboot_ver_str[8];
3767         uint32_t driver_ver_str[8];
3768         uint32_t flash_fw_ver_str[8];
3769         uint32_t functionality;
3770         uint32_t word105;
3771 #define lpfc_cntl_attr_max_cbd_len_SHIFT        0
3772 #define lpfc_cntl_attr_max_cbd_len_MASK         0x0000ffff
3773 #define lpfc_cntl_attr_max_cbd_len_WORD         word105
3774 #define lpfc_cntl_attr_asic_rev_SHIFT           16
3775 #define lpfc_cntl_attr_asic_rev_MASK            0x000000ff
3776 #define lpfc_cntl_attr_asic_rev_WORD            word105
3777 #define lpfc_cntl_attr_gen_guid0_SHIFT          24
3778 #define lpfc_cntl_attr_gen_guid0_MASK           0x000000ff
3779 #define lpfc_cntl_attr_gen_guid0_WORD           word105
3780         uint32_t gen_guid1_12[3];
3781         uint32_t word109;
3782 #define lpfc_cntl_attr_gen_guid13_14_SHIFT      0
3783 #define lpfc_cntl_attr_gen_guid13_14_MASK       0x0000ffff
3784 #define lpfc_cntl_attr_gen_guid13_14_WORD       word109
3785 #define lpfc_cntl_attr_gen_guid15_SHIFT         16
3786 #define lpfc_cntl_attr_gen_guid15_MASK          0x000000ff
3787 #define lpfc_cntl_attr_gen_guid15_WORD          word109
3788 #define lpfc_cntl_attr_hba_port_cnt_SHIFT       24
3789 #define lpfc_cntl_attr_hba_port_cnt_MASK        0x000000ff
3790 #define lpfc_cntl_attr_hba_port_cnt_WORD        word109
3791         uint32_t word110;
3792 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT       0
3793 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK        0x0000ffff
3794 #define lpfc_cntl_attr_dflt_lnk_tmo_WORD        word110
3795 #define lpfc_cntl_attr_multi_func_dev_SHIFT     24
3796 #define lpfc_cntl_attr_multi_func_dev_MASK      0x000000ff
3797 #define lpfc_cntl_attr_multi_func_dev_WORD      word110
3798         uint32_t word111;
3799 #define lpfc_cntl_attr_cache_valid_SHIFT        0
3800 #define lpfc_cntl_attr_cache_valid_MASK         0x000000ff
3801 #define lpfc_cntl_attr_cache_valid_WORD         word111
3802 #define lpfc_cntl_attr_hba_status_SHIFT         8
3803 #define lpfc_cntl_attr_hba_status_MASK          0x000000ff
3804 #define lpfc_cntl_attr_hba_status_WORD          word111
3805 #define lpfc_cntl_attr_max_domain_SHIFT         16
3806 #define lpfc_cntl_attr_max_domain_MASK          0x000000ff
3807 #define lpfc_cntl_attr_max_domain_WORD          word111
3808 #define lpfc_cntl_attr_lnk_numb_SHIFT           24
3809 #define lpfc_cntl_attr_lnk_numb_MASK            0x0000003f
3810 #define lpfc_cntl_attr_lnk_numb_WORD            word111
3811 #define lpfc_cntl_attr_lnk_type_SHIFT           30
3812 #define lpfc_cntl_attr_lnk_type_MASK            0x00000003
3813 #define lpfc_cntl_attr_lnk_type_WORD            word111
3814         uint32_t fw_post_status;
3815         uint32_t hba_mtu[8];
3816         uint32_t word121;
3817         uint32_t reserved1[3];
3818         uint32_t word125;
3819 #define lpfc_cntl_attr_pci_vendor_id_SHIFT      0
3820 #define lpfc_cntl_attr_pci_vendor_id_MASK       0x0000ffff
3821 #define lpfc_cntl_attr_pci_vendor_id_WORD       word125
3822 #define lpfc_cntl_attr_pci_device_id_SHIFT      16
3823 #define lpfc_cntl_attr_pci_device_id_MASK       0x0000ffff
3824 #define lpfc_cntl_attr_pci_device_id_WORD       word125
3825         uint32_t word126;
3826 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT      0
3827 #define lpfc_cntl_attr_pci_subvdr_id_MASK       0x0000ffff
3828 #define lpfc_cntl_attr_pci_subvdr_id_WORD       word126
3829 #define lpfc_cntl_attr_pci_subsys_id_SHIFT      16
3830 #define lpfc_cntl_attr_pci_subsys_id_MASK       0x0000ffff
3831 #define lpfc_cntl_attr_pci_subsys_id_WORD       word126
3832         uint32_t word127;
3833 #define lpfc_cntl_attr_pci_bus_num_SHIFT        0
3834 #define lpfc_cntl_attr_pci_bus_num_MASK         0x000000ff
3835 #define lpfc_cntl_attr_pci_bus_num_WORD         word127
3836 #define lpfc_cntl_attr_pci_dev_num_SHIFT        8
3837 #define lpfc_cntl_attr_pci_dev_num_MASK         0x000000ff
3838 #define lpfc_cntl_attr_pci_dev_num_WORD         word127
3839 #define lpfc_cntl_attr_pci_fnc_num_SHIFT        16
3840 #define lpfc_cntl_attr_pci_fnc_num_MASK         0x000000ff
3841 #define lpfc_cntl_attr_pci_fnc_num_WORD         word127
3842 #define lpfc_cntl_attr_inf_type_SHIFT           24
3843 #define lpfc_cntl_attr_inf_type_MASK            0x000000ff
3844 #define lpfc_cntl_attr_inf_type_WORD            word127
3845         uint32_t unique_id[2];
3846         uint32_t word130;
3847 #define lpfc_cntl_attr_num_netfil_SHIFT         0
3848 #define lpfc_cntl_attr_num_netfil_MASK          0x000000ff
3849 #define lpfc_cntl_attr_num_netfil_WORD          word130
3850         uint32_t reserved2[4];
3851 };
3852
3853 struct lpfc_mbx_get_cntl_attributes {
3854         union  lpfc_sli4_cfg_shdr cfg_shdr;
3855         struct lpfc_controller_attribute cntl_attr;
3856 };
3857
3858 struct lpfc_mbx_get_port_name {
3859         struct mbox_header header;
3860         union {
3861                 struct {
3862                         uint32_t word4;
3863 #define lpfc_mbx_get_port_name_lnk_type_SHIFT   0
3864 #define lpfc_mbx_get_port_name_lnk_type_MASK    0x00000003
3865 #define lpfc_mbx_get_port_name_lnk_type_WORD    word4
3866                 } request;
3867                 struct {
3868                         uint32_t word4;
3869 #define lpfc_mbx_get_port_name_name0_SHIFT      0
3870 #define lpfc_mbx_get_port_name_name0_MASK       0x000000FF
3871 #define lpfc_mbx_get_port_name_name0_WORD       word4
3872 #define lpfc_mbx_get_port_name_name1_SHIFT      8
3873 #define lpfc_mbx_get_port_name_name1_MASK       0x000000FF
3874 #define lpfc_mbx_get_port_name_name1_WORD       word4
3875 #define lpfc_mbx_get_port_name_name2_SHIFT      16
3876 #define lpfc_mbx_get_port_name_name2_MASK       0x000000FF
3877 #define lpfc_mbx_get_port_name_name2_WORD       word4
3878 #define lpfc_mbx_get_port_name_name3_SHIFT      24
3879 #define lpfc_mbx_get_port_name_name3_MASK       0x000000FF
3880 #define lpfc_mbx_get_port_name_name3_WORD       word4
3881 #define LPFC_LINK_NUMBER_0                      0
3882 #define LPFC_LINK_NUMBER_1                      1
3883 #define LPFC_LINK_NUMBER_2                      2
3884 #define LPFC_LINK_NUMBER_3                      3
3885                 } response;
3886         } u;
3887 };
3888
3889 /* Mailbox Completion Queue Error Messages */
3890 #define MB_CQE_STATUS_SUCCESS                   0x0
3891 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES   0x1
3892 #define MB_CQE_STATUS_INVALID_PARAMETER         0x2
3893 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES    0x3
3894 #define MB_CEQ_STATUS_QUEUE_FLUSHING            0x4
3895 #define MB_CQE_STATUS_DMA_FAILED                0x5
3896
3897 #define LPFC_MBX_WR_CONFIG_MAX_BDE              1
3898 struct lpfc_mbx_wr_object {
3899         struct mbox_header header;
3900         union {
3901                 struct {
3902                         uint32_t word4;
3903 #define lpfc_wr_object_eof_SHIFT                31
3904 #define lpfc_wr_object_eof_MASK                 0x00000001
3905 #define lpfc_wr_object_eof_WORD                 word4
3906 #define lpfc_wr_object_eas_SHIFT                29
3907 #define lpfc_wr_object_eas_MASK                 0x00000001
3908 #define lpfc_wr_object_eas_WORD                 word4
3909 #define lpfc_wr_object_write_length_SHIFT       0
3910 #define lpfc_wr_object_write_length_MASK        0x00FFFFFF
3911 #define lpfc_wr_object_write_length_WORD        word4
3912                         uint32_t write_offset;
3913                         uint32_t object_name[26];
3914                         uint32_t bde_count;
3915                         struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE];
3916                 } request;
3917                 struct {
3918                         uint32_t actual_write_length;
3919                         uint32_t word5;
3920 #define lpfc_wr_object_change_status_SHIFT      0
3921 #define lpfc_wr_object_change_status_MASK       0x000000FF
3922 #define lpfc_wr_object_change_status_WORD       word5
3923 #define LPFC_CHANGE_STATUS_NO_RESET_NEEDED      0x00
3924 #define LPFC_CHANGE_STATUS_PHYS_DEV_RESET       0x01
3925 #define LPFC_CHANGE_STATUS_FW_RESET             0x02
3926 #define LPFC_CHANGE_STATUS_PORT_MIGRATION       0x04
3927 #define LPFC_CHANGE_STATUS_PCI_RESET            0x05
3928 #define lpfc_wr_object_csf_SHIFT                8
3929 #define lpfc_wr_object_csf_MASK                 0x00000001
3930 #define lpfc_wr_object_csf_WORD                 word5
3931                 } response;
3932         } u;
3933 };
3934
3935 /* mailbox queue entry structure */
3936 struct lpfc_mqe {
3937         uint32_t word0;
3938 #define lpfc_mqe_status_SHIFT           16
3939 #define lpfc_mqe_status_MASK            0x0000FFFF
3940 #define lpfc_mqe_status_WORD            word0
3941 #define lpfc_mqe_command_SHIFT          8
3942 #define lpfc_mqe_command_MASK           0x000000FF
3943 #define lpfc_mqe_command_WORD           word0
3944         union {
3945                 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1];
3946                 /* sli4 mailbox commands */
3947                 struct lpfc_mbx_sli4_config sli4_config;
3948                 struct lpfc_mbx_init_vfi init_vfi;
3949                 struct lpfc_mbx_reg_vfi reg_vfi;
3950                 struct lpfc_mbx_reg_vfi unreg_vfi;
3951                 struct lpfc_mbx_init_vpi init_vpi;
3952                 struct lpfc_mbx_resume_rpi resume_rpi;
3953                 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl;
3954                 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry;
3955                 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry;
3956                 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl;
3957                 struct lpfc_mbx_reg_fcfi reg_fcfi;
3958                 struct lpfc_mbx_reg_fcfi_mrq reg_fcfi_mrq;
3959                 struct lpfc_mbx_unreg_fcfi unreg_fcfi;
3960                 struct lpfc_mbx_mq_create mq_create;
3961                 struct lpfc_mbx_mq_create_ext mq_create_ext;
3962                 struct lpfc_mbx_eq_create eq_create;
3963                 struct lpfc_mbx_modify_eq_delay eq_delay;
3964                 struct lpfc_mbx_cq_create cq_create;
3965                 struct lpfc_mbx_cq_create_set cq_create_set;
3966                 struct lpfc_mbx_wq_create wq_create;
3967                 struct lpfc_mbx_rq_create rq_create;
3968                 struct lpfc_mbx_rq_create_v2 rq_create_v2;
3969                 struct lpfc_mbx_mq_destroy mq_destroy;
3970                 struct lpfc_mbx_eq_destroy eq_destroy;
3971                 struct lpfc_mbx_cq_destroy cq_destroy;
3972                 struct lpfc_mbx_wq_destroy wq_destroy;
3973                 struct lpfc_mbx_rq_destroy rq_destroy;
3974                 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info;
3975                 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents;
3976                 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents;
3977                 struct lpfc_mbx_post_sgl_pages post_sgl_pages;
3978                 struct lpfc_mbx_nembed_cmd nembed_cmd;
3979                 struct lpfc_mbx_read_rev read_rev;
3980                 struct lpfc_mbx_read_vpi read_vpi;
3981                 struct lpfc_mbx_read_config rd_config;
3982                 struct lpfc_mbx_request_features req_ftrs;
3983                 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl;
3984                 struct lpfc_mbx_query_fw_config query_fw_cfg;
3985                 struct lpfc_mbx_set_beacon_config beacon_config;
3986                 struct lpfc_mbx_supp_pages supp_pages;
3987                 struct lpfc_mbx_pc_sli4_params sli4_params;
3988                 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters;
3989                 struct lpfc_mbx_set_link_diag_state link_diag_state;
3990                 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback;
3991                 struct lpfc_mbx_run_link_diag_test link_diag_test;
3992                 struct lpfc_mbx_get_func_cfg get_func_cfg;
3993                 struct lpfc_mbx_get_prof_cfg get_prof_cfg;
3994                 struct lpfc_mbx_wr_object wr_object;
3995                 struct lpfc_mbx_get_port_name get_port_name;
3996                 struct lpfc_mbx_set_feature  set_feature;
3997                 struct lpfc_mbx_memory_dump_type3 mem_dump_type3;
3998                 struct lpfc_mbx_set_host_data set_host_data;
3999                 struct lpfc_mbx_set_trunk_mode set_trunk_mode;
4000                 struct lpfc_mbx_nop nop;
4001                 struct lpfc_mbx_set_ras_fwlog ras_fwlog;
4002         } un;
4003 };
4004
4005 struct lpfc_mcqe {
4006         uint32_t word0;
4007 #define lpfc_mcqe_status_SHIFT          0
4008 #define lpfc_mcqe_status_MASK           0x0000FFFF
4009 #define lpfc_mcqe_status_WORD           word0
4010 #define lpfc_mcqe_ext_status_SHIFT      16
4011 #define lpfc_mcqe_ext_status_MASK       0x0000FFFF
4012 #define lpfc_mcqe_ext_status_WORD       word0
4013         uint32_t mcqe_tag0;
4014         uint32_t mcqe_tag1;
4015         uint32_t trailer;
4016 #define lpfc_trailer_valid_SHIFT        31
4017 #define lpfc_trailer_valid_MASK         0x00000001
4018 #define lpfc_trailer_valid_WORD         trailer
4019 #define lpfc_trailer_async_SHIFT        30
4020 #define lpfc_trailer_async_MASK         0x00000001
4021 #define lpfc_trailer_async_WORD         trailer
4022 #define lpfc_trailer_hpi_SHIFT          29
4023 #define lpfc_trailer_hpi_MASK           0x00000001
4024 #define lpfc_trailer_hpi_WORD           trailer
4025 #define lpfc_trailer_completed_SHIFT    28
4026 #define lpfc_trailer_completed_MASK     0x00000001
4027 #define lpfc_trailer_completed_WORD     trailer
4028 #define lpfc_trailer_consumed_SHIFT     27
4029 #define lpfc_trailer_consumed_MASK      0x00000001
4030 #define lpfc_trailer_consumed_WORD      trailer
4031 #define lpfc_trailer_type_SHIFT         16
4032 #define lpfc_trailer_type_MASK          0x000000FF
4033 #define lpfc_trailer_type_WORD          trailer
4034 #define lpfc_trailer_code_SHIFT         8
4035 #define lpfc_trailer_code_MASK          0x000000FF
4036 #define lpfc_trailer_code_WORD          trailer
4037 #define LPFC_TRAILER_CODE_LINK  0x1
4038 #define LPFC_TRAILER_CODE_FCOE  0x2
4039 #define LPFC_TRAILER_CODE_DCBX  0x3
4040 #define LPFC_TRAILER_CODE_GRP5  0x5
4041 #define LPFC_TRAILER_CODE_FC    0x10
4042 #define LPFC_TRAILER_CODE_SLI   0x11
4043 };
4044
4045 struct lpfc_acqe_link {
4046         uint32_t word0;
4047 #define lpfc_acqe_link_speed_SHIFT              24
4048 #define lpfc_acqe_link_speed_MASK               0x000000FF
4049 #define lpfc_acqe_link_speed_WORD               word0
4050 #define LPFC_ASYNC_LINK_SPEED_ZERO              0x0
4051 #define LPFC_ASYNC_LINK_SPEED_10MBPS            0x1
4052 #define LPFC_ASYNC_LINK_SPEED_100MBPS           0x2
4053 #define LPFC_ASYNC_LINK_SPEED_1GBPS             0x3
4054 #define LPFC_ASYNC_LINK_SPEED_10GBPS            0x4
4055 #define LPFC_ASYNC_LINK_SPEED_20GBPS            0x5
4056 #define LPFC_ASYNC_LINK_SPEED_25GBPS            0x6
4057 #define LPFC_ASYNC_LINK_SPEED_40GBPS            0x7
4058 #define LPFC_ASYNC_LINK_SPEED_100GBPS           0x8
4059 #define lpfc_acqe_link_duplex_SHIFT             16
4060 #define lpfc_acqe_link_duplex_MASK              0x000000FF
4061 #define lpfc_acqe_link_duplex_WORD              word0
4062 #define LPFC_ASYNC_LINK_DUPLEX_NONE             0x0
4063 #define LPFC_ASYNC_LINK_DUPLEX_HALF             0x1
4064 #define LPFC_ASYNC_LINK_DUPLEX_FULL             0x2
4065 #define lpfc_acqe_link_status_SHIFT             8
4066 #define lpfc_acqe_link_status_MASK              0x000000FF
4067 #define lpfc_acqe_link_status_WORD              word0
4068 #define LPFC_ASYNC_LINK_STATUS_DOWN             0x0
4069 #define LPFC_ASYNC_LINK_STATUS_UP               0x1
4070 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN     0x2
4071 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP       0x3
4072 #define lpfc_acqe_link_type_SHIFT               6
4073 #define lpfc_acqe_link_type_MASK                0x00000003
4074 #define lpfc_acqe_link_type_WORD                word0
4075 #define lpfc_acqe_link_number_SHIFT             0
4076 #define lpfc_acqe_link_number_MASK              0x0000003F
4077 #define lpfc_acqe_link_number_WORD              word0
4078         uint32_t word1;
4079 #define lpfc_acqe_link_fault_SHIFT      0
4080 #define lpfc_acqe_link_fault_MASK       0x000000FF
4081 #define lpfc_acqe_link_fault_WORD       word1
4082 #define LPFC_ASYNC_LINK_FAULT_NONE      0x0
4083 #define LPFC_ASYNC_LINK_FAULT_LOCAL     0x1
4084 #define LPFC_ASYNC_LINK_FAULT_REMOTE    0x2
4085 #define LPFC_ASYNC_LINK_FAULT_LR_LRR    0x3
4086 #define lpfc_acqe_logical_link_speed_SHIFT      16
4087 #define lpfc_acqe_logical_link_speed_MASK       0x0000FFFF
4088 #define lpfc_acqe_logical_link_speed_WORD       word1
4089         uint32_t event_tag;
4090         uint32_t trailer;
4091 #define LPFC_LINK_EVENT_TYPE_PHYSICAL   0x0
4092 #define LPFC_LINK_EVENT_TYPE_VIRTUAL    0x1
4093 };
4094
4095 struct lpfc_acqe_fip {
4096         uint32_t index;
4097         uint32_t word1;
4098 #define lpfc_acqe_fip_fcf_count_SHIFT           0
4099 #define lpfc_acqe_fip_fcf_count_MASK            0x0000FFFF
4100 #define lpfc_acqe_fip_fcf_count_WORD            word1
4101 #define lpfc_acqe_fip_event_type_SHIFT          16
4102 #define lpfc_acqe_fip_event_type_MASK           0x0000FFFF
4103 #define lpfc_acqe_fip_event_type_WORD           word1
4104         uint32_t event_tag;
4105         uint32_t trailer;
4106 #define LPFC_FIP_EVENT_TYPE_NEW_FCF             0x1
4107 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL      0x2
4108 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD            0x3
4109 #define LPFC_FIP_EVENT_TYPE_CVL                 0x4
4110 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD       0x5
4111 };
4112
4113 struct lpfc_acqe_dcbx {
4114         uint32_t tlv_ttl;
4115         uint32_t reserved;
4116         uint32_t event_tag;
4117         uint32_t trailer;
4118 };
4119
4120 struct lpfc_acqe_grp5 {
4121         uint32_t word0;
4122 #define lpfc_acqe_grp5_type_SHIFT               6
4123 #define lpfc_acqe_grp5_type_MASK                0x00000003
4124 #define lpfc_acqe_grp5_type_WORD                word0
4125 #define lpfc_acqe_grp5_number_SHIFT             0
4126 #define lpfc_acqe_grp5_number_MASK              0x0000003F
4127 #define lpfc_acqe_grp5_number_WORD              word0
4128         uint32_t word1;
4129 #define lpfc_acqe_grp5_llink_spd_SHIFT  16
4130 #define lpfc_acqe_grp5_llink_spd_MASK   0x0000FFFF
4131 #define lpfc_acqe_grp5_llink_spd_WORD   word1
4132         uint32_t event_tag;
4133         uint32_t trailer;
4134 };
4135
4136 extern const char *const trunk_errmsg[];
4137
4138 struct lpfc_acqe_fc_la {
4139         uint32_t word0;
4140 #define lpfc_acqe_fc_la_speed_SHIFT             24
4141 #define lpfc_acqe_fc_la_speed_MASK              0x000000FF
4142 #define lpfc_acqe_fc_la_speed_WORD              word0
4143 #define LPFC_FC_LA_SPEED_UNKNOWN                0x0
4144 #define LPFC_FC_LA_SPEED_1G             0x1
4145 #define LPFC_FC_LA_SPEED_2G             0x2
4146 #define LPFC_FC_LA_SPEED_4G             0x4
4147 #define LPFC_FC_LA_SPEED_8G             0x8
4148 #define LPFC_FC_LA_SPEED_10G            0xA
4149 #define LPFC_FC_LA_SPEED_16G            0x10
4150 #define LPFC_FC_LA_SPEED_32G            0x20
4151 #define LPFC_FC_LA_SPEED_64G            0x21
4152 #define LPFC_FC_LA_SPEED_128G           0x22
4153 #define LPFC_FC_LA_SPEED_256G           0x23
4154 #define lpfc_acqe_fc_la_topology_SHIFT          16
4155 #define lpfc_acqe_fc_la_topology_MASK           0x000000FF
4156 #define lpfc_acqe_fc_la_topology_WORD           word0
4157 #define LPFC_FC_LA_TOP_UNKOWN           0x0
4158 #define LPFC_FC_LA_TOP_P2P              0x1
4159 #define LPFC_FC_LA_TOP_FCAL             0x2
4160 #define LPFC_FC_LA_TOP_INTERNAL_LOOP    0x3
4161 #define LPFC_FC_LA_TOP_SERDES_LOOP      0x4
4162 #define lpfc_acqe_fc_la_att_type_SHIFT          8
4163 #define lpfc_acqe_fc_la_att_type_MASK           0x000000FF
4164 #define lpfc_acqe_fc_la_att_type_WORD           word0
4165 #define LPFC_FC_LA_TYPE_LINK_UP         0x1
4166 #define LPFC_FC_LA_TYPE_LINK_DOWN       0x2
4167 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA    0x3
4168 #define LPFC_FC_LA_TYPE_MDS_LINK_DOWN   0x4
4169 #define LPFC_FC_LA_TYPE_MDS_LOOPBACK    0x5
4170 #define LPFC_FC_LA_TYPE_UNEXP_WWPN      0x6
4171 #define LPFC_FC_LA_TYPE_TRUNKING_EVENT  0x7
4172 #define lpfc_acqe_fc_la_port_type_SHIFT         6
4173 #define lpfc_acqe_fc_la_port_type_MASK          0x00000003
4174 #define lpfc_acqe_fc_la_port_type_WORD          word0
4175 #define LPFC_LINK_TYPE_ETHERNET         0x0
4176 #define LPFC_LINK_TYPE_FC               0x1
4177 #define lpfc_acqe_fc_la_port_number_SHIFT       0
4178 #define lpfc_acqe_fc_la_port_number_MASK        0x0000003F
4179 #define lpfc_acqe_fc_la_port_number_WORD        word0
4180
4181 /* Attention Type is 0x07 (Trunking Event) word0 */
4182 #define lpfc_acqe_fc_la_trunk_link_status_port0_SHIFT   16
4183 #define lpfc_acqe_fc_la_trunk_link_status_port0_MASK    0x0000001
4184 #define lpfc_acqe_fc_la_trunk_link_status_port0_WORD    word0
4185 #define lpfc_acqe_fc_la_trunk_link_status_port1_SHIFT   17
4186 #define lpfc_acqe_fc_la_trunk_link_status_port1_MASK    0x0000001
4187 #define lpfc_acqe_fc_la_trunk_link_status_port1_WORD    word0
4188 #define lpfc_acqe_fc_la_trunk_link_status_port2_SHIFT   18
4189 #define lpfc_acqe_fc_la_trunk_link_status_port2_MASK    0x0000001
4190 #define lpfc_acqe_fc_la_trunk_link_status_port2_WORD    word0
4191 #define lpfc_acqe_fc_la_trunk_link_status_port3_SHIFT   19
4192 #define lpfc_acqe_fc_la_trunk_link_status_port3_MASK    0x0000001
4193 #define lpfc_acqe_fc_la_trunk_link_status_port3_WORD    word0
4194 #define lpfc_acqe_fc_la_trunk_config_port0_SHIFT        20
4195 #define lpfc_acqe_fc_la_trunk_config_port0_MASK         0x0000001
4196 #define lpfc_acqe_fc_la_trunk_config_port0_WORD         word0
4197 #define lpfc_acqe_fc_la_trunk_config_port1_SHIFT        21
4198 #define lpfc_acqe_fc_la_trunk_config_port1_MASK         0x0000001
4199 #define lpfc_acqe_fc_la_trunk_config_port1_WORD         word0
4200 #define lpfc_acqe_fc_la_trunk_config_port2_SHIFT        22
4201 #define lpfc_acqe_fc_la_trunk_config_port2_MASK         0x0000001
4202 #define lpfc_acqe_fc_la_trunk_config_port2_WORD         word0
4203 #define lpfc_acqe_fc_la_trunk_config_port3_SHIFT        23
4204 #define lpfc_acqe_fc_la_trunk_config_port3_MASK         0x0000001
4205 #define lpfc_acqe_fc_la_trunk_config_port3_WORD         word0
4206         uint32_t word1;
4207 #define lpfc_acqe_fc_la_llink_spd_SHIFT         16
4208 #define lpfc_acqe_fc_la_llink_spd_MASK          0x0000FFFF
4209 #define lpfc_acqe_fc_la_llink_spd_WORD          word1
4210 #define lpfc_acqe_fc_la_fault_SHIFT             0
4211 #define lpfc_acqe_fc_la_fault_MASK              0x000000FF
4212 #define lpfc_acqe_fc_la_fault_WORD              word1
4213 #define lpfc_acqe_fc_la_trunk_fault_SHIFT               0
4214 #define lpfc_acqe_fc_la_trunk_fault_MASK                0x0000000F
4215 #define lpfc_acqe_fc_la_trunk_fault_WORD                word1
4216 #define lpfc_acqe_fc_la_trunk_linkmask_SHIFT            4
4217 #define lpfc_acqe_fc_la_trunk_linkmask_MASK             0x000000F
4218 #define lpfc_acqe_fc_la_trunk_linkmask_WORD             word1
4219 #define LPFC_FC_LA_FAULT_NONE           0x0
4220 #define LPFC_FC_LA_FAULT_LOCAL          0x1
4221 #define LPFC_FC_LA_FAULT_REMOTE         0x2
4222         uint32_t event_tag;
4223         uint32_t trailer;
4224 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK           0x1
4225 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK       0x2
4226 };
4227
4228 struct lpfc_acqe_misconfigured_event {
4229         struct {
4230         uint32_t word0;
4231 #define lpfc_sli_misconfigured_port0_state_SHIFT        0
4232 #define lpfc_sli_misconfigured_port0_state_MASK         0x000000FF
4233 #define lpfc_sli_misconfigured_port0_state_WORD         word0
4234 #define lpfc_sli_misconfigured_port1_state_SHIFT        8
4235 #define lpfc_sli_misconfigured_port1_state_MASK         0x000000FF
4236 #define lpfc_sli_misconfigured_port1_state_WORD         word0
4237 #define lpfc_sli_misconfigured_port2_state_SHIFT        16
4238 #define lpfc_sli_misconfigured_port2_state_MASK         0x000000FF
4239 #define lpfc_sli_misconfigured_port2_state_WORD         word0
4240 #define lpfc_sli_misconfigured_port3_state_SHIFT        24
4241 #define lpfc_sli_misconfigured_port3_state_MASK         0x000000FF
4242 #define lpfc_sli_misconfigured_port3_state_WORD         word0
4243         uint32_t word1;
4244 #define lpfc_sli_misconfigured_port0_op_SHIFT           0
4245 #define lpfc_sli_misconfigured_port0_op_MASK            0x00000001
4246 #define lpfc_sli_misconfigured_port0_op_WORD            word1
4247 #define lpfc_sli_misconfigured_port0_severity_SHIFT     1
4248 #define lpfc_sli_misconfigured_port0_severity_MASK      0x00000003
4249 #define lpfc_sli_misconfigured_port0_severity_WORD      word1
4250 #define lpfc_sli_misconfigured_port1_op_SHIFT           8
4251 #define lpfc_sli_misconfigured_port1_op_MASK            0x00000001
4252 #define lpfc_sli_misconfigured_port1_op_WORD            word1
4253 #define lpfc_sli_misconfigured_port1_severity_SHIFT     9
4254 #define lpfc_sli_misconfigured_port1_severity_MASK      0x00000003
4255 #define lpfc_sli_misconfigured_port1_severity_WORD      word1
4256 #define lpfc_sli_misconfigured_port2_op_SHIFT           16
4257 #define lpfc_sli_misconfigured_port2_op_MASK            0x00000001
4258 #define lpfc_sli_misconfigured_port2_op_WORD            word1
4259 #define lpfc_sli_misconfigured_port2_severity_SHIFT     17
4260 #define lpfc_sli_misconfigured_port2_severity_MASK      0x00000003
4261 #define lpfc_sli_misconfigured_port2_severity_WORD      word1
4262 #define lpfc_sli_misconfigured_port3_op_SHIFT           24
4263 #define lpfc_sli_misconfigured_port3_op_MASK            0x00000001
4264 #define lpfc_sli_misconfigured_port3_op_WORD            word1
4265 #define lpfc_sli_misconfigured_port3_severity_SHIFT     25
4266 #define lpfc_sli_misconfigured_port3_severity_MASK      0x00000003
4267 #define lpfc_sli_misconfigured_port3_severity_WORD      word1
4268         } theEvent;
4269 #define LPFC_SLI_EVENT_STATUS_VALID                     0x00
4270 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT       0x01
4271 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE        0x02
4272 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED       0x03
4273 #define LPFC_SLI_EVENT_STATUS_UNQUALIFIED       0x04
4274 #define LPFC_SLI_EVENT_STATUS_UNCERTIFIED       0x05
4275 };
4276
4277 struct lpfc_acqe_sli {
4278         uint32_t event_data1;
4279         uint32_t event_data2;
4280         uint32_t reserved;
4281         uint32_t trailer;
4282 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR          0x1
4283 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP           0x2
4284 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP           0x3
4285 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST          0x4
4286 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP           0x5
4287 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED       0x9
4288 #define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT        0xA
4289 #define LPFC_SLI_EVENT_TYPE_MISCONF_FAWWN       0xF
4290 #define LPFC_SLI_EVENT_TYPE_EEPROM_FAILURE      0x10
4291 };
4292
4293 /*
4294  * Define the bootstrap mailbox (bmbx) region used to communicate
4295  * mailbox command between the host and port. The mailbox consists
4296  * of a payload area of 256 bytes and a completion queue of length
4297  * 16 bytes.
4298  */
4299 struct lpfc_bmbx_create {
4300         struct lpfc_mqe mqe;
4301         struct lpfc_mcqe mcqe;
4302 };
4303
4304 #define SGL_ALIGN_SZ 64
4305 #define SGL_PAGE_SIZE 4096
4306 /* align SGL addr on a size boundary - adjust address up */
4307 #define NO_XRI  0xffff
4308
4309 struct wqe_common {
4310         uint32_t word6;
4311 #define wqe_xri_tag_SHIFT     0
4312 #define wqe_xri_tag_MASK      0x0000FFFF
4313 #define wqe_xri_tag_WORD      word6
4314 #define wqe_ctxt_tag_SHIFT    16
4315 #define wqe_ctxt_tag_MASK     0x0000FFFF
4316 #define wqe_ctxt_tag_WORD     word6
4317         uint32_t word7;
4318 #define wqe_dif_SHIFT         0
4319 #define wqe_dif_MASK          0x00000003
4320 #define wqe_dif_WORD          word7
4321 #define LPFC_WQE_DIF_PASSTHRU   1
4322 #define LPFC_WQE_DIF_STRIP      2
4323 #define LPFC_WQE_DIF_INSERT     3
4324 #define wqe_ct_SHIFT          2
4325 #define wqe_ct_MASK           0x00000003
4326 #define wqe_ct_WORD           word7
4327 #define wqe_status_SHIFT      4
4328 #define wqe_status_MASK       0x0000000f
4329 #define wqe_status_WORD       word7
4330 #define wqe_cmnd_SHIFT        8
4331 #define wqe_cmnd_MASK         0x000000ff
4332 #define wqe_cmnd_WORD         word7
4333 #define wqe_class_SHIFT       16
4334 #define wqe_class_MASK        0x00000007
4335 #define wqe_class_WORD        word7
4336 #define wqe_ar_SHIFT          19
4337 #define wqe_ar_MASK           0x00000001
4338 #define wqe_ar_WORD           word7
4339 #define wqe_ag_SHIFT          wqe_ar_SHIFT
4340 #define wqe_ag_MASK           wqe_ar_MASK
4341 #define wqe_ag_WORD           wqe_ar_WORD
4342 #define wqe_pu_SHIFT          20
4343 #define wqe_pu_MASK           0x00000003
4344 #define wqe_pu_WORD           word7
4345 #define wqe_erp_SHIFT         22
4346 #define wqe_erp_MASK          0x00000001
4347 #define wqe_erp_WORD          word7
4348 #define wqe_conf_SHIFT        wqe_erp_SHIFT
4349 #define wqe_conf_MASK         wqe_erp_MASK
4350 #define wqe_conf_WORD         wqe_erp_WORD
4351 #define wqe_lnk_SHIFT         23
4352 #define wqe_lnk_MASK          0x00000001
4353 #define wqe_lnk_WORD          word7
4354 #define wqe_tmo_SHIFT         24
4355 #define wqe_tmo_MASK          0x000000ff
4356 #define wqe_tmo_WORD          word7
4357         uint32_t abort_tag; /* word 8 in WQE */
4358         uint32_t word9;
4359 #define wqe_reqtag_SHIFT      0
4360 #define wqe_reqtag_MASK       0x0000FFFF
4361 #define wqe_reqtag_WORD       word9
4362 #define wqe_temp_rpi_SHIFT    16
4363 #define wqe_temp_rpi_MASK     0x0000FFFF
4364 #define wqe_temp_rpi_WORD     word9
4365 #define wqe_rcvoxid_SHIFT     16
4366 #define wqe_rcvoxid_MASK      0x0000FFFF
4367 #define wqe_rcvoxid_WORD      word9
4368 #define wqe_sof_SHIFT         24
4369 #define wqe_sof_MASK          0x000000FF
4370 #define wqe_sof_WORD          word9
4371 #define wqe_eof_SHIFT         16
4372 #define wqe_eof_MASK          0x000000FF
4373 #define wqe_eof_WORD          word9
4374         uint32_t word10;
4375 #define wqe_ebde_cnt_SHIFT    0
4376 #define wqe_ebde_cnt_MASK     0x0000000f
4377 #define wqe_ebde_cnt_WORD     word10
4378 #define wqe_nvme_SHIFT        4
4379 #define wqe_nvme_MASK         0x00000001
4380 #define wqe_nvme_WORD         word10
4381 #define wqe_oas_SHIFT         6
4382 #define wqe_oas_MASK          0x00000001
4383 #define wqe_oas_WORD          word10
4384 #define wqe_lenloc_SHIFT      7
4385 #define wqe_lenloc_MASK       0x00000003
4386 #define wqe_lenloc_WORD       word10
4387 #define LPFC_WQE_LENLOC_NONE            0
4388 #define LPFC_WQE_LENLOC_WORD3   1
4389 #define LPFC_WQE_LENLOC_WORD12  2
4390 #define LPFC_WQE_LENLOC_WORD4   3
4391 #define wqe_qosd_SHIFT        9
4392 #define wqe_qosd_MASK         0x00000001
4393 #define wqe_qosd_WORD         word10
4394 #define wqe_xbl_SHIFT         11
4395 #define wqe_xbl_MASK          0x00000001
4396 #define wqe_xbl_WORD          word10
4397 #define wqe_iod_SHIFT         13
4398 #define wqe_iod_MASK          0x00000001
4399 #define wqe_iod_WORD          word10
4400 #define LPFC_WQE_IOD_NONE       0
4401 #define LPFC_WQE_IOD_WRITE      0
4402 #define LPFC_WQE_IOD_READ       1
4403 #define wqe_dbde_SHIFT        14
4404 #define wqe_dbde_MASK         0x00000001
4405 #define wqe_dbde_WORD         word10
4406 #define wqe_wqes_SHIFT        15
4407 #define wqe_wqes_MASK         0x00000001
4408 #define wqe_wqes_WORD         word10
4409 /* Note that this field overlaps above fields */
4410 #define wqe_wqid_SHIFT        1
4411 #define wqe_wqid_MASK         0x00007fff
4412 #define wqe_wqid_WORD         word10
4413 #define wqe_pri_SHIFT         16
4414 #define wqe_pri_MASK          0x00000007
4415 #define wqe_pri_WORD          word10
4416 #define wqe_pv_SHIFT          19
4417 #define wqe_pv_MASK           0x00000001
4418 #define wqe_pv_WORD           word10
4419 #define wqe_xc_SHIFT          21
4420 #define wqe_xc_MASK           0x00000001
4421 #define wqe_xc_WORD           word10
4422 #define wqe_sr_SHIFT          22
4423 #define wqe_sr_MASK           0x00000001
4424 #define wqe_sr_WORD           word10
4425 #define wqe_ccpe_SHIFT        23
4426 #define wqe_ccpe_MASK         0x00000001
4427 #define wqe_ccpe_WORD         word10
4428 #define wqe_ccp_SHIFT         24
4429 #define wqe_ccp_MASK          0x000000ff
4430 #define wqe_ccp_WORD          word10
4431         uint32_t word11;
4432 #define wqe_cmd_type_SHIFT    0
4433 #define wqe_cmd_type_MASK     0x0000000f
4434 #define wqe_cmd_type_WORD     word11
4435 #define wqe_els_id_SHIFT      4
4436 #define wqe_els_id_MASK       0x00000003
4437 #define wqe_els_id_WORD       word11
4438 #define LPFC_ELS_ID_FLOGI       3
4439 #define LPFC_ELS_ID_FDISC       2
4440 #define LPFC_ELS_ID_LOGO        1
4441 #define LPFC_ELS_ID_DEFAULT     0
4442 #define wqe_irsp_SHIFT        4
4443 #define wqe_irsp_MASK         0x00000001
4444 #define wqe_irsp_WORD         word11
4445 #define wqe_pbde_SHIFT        5
4446 #define wqe_pbde_MASK         0x00000001
4447 #define wqe_pbde_WORD         word11
4448 #define wqe_sup_SHIFT         6
4449 #define wqe_sup_MASK          0x00000001
4450 #define wqe_sup_WORD          word11
4451 #define wqe_wqec_SHIFT        7
4452 #define wqe_wqec_MASK         0x00000001
4453 #define wqe_wqec_WORD         word11
4454 #define wqe_irsplen_SHIFT     8
4455 #define wqe_irsplen_MASK      0x0000000f
4456 #define wqe_irsplen_WORD      word11
4457 #define wqe_cqid_SHIFT        16
4458 #define wqe_cqid_MASK         0x0000ffff
4459 #define wqe_cqid_WORD         word11
4460 #define LPFC_WQE_CQ_ID_DEFAULT  0xffff
4461 };
4462
4463 struct wqe_did {
4464         uint32_t word5;
4465 #define wqe_els_did_SHIFT         0
4466 #define wqe_els_did_MASK          0x00FFFFFF
4467 #define wqe_els_did_WORD          word5
4468 #define wqe_xmit_bls_pt_SHIFT         28
4469 #define wqe_xmit_bls_pt_MASK          0x00000003
4470 #define wqe_xmit_bls_pt_WORD          word5
4471 #define wqe_xmit_bls_ar_SHIFT         30
4472 #define wqe_xmit_bls_ar_MASK          0x00000001
4473 #define wqe_xmit_bls_ar_WORD          word5
4474 #define wqe_xmit_bls_xo_SHIFT         31
4475 #define wqe_xmit_bls_xo_MASK          0x00000001
4476 #define wqe_xmit_bls_xo_WORD          word5
4477 };
4478
4479 struct lpfc_wqe_generic{
4480         struct ulp_bde64 bde;
4481         uint32_t word3;
4482         uint32_t word4;
4483         uint32_t word5;
4484         struct wqe_common wqe_com;
4485         uint32_t payload[4];
4486 };
4487
4488 struct els_request64_wqe {
4489         struct ulp_bde64 bde;
4490         uint32_t payload_len;
4491         uint32_t word4;
4492 #define els_req64_sid_SHIFT         0
4493 #define els_req64_sid_MASK          0x00FFFFFF
4494 #define els_req64_sid_WORD          word4
4495 #define els_req64_sp_SHIFT          24
4496 #define els_req64_sp_MASK           0x00000001
4497 #define els_req64_sp_WORD           word4
4498 #define els_req64_vf_SHIFT          25
4499 #define els_req64_vf_MASK           0x00000001
4500 #define els_req64_vf_WORD           word4
4501         struct wqe_did  wqe_dest;
4502         struct wqe_common wqe_com; /* words 6-11 */
4503         uint32_t word12;
4504 #define els_req64_vfid_SHIFT        1
4505 #define els_req64_vfid_MASK         0x00000FFF
4506 #define els_req64_vfid_WORD         word12
4507 #define els_req64_pri_SHIFT         13
4508 #define els_req64_pri_MASK          0x00000007
4509 #define els_req64_pri_WORD          word12
4510         uint32_t word13;
4511 #define els_req64_hopcnt_SHIFT      24
4512 #define els_req64_hopcnt_MASK       0x000000ff
4513 #define els_req64_hopcnt_WORD       word13
4514         uint32_t word14;
4515         uint32_t max_response_payload_len;
4516 };
4517
4518 struct xmit_els_rsp64_wqe {
4519         struct ulp_bde64 bde;
4520         uint32_t response_payload_len;
4521         uint32_t word4;
4522 #define els_rsp64_sid_SHIFT         0
4523 #define els_rsp64_sid_MASK          0x00FFFFFF
4524 #define els_rsp64_sid_WORD          word4
4525 #define els_rsp64_sp_SHIFT          24
4526 #define els_rsp64_sp_MASK           0x00000001
4527 #define els_rsp64_sp_WORD           word4
4528         struct wqe_did wqe_dest;
4529         struct wqe_common wqe_com; /* words 6-11 */
4530         uint32_t word12;
4531 #define wqe_rsp_temp_rpi_SHIFT    0
4532 #define wqe_rsp_temp_rpi_MASK     0x0000FFFF
4533 #define wqe_rsp_temp_rpi_WORD     word12
4534         uint32_t rsvd_13_15[3];
4535 };
4536
4537 struct xmit_bls_rsp64_wqe {
4538         uint32_t payload0;
4539 /* Payload0 for BA_ACC */
4540 #define xmit_bls_rsp64_acc_seq_id_SHIFT        16
4541 #define xmit_bls_rsp64_acc_seq_id_MASK         0x000000ff
4542 #define xmit_bls_rsp64_acc_seq_id_WORD         payload0
4543 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT   24
4544 #define xmit_bls_rsp64_acc_seq_id_vald_MASK    0x000000ff
4545 #define xmit_bls_rsp64_acc_seq_id_vald_WORD    payload0
4546 /* Payload0 for BA_RJT */
4547 #define xmit_bls_rsp64_rjt_vspec_SHIFT   0
4548 #define xmit_bls_rsp64_rjt_vspec_MASK    0x000000ff
4549 #define xmit_bls_rsp64_rjt_vspec_WORD    payload0
4550 #define xmit_bls_rsp64_rjt_expc_SHIFT    8
4551 #define xmit_bls_rsp64_rjt_expc_MASK     0x000000ff
4552 #define xmit_bls_rsp64_rjt_expc_WORD     payload0
4553 #define xmit_bls_rsp64_rjt_rsnc_SHIFT    16
4554 #define xmit_bls_rsp64_rjt_rsnc_MASK     0x000000ff
4555 #define xmit_bls_rsp64_rjt_rsnc_WORD     payload0
4556         uint32_t word1;
4557 #define xmit_bls_rsp64_rxid_SHIFT  0
4558 #define xmit_bls_rsp64_rxid_MASK   0x0000ffff
4559 #define xmit_bls_rsp64_rxid_WORD   word1
4560 #define xmit_bls_rsp64_oxid_SHIFT  16
4561 #define xmit_bls_rsp64_oxid_MASK   0x0000ffff
4562 #define xmit_bls_rsp64_oxid_WORD   word1
4563         uint32_t word2;
4564 #define xmit_bls_rsp64_seqcnthi_SHIFT  0
4565 #define xmit_bls_rsp64_seqcnthi_MASK   0x0000ffff
4566 #define xmit_bls_rsp64_seqcnthi_WORD   word2
4567 #define xmit_bls_rsp64_seqcntlo_SHIFT  16
4568 #define xmit_bls_rsp64_seqcntlo_MASK   0x0000ffff
4569 #define xmit_bls_rsp64_seqcntlo_WORD   word2
4570         uint32_t rsrvd3;
4571         uint32_t rsrvd4;
4572         struct wqe_did  wqe_dest;
4573         struct wqe_common wqe_com; /* words 6-11 */
4574         uint32_t word12;
4575 #define xmit_bls_rsp64_temprpi_SHIFT  0
4576 #define xmit_bls_rsp64_temprpi_MASK   0x0000ffff
4577 #define xmit_bls_rsp64_temprpi_WORD   word12
4578         uint32_t rsvd_13_15[3];
4579 };
4580
4581 struct wqe_rctl_dfctl {
4582         uint32_t word5;
4583 #define wqe_si_SHIFT 2
4584 #define wqe_si_MASK  0x000000001
4585 #define wqe_si_WORD  word5
4586 #define wqe_la_SHIFT 3
4587 #define wqe_la_MASK  0x000000001
4588 #define wqe_la_WORD  word5
4589 #define wqe_xo_SHIFT    6
4590 #define wqe_xo_MASK     0x000000001
4591 #define wqe_xo_WORD     word5
4592 #define wqe_ls_SHIFT 7
4593 #define wqe_ls_MASK  0x000000001
4594 #define wqe_ls_WORD  word5
4595 #define wqe_dfctl_SHIFT 8
4596 #define wqe_dfctl_MASK  0x0000000ff
4597 #define wqe_dfctl_WORD  word5
4598 #define wqe_type_SHIFT 16
4599 #define wqe_type_MASK  0x0000000ff
4600 #define wqe_type_WORD  word5
4601 #define wqe_rctl_SHIFT 24
4602 #define wqe_rctl_MASK  0x0000000ff
4603 #define wqe_rctl_WORD  word5
4604 };
4605
4606 struct xmit_seq64_wqe {
4607         struct ulp_bde64 bde;
4608         uint32_t rsvd3;
4609         uint32_t relative_offset;
4610         struct wqe_rctl_dfctl wge_ctl;
4611         struct wqe_common wqe_com; /* words 6-11 */
4612         uint32_t xmit_len;
4613         uint32_t rsvd_12_15[3];
4614 };
4615 struct xmit_bcast64_wqe {
4616         struct ulp_bde64 bde;
4617         uint32_t seq_payload_len;
4618         uint32_t rsvd4;
4619         struct wqe_rctl_dfctl wge_ctl; /* word 5 */
4620         struct wqe_common wqe_com;     /* words 6-11 */
4621         uint32_t rsvd_12_15[4];
4622 };
4623
4624 struct gen_req64_wqe {
4625         struct ulp_bde64 bde;
4626         uint32_t request_payload_len;
4627         uint32_t relative_offset;
4628         struct wqe_rctl_dfctl wge_ctl; /* word 5 */
4629         struct wqe_common wqe_com;     /* words 6-11 */
4630         uint32_t rsvd_12_14[3];
4631         uint32_t max_response_payload_len;
4632 };
4633
4634 /* Define NVME PRLI request to fabric. NVME is a
4635  * fabric-only protocol.
4636  * Updated to red-lined v1.08 on Sept 16, 2016
4637  */
4638 struct lpfc_nvme_prli {
4639         uint32_t word1;
4640         /* The Response Code is defined in the FCP PRLI lpfc_hw.h */
4641 #define prli_acc_rsp_code_SHIFT         8
4642 #define prli_acc_rsp_code_MASK          0x0000000f
4643 #define prli_acc_rsp_code_WORD          word1
4644 #define prli_estabImagePair_SHIFT       13
4645 #define prli_estabImagePair_MASK        0x00000001
4646 #define prli_estabImagePair_WORD        word1
4647 #define prli_type_code_ext_SHIFT        16
4648 #define prli_type_code_ext_MASK         0x000000ff
4649 #define prli_type_code_ext_WORD         word1
4650 #define prli_type_code_SHIFT            24
4651 #define prli_type_code_MASK             0x000000ff
4652 #define prli_type_code_WORD             word1
4653         uint32_t word_rsvd2;
4654         uint32_t word_rsvd3;
4655
4656         uint32_t word4;
4657 #define prli_fba_SHIFT                  0
4658 #define prli_fba_MASK                   0x00000001
4659 #define prli_fba_WORD                   word4
4660 #define prli_disc_SHIFT                 3
4661 #define prli_disc_MASK                  0x00000001
4662 #define prli_disc_WORD                  word4
4663 #define prli_tgt_SHIFT                  4
4664 #define prli_tgt_MASK                   0x00000001
4665 #define prli_tgt_WORD                   word4
4666 #define prli_init_SHIFT                 5
4667 #define prli_init_MASK                  0x00000001
4668 #define prli_init_WORD                  word4
4669 #define prli_conf_SHIFT                 7
4670 #define prli_conf_MASK                  0x00000001
4671 #define prli_conf_WORD                  word4
4672 #define prli_nsler_SHIFT                8
4673 #define prli_nsler_MASK                 0x00000001
4674 #define prli_nsler_WORD                 word4
4675         uint32_t word5;
4676 #define prli_fb_sz_SHIFT                0
4677 #define prli_fb_sz_MASK                 0x0000ffff
4678 #define prli_fb_sz_WORD                 word5
4679 #define LPFC_NVMET_FB_SZ_MAX  65536   /* Driver target mode only. */
4680 };
4681
4682 struct create_xri_wqe {
4683         uint32_t rsrvd[5];           /* words 0-4 */
4684         struct wqe_did  wqe_dest;  /* word 5 */
4685         struct wqe_common wqe_com; /* words 6-11 */
4686         uint32_t rsvd_12_15[4];         /* word 12-15 */
4687 };
4688
4689 #define INHIBIT_ABORT 1
4690 #define T_REQUEST_TAG 3
4691 #define T_XRI_TAG 1
4692
4693 struct abort_cmd_wqe {
4694         uint32_t rsrvd[3];
4695         uint32_t word3;
4696 #define abort_cmd_ia_SHIFT  0
4697 #define abort_cmd_ia_MASK  0x000000001
4698 #define abort_cmd_ia_WORD  word3
4699 #define abort_cmd_criteria_SHIFT  8
4700 #define abort_cmd_criteria_MASK  0x0000000ff
4701 #define abort_cmd_criteria_WORD  word3
4702         uint32_t rsrvd4;
4703         uint32_t rsrvd5;
4704         struct wqe_common wqe_com;     /* words 6-11 */
4705         uint32_t rsvd_12_15[4];         /* word 12-15 */
4706 };
4707
4708 struct fcp_iwrite64_wqe {
4709         struct ulp_bde64 bde;
4710         uint32_t word3;
4711 #define cmd_buff_len_SHIFT  16
4712 #define cmd_buff_len_MASK  0x00000ffff
4713 #define cmd_buff_len_WORD  word3
4714 #define payload_offset_len_SHIFT 0
4715 #define payload_offset_len_MASK 0x0000ffff
4716 #define payload_offset_len_WORD word3
4717         uint32_t total_xfer_len;
4718         uint32_t initial_xfer_len;
4719         struct wqe_common wqe_com;     /* words 6-11 */
4720         uint32_t rsrvd12;
4721         struct ulp_bde64 ph_bde;       /* words 13-15 */
4722 };
4723
4724 struct fcp_iread64_wqe {
4725         struct ulp_bde64 bde;
4726         uint32_t word3;
4727 #define cmd_buff_len_SHIFT  16
4728 #define cmd_buff_len_MASK  0x00000ffff
4729 #define cmd_buff_len_WORD  word3
4730 #define payload_offset_len_SHIFT 0
4731 #define payload_offset_len_MASK 0x0000ffff
4732 #define payload_offset_len_WORD word3
4733         uint32_t total_xfer_len;       /* word 4 */
4734         uint32_t rsrvd5;               /* word 5 */
4735         struct wqe_common wqe_com;     /* words 6-11 */
4736         uint32_t rsrvd12;
4737         struct ulp_bde64 ph_bde;       /* words 13-15 */
4738 };
4739
4740 struct fcp_icmnd64_wqe {
4741         struct ulp_bde64 bde;          /* words 0-2 */
4742         uint32_t word3;
4743 #define cmd_buff_len_SHIFT  16
4744 #define cmd_buff_len_MASK  0x00000ffff
4745 #define cmd_buff_len_WORD  word3
4746 #define payload_offset_len_SHIFT 0
4747 #define payload_offset_len_MASK 0x0000ffff
4748 #define payload_offset_len_WORD word3
4749         uint32_t rsrvd4;               /* word 4 */
4750         uint32_t rsrvd5;               /* word 5 */
4751         struct wqe_common wqe_com;     /* words 6-11 */
4752         uint32_t rsvd_12_15[4];        /* word 12-15 */
4753 };
4754
4755 struct fcp_trsp64_wqe {
4756         struct ulp_bde64 bde;
4757         uint32_t response_len;
4758         uint32_t rsvd_4_5[2];
4759         struct wqe_common wqe_com;      /* words 6-11 */
4760         uint32_t rsvd_12_15[4];         /* word 12-15 */
4761 };
4762
4763 struct fcp_tsend64_wqe {
4764         struct ulp_bde64 bde;
4765         uint32_t payload_offset_len;
4766         uint32_t relative_offset;
4767         uint32_t reserved;
4768         struct wqe_common wqe_com;     /* words 6-11 */
4769         uint32_t fcp_data_len;         /* word 12 */
4770         uint32_t rsvd_13_15[3];        /* word 13-15 */
4771 };
4772
4773 struct fcp_treceive64_wqe {
4774         struct ulp_bde64 bde;
4775         uint32_t payload_offset_len;
4776         uint32_t relative_offset;
4777         uint32_t reserved;
4778         struct wqe_common wqe_com;     /* words 6-11 */
4779         uint32_t fcp_data_len;         /* word 12 */
4780         uint32_t rsvd_13_15[3];        /* word 13-15 */
4781 };
4782 #define TXRDY_PAYLOAD_LEN      12
4783
4784 #define CMD_SEND_FRAME  0xE1
4785
4786 struct send_frame_wqe {
4787         struct ulp_bde64 bde;          /* words 0-2 */
4788         uint32_t frame_len;            /* word 3 */
4789         uint32_t fc_hdr_wd0;           /* word 4 */
4790         uint32_t fc_hdr_wd1;           /* word 5 */
4791         struct wqe_common wqe_com;     /* words 6-11 */
4792         uint32_t fc_hdr_wd2;           /* word 12 */
4793         uint32_t fc_hdr_wd3;           /* word 13 */
4794         uint32_t fc_hdr_wd4;           /* word 14 */
4795         uint32_t fc_hdr_wd5;           /* word 15 */
4796 };
4797
4798 union lpfc_wqe {
4799         uint32_t words[16];
4800         struct lpfc_wqe_generic generic;
4801         struct fcp_icmnd64_wqe fcp_icmd;
4802         struct fcp_iread64_wqe fcp_iread;
4803         struct fcp_iwrite64_wqe fcp_iwrite;
4804         struct abort_cmd_wqe abort_cmd;
4805         struct create_xri_wqe create_xri;
4806         struct xmit_bcast64_wqe xmit_bcast64;
4807         struct xmit_seq64_wqe xmit_sequence;
4808         struct xmit_bls_rsp64_wqe xmit_bls_rsp;
4809         struct xmit_els_rsp64_wqe xmit_els_rsp;
4810         struct els_request64_wqe els_req;
4811         struct gen_req64_wqe gen_req;
4812         struct fcp_trsp64_wqe fcp_trsp;
4813         struct fcp_tsend64_wqe fcp_tsend;
4814         struct fcp_treceive64_wqe fcp_treceive;
4815         struct send_frame_wqe send_frame;
4816 };
4817
4818 union lpfc_wqe128 {
4819         uint32_t words[32];
4820         struct lpfc_wqe_generic generic;
4821         struct fcp_icmnd64_wqe fcp_icmd;
4822         struct fcp_iread64_wqe fcp_iread;
4823         struct fcp_iwrite64_wqe fcp_iwrite;
4824         struct abort_cmd_wqe abort_cmd;
4825         struct create_xri_wqe create_xri;
4826         struct xmit_bcast64_wqe xmit_bcast64;
4827         struct xmit_seq64_wqe xmit_sequence;
4828         struct xmit_bls_rsp64_wqe xmit_bls_rsp;
4829         struct xmit_els_rsp64_wqe xmit_els_rsp;
4830         struct els_request64_wqe els_req;
4831         struct gen_req64_wqe gen_req;
4832         struct fcp_trsp64_wqe fcp_trsp;
4833         struct fcp_tsend64_wqe fcp_tsend;
4834         struct fcp_treceive64_wqe fcp_treceive;
4835         struct send_frame_wqe send_frame;
4836 };
4837
4838 #define MAGIC_NUMBER_G6 0xFEAA0003
4839 #define MAGIC_NUMBER_G7 0xFEAA0005
4840
4841 struct lpfc_grp_hdr {
4842         uint32_t size;
4843         uint32_t magic_number;
4844         uint32_t word2;
4845 #define lpfc_grp_hdr_file_type_SHIFT    24
4846 #define lpfc_grp_hdr_file_type_MASK     0x000000FF
4847 #define lpfc_grp_hdr_file_type_WORD     word2
4848 #define lpfc_grp_hdr_id_SHIFT           16
4849 #define lpfc_grp_hdr_id_MASK            0x000000FF
4850 #define lpfc_grp_hdr_id_WORD            word2
4851         uint8_t rev_name[128];
4852         uint8_t date[12];
4853         uint8_t revision[32];
4854 };
4855
4856 /* Defines for WQE command type */
4857 #define FCP_COMMAND             0x0
4858 #define NVME_READ_CMD           0x0
4859 #define FCP_COMMAND_DATA_OUT    0x1
4860 #define NVME_WRITE_CMD          0x1
4861 #define FCP_COMMAND_TRECEIVE    0x2
4862 #define FCP_COMMAND_TRSP        0x3
4863 #define FCP_COMMAND_TSEND       0x7
4864 #define OTHER_COMMAND           0x8
4865 #define ELS_COMMAND_NON_FIP     0xC
4866 #define ELS_COMMAND_FIP         0xD
4867
4868 #define LPFC_NVME_EMBED_CMD     0x0
4869 #define LPFC_NVME_EMBED_WRITE   0x1
4870 #define LPFC_NVME_EMBED_READ    0x2
4871
4872 /* WQE Commands */
4873 #define CMD_ABORT_XRI_WQE       0x0F
4874 #define CMD_XMIT_SEQUENCE64_WQE 0x82
4875 #define CMD_XMIT_BCAST64_WQE    0x84
4876 #define CMD_ELS_REQUEST64_WQE   0x8A
4877 #define CMD_XMIT_ELS_RSP64_WQE  0x95
4878 #define CMD_XMIT_BLS_RSP64_WQE  0x97
4879 #define CMD_FCP_IWRITE64_WQE    0x98
4880 #define CMD_FCP_IREAD64_WQE     0x9A
4881 #define CMD_FCP_ICMND64_WQE     0x9C
4882 #define CMD_FCP_TSEND64_WQE     0x9F
4883 #define CMD_FCP_TRECEIVE64_WQE  0xA1
4884 #define CMD_FCP_TRSP64_WQE      0xA3
4885 #define CMD_GEN_REQUEST64_WQE   0xC2
4886
4887 #define CMD_WQE_MASK            0xff
4888
4889
4890 #define LPFC_FW_DUMP    1
4891 #define LPFC_FW_RESET   2
4892 #define LPFC_DV_RESET   3