drivers/scsi/qla2xxx/qla_nx.c

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2014 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7 #include "qla_def.h"
   8 #include <linux/delay.h>
   9 #include <linux/io-64-nonatomic-lo-hi.h>
  10 #include <linux/pci.h>
  11 #include <linux/ratelimit.h>
  12 #include <linux/vmalloc.h>
  13 #include <scsi/scsi_tcq.h>
  14
  15 #define MASK(n)                 ((1ULL<<(n))-1)
  16 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
  17         ((addr >> 25) & 0x3ff))
  18 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
  19         ((addr >> 25) & 0x3ff))
  20 #define MS_WIN(addr) (addr & 0x0ffc0000)
  21 #define QLA82XX_PCI_MN_2M   (0)
  22 #define QLA82XX_PCI_MS_2M   (0x80000)
  23 #define QLA82XX_PCI_OCM0_2M (0xc0000)
  24 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
  25 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
  26 #define BLOCK_PROTECT_BITS 0x0F
  27
  28 /* CRB window related */
  29 #define CRB_BLK(off)    ((off >> 20) & 0x3f)
  30 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  31 #define CRB_WINDOW_2M   (0x130060)
  32 #define QLA82XX_PCI_CAMQM_2M_END        (0x04800800UL)
  33 #define CRB_HI(off)     ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
  34                         ((off) & 0xf0000))
  35 #define QLA82XX_PCI_CAMQM_2M_BASE       (0x000ff800UL)
  36 #define CRB_INDIRECT_2M (0x1e0000UL)
  37
  38 #define MAX_CRB_XFORM 60
  39 static unsigned long crb_addr_xform[MAX_CRB_XFORM];
  40 static int qla82xx_crb_table_initialized;
  41
  42 #define qla82xx_crb_addr_transform(name) \
  43         (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
  44         QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
  45
  46 const int MD_MIU_TEST_AGT_RDDATA[] = {
  47         0x410000A8, 0x410000AC,
  48         0x410000B8, 0x410000BC
  49 };
  50
  51 static void qla82xx_crb_addr_transform_setup(void)
  52 {
  53         qla82xx_crb_addr_transform(XDMA);
  54         qla82xx_crb_addr_transform(TIMR);
  55         qla82xx_crb_addr_transform(SRE);
  56         qla82xx_crb_addr_transform(SQN3);
  57         qla82xx_crb_addr_transform(SQN2);
  58         qla82xx_crb_addr_transform(SQN1);
  59         qla82xx_crb_addr_transform(SQN0);
  60         qla82xx_crb_addr_transform(SQS3);
  61         qla82xx_crb_addr_transform(SQS2);
  62         qla82xx_crb_addr_transform(SQS1);
  63         qla82xx_crb_addr_transform(SQS0);
  64         qla82xx_crb_addr_transform(RPMX7);
  65         qla82xx_crb_addr_transform(RPMX6);
  66         qla82xx_crb_addr_transform(RPMX5);
  67         qla82xx_crb_addr_transform(RPMX4);
  68         qla82xx_crb_addr_transform(RPMX3);
  69         qla82xx_crb_addr_transform(RPMX2);
  70         qla82xx_crb_addr_transform(RPMX1);
  71         qla82xx_crb_addr_transform(RPMX0);
  72         qla82xx_crb_addr_transform(ROMUSB);
  73         qla82xx_crb_addr_transform(SN);
  74         qla82xx_crb_addr_transform(QMN);
  75         qla82xx_crb_addr_transform(QMS);
  76         qla82xx_crb_addr_transform(PGNI);
  77         qla82xx_crb_addr_transform(PGND);
  78         qla82xx_crb_addr_transform(PGN3);
  79         qla82xx_crb_addr_transform(PGN2);
  80         qla82xx_crb_addr_transform(PGN1);
  81         qla82xx_crb_addr_transform(PGN0);
  82         qla82xx_crb_addr_transform(PGSI);
  83         qla82xx_crb_addr_transform(PGSD);
  84         qla82xx_crb_addr_transform(PGS3);
  85         qla82xx_crb_addr_transform(PGS2);
  86         qla82xx_crb_addr_transform(PGS1);
  87         qla82xx_crb_addr_transform(PGS0);
  88         qla82xx_crb_addr_transform(PS);
  89         qla82xx_crb_addr_transform(PH);
  90         qla82xx_crb_addr_transform(NIU);
  91         qla82xx_crb_addr_transform(I2Q);
  92         qla82xx_crb_addr_transform(EG);
  93         qla82xx_crb_addr_transform(MN);
  94         qla82xx_crb_addr_transform(MS);
  95         qla82xx_crb_addr_transform(CAS2);
  96         qla82xx_crb_addr_transform(CAS1);
  97         qla82xx_crb_addr_transform(CAS0);
  98         qla82xx_crb_addr_transform(CAM);
  99         qla82xx_crb_addr_transform(C2C1);
 100         qla82xx_crb_addr_transform(C2C0);
 101         qla82xx_crb_addr_transform(SMB);
 102         qla82xx_crb_addr_transform(OCM0);
 103         /*
 104          * Used only in P3 just define it for P2 also.
 105          */
 106         qla82xx_crb_addr_transform(I2C0);
 107
 108         qla82xx_crb_table_initialized = 1;
 109 }
 110
 111 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
 112         {{{0, 0,         0,         0} } },
 113         {{{1, 0x0100000, 0x0102000, 0x120000},
 114         {1, 0x0110000, 0x0120000, 0x130000},
 115         {1, 0x0120000, 0x0122000, 0x124000},
 116         {1, 0x0130000, 0x0132000, 0x126000},
 117         {1, 0x0140000, 0x0142000, 0x128000},
 118         {1, 0x0150000, 0x0152000, 0x12a000},
 119         {1, 0x0160000, 0x0170000, 0x110000},
 120         {1, 0x0170000, 0x0172000, 0x12e000},
 121         {0, 0x0000000, 0x0000000, 0x000000},
 122         {0, 0x0000000, 0x0000000, 0x000000},
 123         {0, 0x0000000, 0x0000000, 0x000000},
 124         {0, 0x0000000, 0x0000000, 0x000000},
 125         {0, 0x0000000, 0x0000000, 0x000000},
 126         {0, 0x0000000, 0x0000000, 0x000000},
 127         {1, 0x01e0000, 0x01e0800, 0x122000},
 128         {0, 0x0000000, 0x0000000, 0x000000} } } ,
 129         {{{1, 0x0200000, 0x0210000, 0x180000} } },
 130         {{{0, 0,         0,         0} } },
 131         {{{1, 0x0400000, 0x0401000, 0x169000} } },
 132         {{{1, 0x0500000, 0x0510000, 0x140000} } },
 133         {{{1, 0x0600000, 0x0610000, 0x1c0000} } },
 134         {{{1, 0x0700000, 0x0704000, 0x1b8000} } },
 135         {{{1, 0x0800000, 0x0802000, 0x170000},
 136         {0, 0x0000000, 0x0000000, 0x000000},
 137         {0, 0x0000000, 0x0000000, 0x000000},
 138         {0, 0x0000000, 0x0000000, 0x000000},
 139         {0, 0x0000000, 0x0000000, 0x000000},
 140         {0, 0x0000000, 0x0000000, 0x000000},
 141         {0, 0x0000000, 0x0000000, 0x000000},
 142         {0, 0x0000000, 0x0000000, 0x000000},
 143         {0, 0x0000000, 0x0000000, 0x000000},
 144         {0, 0x0000000, 0x0000000, 0x000000},
 145         {0, 0x0000000, 0x0000000, 0x000000},
 146         {0, 0x0000000, 0x0000000, 0x000000},
 147         {0, 0x0000000, 0x0000000, 0x000000},
 148         {0, 0x0000000, 0x0000000, 0x000000},
 149         {0, 0x0000000, 0x0000000, 0x000000},
 150         {1, 0x08f0000, 0x08f2000, 0x172000} } },
 151         {{{1, 0x0900000, 0x0902000, 0x174000},
 152         {0, 0x0000000, 0x0000000, 0x000000},
 153         {0, 0x0000000, 0x0000000, 0x000000},
 154         {0, 0x0000000, 0x0000000, 0x000000},
 155         {0, 0x0000000, 0x0000000, 0x000000},
 156         {0, 0x0000000, 0x0000000, 0x000000},
 157         {0, 0x0000000, 0x0000000, 0x000000},
 158         {0, 0x0000000, 0x0000000, 0x000000},
 159         {0, 0x0000000, 0x0000000, 0x000000},
 160         {0, 0x0000000, 0x0000000, 0x000000},
 161         {0, 0x0000000, 0x0000000, 0x000000},
 162         {0, 0x0000000, 0x0000000, 0x000000},
 163         {0, 0x0000000, 0x0000000, 0x000000},
 164         {0, 0x0000000, 0x0000000, 0x000000},
 165         {0, 0x0000000, 0x0000000, 0x000000},
 166         {1, 0x09f0000, 0x09f2000, 0x176000} } },
 167         {{{0, 0x0a00000, 0x0a02000, 0x178000},
 168         {0, 0x0000000, 0x0000000, 0x000000},
 169         {0, 0x0000000, 0x0000000, 0x000000},
 170         {0, 0x0000000, 0x0000000, 0x000000},
 171         {0, 0x0000000, 0x0000000, 0x000000},
 172         {0, 0x0000000, 0x0000000, 0x000000},
 173         {0, 0x0000000, 0x0000000, 0x000000},
 174         {0, 0x0000000, 0x0000000, 0x000000},
 175         {0, 0x0000000, 0x0000000, 0x000000},
 176         {0, 0x0000000, 0x0000000, 0x000000},
 177         {0, 0x0000000, 0x0000000, 0x000000},
 178         {0, 0x0000000, 0x0000000, 0x000000},
 179         {0, 0x0000000, 0x0000000, 0x000000},
 180         {0, 0x0000000, 0x0000000, 0x000000},
 181         {0, 0x0000000, 0x0000000, 0x000000},
 182         {1, 0x0af0000, 0x0af2000, 0x17a000} } },
 183         {{{0, 0x0b00000, 0x0b02000, 0x17c000},
 184         {0, 0x0000000, 0x0000000, 0x000000},
 185         {0, 0x0000000, 0x0000000, 0x000000},
 186         {0, 0x0000000, 0x0000000, 0x000000},
 187         {0, 0x0000000, 0x0000000, 0x000000},
 188         {0, 0x0000000, 0x0000000, 0x000000},
 189         {0, 0x0000000, 0x0000000, 0x000000},
 190         {0, 0x0000000, 0x0000000, 0x000000},
 191         {0, 0x0000000, 0x0000000, 0x000000},
 192         {0, 0x0000000, 0x0000000, 0x000000},
 193         {0, 0x0000000, 0x0000000, 0x000000},
 194         {0, 0x0000000, 0x0000000, 0x000000},
 195         {0, 0x0000000, 0x0000000, 0x000000},
 196         {0, 0x0000000, 0x0000000, 0x000000},
 197         {0, 0x0000000, 0x0000000, 0x000000},
 198         {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
 199         {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },
 200         {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },
 201         {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },
 202         {{{1, 0x0f00000, 0x0f01000, 0x164000} } },
 203         {{{0, 0x1000000, 0x1004000, 0x1a8000} } },
 204         {{{1, 0x1100000, 0x1101000, 0x160000} } },
 205         {{{1, 0x1200000, 0x1201000, 0x161000} } },
 206         {{{1, 0x1300000, 0x1301000, 0x162000} } },
 207         {{{1, 0x1400000, 0x1401000, 0x163000} } },
 208         {{{1, 0x1500000, 0x1501000, 0x165000} } },
 209         {{{1, 0x1600000, 0x1601000, 0x166000} } },
 210         {{{0, 0,         0,         0} } },
 211         {{{0, 0,         0,         0} } },
 212         {{{0, 0,         0,         0} } },
 213         {{{0, 0,         0,         0} } },
 214         {{{0, 0,         0,         0} } },
 215         {{{0, 0,         0,         0} } },
 216         {{{1, 0x1d00000, 0x1d10000, 0x190000} } },
 217         {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },
 218         {{{1, 0x1f00000, 0x1f10000, 0x150000} } },
 219         {{{0} } },
 220         {{{1, 0x2100000, 0x2102000, 0x120000},
 221         {1, 0x2110000, 0x2120000, 0x130000},
 222         {1, 0x2120000, 0x2122000, 0x124000},
 223         {1, 0x2130000, 0x2132000, 0x126000},
 224         {1, 0x2140000, 0x2142000, 0x128000},
 225         {1, 0x2150000, 0x2152000, 0x12a000},
 226         {1, 0x2160000, 0x2170000, 0x110000},
 227         {1, 0x2170000, 0x2172000, 0x12e000},
 228         {0, 0x0000000, 0x0000000, 0x000000},
 229         {0, 0x0000000, 0x0000000, 0x000000},
 230         {0, 0x0000000, 0x0000000, 0x000000},
 231         {0, 0x0000000, 0x0000000, 0x000000},
 232         {0, 0x0000000, 0x0000000, 0x000000},
 233         {0, 0x0000000, 0x0000000, 0x000000},
 234         {0, 0x0000000, 0x0000000, 0x000000},
 235         {0, 0x0000000, 0x0000000, 0x000000} } },
 236         {{{1, 0x2200000, 0x2204000, 0x1b0000} } },
 237         {{{0} } },
 238         {{{0} } },
 239         {{{0} } },
 240         {{{0} } },
 241         {{{0} } },
 242         {{{1, 0x2800000, 0x2804000, 0x1a4000} } },
 243         {{{1, 0x2900000, 0x2901000, 0x16b000} } },
 244         {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },
 245         {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },
 246         {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },
 247         {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },
 248         {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },
 249         {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },
 250         {{{1, 0x3000000, 0x3000400, 0x1adc00} } },
 251         {{{0, 0x3100000, 0x3104000, 0x1a8000} } },
 252         {{{1, 0x3200000, 0x3204000, 0x1d4000} } },
 253         {{{1, 0x3300000, 0x3304000, 0x1a0000} } },
 254         {{{0} } },
 255         {{{1, 0x3500000, 0x3500400, 0x1ac000} } },
 256         {{{1, 0x3600000, 0x3600400, 0x1ae000} } },
 257         {{{1, 0x3700000, 0x3700400, 0x1ae400} } },
 258         {{{1, 0x3800000, 0x3804000, 0x1d0000} } },
 259         {{{1, 0x3900000, 0x3904000, 0x1b4000} } },
 260         {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },
 261         {{{0} } },
 262         {{{0} } },
 263         {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },
 264         {{{1, 0x3e00000, 0x3e01000, 0x167000} } },
 265         {{{1, 0x3f00000, 0x3f01000, 0x168000} } }
 266 };
 267
 268 /*
 269  * top 12 bits of crb internal address (hub, agent)
 270  */
 271 static unsigned qla82xx_crb_hub_agt[64] = {
 272         0,
 273         QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
 274         QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
 275         QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
 276         0,
 277         QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
 278         QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
 279         QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
 280         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
 281         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
 282         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
 283         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
 284         QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
 285         QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
 286         QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
 287         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
 288         QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
 289         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
 290         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
 291         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
 292         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
 293         QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
 294         QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
 295         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
 296         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
 297         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
 298         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
 299         0,
 300         QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
 301         QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
 302         0,
 303         QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
 304         0,
 305         QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
 306         QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
 307         0,
 308         0,
 309         0,
 310         0,
 311         0,
 312         QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
 313         0,
 314         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
 315         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
 316         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
 317         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
 318         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
 319         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
 320         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
 321         QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
 322         QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
 323         QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
 324         0,
 325         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
 326         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
 327         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
 328         QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
 329         0,
 330         QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
 331         QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
 332         QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
 333         0,
 334         QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
 335         0,
 336 };
 337
 338 /* Device states */
 339 static char *q_dev_state[] = {
 340          "Unknown",
 341         "Cold",
 342         "Initializing",
 343         "Ready",
 344         "Need Reset",
 345         "Need Quiescent",
 346         "Failed",
 347         "Quiescent",
 348 };
 349
 350 char *qdev_state(uint32_t dev_state)
 351 {
 352         return q_dev_state[dev_state];
 353 }
 354
 355 /*
 356  * In: 'off_in' is offset from CRB space in 128M pci map
 357  * Out: 'off_out' is 2M pci map addr
 358  * side effect: lock crb window
 359  */
 360 static void
 361 qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong off_in,
 362                              void __iomem **off_out)
 363 {
 364         u32 win_read;
 365         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 366
 367         ha->crb_win = CRB_HI(off_in);
 368         writel(ha->crb_win, CRB_WINDOW_2M + ha->nx_pcibase);
 369
 370         /* Read back value to make sure write has gone through before trying
 371          * to use it.
 372          */
 373         win_read = RD_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase);
 374         if (win_read != ha->crb_win) {
 375                 ql_dbg(ql_dbg_p3p, vha, 0xb000,
 376                     "%s: Written crbwin (0x%x) "
 377                     "!= Read crbwin (0x%x), off=0x%lx.\n",
 378                     __func__, ha->crb_win, win_read, off_in);
 379         }
 380         *off_out = (off_in & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
 381 }
 382
 383 static inline unsigned long
 384 qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off)
 385 {
 386         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 387         /* See if we are currently pointing to the region we want to use next */
 388         if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) {
 389                 /* No need to change window. PCIX and PCIEregs are in both
 390                  * regs are in both windows.
 391                  */
 392                 return off;
 393         }
 394
 395         if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) {
 396                 /* We are in first CRB window */
 397                 if (ha->curr_window != 0)
 398                         WARN_ON(1);
 399                 return off;
 400         }
 401
 402         if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) {
 403                 /* We are in second CRB window */
 404                 off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST;
 405
 406                 if (ha->curr_window != 1)
 407                         return off;
 408
 409                 /* We are in the QM or direct access
 410                  * register region - do nothing
 411                  */
 412                 if ((off >= QLA82XX_PCI_DIRECT_CRB) &&
 413                         (off < QLA82XX_PCI_CAMQM_MAX))
 414                         return off;
 415         }
 416         /* strange address given */
 417         ql_dbg(ql_dbg_p3p, vha, 0xb001,
 418             "%s: Warning: unm_nic_pci_set_crbwindow "
 419             "called with an unknown address(%llx).\n",
 420             QLA2XXX_DRIVER_NAME, off);
 421         return off;
 422 }
 423
 424 static int
 425 qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong off_in,
 426                             void __iomem **off_out)
 427 {
 428         struct crb_128M_2M_sub_block_map *m;
 429
 430         if (off_in >= QLA82XX_CRB_MAX)
 431                 return -1;
 432
 433         if (off_in >= QLA82XX_PCI_CAMQM && off_in < QLA82XX_PCI_CAMQM_2M_END) {
 434                 *off_out = (off_in - QLA82XX_PCI_CAMQM) +
 435                     QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
 436                 return 0;
 437         }
 438
 439         if (off_in < QLA82XX_PCI_CRBSPACE)
 440                 return -1;
 441
 442         off_in -= QLA82XX_PCI_CRBSPACE;
 443
 444         /* Try direct map */
 445         m = &crb_128M_2M_map[CRB_BLK(off_in)].sub_block[CRB_SUBBLK(off_in)];
 446
 447         if (m->valid && (m->start_128M <= off_in) && (m->end_128M > off_in)) {
 448                 *off_out = off_in + m->start_2M - m->start_128M + ha->nx_pcibase;
 449                 return 0;
 450         }
 451         /* Not in direct map, use crb window */
 452         *off_out = (void __iomem *)off_in;
 453         return 1;
 454 }
 455
 456 #define CRB_WIN_LOCK_TIMEOUT 100000000
 457 static int qla82xx_crb_win_lock(struct qla_hw_data *ha)
 458 {
 459         int done = 0, timeout = 0;
 460
 461         while (!done) {
 462                 /* acquire semaphore3 from PCI HW block */
 463                 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
 464                 if (done == 1)
 465                         break;
 466                 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
 467                         return -1;
 468                 timeout++;
 469         }
 470         qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum);
 471         return 0;
 472 }
 473
 474 int
 475 qla82xx_wr_32(struct qla_hw_data *ha, ulong off_in, u32 data)
 476 {
 477         void __iomem *off;
 478         unsigned long flags = 0;
 479         int rv;
 480
 481         rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off);
 482
 483         BUG_ON(rv == -1);
 484
 485         if (rv == 1) {
 486 #ifndef __CHECKER__
 487                 write_lock_irqsave(&ha->hw_lock, flags);
 488 #endif
 489                 qla82xx_crb_win_lock(ha);
 490                 qla82xx_pci_set_crbwindow_2M(ha, off_in, &off);
 491         }
 492
 493         writel(data, (void __iomem *)off);
 494
 495         if (rv == 1) {
 496                 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
 497 #ifndef __CHECKER__
 498                 write_unlock_irqrestore(&ha->hw_lock, flags);
 499 #endif
 500         }
 501         return 0;
 502 }
 503
 504 int
 505 qla82xx_rd_32(struct qla_hw_data *ha, ulong off_in)
 506 {
 507         void __iomem *off;
 508         unsigned long flags = 0;
 509         int rv;
 510         u32 data;
 511
 512         rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off);
 513
 514         BUG_ON(rv == -1);
 515
 516         if (rv == 1) {
 517 #ifndef __CHECKER__
 518                 write_lock_irqsave(&ha->hw_lock, flags);
 519 #endif
 520                 qla82xx_crb_win_lock(ha);
 521                 qla82xx_pci_set_crbwindow_2M(ha, off_in, &off);
 522         }
 523         data = RD_REG_DWORD(off);
 524
 525         if (rv == 1) {
 526                 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
 527 #ifndef __CHECKER__
 528                 write_unlock_irqrestore(&ha->hw_lock, flags);
 529 #endif
 530         }
 531         return data;
 532 }
 533
 534 #define IDC_LOCK_TIMEOUT 100000000
 535 int qla82xx_idc_lock(struct qla_hw_data *ha)
 536 {
 537         int i;
 538         int done = 0, timeout = 0;
 539
 540         while (!done) {
 541                 /* acquire semaphore5 from PCI HW block */
 542                 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
 543                 if (done == 1)
 544                         break;
 545                 if (timeout >= IDC_LOCK_TIMEOUT)
 546                         return -1;
 547
 548                 timeout++;
 549
 550                 /* Yield CPU */
 551                 if (!in_interrupt())
 552                         schedule();
 553                 else {
 554                         for (i = 0; i < 20; i++)
 555                                 cpu_relax();
 556                 }
 557         }
 558
 559         return 0;
 560 }
 561
 562 void qla82xx_idc_unlock(struct qla_hw_data *ha)
 563 {
 564         qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
 565 }
 566
 567 /*
 568  * check memory access boundary.
 569  * used by test agent. support ddr access only for now
 570  */
 571 static unsigned long
 572 qla82xx_pci_mem_bound_check(struct qla_hw_data *ha,
 573         unsigned long long addr, int size)
 574 {
 575         if (!addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
 576                 QLA82XX_ADDR_DDR_NET_MAX) ||
 577                 !addr_in_range(addr + size - 1, QLA82XX_ADDR_DDR_NET,
 578                 QLA82XX_ADDR_DDR_NET_MAX) ||
 579                 ((size != 1) && (size != 2) && (size != 4) && (size != 8)))
 580                         return 0;
 581         else
 582                 return 1;
 583 }
 584
 585 static int qla82xx_pci_set_window_warning_count;
 586
 587 static unsigned long
 588 qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr)
 589 {
 590         int window;
 591         u32 win_read;
 592         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 593
 594         if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
 595                 QLA82XX_ADDR_DDR_NET_MAX)) {
 596                 /* DDR network side */
 597                 window = MN_WIN(addr);
 598                 ha->ddr_mn_window = window;
 599                 qla82xx_wr_32(ha,
 600                         ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
 601                 win_read = qla82xx_rd_32(ha,
 602                         ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
 603                 if ((win_read << 17) != window) {
 604                         ql_dbg(ql_dbg_p3p, vha, 0xb003,
 605                             "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n",
 606                             __func__, window, win_read);
 607                 }
 608                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
 609         } else if (addr_in_range(addr, QLA82XX_ADDR_OCM0,
 610                 QLA82XX_ADDR_OCM0_MAX)) {
 611                 unsigned int temp1;
 612
 613                 if ((addr & 0x00ff800) == 0xff800) {
 614                         ql_log(ql_log_warn, vha, 0xb004,
 615                             "%s: QM access not handled.\n", __func__);
 616                         addr = -1UL;
 617                 }
 618                 window = OCM_WIN(addr);
 619                 ha->ddr_mn_window = window;
 620                 qla82xx_wr_32(ha,
 621                         ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
 622                 win_read = qla82xx_rd_32(ha,
 623                         ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
 624                 temp1 = ((window & 0x1FF) << 7) |
 625                     ((window & 0x0FFFE0000) >> 17);
 626                 if (win_read != temp1) {
 627                         ql_log(ql_log_warn, vha, 0xb005,
 628                             "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n",
 629                             __func__, temp1, win_read);
 630                 }
 631                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
 632
 633         } else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET,
 634                 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
 635                 /* QDR network side */
 636                 window = MS_WIN(addr);
 637                 ha->qdr_sn_window = window;
 638                 qla82xx_wr_32(ha,
 639                         ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window);
 640                 win_read = qla82xx_rd_32(ha,
 641                         ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
 642                 if (win_read != window) {
 643                         ql_log(ql_log_warn, vha, 0xb006,
 644                             "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n",
 645                             __func__, window, win_read);
 646                 }
 647                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
 648         } else {
 649                 /*
 650                  * peg gdb frequently accesses memory that doesn't exist,
 651                  * this limits the chit chat so debugging isn't slowed down.
 652                  */
 653                 if ((qla82xx_pci_set_window_warning_count++ < 8) ||
 654                     (qla82xx_pci_set_window_warning_count%64 == 0)) {
 655                         ql_log(ql_log_warn, vha, 0xb007,
 656                             "%s: Warning:%s Unknown address range!.\n",
 657                             __func__, QLA2XXX_DRIVER_NAME);
 658                 }
 659                 addr = -1UL;
 660         }
 661         return addr;
 662 }
 663
 664 /* check if address is in the same windows as the previous access */
 665 static int qla82xx_pci_is_same_window(struct qla_hw_data *ha,
 666         unsigned long long addr)
 667 {
 668         int                     window;
 669         unsigned long long      qdr_max;
 670
 671         qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
 672
 673         /* DDR network side */
 674         if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
 675                 QLA82XX_ADDR_DDR_NET_MAX))
 676                 BUG();
 677         else if (addr_in_range(addr, QLA82XX_ADDR_OCM0,
 678                 QLA82XX_ADDR_OCM0_MAX))
 679                 return 1;
 680         else if (addr_in_range(addr, QLA82XX_ADDR_OCM1,
 681                 QLA82XX_ADDR_OCM1_MAX))
 682                 return 1;
 683         else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) {
 684                 /* QDR network side */
 685                 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
 686                 if (ha->qdr_sn_window == window)
 687                         return 1;
 688         }
 689         return 0;
 690 }
 691
 692 static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha,
 693         u64 off, void *data, int size)
 694 {
 695         unsigned long   flags;
 696         void __iomem *addr = NULL;
 697         int             ret = 0;
 698         u64             start;
 699         uint8_t __iomem  *mem_ptr = NULL;
 700         unsigned long   mem_base;
 701         unsigned long   mem_page;
 702         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 703
 704         write_lock_irqsave(&ha->hw_lock, flags);
 705
 706         /*
 707          * If attempting to access unknown address or straddle hw windows,
 708          * do not access.
 709          */
 710         start = qla82xx_pci_set_window(ha, off);
 711         if ((start == -1UL) ||
 712                 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
 713                 write_unlock_irqrestore(&ha->hw_lock, flags);
 714                 ql_log(ql_log_fatal, vha, 0xb008,
 715                     "%s out of bound pci memory "
 716                     "access, offset is 0x%llx.\n",
 717                     QLA2XXX_DRIVER_NAME, off);
 718                 return -1;
 719         }
 720
 721         write_unlock_irqrestore(&ha->hw_lock, flags);
 722         mem_base = pci_resource_start(ha->pdev, 0);
 723         mem_page = start & PAGE_MASK;
 724         /* Map two pages whenever user tries to access addresses in two
 725         * consecutive pages.
 726         */
 727         if (mem_page != ((start + size - 1) & PAGE_MASK))
 728                 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
 729         else
 730                 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
 731         if (mem_ptr == NULL) {
 732                 *(u8  *)data = 0;
 733                 return -1;
 734         }
 735         addr = mem_ptr;
 736         addr += start & (PAGE_SIZE - 1);
 737         write_lock_irqsave(&ha->hw_lock, flags);
 738
 739         switch (size) {
 740         case 1:
 741                 *(u8  *)data = readb(addr);
 742                 break;
 743         case 2:
 744                 *(u16 *)data = readw(addr);
 745                 break;
 746         case 4:
 747                 *(u32 *)data = readl(addr);
 748                 break;
 749         case 8:
 750                 *(u64 *)data = readq(addr);
 751                 break;
 752         default:
 753                 ret = -1;
 754                 break;
 755         }
 756         write_unlock_irqrestore(&ha->hw_lock, flags);
 757
 758         if (mem_ptr)
 759                 iounmap(mem_ptr);
 760         return ret;
 761 }
 762
 763 static int
 764 qla82xx_pci_mem_write_direct(struct qla_hw_data *ha,
 765         u64 off, void *data, int size)
 766 {
 767         unsigned long   flags;
 768         void  __iomem *addr = NULL;
 769         int             ret = 0;
 770         u64             start;
 771         uint8_t __iomem *mem_ptr = NULL;
 772         unsigned long   mem_base;
 773         unsigned long   mem_page;
 774         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 775
 776         write_lock_irqsave(&ha->hw_lock, flags);
 777
 778         /*
 779          * If attempting to access unknown address or straddle hw windows,
 780          * do not access.
 781          */
 782         start = qla82xx_pci_set_window(ha, off);
 783         if ((start == -1UL) ||
 784                 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
 785                 write_unlock_irqrestore(&ha->hw_lock, flags);
 786                 ql_log(ql_log_fatal, vha, 0xb009,
 787                     "%s out of bound memory "
 788                     "access, offset is 0x%llx.\n",
 789                     QLA2XXX_DRIVER_NAME, off);
 790                 return -1;
 791         }
 792
 793         write_unlock_irqrestore(&ha->hw_lock, flags);
 794         mem_base = pci_resource_start(ha->pdev, 0);
 795         mem_page = start & PAGE_MASK;
 796         /* Map two pages whenever user tries to access addresses in two
 797          * consecutive pages.
 798          */
 799         if (mem_page != ((start + size - 1) & PAGE_MASK))
 800                 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
 801         else
 802                 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
 803         if (mem_ptr == NULL)
 804                 return -1;
 805
 806         addr = mem_ptr;
 807         addr += start & (PAGE_SIZE - 1);
 808         write_lock_irqsave(&ha->hw_lock, flags);
 809
 810         switch (size) {
 811         case 1:
 812                 writeb(*(u8  *)data, addr);
 813                 break;
 814         case 2:
 815                 writew(*(u16 *)data, addr);
 816                 break;
 817         case 4:
 818                 writel(*(u32 *)data, addr);
 819                 break;
 820         case 8:
 821                 writeq(*(u64 *)data, addr);
 822                 break;
 823         default:
 824                 ret = -1;
 825                 break;
 826         }
 827         write_unlock_irqrestore(&ha->hw_lock, flags);
 828         if (mem_ptr)
 829                 iounmap(mem_ptr);
 830         return ret;
 831 }
 832
 833 #define MTU_FUDGE_FACTOR 100
 834 static unsigned long
 835 qla82xx_decode_crb_addr(unsigned long addr)
 836 {
 837         int i;
 838         unsigned long base_addr, offset, pci_base;
 839
 840         if (!qla82xx_crb_table_initialized)
 841                 qla82xx_crb_addr_transform_setup();
 842
 843         pci_base = ADDR_ERROR;
 844         base_addr = addr & 0xfff00000;
 845         offset = addr & 0x000fffff;
 846
 847         for (i = 0; i < MAX_CRB_XFORM; i++) {
 848                 if (crb_addr_xform[i] == base_addr) {
 849                         pci_base = i << 20;
 850                         break;
 851                 }
 852         }
 853         if (pci_base == ADDR_ERROR)
 854                 return pci_base;
 855         return pci_base + offset;
 856 }
 857
 858 static long rom_max_timeout = 100;
 859 static long qla82xx_rom_lock_timeout = 100;
 860
 861 static int
 862 qla82xx_rom_lock(struct qla_hw_data *ha)
 863 {
 864         int done = 0, timeout = 0;
 865         uint32_t lock_owner = 0;
 866         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 867
 868         while (!done) {
 869                 /* acquire semaphore2 from PCI HW block */
 870                 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
 871                 if (done == 1)
 872                         break;
 873                 if (timeout >= qla82xx_rom_lock_timeout) {
 874                         lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
 875                         ql_dbg(ql_dbg_p3p, vha, 0xb157,
 876                             "%s: Simultaneous flash access by following ports, active port = %d: accessing port = %d",
 877                             __func__, ha->portnum, lock_owner);
 878                         return -1;
 879                 }
 880                 timeout++;
 881         }
 882         qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ha->portnum);
 883         return 0;
 884 }
 885
 886 static void
 887 qla82xx_rom_unlock(struct qla_hw_data *ha)
 888 {
 889         qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, 0xffffffff);
 890         qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
 891 }
 892
 893 static int
 894 qla82xx_wait_rom_busy(struct qla_hw_data *ha)
 895 {
 896         long timeout = 0;
 897         long done = 0 ;
 898         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 899
 900         while (done == 0) {
 901                 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
 902                 done &= 4;
 903                 timeout++;
 904                 if (timeout >= rom_max_timeout) {
 905                         ql_dbg(ql_dbg_p3p, vha, 0xb00a,
 906                             "%s: Timeout reached waiting for rom busy.\n",
 907                             QLA2XXX_DRIVER_NAME);
 908                         return -1;
 909                 }
 910         }
 911         return 0;
 912 }
 913
 914 static int
 915 qla82xx_wait_rom_done(struct qla_hw_data *ha)
 916 {
 917         long timeout = 0;
 918         long done = 0 ;
 919         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 920
 921         while (done == 0) {
 922                 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
 923                 done &= 2;
 924                 timeout++;
 925                 if (timeout >= rom_max_timeout) {
 926                         ql_dbg(ql_dbg_p3p, vha, 0xb00b,
 927                             "%s: Timeout reached waiting for rom done.\n",
 928                             QLA2XXX_DRIVER_NAME);
 929                         return -1;
 930                 }
 931         }
 932         return 0;
 933 }
 934
 935 static int
 936 qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag)
 937 {
 938         uint32_t  off_value, rval = 0;
 939
 940         WRT_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase, off & 0xFFFF0000);
 941
 942         /* Read back value to make sure write has gone through */
 943         RD_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase);
 944         off_value  = (off & 0x0000FFFF);
 945
 946         if (flag)
 947                 WRT_REG_DWORD(off_value + CRB_INDIRECT_2M + ha->nx_pcibase,
 948                               data);
 949         else
 950                 rval = RD_REG_DWORD(off_value + CRB_INDIRECT_2M +
 951                                     ha->nx_pcibase);
 952
 953         return rval;
 954 }
 955
 956 static int
 957 qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
 958 {
 959         /* Dword reads to flash. */
 960         qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1);
 961         *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE +
 962             (addr & 0x0000FFFF), 0, 0);
 963
 964         return 0;
 965 }
 966
 967 static int
 968 qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
 969 {
 970         int ret, loops = 0;
 971         uint32_t lock_owner = 0;
 972         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 973
 974         while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
 975                 udelay(100);
 976                 schedule();
 977                 loops++;
 978         }
 979         if (loops >= 50000) {
 980                 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
 981                 ql_log(ql_log_fatal, vha, 0x00b9,
 982                     "Failed to acquire SEM2 lock, Lock Owner %u.\n",
 983                     lock_owner);
 984                 return -1;
 985         }
 986         ret = qla82xx_do_rom_fast_read(ha, addr, valp);
 987         qla82xx_rom_unlock(ha);
 988         return ret;
 989 }
 990
 991 static int
 992 qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val)
 993 {
 994         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 995
 996         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR);
 997         qla82xx_wait_rom_busy(ha);
 998         if (qla82xx_wait_rom_done(ha)) {
 999                 ql_log(ql_log_warn, vha, 0xb00c,
1000                     "Error waiting for rom done.\n");
1001                 return -1;
1002         }
1003         *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
1004         return 0;
1005 }
1006
1007 static int
1008 qla82xx_flash_wait_write_finish(struct qla_hw_data *ha)
1009 {
1010         long timeout = 0;
1011         uint32_t done = 1 ;
1012         uint32_t val;
1013         int ret = 0;
1014         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1015
1016         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
1017         while ((done != 0) && (ret == 0)) {
1018                 ret = qla82xx_read_status_reg(ha, &val);
1019                 done = val & 1;
1020                 timeout++;
1021                 udelay(10);
1022                 cond_resched();
1023                 if (timeout >= 50000) {
1024                         ql_log(ql_log_warn, vha, 0xb00d,
1025                             "Timeout reached waiting for write finish.\n");
1026                         return -1;
1027                 }
1028         }
1029         return ret;
1030 }
1031
1032 static int
1033 qla82xx_flash_set_write_enable(struct qla_hw_data *ha)
1034 {
1035         uint32_t val;
1036
1037         qla82xx_wait_rom_busy(ha);
1038         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
1039         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN);
1040         qla82xx_wait_rom_busy(ha);
1041         if (qla82xx_wait_rom_done(ha))
1042                 return -1;
1043         if (qla82xx_read_status_reg(ha, &val) != 0)
1044                 return -1;
1045         if ((val & 2) != 2)
1046                 return -1;
1047         return 0;
1048 }
1049
1050 static int
1051 qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val)
1052 {
1053         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1054
1055         if (qla82xx_flash_set_write_enable(ha))
1056                 return -1;
1057         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val);
1058         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1);
1059         if (qla82xx_wait_rom_done(ha)) {
1060                 ql_log(ql_log_warn, vha, 0xb00e,
1061                     "Error waiting for rom done.\n");
1062                 return -1;
1063         }
1064         return qla82xx_flash_wait_write_finish(ha);
1065 }
1066
1067 static int
1068 qla82xx_write_disable_flash(struct qla_hw_data *ha)
1069 {
1070         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1071
1072         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI);
1073         if (qla82xx_wait_rom_done(ha)) {
1074                 ql_log(ql_log_warn, vha, 0xb00f,
1075                     "Error waiting for rom done.\n");
1076                 return -1;
1077         }
1078         return 0;
1079 }
1080
1081 static int
1082 ql82xx_rom_lock_d(struct qla_hw_data *ha)
1083 {
1084         int loops = 0;
1085         uint32_t lock_owner = 0;
1086         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1087
1088         while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
1089                 udelay(100);
1090                 cond_resched();
1091                 loops++;
1092         }
1093         if (loops >= 50000) {
1094                 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
1095                 ql_log(ql_log_warn, vha, 0xb010,
1096                     "ROM lock failed, Lock Owner %u.\n", lock_owner);
1097                 return -1;
1098         }
1099         return 0;
1100 }
1101
1102 static int
1103 qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr,
1104         uint32_t data)
1105 {
1106         int ret = 0;
1107         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1108
1109         ret = ql82xx_rom_lock_d(ha);
1110         if (ret < 0) {
1111                 ql_log(ql_log_warn, vha, 0xb011,
1112                     "ROM lock failed.\n");
1113                 return ret;
1114         }
1115
1116         if (qla82xx_flash_set_write_enable(ha))
1117                 goto done_write;
1118
1119         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data);
1120         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr);
1121         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
1122         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP);
1123         qla82xx_wait_rom_busy(ha);
1124         if (qla82xx_wait_rom_done(ha)) {
1125                 ql_log(ql_log_warn, vha, 0xb012,
1126                     "Error waiting for rom done.\n");
1127                 ret = -1;
1128                 goto done_write;
1129         }
1130
1131         ret = qla82xx_flash_wait_write_finish(ha);
1132
1133 done_write:
1134         qla82xx_rom_unlock(ha);
1135         return ret;
1136 }
1137
1138 /* This routine does CRB initialize sequence
1139  *  to put the ISP into operational state
1140  */
1141 static int
1142 qla82xx_pinit_from_rom(scsi_qla_host_t *vha)
1143 {
1144         int addr, val;
1145         int i ;
1146         struct crb_addr_pair *buf;
1147         unsigned long off;
1148         unsigned offset, n;
1149         struct qla_hw_data *ha = vha->hw;
1150
1151         struct crb_addr_pair {
1152                 long addr;
1153                 long data;
1154         };
1155
1156         /* Halt all the individual PEGs and other blocks of the ISP */
1157         qla82xx_rom_lock(ha);
1158
1159         /* disable all I2Q */
1160         qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
1161         qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
1162         qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
1163         qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
1164         qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
1165         qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
1166
1167         /* disable all niu interrupts */
1168         qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
1169         /* disable xge rx/tx */
1170         qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
1171         /* disable xg1 rx/tx */
1172         qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
1173         /* disable sideband mac */
1174         qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
1175         /* disable ap0 mac */
1176         qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
1177         /* disable ap1 mac */
1178         qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
1179
1180         /* halt sre */
1181         val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1182         qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
1183
1184         /* halt epg */
1185         qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
1186
1187         /* halt timers */
1188         qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1189         qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1190         qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1191         qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1192         qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
1193         qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
1194
1195         /* halt pegs */
1196         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1197         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1198         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1199         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1200         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
1201         msleep(20);
1202
1203         /* big hammer */
1204         if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
1205                 /* don't reset CAM block on reset */
1206                 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1207         else
1208                 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
1209         qla82xx_rom_unlock(ha);
1210
1211         /* Read the signature value from the flash.
1212          * Offset 0: Contain signature (0xcafecafe)
1213          * Offset 4: Offset and number of addr/value pairs
1214          * that present in CRB initialize sequence
1215          */
1216         if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1217             qla82xx_rom_fast_read(ha, 4, &n) != 0) {
1218                 ql_log(ql_log_fatal, vha, 0x006e,
1219                     "Error Reading crb_init area: n: %08x.\n", n);
1220                 return -1;
1221         }
1222
1223         /* Offset in flash = lower 16 bits
1224          * Number of entries = upper 16 bits
1225          */
1226         offset = n & 0xffffU;
1227         n = (n >> 16) & 0xffffU;
1228
1229         /* number of addr/value pair should not exceed 1024 entries */
1230         if (n  >= 1024) {
1231                 ql_log(ql_log_fatal, vha, 0x0071,
1232                     "Card flash not initialized:n=0x%x.\n", n);
1233                 return -1;
1234         }
1235
1236         ql_log(ql_log_info, vha, 0x0072,
1237             "%d CRB init values found in ROM.\n", n);
1238
1239         buf = kmalloc_array(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
1240         if (buf == NULL) {
1241                 ql_log(ql_log_fatal, vha, 0x010c,
1242                     "Unable to allocate memory.\n");
1243                 return -ENOMEM;
1244         }
1245
1246         for (i = 0; i < n; i++) {
1247                 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1248                     qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) {
1249                         kfree(buf);
1250                         return -1;
1251                 }
1252
1253                 buf[i].addr = addr;
1254                 buf[i].data = val;
1255         }
1256
1257         for (i = 0; i < n; i++) {
1258                 /* Translate internal CRB initialization
1259                  * address to PCI bus address
1260                  */
1261                 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) +
1262                     QLA82XX_PCI_CRBSPACE;
1263                 /* Not all CRB  addr/value pair to be written,
1264                  * some of them are skipped
1265                  */
1266
1267                 /* skipping cold reboot MAGIC */
1268                 if (off == QLA82XX_CAM_RAM(0x1fc))
1269                         continue;
1270
1271                 /* do not reset PCI */
1272                 if (off == (ROMUSB_GLB + 0xbc))
1273                         continue;
1274
1275                 /* skip core clock, so that firmware can increase the clock */
1276                 if (off == (ROMUSB_GLB + 0xc8))
1277                         continue;
1278
1279                 /* skip the function enable register */
1280                 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1281                         continue;
1282
1283                 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1284                         continue;
1285
1286                 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1287                         continue;
1288
1289                 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1290                         continue;
1291
1292                 if (off == ADDR_ERROR) {
1293                         ql_log(ql_log_fatal, vha, 0x0116,
1294                             "Unknown addr: 0x%08lx.\n", buf[i].addr);
1295                         continue;
1296                 }
1297
1298                 qla82xx_wr_32(ha, off, buf[i].data);
1299
1300                 /* ISP requires much bigger delay to settle down,
1301                  * else crb_window returns 0xffffffff
1302                  */
1303                 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1304                         msleep(1000);
1305
1306                 /* ISP requires millisec delay between
1307                  * successive CRB register updation
1308                  */
1309                 msleep(1);
1310         }
1311
1312         kfree(buf);
1313
1314         /* Resetting the data and instruction cache */
1315         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1316         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1317         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1318
1319         /* Clear all protocol processing engines */
1320         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1321         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1322         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1323         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1324         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1325         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1326         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1327         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1328         return 0;
1329 }
1330
1331 static int
1332 qla82xx_pci_mem_write_2M(struct qla_hw_data *ha,
1333                 u64 off, void *data, int size)
1334 {
1335         int i, j, ret = 0, loop, sz[2], off0;
1336         int scale, shift_amount, startword;
1337         uint32_t temp;
1338         uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1339
1340         /*
1341          * If not MN, go check for MS or invalid.
1342          */
1343         if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1344                 mem_crb = QLA82XX_CRB_QDR_NET;
1345         else {
1346                 mem_crb = QLA82XX_CRB_DDR_NET;
1347                 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1348                         return qla82xx_pci_mem_write_direct(ha,
1349                             off, data, size);
1350         }
1351
1352         off0 = off & 0x7;
1353         sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1354         sz[1] = size - sz[0];
1355
1356         off8 = off & 0xfffffff0;
1357         loop = (((off & 0xf) + size - 1) >> 4) + 1;
1358         shift_amount = 4;
1359         scale = 2;
1360         startword = (off & 0xf)/8;
1361
1362         for (i = 0; i < loop; i++) {
1363                 if (qla82xx_pci_mem_read_2M(ha, off8 +
1364                     (i << shift_amount), &word[i * scale], 8))
1365                         return -1;
1366         }
1367
1368         switch (size) {
1369         case 1:
1370                 tmpw = *((uint8_t *)data);
1371                 break;
1372         case 2:
1373                 tmpw = *((uint16_t *)data);
1374                 break;
1375         case 4:
1376                 tmpw = *((uint32_t *)data);
1377                 break;
1378         case 8:
1379         default:
1380                 tmpw = *((uint64_t *)data);
1381                 break;
1382         }
1383
1384         if (sz[0] == 8) {
1385                 word[startword] = tmpw;
1386         } else {
1387                 word[startword] &=
1388                         ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1389                 word[startword] |= tmpw << (off0 * 8);
1390         }
1391         if (sz[1] != 0) {
1392                 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1393                 word[startword+1] |= tmpw >> (sz[0] * 8);
1394         }
1395
1396         for (i = 0; i < loop; i++) {
1397                 temp = off8 + (i << shift_amount);
1398                 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1399                 temp = 0;
1400                 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1401                 temp = word[i * scale] & 0xffffffff;
1402                 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1403                 temp = (word[i * scale] >> 32) & 0xffffffff;
1404                 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1405                 temp = word[i*scale + 1] & 0xffffffff;
1406                 qla82xx_wr_32(ha, mem_crb +
1407                     MIU_TEST_AGT_WRDATA_UPPER_LO, temp);
1408                 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1409                 qla82xx_wr_32(ha, mem_crb +
1410                     MIU_TEST_AGT_WRDATA_UPPER_HI, temp);
1411
1412                 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1413                 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1414                 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1415                 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1416
1417                 for (j = 0; j < MAX_CTL_CHECK; j++) {
1418                         temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1419                         if ((temp & MIU_TA_CTL_BUSY) == 0)
1420                                 break;
1421                 }
1422
1423                 if (j >= MAX_CTL_CHECK) {
1424                         if (printk_ratelimit())
1425                                 dev_err(&ha->pdev->dev,
1426                                     "failed to write through agent.\n");
1427                         ret = -1;
1428                         break;
1429                 }
1430         }
1431
1432         return ret;
1433 }
1434
1435 static int
1436 qla82xx_fw_load_from_flash(struct qla_hw_data *ha)
1437 {
1438         int  i;
1439         long size = 0;
1440         long flashaddr = ha->flt_region_bootload << 2;
1441         long memaddr = BOOTLD_START;
1442         u64 data;
1443         u32 high, low;
1444
1445         size = (IMAGE_START - BOOTLD_START) / 8;
1446
1447         for (i = 0; i < size; i++) {
1448                 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1449                     (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) {
1450                         return -1;
1451                 }
1452                 data = ((u64)high << 32) | low ;
1453                 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
1454                 flashaddr += 8;
1455                 memaddr += 8;
1456
1457                 if (i % 0x1000 == 0)
1458                         msleep(1);
1459         }
1460         udelay(100);
1461         read_lock(&ha->hw_lock);
1462         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1463         qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1464         read_unlock(&ha->hw_lock);
1465         return 0;
1466 }
1467
1468 int
1469 qla82xx_pci_mem_read_2M(struct qla_hw_data *ha,
1470                 u64 off, void *data, int size)
1471 {
1472         int i, j = 0, k, start, end, loop, sz[2], off0[2];
1473         int           shift_amount;
1474         uint32_t      temp;
1475         uint64_t      off8, val, mem_crb, word[2] = {0, 0};
1476
1477         /*
1478          * If not MN, go check for MS or invalid.
1479          */
1480
1481         if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1482                 mem_crb = QLA82XX_CRB_QDR_NET;
1483         else {
1484                 mem_crb = QLA82XX_CRB_DDR_NET;
1485                 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1486                         return qla82xx_pci_mem_read_direct(ha,
1487                             off, data, size);
1488         }
1489
1490         off8 = off & 0xfffffff0;
1491         off0[0] = off & 0xf;
1492         sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1493         shift_amount = 4;
1494         loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1495         off0[1] = 0;
1496         sz[1] = size - sz[0];
1497
1498         for (i = 0; i < loop; i++) {
1499                 temp = off8 + (i << shift_amount);
1500                 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1501                 temp = 0;
1502                 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1503                 temp = MIU_TA_CTL_ENABLE;
1504                 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1505                 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1506                 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1507
1508                 for (j = 0; j < MAX_CTL_CHECK; j++) {
1509                         temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1510                         if ((temp & MIU_TA_CTL_BUSY) == 0)
1511                                 break;
1512                 }
1513
1514                 if (j >= MAX_CTL_CHECK) {
1515                         if (printk_ratelimit())
1516                                 dev_err(&ha->pdev->dev,
1517                                     "failed to read through agent.\n");
1518                         break;
1519                 }
1520
1521                 start = off0[i] >> 2;
1522                 end   = (off0[i] + sz[i] - 1) >> 2;
1523                 for (k = start; k <= end; k++) {
1524                         temp = qla82xx_rd_32(ha,
1525                                         mem_crb + MIU_TEST_AGT_RDDATA(k));
1526                         word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1527                 }
1528         }
1529
1530         if (j >= MAX_CTL_CHECK)
1531                 return -1;
1532
1533         if ((off0[0] & 7) == 0) {
1534                 val = word[0];
1535         } else {
1536                 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1537                         ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1538         }
1539
1540         switch (size) {
1541         case 1:
1542                 *(uint8_t  *)data = val;
1543                 break;
1544         case 2:
1545                 *(uint16_t *)data = val;
1546                 break;
1547         case 4:
1548                 *(uint32_t *)data = val;
1549                 break;
1550         case 8:
1551                 *(uint64_t *)data = val;
1552                 break;
1553         }
1554         return 0;
1555 }
1556
1557
1558 static struct qla82xx_uri_table_desc *
1559 qla82xx_get_table_desc(const u8 *unirom, int section)
1560 {
1561         uint32_t i;
1562         struct qla82xx_uri_table_desc *directory =
1563                 (struct qla82xx_uri_table_desc *)&unirom[0];
1564         __le32 offset;
1565         __le32 tab_type;
1566         __le32 entries = cpu_to_le32(directory->num_entries);
1567
1568         for (i = 0; i < entries; i++) {
1569                 offset = cpu_to_le32(directory->findex) +
1570                     (i * cpu_to_le32(directory->entry_size));
1571                 tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8));
1572
1573                 if (tab_type == section)
1574                         return (struct qla82xx_uri_table_desc *)&unirom[offset];
1575         }
1576
1577         return NULL;
1578 }
1579
1580 static struct qla82xx_uri_data_desc *
1581 qla82xx_get_data_desc(struct qla_hw_data *ha,
1582         u32 section, u32 idx_offset)
1583 {
1584         const u8 *unirom = ha->hablob->fw->data;
1585         int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset));
1586         struct qla82xx_uri_table_desc *tab_desc = NULL;
1587         __le32 offset;
1588
1589         tab_desc = qla82xx_get_table_desc(unirom, section);
1590         if (!tab_desc)
1591                 return NULL;
1592
1593         offset = cpu_to_le32(tab_desc->findex) +
1594             (cpu_to_le32(tab_desc->entry_size) * idx);
1595
1596         return (struct qla82xx_uri_data_desc *)&unirom[offset];
1597 }
1598
1599 static u8 *
1600 qla82xx_get_bootld_offset(struct qla_hw_data *ha)
1601 {
1602         u32 offset = BOOTLD_START;
1603         struct qla82xx_uri_data_desc *uri_desc = NULL;
1604
1605         if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1606                 uri_desc = qla82xx_get_data_desc(ha,
1607                     QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF);
1608                 if (uri_desc)
1609                         offset = cpu_to_le32(uri_desc->findex);
1610         }
1611
1612         return (u8 *)&ha->hablob->fw->data[offset];
1613 }
1614
1615 static __le32
1616 qla82xx_get_fw_size(struct qla_hw_data *ha)
1617 {
1618         struct qla82xx_uri_data_desc *uri_desc = NULL;
1619
1620         if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1621                 uri_desc =  qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1622                     QLA82XX_URI_FIRMWARE_IDX_OFF);
1623                 if (uri_desc)
1624                         return cpu_to_le32(uri_desc->size);
1625         }
1626
1627         return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]);
1628 }
1629
1630 static u8 *
1631 qla82xx_get_fw_offs(struct qla_hw_data *ha)
1632 {
1633         u32 offset = IMAGE_START;
1634         struct qla82xx_uri_data_desc *uri_desc = NULL;
1635
1636         if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1637                 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1638                         QLA82XX_URI_FIRMWARE_IDX_OFF);
1639                 if (uri_desc)
1640                         offset = cpu_to_le32(uri_desc->findex);
1641         }
1642
1643         return (u8 *)&ha->hablob->fw->data[offset];
1644 }
1645
1646 /* PCI related functions */
1647 int qla82xx_pci_region_offset(struct pci_dev *pdev, int region)
1648 {
1649         unsigned long val = 0;
1650         u32 control;
1651
1652         switch (region) {
1653         case 0:
1654                 val = 0;
1655                 break;
1656         case 1:
1657                 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control);
1658                 val = control + QLA82XX_MSIX_TBL_SPACE;
1659                 break;
1660         }
1661         return val;
1662 }
1663
1664
1665 int
1666 qla82xx_iospace_config(struct qla_hw_data *ha)
1667 {
1668         uint32_t len = 0;
1669
1670         if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) {
1671                 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c,
1672                     "Failed to reserver selected regions.\n");
1673                 goto iospace_error_exit;
1674         }
1675
1676         /* Use MMIO operations for all accesses. */
1677         if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1678                 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d,
1679                     "Region #0 not an MMIO resource, aborting.\n");
1680                 goto iospace_error_exit;
1681         }
1682
1683         len = pci_resource_len(ha->pdev, 0);
1684         ha->nx_pcibase = ioremap(pci_resource_start(ha->pdev, 0), len);
1685         if (!ha->nx_pcibase) {
1686                 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e,
1687                     "Cannot remap pcibase MMIO, aborting.\n");
1688                 goto iospace_error_exit;
1689         }
1690
1691         /* Mapping of IO base pointer */
1692         if (IS_QLA8044(ha)) {
1693                 ha->iobase = ha->nx_pcibase;
1694         } else if (IS_QLA82XX(ha)) {
1695                 ha->iobase = ha->nx_pcibase + 0xbc000 + (ha->pdev->devfn << 11);
1696         }
1697
1698         if (!ql2xdbwr) {
1699                 ha->nxdb_wr_ptr = ioremap((pci_resource_start(ha->pdev, 4) +
1700                     (ha->pdev->devfn << 12)), 4);
1701                 if (!ha->nxdb_wr_ptr) {
1702                         ql_log_pci(ql_log_fatal, ha->pdev, 0x000f,
1703                             "Cannot remap MMIO, aborting.\n");
1704                         goto iospace_error_exit;
1705                 }
1706
1707                 /* Mapping of IO base pointer,
1708                  * door bell read and write pointer
1709                  */
1710                 ha->nxdb_rd_ptr = ha->nx_pcibase + (512 * 1024) +
1711                     (ha->pdev->devfn * 8);
1712         } else {
1713                 ha->nxdb_wr_ptr = (void __iomem *)(ha->pdev->devfn == 6 ?
1714                         QLA82XX_CAMRAM_DB1 :
1715                         QLA82XX_CAMRAM_DB2);
1716         }
1717
1718         ha->max_req_queues = ha->max_rsp_queues = 1;
1719         ha->msix_count = ha->max_rsp_queues + 1;
1720         ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006,
1721             "nx_pci_base=%p iobase=%p "
1722             "max_req_queues=%d msix_count=%d.\n",
1723             ha->nx_pcibase, ha->iobase,
1724             ha->max_req_queues, ha->msix_count);
1725         ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010,
1726             "nx_pci_base=%p iobase=%p "
1727             "max_req_queues=%d msix_count=%d.\n",
1728             ha->nx_pcibase, ha->iobase,
1729             ha->max_req_queues, ha->msix_count);
1730         return 0;
1731
1732 iospace_error_exit:
1733         return -ENOMEM;
1734 }
1735
1736 /* GS related functions */
1737
1738 /* Initialization related functions */
1739
1740 /**
1741  * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers.
1742  * @vha: HA context
1743  *
1744  * Returns 0 on success.
1745 */
1746 int
1747 qla82xx_pci_config(scsi_qla_host_t *vha)
1748 {
1749         struct qla_hw_data *ha = vha->hw;
1750         int ret;
1751
1752         pci_set_master(ha->pdev);
1753         ret = pci_set_mwi(ha->pdev);
1754         ha->chip_revision = ha->pdev->revision;
1755         ql_dbg(ql_dbg_init, vha, 0x0043,
1756             "Chip revision:%d; pci_set_mwi() returned %d.\n",
1757             ha->chip_revision, ret);
1758         return 0;
1759 }
1760
1761 /**
1762  * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers.
1763  * @vha: HA context
1764  *
1765  * Returns 0 on success.
1766  */
1767 int
1768 qla82xx_reset_chip(scsi_qla_host_t *vha)
1769 {
1770         struct qla_hw_data *ha = vha->hw;
1771
1772         ha->isp_ops->disable_intrs(ha);
1773
1774         return QLA_SUCCESS;
1775 }
1776
1777 void qla82xx_config_rings(struct scsi_qla_host *vha)
1778 {
1779         struct qla_hw_data *ha = vha->hw;
1780         struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1781         struct init_cb_81xx *icb;
1782         struct req_que *req = ha->req_q_map[0];
1783         struct rsp_que *rsp = ha->rsp_q_map[0];
1784
1785         /* Setup ring parameters in initialization control block. */
1786         icb = (struct init_cb_81xx *)ha->init_cb;
1787         icb->request_q_outpointer = cpu_to_le16(0);
1788         icb->response_q_inpointer = cpu_to_le16(0);
1789         icb->request_q_length = cpu_to_le16(req->length);
1790         icb->response_q_length = cpu_to_le16(rsp->length);
1791         put_unaligned_le64(req->dma, &icb->request_q_address);
1792         put_unaligned_le64(rsp->dma, &icb->response_q_address);
1793
1794         WRT_REG_DWORD(&reg->req_q_out[0], 0);
1795         WRT_REG_DWORD(&reg->rsp_q_in[0], 0);
1796         WRT_REG_DWORD(&reg->rsp_q_out[0], 0);
1797 }
1798
1799 static int
1800 qla82xx_fw_load_from_blob(struct qla_hw_data *ha)
1801 {
1802         u64 *ptr64;
1803         u32 i, flashaddr, size;
1804         __le64 data;
1805
1806         size = (IMAGE_START - BOOTLD_START) / 8;
1807
1808         ptr64 = (u64 *)qla82xx_get_bootld_offset(ha);
1809         flashaddr = BOOTLD_START;
1810
1811         for (i = 0; i < size; i++) {
1812                 data = cpu_to_le64(ptr64[i]);
1813                 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1814                         return -EIO;
1815                 flashaddr += 8;
1816         }
1817
1818         flashaddr = FLASH_ADDR_START;
1819         size = (__force u32)qla82xx_get_fw_size(ha) / 8;
1820         ptr64 = (u64 *)qla82xx_get_fw_offs(ha);
1821
1822         for (i = 0; i < size; i++) {
1823                 data = cpu_to_le64(ptr64[i]);
1824
1825                 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1826                         return -EIO;
1827                 flashaddr += 8;
1828         }
1829         udelay(100);
1830
1831         /* Write a magic value to CAMRAM register
1832          * at a specified offset to indicate
1833          * that all data is written and
1834          * ready for firmware to initialize.
1835          */
1836         qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC);
1837
1838         read_lock(&ha->hw_lock);
1839         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1840         qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1841         read_unlock(&ha->hw_lock);
1842         return 0;
1843 }
1844
1845 static int
1846 qla82xx_set_product_offset(struct qla_hw_data *ha)
1847 {
1848         struct qla82xx_uri_table_desc *ptab_desc = NULL;
1849         const uint8_t *unirom = ha->hablob->fw->data;
1850         uint32_t i;
1851         __le32 entries;
1852         __le32 flags, file_chiprev, offset;
1853         uint8_t chiprev = ha->chip_revision;
1854         /* Hardcoding mn_present flag for P3P */
1855         int mn_present = 0;
1856         uint32_t flagbit;
1857
1858         ptab_desc = qla82xx_get_table_desc(unirom,
1859                  QLA82XX_URI_DIR_SECT_PRODUCT_TBL);
1860         if (!ptab_desc)
1861                 return -1;
1862
1863         entries = cpu_to_le32(ptab_desc->num_entries);
1864
1865         for (i = 0; i < entries; i++) {
1866                 offset = cpu_to_le32(ptab_desc->findex) +
1867                         (i * cpu_to_le32(ptab_desc->entry_size));
1868                 flags = cpu_to_le32(*((int *)&unirom[offset] +
1869                         QLA82XX_URI_FLAGS_OFF));
1870                 file_chiprev = cpu_to_le32(*((int *)&unirom[offset] +
1871                         QLA82XX_URI_CHIP_REV_OFF));
1872
1873                 flagbit = mn_present ? 1 : 2;
1874
1875                 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) {
1876                         ha->file_prd_off = offset;
1877                         return 0;
1878                 }
1879         }
1880         return -1;
1881 }
1882
1883 static int
1884 qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type)
1885 {
1886         __le32 val;
1887         uint32_t min_size;
1888         struct qla_hw_data *ha = vha->hw;
1889         const struct firmware *fw = ha->hablob->fw;
1890
1891         ha->fw_type = fw_type;
1892
1893         if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1894                 if (qla82xx_set_product_offset(ha))
1895                         return -EINVAL;
1896
1897                 min_size = QLA82XX_URI_FW_MIN_SIZE;
1898         } else {
1899                 val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]);
1900                 if ((__force u32)val != QLA82XX_BDINFO_MAGIC)
1901                         return -EINVAL;
1902
1903                 min_size = QLA82XX_FW_MIN_SIZE;
1904         }
1905
1906         if (fw->size < min_size)
1907                 return -EINVAL;
1908         return 0;
1909 }
1910
1911 static int
1912 qla82xx_check_cmdpeg_state(struct qla_hw_data *ha)
1913 {
1914         u32 val = 0;
1915         int retries = 60;
1916         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1917
1918         do {
1919                 read_lock(&ha->hw_lock);
1920                 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE);
1921                 read_unlock(&ha->hw_lock);
1922
1923                 switch (val) {
1924                 case PHAN_INITIALIZE_COMPLETE:
1925                 case PHAN_INITIALIZE_ACK:
1926                         return QLA_SUCCESS;
1927                 case PHAN_INITIALIZE_FAILED:
1928                         break;
1929                 default:
1930                         break;
1931                 }
1932                 ql_log(ql_log_info, vha, 0x00a8,
1933                     "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n",
1934                     val, retries);
1935
1936                 msleep(500);
1937
1938         } while (--retries);
1939
1940         ql_log(ql_log_fatal, vha, 0x00a9,
1941             "Cmd Peg initialization failed: 0x%x.\n", val);
1942
1943         val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1944         read_lock(&ha->hw_lock);
1945         qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
1946         read_unlock(&ha->hw_lock);
1947         return QLA_FUNCTION_FAILED;
1948 }
1949
1950 static int
1951 qla82xx_check_rcvpeg_state(struct qla_hw_data *ha)
1952 {
1953         u32 val = 0;
1954         int retries = 60;
1955         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1956
1957         do {
1958                 read_lock(&ha->hw_lock);
1959                 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE);
1960                 read_unlock(&ha->hw_lock);
1961
1962                 switch (val) {
1963                 case PHAN_INITIALIZE_COMPLETE:
1964                 case PHAN_INITIALIZE_ACK:
1965                         return QLA_SUCCESS;
1966                 case PHAN_INITIALIZE_FAILED:
1967                         break;
1968                 default:
1969                         break;
1970                 }
1971                 ql_log(ql_log_info, vha, 0x00ab,
1972                     "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n",
1973                     val, retries);
1974
1975                 msleep(500);
1976
1977         } while (--retries);
1978
1979         ql_log(ql_log_fatal, vha, 0x00ac,
1980             "Rcv Peg initialization failed: 0x%x.\n", val);
1981         read_lock(&ha->hw_lock);
1982         qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED);
1983         read_unlock(&ha->hw_lock);
1984         return QLA_FUNCTION_FAILED;
1985 }
1986
1987 /* ISR related functions */
1988 static struct qla82xx_legacy_intr_set legacy_intr[] =
1989         QLA82XX_LEGACY_INTR_CONFIG;
1990
1991 /*
1992  * qla82xx_mbx_completion() - Process mailbox command completions.
1993  * @ha: SCSI driver HA context
1994  * @mb0: Mailbox0 register
1995  */
1996 void
1997 qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
1998 {
1999         uint16_t        cnt;
2000         uint16_t __iomem *wptr;
2001         struct qla_hw_data *ha = vha->hw;
2002         struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
2003
2004         wptr = (uint16_t __iomem *)&reg->mailbox_out[1];
2005
2006         /* Load return mailbox registers. */
2007         ha->flags.mbox_int = 1;
2008         ha->mailbox_out[0] = mb0;
2009
2010         for (cnt = 1; cnt < ha->mbx_count; cnt++) {
2011                 ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
2012                 wptr++;
2013         }
2014
2015         if (!ha->mcp)
2016                 ql_dbg(ql_dbg_async, vha, 0x5053,
2017                     "MBX pointer ERROR.\n");
2018 }
2019
2020 /**
2021  * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
2022  * @irq: interrupt number
2023  * @dev_id: SCSI driver HA context
2024  *
2025  * Called by system whenever the host adapter generates an interrupt.
2026  *
2027  * Returns handled flag.
2028  */
2029 irqreturn_t
2030 qla82xx_intr_handler(int irq, void *dev_id)
2031 {
2032         scsi_qla_host_t *vha;
2033         struct qla_hw_data *ha;
2034         struct rsp_que *rsp;
2035         struct device_reg_82xx __iomem *reg;
2036         int status = 0, status1 = 0;
2037         unsigned long   flags;
2038         unsigned long   iter;
2039         uint32_t        stat = 0;
2040         uint16_t        mb[8];
2041
2042         rsp = (struct rsp_que *) dev_id;
2043         if (!rsp) {
2044                 ql_log(ql_log_info, NULL, 0xb053,
2045                     "%s: NULL response queue pointer.\n", __func__);
2046                 return IRQ_NONE;
2047         }
2048         ha = rsp->hw;
2049
2050         if (!ha->flags.msi_enabled) {
2051                 status = qla82xx_rd_32(ha, ISR_INT_VECTOR);
2052                 if (!(status & ha->nx_legacy_intr.int_vec_bit))
2053                         return IRQ_NONE;
2054
2055                 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG);
2056                 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1))
2057                         return IRQ_NONE;
2058         }
2059
2060         /* clear the interrupt */
2061         qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff);
2062
2063         /* read twice to ensure write is flushed */
2064         qla82xx_rd_32(ha, ISR_INT_VECTOR);
2065         qla82xx_rd_32(ha, ISR_INT_VECTOR);
2066
2067         reg = &ha->iobase->isp82;
2068
2069         spin_lock_irqsave(&ha->hardware_lock, flags);
2070         vha = pci_get_drvdata(ha->pdev);
2071         for (iter = 1; iter--; ) {
2072
2073                 if (RD_REG_DWORD(&reg->host_int)) {
2074                         stat = RD_REG_DWORD(&reg->host_status);
2075
2076                         switch (stat & 0xff) {
2077                         case 0x1:
2078                         case 0x2:
2079                         case 0x10:
2080                         case 0x11:
2081                                 qla82xx_mbx_completion(vha, MSW(stat));
2082                                 status |= MBX_INTERRUPT;
2083                                 break;
2084                         case 0x12:
2085                                 mb[0] = MSW(stat);
2086                                 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2087                                 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2088                                 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2089                                 qla2x00_async_event(vha, rsp, mb);
2090                                 break;
2091                         case 0x13:
2092                                 qla24xx_process_response_queue(vha, rsp);
2093                                 break;
2094                         default:
2095                                 ql_dbg(ql_dbg_async, vha, 0x5054,
2096                                     "Unrecognized interrupt type (%d).\n",
2097                                     stat & 0xff);
2098                                 break;
2099                         }
2100                 }
2101                 WRT_REG_DWORD(&reg->host_int, 0);
2102         }
2103
2104         qla2x00_handle_mbx_completion(ha, status);
2105         spin_unlock_irqrestore(&ha->hardware_lock, flags);
2106
2107         if (!ha->flags.msi_enabled)
2108                 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2109
2110         return IRQ_HANDLED;
2111 }
2112
2113 irqreturn_t
2114 qla82xx_msix_default(int irq, void *dev_id)
2115 {
2116         scsi_qla_host_t *vha;
2117         struct qla_hw_data *ha;
2118         struct rsp_que *rsp;
2119         struct device_reg_82xx __iomem *reg;
2120         int status = 0;
2121         unsigned long flags;
2122         uint32_t stat = 0;
2123         uint32_t host_int = 0;
2124         uint16_t mb[8];
2125
2126         rsp = (struct rsp_que *) dev_id;
2127         if (!rsp) {
2128                 printk(KERN_INFO
2129                         "%s(): NULL response queue pointer.\n", __func__);
2130                 return IRQ_NONE;
2131         }
2132         ha = rsp->hw;
2133
2134         reg = &ha->iobase->isp82;
2135
2136         spin_lock_irqsave(&ha->hardware_lock, flags);
2137         vha = pci_get_drvdata(ha->pdev);
2138         do {
2139                 host_int = RD_REG_DWORD(&reg->host_int);
2140                 if (qla2x00_check_reg32_for_disconnect(vha, host_int))
2141                         break;
2142                 if (host_int) {
2143                         stat = RD_REG_DWORD(&reg->host_status);
2144
2145                         switch (stat & 0xff) {
2146                         case 0x1:
2147                         case 0x2:
2148                         case 0x10:
2149                         case 0x11:
2150                                 qla82xx_mbx_completion(vha, MSW(stat));
2151                                 status |= MBX_INTERRUPT;
2152                                 break;
2153                         case 0x12:
2154                                 mb[0] = MSW(stat);
2155                                 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2156                                 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2157                                 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2158                                 qla2x00_async_event(vha, rsp, mb);
2159                                 break;
2160                         case 0x13:
2161                                 qla24xx_process_response_queue(vha, rsp);
2162                                 break;
2163                         default:
2164                                 ql_dbg(ql_dbg_async, vha, 0x5041,
2165                                     "Unrecognized interrupt type (%d).\n",
2166                                     stat & 0xff);
2167                                 break;
2168                         }
2169                 }
2170                 WRT_REG_DWORD(&reg->host_int, 0);
2171         } while (0);
2172
2173         qla2x00_handle_mbx_completion(ha, status);
2174         spin_unlock_irqrestore(&ha->hardware_lock, flags);
2175
2176         return IRQ_HANDLED;
2177 }
2178
2179 irqreturn_t
2180 qla82xx_msix_rsp_q(int irq, void *dev_id)
2181 {
2182         scsi_qla_host_t *vha;
2183         struct qla_hw_data *ha;
2184         struct rsp_que *rsp;
2185         struct device_reg_82xx __iomem *reg;
2186         unsigned long flags;
2187         uint32_t host_int = 0;
2188
2189         rsp = (struct rsp_que *) dev_id;
2190         if (!rsp) {
2191                 printk(KERN_INFO
2192                         "%s(): NULL response queue pointer.\n", __func__);
2193                 return IRQ_NONE;
2194         }
2195
2196         ha = rsp->hw;
2197         reg = &ha->iobase->isp82;
2198         spin_lock_irqsave(&ha->hardware_lock, flags);
2199         vha = pci_get_drvdata(ha->pdev);
2200         host_int = RD_REG_DWORD(&reg->host_int);
2201         if (qla2x00_check_reg32_for_disconnect(vha, host_int))
2202                 goto out;
2203         qla24xx_process_response_queue(vha, rsp);
2204         WRT_REG_DWORD(&reg->host_int, 0);
2205 out:
2206         spin_unlock_irqrestore(&ha->hardware_lock, flags);
2207         return IRQ_HANDLED;
2208 }
2209
2210 void
2211 qla82xx_poll(int irq, void *dev_id)
2212 {
2213         scsi_qla_host_t *vha;
2214         struct qla_hw_data *ha;
2215         struct rsp_que *rsp;
2216         struct device_reg_82xx __iomem *reg;
2217         int status = 0;
2218         uint32_t stat;
2219         uint32_t host_int = 0;
2220         uint16_t mb[8];
2221         unsigned long flags;
2222
2223         rsp = (struct rsp_que *) dev_id;
2224         if (!rsp) {
2225                 printk(KERN_INFO
2226                         "%s(): NULL response queue pointer.\n", __func__);
2227                 return;
2228         }
2229         ha = rsp->hw;
2230
2231         reg = &ha->iobase->isp82;
2232         spin_lock_irqsave(&ha->hardware_lock, flags);
2233         vha = pci_get_drvdata(ha->pdev);
2234
2235         host_int = RD_REG_DWORD(&reg->host_int);
2236         if (qla2x00_check_reg32_for_disconnect(vha, host_int))
2237                 goto out;
2238         if (host_int) {
2239                 stat = RD_REG_DWORD(&reg->host_status);
2240                 switch (stat & 0xff) {
2241                 case 0x1:
2242                 case 0x2:
2243                 case 0x10:
2244                 case 0x11:
2245                         qla82xx_mbx_completion(vha, MSW(stat));
2246                         status |= MBX_INTERRUPT;
2247                         break;
2248                 case 0x12:
2249                         mb[0] = MSW(stat);
2250                         mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2251                         mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2252                         mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2253                         qla2x00_async_event(vha, rsp, mb);
2254                         break;
2255                 case 0x13:
2256                         qla24xx_process_response_queue(vha, rsp);
2257                         break;
2258                 default:
2259                         ql_dbg(ql_dbg_p3p, vha, 0xb013,
2260                             "Unrecognized interrupt type (%d).\n",
2261                             stat * 0xff);
2262                         break;
2263                 }
2264                 WRT_REG_DWORD(&reg->host_int, 0);
2265         }
2266 out:
2267         spin_unlock_irqrestore(&ha->hardware_lock, flags);
2268 }
2269
2270 void
2271 qla82xx_enable_intrs(struct qla_hw_data *ha)
2272 {
2273         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2274
2275         qla82xx_mbx_intr_enable(vha);
2276         spin_lock_irq(&ha->hardware_lock);
2277         if (IS_QLA8044(ha))
2278                 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 0);
2279         else
2280                 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2281         spin_unlock_irq(&ha->hardware_lock);
2282         ha->interrupts_on = 1;
2283 }
2284
2285 void
2286 qla82xx_disable_intrs(struct qla_hw_data *ha)
2287 {
2288         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2289
2290         if (ha->interrupts_on)
2291                 qla82xx_mbx_intr_disable(vha);
2292
2293         spin_lock_irq(&ha->hardware_lock);
2294         if (IS_QLA8044(ha))
2295                 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 1);
2296         else
2297                 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
2298         spin_unlock_irq(&ha->hardware_lock);
2299         ha->interrupts_on = 0;
2300 }
2301
2302 void qla82xx_init_flags(struct qla_hw_data *ha)
2303 {
2304         struct qla82xx_legacy_intr_set *nx_legacy_intr;
2305
2306         /* ISP 8021 initializations */
2307         rwlock_init(&ha->hw_lock);
2308         ha->qdr_sn_window = -1;
2309         ha->ddr_mn_window = -1;
2310         ha->curr_window = 255;
2311         ha->portnum = PCI_FUNC(ha->pdev->devfn);
2312         nx_legacy_intr = &legacy_intr[ha->portnum];
2313         ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit;
2314         ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg;
2315         ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg;
2316         ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg;
2317 }
2318
2319 static inline void
2320 qla82xx_set_idc_version(scsi_qla_host_t *vha)
2321 {
2322         int idc_ver;
2323         uint32_t drv_active;
2324         struct qla_hw_data *ha = vha->hw;
2325
2326         drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2327         if (drv_active == (QLA82XX_DRV_ACTIVE << (ha->portnum * 4))) {
2328                 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
2329                     QLA82XX_IDC_VERSION);
2330                 ql_log(ql_log_info, vha, 0xb082,
2331                     "IDC version updated to %d\n", QLA82XX_IDC_VERSION);
2332         } else {
2333                 idc_ver = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_IDC_VERSION);
2334                 if (idc_ver != QLA82XX_IDC_VERSION)
2335                         ql_log(ql_log_info, vha, 0xb083,
2336                             "qla2xxx driver IDC version %d is not compatible "
2337                             "with IDC version %d of the other drivers\n",
2338                             QLA82XX_IDC_VERSION, idc_ver);
2339         }
2340 }
2341
2342 inline void
2343 qla82xx_set_drv_active(scsi_qla_host_t *vha)
2344 {
2345         uint32_t drv_active;
2346         struct qla_hw_data *ha = vha->hw;
2347
2348         drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2349
2350         /* If reset value is all FF's, initialize DRV_ACTIVE */
2351         if (drv_active == 0xffffffff) {
2352                 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE,
2353                         QLA82XX_DRV_NOT_ACTIVE);
2354                 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2355         }
2356         drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
2357         qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2358 }
2359
2360 inline void
2361 qla82xx_clear_drv_active(struct qla_hw_data *ha)
2362 {
2363         uint32_t drv_active;
2364
2365         drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2366         drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
2367         qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2368 }
2369
2370 static inline int
2371 qla82xx_need_reset(struct qla_hw_data *ha)
2372 {
2373         uint32_t drv_state;
2374         int rval;
2375
2376         if (ha->flags.nic_core_reset_owner)
2377                 return 1;
2378         else {
2379                 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2380                 rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2381                 return rval;
2382         }
2383 }
2384
2385 static inline void
2386 qla82xx_set_rst_ready(struct qla_hw_data *ha)
2387 {
2388         uint32_t drv_state;
2389         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2390
2391         drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2392
2393         /* If reset value is all FF's, initialize DRV_STATE */
2394         if (drv_state == 0xffffffff) {
2395                 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY);
2396                 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2397         }
2398         drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2399         ql_dbg(ql_dbg_init, vha, 0x00bb,
2400             "drv_state = 0x%08x.\n", drv_state);
2401         qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2402 }
2403
2404 static inline void
2405 qla82xx_clear_rst_ready(struct qla_hw_data *ha)
2406 {
2407         uint32_t drv_state;
2408
2409         drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2410         drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2411         qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2412 }
2413
2414 static inline void
2415 qla82xx_set_qsnt_ready(struct qla_hw_data *ha)
2416 {
2417         uint32_t qsnt_state;
2418
2419         qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2420         qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2421         qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2422 }
2423
2424 void
2425 qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha)
2426 {
2427         struct qla_hw_data *ha = vha->hw;
2428         uint32_t qsnt_state;
2429
2430         qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2431         qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2432         qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2433 }
2434
2435 static int
2436 qla82xx_load_fw(scsi_qla_host_t *vha)
2437 {
2438         int rst;
2439         struct fw_blob *blob;
2440         struct qla_hw_data *ha = vha->hw;
2441
2442         if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) {
2443                 ql_log(ql_log_fatal, vha, 0x009f,
2444                     "Error during CRB initialization.\n");
2445                 return QLA_FUNCTION_FAILED;
2446         }
2447         udelay(500);
2448
2449         /* Bring QM and CAMRAM out of reset */
2450         rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
2451         rst &= ~((1 << 28) | (1 << 24));
2452         qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
2453
2454         /*
2455          * FW Load priority:
2456          * 1) Operational firmware residing in flash.
2457          * 2) Firmware via request-firmware interface (.bin file).
2458          */
2459         if (ql2xfwloadbin == 2)
2460                 goto try_blob_fw;
2461
2462         ql_log(ql_log_info, vha, 0x00a0,
2463             "Attempting to load firmware from flash.\n");
2464
2465         if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) {
2466                 ql_log(ql_log_info, vha, 0x00a1,
2467                     "Firmware loaded successfully from flash.\n");
2468                 return QLA_SUCCESS;
2469         } else {
2470                 ql_log(ql_log_warn, vha, 0x0108,
2471                     "Firmware load from flash failed.\n");
2472         }
2473
2474 try_blob_fw:
2475         ql_log(ql_log_info, vha, 0x00a2,
2476             "Attempting to load firmware from blob.\n");
2477
2478         /* Load firmware blob. */
2479         blob = ha->hablob = qla2x00_request_firmware(vha);
2480         if (!blob) {
2481                 ql_log(ql_log_fatal, vha, 0x00a3,
2482                     "Firmware image not present.\n");
2483                 goto fw_load_failed;
2484         }
2485
2486         /* Validating firmware blob */
2487         if (qla82xx_validate_firmware_blob(vha,
2488                 QLA82XX_FLASH_ROMIMAGE)) {
2489                 /* Fallback to URI format */
2490                 if (qla82xx_validate_firmware_blob(vha,
2491                         QLA82XX_UNIFIED_ROMIMAGE)) {
2492                         ql_log(ql_log_fatal, vha, 0x00a4,
2493                             "No valid firmware image found.\n");
2494                         return QLA_FUNCTION_FAILED;
2495                 }
2496         }
2497
2498         if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) {
2499                 ql_log(ql_log_info, vha, 0x00a5,
2500                     "Firmware loaded successfully from binary blob.\n");
2501                 return QLA_SUCCESS;
2502         }
2503
2504         ql_log(ql_log_fatal, vha, 0x00a6,
2505                "Firmware load failed for binary blob.\n");
2506         blob->fw = NULL;
2507         blob = NULL;
2508
2509 fw_load_failed:
2510         return QLA_FUNCTION_FAILED;
2511 }
2512
2513 int
2514 qla82xx_start_firmware(scsi_qla_host_t *vha)
2515 {
2516         uint16_t      lnk;
2517         struct qla_hw_data *ha = vha->hw;
2518
2519         /* scrub dma mask expansion register */
2520         qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE);
2521
2522         /* Put both the PEG CMD and RCV PEG to default state
2523          * of 0 before resetting the hardware
2524          */
2525         qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
2526         qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
2527
2528         /* Overwrite stale initialization register values */
2529         qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
2530         qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
2531
2532         if (qla82xx_load_fw(vha) != QLA_SUCCESS) {
2533                 ql_log(ql_log_fatal, vha, 0x00a7,
2534                     "Error trying to start fw.\n");
2535                 return QLA_FUNCTION_FAILED;
2536         }
2537
2538         /* Handshake with the card before we register the devices. */
2539         if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) {
2540                 ql_log(ql_log_fatal, vha, 0x00aa,
2541                     "Error during card handshake.\n");
2542                 return QLA_FUNCTION_FAILED;
2543         }
2544
2545         /* Negotiated Link width */
2546         pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
2547         ha->link_width = (lnk >> 4) & 0x3f;
2548
2549         /* Synchronize with Receive peg */
2550         return qla82xx_check_rcvpeg_state(ha);
2551 }
2552
2553 static uint32_t *
2554 qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
2555         uint32_t length)
2556 {
2557         uint32_t i;
2558         uint32_t val;
2559         struct qla_hw_data *ha = vha->hw;
2560
2561         /* Dword reads to flash. */
2562         for (i = 0; i < length/4; i++, faddr += 4) {
2563                 if (qla82xx_rom_fast_read(ha, faddr, &val)) {
2564                         ql_log(ql_log_warn, vha, 0x0106,
2565                             "Do ROM fast read failed.\n");
2566                         goto done_read;
2567                 }
2568                 dwptr[i] = cpu_to_le32(val);
2569         }
2570 done_read:
2571         return dwptr;
2572 }
2573
2574 static int
2575 qla82xx_unprotect_flash(struct qla_hw_data *ha)
2576 {
2577         int ret;
2578         uint32_t val;
2579         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2580
2581         ret = ql82xx_rom_lock_d(ha);
2582         if (ret < 0) {
2583                 ql_log(ql_log_warn, vha, 0xb014,
2584                     "ROM Lock failed.\n");
2585                 return ret;
2586         }
2587
2588         ret = qla82xx_read_status_reg(ha, &val);
2589         if (ret < 0)
2590                 goto done_unprotect;
2591
2592         val &= ~(BLOCK_PROTECT_BITS << 2);
2593         ret = qla82xx_write_status_reg(ha, val);
2594         if (ret < 0) {
2595                 val |= (BLOCK_PROTECT_BITS << 2);
2596                 qla82xx_write_status_reg(ha, val);
2597         }
2598
2599         if (qla82xx_write_disable_flash(ha) != 0)
2600                 ql_log(ql_log_warn, vha, 0xb015,
2601                     "Write disable failed.\n");
2602
2603 done_unprotect:
2604         qla82xx_rom_unlock(ha);
2605         return ret;
2606 }
2607
2608 static int
2609 qla82xx_protect_flash(struct qla_hw_data *ha)
2610 {
2611         int ret;
2612         uint32_t val;
2613         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2614
2615         ret = ql82xx_rom_lock_d(ha);
2616         if (ret < 0) {
2617                 ql_log(ql_log_warn, vha, 0xb016,
2618                     "ROM Lock failed.\n");
2619                 return ret;
2620         }
2621
2622         ret = qla82xx_read_status_reg(ha, &val);
2623         if (ret < 0)
2624                 goto done_protect;
2625
2626         val |= (BLOCK_PROTECT_BITS << 2);
2627         /* LOCK all sectors */
2628         ret = qla82xx_write_status_reg(ha, val);
2629         if (ret < 0)
2630                 ql_log(ql_log_warn, vha, 0xb017,
2631                     "Write status register failed.\n");
2632
2633         if (qla82xx_write_disable_flash(ha) != 0)
2634                 ql_log(ql_log_warn, vha, 0xb018,
2635                     "Write disable failed.\n");
2636 done_protect:
2637         qla82xx_rom_unlock(ha);
2638         return ret;
2639 }
2640
2641 static int
2642 qla82xx_erase_sector(struct qla_hw_data *ha, int addr)
2643 {
2644         int ret = 0;
2645         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2646
2647         ret = ql82xx_rom_lock_d(ha);
2648         if (ret < 0) {
2649                 ql_log(ql_log_warn, vha, 0xb019,
2650                     "ROM Lock failed.\n");
2651                 return ret;
2652         }
2653
2654         qla82xx_flash_set_write_enable(ha);
2655         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
2656         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
2657         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE);
2658
2659         if (qla82xx_wait_rom_done(ha)) {
2660                 ql_log(ql_log_warn, vha, 0xb01a,
2661                     "Error waiting for rom done.\n");
2662                 ret = -1;
2663                 goto done;
2664         }
2665         ret = qla82xx_flash_wait_write_finish(ha);
2666 done:
2667         qla82xx_rom_unlock(ha);
2668         return ret;
2669 }
2670
2671 /*
2672  * Address and length are byte address
2673  */
2674 void *
2675 qla82xx_read_optrom_data(struct scsi_qla_host *vha, void *buf,
2676         uint32_t offset, uint32_t length)
2677 {
2678         scsi_block_requests(vha->host);
2679         qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length);
2680         scsi_unblock_requests(vha->host);
2681         return buf;
2682 }
2683
2684 static int
2685 qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr,
2686         uint32_t faddr, uint32_t dwords)
2687 {
2688         int ret;
2689         uint32_t liter;
2690         uint32_t rest_addr;
2691         dma_addr_t optrom_dma;
2692         void *optrom = NULL;
2693         int page_mode = 0;
2694         struct qla_hw_data *ha = vha->hw;
2695
2696         ret = -1;
2697
2698         /* Prepare burst-capable write on supported ISPs. */
2699         if (page_mode && !(faddr & 0xfff) &&
2700             dwords > OPTROM_BURST_DWORDS) {
2701                 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2702                     &optrom_dma, GFP_KERNEL);
2703                 if (!optrom) {
2704                         ql_log(ql_log_warn, vha, 0xb01b,
2705                             "Unable to allocate memory "
2706                             "for optrom burst write (%x KB).\n",
2707                             OPTROM_BURST_SIZE / 1024);
2708                 }
2709         }
2710
2711         rest_addr = ha->fdt_block_size - 1;
2712
2713         ret = qla82xx_unprotect_flash(ha);
2714         if (ret) {
2715                 ql_log(ql_log_warn, vha, 0xb01c,
2716                     "Unable to unprotect flash for update.\n");
2717                 goto write_done;
2718         }
2719
2720         for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) {
2721                 /* Are we at the beginning of a sector? */
2722                 if ((faddr & rest_addr) == 0) {
2723
2724                         ret = qla82xx_erase_sector(ha, faddr);
2725                         if (ret) {
2726                                 ql_log(ql_log_warn, vha, 0xb01d,
2727                                     "Unable to erase sector: address=%x.\n",
2728                                     faddr);
2729                                 break;
2730                         }
2731                 }
2732
2733                 /* Go with burst-write. */
2734                 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
2735                         /* Copy data to DMA'ble buffer. */
2736                         memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
2737
2738                         ret = qla2x00_load_ram(vha, optrom_dma,
2739                             (ha->flash_data_off | faddr),
2740                             OPTROM_BURST_DWORDS);
2741                         if (ret != QLA_SUCCESS) {
2742                                 ql_log(ql_log_warn, vha, 0xb01e,
2743                                     "Unable to burst-write optrom segment "
2744                                     "(%x/%x/%llx).\n", ret,
2745                                     (ha->flash_data_off | faddr),
2746                                     (unsigned long long)optrom_dma);
2747                                 ql_log(ql_log_warn, vha, 0xb01f,
2748                                     "Reverting to slow-write.\n");
2749
2750                                 dma_free_coherent(&ha->pdev->dev,
2751                                     OPTROM_BURST_SIZE, optrom, optrom_dma);
2752                                 optrom = NULL;
2753                         } else {
2754                                 liter += OPTROM_BURST_DWORDS - 1;
2755                                 faddr += OPTROM_BURST_DWORDS - 1;
2756                                 dwptr += OPTROM_BURST_DWORDS - 1;
2757                                 continue;
2758                         }
2759                 }
2760
2761                 ret = qla82xx_write_flash_dword(ha, faddr,
2762                     cpu_to_le32(*dwptr));
2763                 if (ret) {
2764                         ql_dbg(ql_dbg_p3p, vha, 0xb020,
2765                             "Unable to program flash address=%x data=%x.\n",
2766                             faddr, *dwptr);
2767                         break;
2768                 }
2769         }
2770
2771         ret = qla82xx_protect_flash(ha);
2772         if (ret)
2773                 ql_log(ql_log_warn, vha, 0xb021,
2774                     "Unable to protect flash after update.\n");
2775 write_done:
2776         if (optrom)
2777                 dma_free_coherent(&ha->pdev->dev,
2778                     OPTROM_BURST_SIZE, optrom, optrom_dma);
2779         return ret;
2780 }
2781
2782 int
2783 qla82xx_write_optrom_data(struct scsi_qla_host *vha, void *buf,
2784         uint32_t offset, uint32_t length)
2785 {
2786         int rval;
2787
2788         /* Suspend HBA. */
2789         scsi_block_requests(vha->host);
2790         rval = qla82xx_write_flash_data(vha, buf, offset, length >> 2);
2791         scsi_unblock_requests(vha->host);
2792
2793         /* Convert return ISP82xx to generic */
2794         if (rval)
2795                 rval = QLA_FUNCTION_FAILED;
2796         else
2797                 rval = QLA_SUCCESS;
2798         return rval;
2799 }
2800
2801 void
2802 qla82xx_start_iocbs(scsi_qla_host_t *vha)
2803 {
2804         struct qla_hw_data *ha = vha->hw;
2805         struct req_que *req = ha->req_q_map[0];
2806         uint32_t dbval;
2807
2808         /* Adjust ring index. */
2809         req->ring_index++;
2810         if (req->ring_index == req->length) {
2811                 req->ring_index = 0;
2812                 req->ring_ptr = req->ring;
2813         } else
2814                 req->ring_ptr++;
2815
2816         dbval = 0x04 | (ha->portnum << 5);
2817
2818         dbval = dbval | (req->id << 8) | (req->ring_index << 16);
2819         if (ql2xdbwr)
2820                 qla82xx_wr_32(ha, (unsigned long)ha->nxdb_wr_ptr, dbval);
2821         else {
2822                 WRT_REG_DWORD(ha->nxdb_wr_ptr, dbval);
2823                 wmb();
2824                 while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) {
2825                         WRT_REG_DWORD(ha->nxdb_wr_ptr, dbval);
2826                         wmb();
2827                 }
2828         }
2829 }
2830
2831 static void
2832 qla82xx_rom_lock_recovery(struct qla_hw_data *ha)
2833 {
2834         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2835         uint32_t lock_owner = 0;
2836
2837         if (qla82xx_rom_lock(ha)) {
2838                 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
2839                 /* Someone else is holding the lock. */
2840                 ql_log(ql_log_info, vha, 0xb022,
2841                     "Resetting rom_lock, Lock Owner %u.\n", lock_owner);
2842         }
2843         /*
2844          * Either we got the lock, or someone
2845          * else died while holding it.
2846          * In either case, unlock.
2847          */
2848         qla82xx_rom_unlock(ha);
2849 }
2850
2851 /*
2852  * qla82xx_device_bootstrap
2853  *    Initialize device, set DEV_READY, start fw
2854  *
2855  * Note:
2856  *      IDC lock must be held upon entry
2857  *
2858  * Return:
2859  *    Success : 0
2860  *    Failed  : 1
2861  */
2862 static int
2863 qla82xx_device_bootstrap(scsi_qla_host_t *vha)
2864 {
2865         int rval = QLA_SUCCESS;
2866         int i;
2867         uint32_t old_count, count;
2868         struct qla_hw_data *ha = vha->hw;
2869         int need_reset = 0;
2870
2871         need_reset = qla82xx_need_reset(ha);
2872
2873         if (need_reset) {
2874                 /* We are trying to perform a recovery here. */
2875                 if (ha->flags.isp82xx_fw_hung)
2876                         qla82xx_rom_lock_recovery(ha);
2877         } else  {
2878                 old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2879                 for (i = 0; i < 10; i++) {
2880                         msleep(200);
2881                         count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2882                         if (count != old_count) {
2883                                 rval = QLA_SUCCESS;
2884                                 goto dev_ready;
2885                         }
2886                 }
2887                 qla82xx_rom_lock_recovery(ha);
2888         }
2889
2890         /* set to DEV_INITIALIZING */
2891         ql_log(ql_log_info, vha, 0x009e,
2892             "HW State: INITIALIZING.\n");
2893         qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
2894
2895         qla82xx_idc_unlock(ha);
2896         rval = qla82xx_start_firmware(vha);
2897         qla82xx_idc_lock(ha);
2898
2899         if (rval != QLA_SUCCESS) {
2900                 ql_log(ql_log_fatal, vha, 0x00ad,
2901                     "HW State: FAILED.\n");
2902                 qla82xx_clear_drv_active(ha);
2903                 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED);
2904                 return rval;
2905         }
2906
2907 dev_ready:
2908         ql_log(ql_log_info, vha, 0x00ae,
2909             "HW State: READY.\n");
2910         qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY);
2911
2912         return QLA_SUCCESS;
2913 }
2914
2915 /*
2916 * qla82xx_need_qsnt_handler
2917 *    Code to start quiescence sequence
2918 *
2919 * Note:
2920 *      IDC lock must be held upon entry
2921 *
2922 * Return: void
2923 */
2924
2925 static void
2926 qla82xx_need_qsnt_handler(scsi_qla_host_t *vha)
2927 {
2928         struct qla_hw_data *ha = vha->hw;
2929         uint32_t dev_state, drv_state, drv_active;
2930         unsigned long reset_timeout;
2931
2932         if (vha->flags.online) {
2933                 /*Block any further I/O and wait for pending cmnds to complete*/
2934                 qla2x00_quiesce_io(vha);
2935         }
2936
2937         /* Set the quiescence ready bit */
2938         qla82xx_set_qsnt_ready(ha);
2939
2940         /*wait for 30 secs for other functions to ack */
2941         reset_timeout = jiffies + (30 * HZ);
2942
2943         drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2944         drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2945         /* Its 2 that is written when qsnt is acked, moving one bit */
2946         drv_active = drv_active << 0x01;
2947
2948         while (drv_state != drv_active) {
2949
2950                 if (time_after_eq(jiffies, reset_timeout)) {
2951                         /* quiescence timeout, other functions didn't ack
2952                          * changing the state to DEV_READY
2953                          */
2954                         ql_log(ql_log_info, vha, 0xb023,
2955                             "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d "
2956                             "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME,
2957                             drv_active, drv_state);
2958                         qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2959                             QLA8XXX_DEV_READY);
2960                         ql_log(ql_log_info, vha, 0xb025,
2961                             "HW State: DEV_READY.\n");
2962                         qla82xx_idc_unlock(ha);
2963                         qla2x00_perform_loop_resync(vha);
2964                         qla82xx_idc_lock(ha);
2965
2966                         qla82xx_clear_qsnt_ready(vha);
2967                         return;
2968                 }
2969
2970                 qla82xx_idc_unlock(ha);
2971                 msleep(1000);
2972                 qla82xx_idc_lock(ha);
2973
2974                 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2975                 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2976                 drv_active = drv_active << 0x01;
2977         }
2978         dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2979         /* everyone acked so set the state to DEV_QUIESCENCE */
2980         if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
2981                 ql_log(ql_log_info, vha, 0xb026,
2982                     "HW State: DEV_QUIESCENT.\n");
2983                 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_QUIESCENT);
2984         }
2985 }
2986
2987 /*
2988 * qla82xx_wait_for_state_change
2989 *    Wait for device state to change from given current state
2990 *
2991 * Note:
2992 *     IDC lock must not be held upon entry
2993 *
2994 * Return:
2995 *    Changed device state.
2996 */
2997 uint32_t
2998 qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state)
2999 {
3000         struct qla_hw_data *ha = vha->hw;
3001         uint32_t dev_state;
3002
3003         do {
3004                 msleep(1000);
3005                 qla82xx_idc_lock(ha);
3006                 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3007                 qla82xx_idc_unlock(ha);
3008         } while (dev_state == curr_state);
3009
3010         return dev_state;
3011 }
3012
3013 void
3014 qla8xxx_dev_failed_handler(scsi_qla_host_t *vha)
3015 {
3016         struct qla_hw_data *ha = vha->hw;
3017
3018         /* Disable the board */
3019         ql_log(ql_log_fatal, vha, 0x00b8,
3020             "Disabling the board.\n");
3021
3022         if (IS_QLA82XX(ha)) {
3023                 qla82xx_clear_drv_active(ha);
3024                 qla82xx_idc_unlock(ha);
3025         } else if (IS_QLA8044(ha)) {
3026                 qla8044_clear_drv_active(ha);
3027                 qla8044_idc_unlock(ha);
3028         }
3029
3030         /* Set DEV_FAILED flag to disable timer */
3031         vha->device_flags |= DFLG_DEV_FAILED;
3032         qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3033         qla2x00_mark_all_devices_lost(vha, 0);
3034         vha->flags.online = 0;
3035         vha->flags.init_done = 0;
3036 }
3037
3038 /*
3039  * qla82xx_need_reset_handler
3040  *    Code to start reset sequence
3041  *
3042  * Note:
3043  *      IDC lock must be held upon entry
3044  *
3045  * Return:
3046  *    Success : 0
3047  *    Failed  : 1
3048  */
3049 static void
3050 qla82xx_need_reset_handler(scsi_qla_host_t *vha)
3051 {
3052         uint32_t dev_state, drv_state, drv_active;
3053         uint32_t active_mask = 0;
3054         unsigned long reset_timeout;
3055         struct qla_hw_data *ha = vha->hw;
3056         struct req_que *req = ha->req_q_map[0];
3057
3058         if (vha->flags.online) {
3059                 qla82xx_idc_unlock(ha);
3060                 qla2x00_abort_isp_cleanup(vha);
3061                 ha->isp_ops->get_flash_version(vha, req->ring);
3062                 ha->isp_ops->nvram_config(vha);
3063                 qla82xx_idc_lock(ha);
3064         }
3065
3066         drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3067         if (!ha->flags.nic_core_reset_owner) {
3068                 ql_dbg(ql_dbg_p3p, vha, 0xb028,
3069                     "reset_acknowledged by 0x%x\n", ha->portnum);
3070                 qla82xx_set_rst_ready(ha);
3071         } else {
3072                 active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
3073                 drv_active &= active_mask;
3074                 ql_dbg(ql_dbg_p3p, vha, 0xb029,
3075                     "active_mask: 0x%08x\n", active_mask);
3076         }
3077
3078         /* wait for 10 seconds for reset ack from all functions */
3079         reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
3080
3081         drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3082         drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3083         dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3084
3085         ql_dbg(ql_dbg_p3p, vha, 0xb02a,
3086             "drv_state: 0x%08x, drv_active: 0x%08x, "
3087             "dev_state: 0x%08x, active_mask: 0x%08x\n",
3088             drv_state, drv_active, dev_state, active_mask);
3089
3090         while (drv_state != drv_active &&
3091             dev_state != QLA8XXX_DEV_INITIALIZING) {
3092                 if (time_after_eq(jiffies, reset_timeout)) {
3093                         ql_log(ql_log_warn, vha, 0x00b5,
3094                             "Reset timeout.\n");
3095                         break;
3096                 }
3097                 qla82xx_idc_unlock(ha);
3098                 msleep(1000);
3099                 qla82xx_idc_lock(ha);
3100                 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3101                 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3102                 if (ha->flags.nic_core_reset_owner)
3103                         drv_active &= active_mask;
3104                 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3105         }
3106
3107         ql_dbg(ql_dbg_p3p, vha, 0xb02b,
3108             "drv_state: 0x%08x, drv_active: 0x%08x, "
3109             "dev_state: 0x%08x, active_mask: 0x%08x\n",
3110             drv_state, drv_active, dev_state, active_mask);
3111
3112         ql_log(ql_log_info, vha, 0x00b6,
3113             "Device state is 0x%x = %s.\n",
3114             dev_state,
3115             dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3116
3117         /* Force to DEV_COLD unless someone else is starting a reset */
3118         if (dev_state != QLA8XXX_DEV_INITIALIZING &&
3119             dev_state != QLA8XXX_DEV_COLD) {
3120                 ql_log(ql_log_info, vha, 0x00b7,
3121                     "HW State: COLD/RE-INIT.\n");
3122                 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD);
3123                 qla82xx_set_rst_ready(ha);
3124                 if (ql2xmdenable) {
3125                         if (qla82xx_md_collect(vha))
3126                                 ql_log(ql_log_warn, vha, 0xb02c,
3127                                     "Minidump not collected.\n");
3128                 } else
3129                         ql_log(ql_log_warn, vha, 0xb04f,
3130                             "Minidump disabled.\n");
3131         }
3132 }
3133
3134 int
3135 qla82xx_check_md_needed(scsi_qla_host_t *vha)
3136 {
3137         struct qla_hw_data *ha = vha->hw;
3138         uint16_t fw_major_version, fw_minor_version, fw_subminor_version;
3139         int rval = QLA_SUCCESS;
3140
3141         fw_major_version = ha->fw_major_version;
3142         fw_minor_version = ha->fw_minor_version;
3143         fw_subminor_version = ha->fw_subminor_version;
3144
3145         rval = qla2x00_get_fw_version(vha);
3146         if (rval != QLA_SUCCESS)
3147                 return rval;
3148
3149         if (ql2xmdenable) {
3150                 if (!ha->fw_dumped) {
3151                         if ((fw_major_version != ha->fw_major_version ||
3152                             fw_minor_version != ha->fw_minor_version ||
3153                             fw_subminor_version != ha->fw_subminor_version) ||
3154                             (ha->prev_minidump_failed)) {
3155                                 ql_dbg(ql_dbg_p3p, vha, 0xb02d,
3156                                     "Firmware version differs Previous version: %d:%d:%d - New version: %d:%d:%d, prev_minidump_failed: %d.\n",
3157                                     fw_major_version, fw_minor_version,
3158                                     fw_subminor_version,
3159                                     ha->fw_major_version,
3160                                     ha->fw_minor_version,
3161                                     ha->fw_subminor_version,
3162                                     ha->prev_minidump_failed);
3163                                 /* Release MiniDump resources */
3164                                 qla82xx_md_free(vha);
3165                                 /* ALlocate MiniDump resources */
3166                                 qla82xx_md_prep(vha);
3167                         }
3168                 } else
3169                         ql_log(ql_log_info, vha, 0xb02e,
3170                             "Firmware dump available to retrieve\n");
3171         }
3172         return rval;
3173 }
3174
3175
3176 static int
3177 qla82xx_check_fw_alive(scsi_qla_host_t *vha)
3178 {
3179         uint32_t fw_heartbeat_counter;
3180         int status = 0;
3181
3182         fw_heartbeat_counter = qla82xx_rd_32(vha->hw,
3183                 QLA82XX_PEG_ALIVE_COUNTER);
3184         /* all 0xff, assume AER/EEH in progress, ignore */
3185         if (fw_heartbeat_counter == 0xffffffff) {
3186                 ql_dbg(ql_dbg_timer, vha, 0x6003,
3187                     "FW heartbeat counter is 0xffffffff, "
3188                     "returning status=%d.\n", status);
3189                 return status;
3190         }
3191         if (vha->fw_heartbeat_counter == fw_heartbeat_counter) {
3192                 vha->seconds_since_last_heartbeat++;
3193                 /* FW not alive after 2 seconds */
3194                 if (vha->seconds_since_last_heartbeat == 2) {
3195                         vha->seconds_since_last_heartbeat = 0;
3196                         status = 1;
3197                 }
3198         } else
3199                 vha->seconds_since_last_heartbeat = 0;
3200         vha->fw_heartbeat_counter = fw_heartbeat_counter;
3201         if (status)
3202                 ql_dbg(ql_dbg_timer, vha, 0x6004,
3203                     "Returning status=%d.\n", status);
3204         return status;
3205 }
3206
3207 /*
3208  * qla82xx_device_state_handler
3209  *      Main state handler
3210  *
3211  * Note:
3212  *      IDC lock must be held upon entry
3213  *
3214  * Return:
3215  *    Success : 0
3216  *    Failed  : 1
3217  */
3218 int
3219 qla82xx_device_state_handler(scsi_qla_host_t *vha)
3220 {
3221         uint32_t dev_state;
3222         uint32_t old_dev_state;
3223         int rval = QLA_SUCCESS;
3224         unsigned long dev_init_timeout;
3225         struct qla_hw_data *ha = vha->hw;
3226         int loopcount = 0;
3227
3228         qla82xx_idc_lock(ha);
3229         if (!vha->flags.init_done) {
3230                 qla82xx_set_drv_active(vha);
3231                 qla82xx_set_idc_version(vha);
3232         }
3233
3234         dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3235         old_dev_state = dev_state;
3236         ql_log(ql_log_info, vha, 0x009b,
3237             "Device state is 0x%x = %s.\n",
3238             dev_state,
3239             dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3240
3241         /* wait for 30 seconds for device to go ready */
3242         dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
3243
3244         while (1) {
3245
3246                 if (time_after_eq(jiffies, dev_init_timeout)) {
3247                         ql_log(ql_log_fatal, vha, 0x009c,
3248                             "Device init failed.\n");
3249                         rval = QLA_FUNCTION_FAILED;
3250                         break;
3251                 }
3252                 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3253                 if (old_dev_state != dev_state) {
3254                         loopcount = 0;
3255                         old_dev_state = dev_state;
3256                 }
3257                 if (loopcount < 5) {
3258                         ql_log(ql_log_info, vha, 0x009d,
3259                             "Device state is 0x%x = %s.\n",
3260                             dev_state,
3261                             dev_state < MAX_STATES ? qdev_state(dev_state) :
3262                             "Unknown");
3263                 }
3264
3265                 switch (dev_state) {
3266                 case QLA8XXX_DEV_READY:
3267                         ha->flags.nic_core_reset_owner = 0;
3268                         goto rel_lock;
3269                 case QLA8XXX_DEV_COLD:
3270                         rval = qla82xx_device_bootstrap(vha);
3271                         break;
3272                 case QLA8XXX_DEV_INITIALIZING:
3273                         qla82xx_idc_unlock(ha);
3274                         msleep(1000);
3275                         qla82xx_idc_lock(ha);
3276                         break;
3277                 case QLA8XXX_DEV_NEED_RESET:
3278                         if (!ql2xdontresethba)
3279                                 qla82xx_need_reset_handler(vha);
3280                         else {
3281                                 qla82xx_idc_unlock(ha);
3282                                 msleep(1000);
3283                                 qla82xx_idc_lock(ha);
3284                         }
3285                         dev_init_timeout = jiffies +
3286                             (ha->fcoe_dev_init_timeout * HZ);
3287                         break;
3288                 case QLA8XXX_DEV_NEED_QUIESCENT:
3289                         qla82xx_need_qsnt_handler(vha);
3290                         /* Reset timeout value after quiescence handler */
3291                         dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout
3292                                                          * HZ);
3293                         break;
3294                 case QLA8XXX_DEV_QUIESCENT:
3295                         /* Owner will exit and other will wait for the state
3296                          * to get changed
3297                          */
3298                         if (ha->flags.quiesce_owner)
3299                                 goto rel_lock;
3300
3301                         qla82xx_idc_unlock(ha);
3302                         msleep(1000);
3303                         qla82xx_idc_lock(ha);
3304
3305                         /* Reset timeout value after quiescence handler */
3306                         dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout
3307                                                          * HZ);
3308                         break;
3309                 case QLA8XXX_DEV_FAILED:
3310                         qla8xxx_dev_failed_handler(vha);
3311                         rval = QLA_FUNCTION_FAILED;
3312                         goto exit;
3313                 default:
3314                         qla82xx_idc_unlock(ha);
3315                         msleep(1000);
3316                         qla82xx_idc_lock(ha);
3317                 }
3318                 loopcount++;
3319         }
3320 rel_lock:
3321         qla82xx_idc_unlock(ha);
3322 exit:
3323         return rval;
3324 }
3325
3326 static int qla82xx_check_temp(scsi_qla_host_t *vha)
3327 {
3328         uint32_t temp, temp_state, temp_val;
3329         struct qla_hw_data *ha = vha->hw;
3330
3331         temp = qla82xx_rd_32(ha, CRB_TEMP_STATE);
3332         temp_state = qla82xx_get_temp_state(temp);
3333         temp_val = qla82xx_get_temp_val(temp);
3334
3335         if (temp_state == QLA82XX_TEMP_PANIC) {
3336                 ql_log(ql_log_warn, vha, 0x600e,
3337                     "Device temperature %d degrees C exceeds "
3338                     " maximum allowed. Hardware has been shut down.\n",
3339                     temp_val);
3340                 return 1;
3341         } else if (temp_state == QLA82XX_TEMP_WARN) {
3342                 ql_log(ql_log_warn, vha, 0x600f,
3343                     "Device temperature %d degrees C exceeds "
3344                     "operating range. Immediate action needed.\n",
3345                     temp_val);
3346         }
3347         return 0;
3348 }
3349
3350 int qla82xx_read_temperature(scsi_qla_host_t *vha)
3351 {
3352         uint32_t temp;
3353
3354         temp = qla82xx_rd_32(vha->hw, CRB_TEMP_STATE);
3355         return qla82xx_get_temp_val(temp);
3356 }
3357
3358 void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha)
3359 {
3360         struct qla_hw_data *ha = vha->hw;
3361
3362         if (ha->flags.mbox_busy) {
3363                 ha->flags.mbox_int = 1;
3364                 ha->flags.mbox_busy = 0;
3365                 ql_log(ql_log_warn, vha, 0x6010,
3366                     "Doing premature completion of mbx command.\n");
3367                 if (test_and_clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags))
3368                         complete(&ha->mbx_intr_comp);
3369         }
3370 }
3371
3372 void qla82xx_watchdog(scsi_qla_host_t *vha)
3373 {
3374         uint32_t dev_state, halt_status;
3375         struct qla_hw_data *ha = vha->hw;
3376
3377         /* don't poll if reset is going on */
3378         if (!ha->flags.nic_core_reset_hdlr_active) {
3379                 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3380                 if (qla82xx_check_temp(vha)) {
3381                         set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
3382                         ha->flags.isp82xx_fw_hung = 1;
3383                         qla82xx_clear_pending_mbx(vha);
3384                 } else if (dev_state == QLA8XXX_DEV_NEED_RESET &&
3385                     !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) {
3386                         ql_log(ql_log_warn, vha, 0x6001,
3387                             "Adapter reset needed.\n");
3388                         set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
3389                 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT &&
3390                         !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) {
3391                         ql_log(ql_log_warn, vha, 0x6002,
3392                             "Quiescent needed.\n");
3393                         set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
3394                 } else if (dev_state == QLA8XXX_DEV_FAILED &&
3395                         !test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) &&
3396                         vha->flags.online == 1) {
3397                         ql_log(ql_log_warn, vha, 0xb055,
3398                             "Adapter state is failed. Offlining.\n");
3399                         set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
3400                         ha->flags.isp82xx_fw_hung = 1;
3401                         qla82xx_clear_pending_mbx(vha);
3402                 } else {
3403                         if (qla82xx_check_fw_alive(vha)) {
3404                                 ql_dbg(ql_dbg_timer, vha, 0x6011,
3405                                     "disabling pause transmit on port 0 & 1.\n");
3406                                 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
3407                                     CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1);
3408                                 halt_status = qla82xx_rd_32(ha,
3409                                     QLA82XX_PEG_HALT_STATUS1);
3410                                 ql_log(ql_log_info, vha, 0x6005,
3411                                     "dumping hw/fw registers:.\n "
3412                                     " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n "
3413                                     " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n "
3414                                     " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n "
3415                                     " PEG_NET_4_PC: 0x%x.\n", halt_status,
3416                                     qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2),
3417                                     qla82xx_rd_32(ha,
3418                                             QLA82XX_CRB_PEG_NET_0 + 0x3c),
3419                                     qla82xx_rd_32(ha,
3420                                             QLA82XX_CRB_PEG_NET_1 + 0x3c),
3421                                     qla82xx_rd_32(ha,
3422                                             QLA82XX_CRB_PEG_NET_2 + 0x3c),
3423                                     qla82xx_rd_32(ha,
3424                                             QLA82XX_CRB_PEG_NET_3 + 0x3c),
3425                                     qla82xx_rd_32(ha,
3426                                             QLA82XX_CRB_PEG_NET_4 + 0x3c));
3427                                 if (((halt_status & 0x1fffff00) >> 8) == 0x67)
3428                                         ql_log(ql_log_warn, vha, 0xb052,
3429                                             "Firmware aborted with "
3430                                             "error code 0x00006700. Device is "
3431                                             "being reset.\n");
3432                                 if (halt_status & HALT_STATUS_UNRECOVERABLE) {
3433                                         set_bit(ISP_UNRECOVERABLE,
3434                                             &vha->dpc_flags);
3435                                 } else {
3436                                         ql_log(ql_log_info, vha, 0x6006,
3437                                             "Detect abort  needed.\n");
3438                                         set_bit(ISP_ABORT_NEEDED,
3439                                             &vha->dpc_flags);
3440                                 }
3441                                 ha->flags.isp82xx_fw_hung = 1;
3442                                 ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n");
3443                                 qla82xx_clear_pending_mbx(vha);
3444                         }
3445                 }
3446         }
3447 }
3448
3449 int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
3450 {
3451         int rval = -1;
3452         struct qla_hw_data *ha = vha->hw;
3453
3454         if (IS_QLA82XX(ha))
3455                 rval = qla82xx_device_state_handler(vha);
3456         else if (IS_QLA8044(ha)) {
3457                 qla8044_idc_lock(ha);
3458                 /* Decide the reset ownership */
3459                 qla83xx_reset_ownership(vha);
3460                 qla8044_idc_unlock(ha);
3461                 rval = qla8044_device_state_handler(vha);
3462         }
3463         return rval;
3464 }
3465
3466 void
3467 qla82xx_set_reset_owner(scsi_qla_host_t *vha)
3468 {
3469         struct qla_hw_data *ha = vha->hw;
3470         uint32_t dev_state = 0;
3471
3472         if (IS_QLA82XX(ha))
3473                 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3474         else if (IS_QLA8044(ha))
3475                 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
3476
3477         if (dev_state == QLA8XXX_DEV_READY) {
3478                 ql_log(ql_log_info, vha, 0xb02f,
3479                     "HW State: NEED RESET\n");
3480                 if (IS_QLA82XX(ha)) {
3481                         qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3482                             QLA8XXX_DEV_NEED_RESET);
3483                         ha->flags.nic_core_reset_owner = 1;
3484                         ql_dbg(ql_dbg_p3p, vha, 0xb030,
3485                             "reset_owner is 0x%x\n", ha->portnum);
3486                 } else if (IS_QLA8044(ha))
3487                         qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
3488                             QLA8XXX_DEV_NEED_RESET);
3489         } else
3490                 ql_log(ql_log_info, vha, 0xb031,
3491                     "Device state is 0x%x = %s.\n",
3492                     dev_state,
3493                     dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3494 }
3495
3496 /*
3497  *  qla82xx_abort_isp
3498  *      Resets ISP and aborts all outstanding commands.
3499  *
3500  * Input:
3501  *      ha           = adapter block pointer.
3502  *
3503  * Returns:
3504  *      0 = success
3505  */
3506 int
3507 qla82xx_abort_isp(scsi_qla_host_t *vha)
3508 {
3509         int rval = -1;
3510         struct qla_hw_data *ha = vha->hw;
3511
3512         if (vha->device_flags & DFLG_DEV_FAILED) {
3513                 ql_log(ql_log_warn, vha, 0x8024,
3514                     "Device in failed state, exiting.\n");
3515                 return QLA_SUCCESS;
3516         }
3517         ha->flags.nic_core_reset_hdlr_active = 1;
3518
3519         qla82xx_idc_lock(ha);
3520         qla82xx_set_reset_owner(vha);
3521         qla82xx_idc_unlock(ha);
3522
3523         if (IS_QLA82XX(ha))
3524                 rval = qla82xx_device_state_handler(vha);
3525         else if (IS_QLA8044(ha)) {
3526                 qla8044_idc_lock(ha);
3527                 /* Decide the reset ownership */
3528                 qla83xx_reset_ownership(vha);
3529                 qla8044_idc_unlock(ha);
3530                 rval = qla8044_device_state_handler(vha);
3531         }
3532
3533         qla82xx_idc_lock(ha);
3534         qla82xx_clear_rst_ready(ha);
3535         qla82xx_idc_unlock(ha);
3536
3537         if (rval == QLA_SUCCESS) {
3538                 ha->flags.isp82xx_fw_hung = 0;
3539                 ha->flags.nic_core_reset_hdlr_active = 0;
3540                 qla82xx_restart_isp(vha);
3541         }
3542
3543         if (rval) {
3544                 vha->flags.online = 1;
3545                 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
3546                         if (ha->isp_abort_cnt == 0) {
3547                                 ql_log(ql_log_warn, vha, 0x8027,
3548                                     "ISP error recover failed - board "
3549                                     "disabled.\n");
3550                                 /*
3551                                  * The next call disables the board
3552                                  * completely.
3553                                  */
3554                                 ha->isp_ops->reset_adapter(vha);
3555                                 vha->flags.online = 0;
3556                                 clear_bit(ISP_ABORT_RETRY,
3557                                     &vha->dpc_flags);
3558                                 rval = QLA_SUCCESS;
3559                         } else { /* schedule another ISP abort */
3560                                 ha->isp_abort_cnt--;
3561                                 ql_log(ql_log_warn, vha, 0x8036,
3562                                     "ISP abort - retry remaining %d.\n",
3563                                     ha->isp_abort_cnt);
3564                                 rval = QLA_FUNCTION_FAILED;
3565                         }
3566                 } else {
3567                         ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
3568                         ql_dbg(ql_dbg_taskm, vha, 0x8029,
3569                             "ISP error recovery - retrying (%d) more times.\n",
3570                             ha->isp_abort_cnt);
3571                         set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3572                         rval = QLA_FUNCTION_FAILED;
3573                 }
3574         }
3575         return rval;
3576 }
3577
3578 /*
3579  *  qla82xx_fcoe_ctx_reset
3580  *      Perform a quick reset and aborts all outstanding commands.
3581  *      This will only perform an FCoE context reset and avoids a full blown
3582  *      chip reset.
3583  *
3584  * Input:
3585  *      ha = adapter block pointer.
3586  *      is_reset_path = flag for identifying the reset path.
3587  *
3588  * Returns:
3589  *      0 = success
3590  */
3591 int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha)
3592 {
3593         int rval = QLA_FUNCTION_FAILED;
3594
3595         if (vha->flags.online) {
3596                 /* Abort all outstanding commands, so as to be requeued later */
3597                 qla2x00_abort_isp_cleanup(vha);
3598         }
3599
3600         /* Stop currently executing firmware.
3601          * This will destroy existing FCoE context at the F/W end.
3602          */
3603         qla2x00_try_to_stop_firmware(vha);
3604
3605         /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */
3606         rval = qla82xx_restart_isp(vha);
3607
3608         return rval;
3609 }
3610
3611 /*
3612  * qla2x00_wait_for_fcoe_ctx_reset
3613  *    Wait till the FCoE context is reset.
3614  *
3615  * Note:
3616  *    Does context switching here.
3617  *    Release SPIN_LOCK (if any) before calling this routine.
3618  *
3619  * Return:
3620  *    Success (fcoe_ctx reset is done) : 0
3621  *    Failed  (fcoe_ctx reset not completed within max loop timout ) : 1
3622  */
3623 int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha)
3624 {
3625         int status = QLA_FUNCTION_FAILED;
3626         unsigned long wait_reset;
3627
3628         wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
3629         while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
3630             test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
3631             && time_before(jiffies, wait_reset)) {
3632
3633                 set_current_state(TASK_UNINTERRUPTIBLE);
3634                 schedule_timeout(HZ);
3635
3636                 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) &&
3637                     !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) {
3638                         status = QLA_SUCCESS;
3639                         break;
3640                 }
3641         }
3642         ql_dbg(ql_dbg_p3p, vha, 0xb027,
3643                "%s: status=%d.\n", __func__, status);
3644
3645         return status;
3646 }
3647
3648 void
3649 qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha)
3650 {
3651         int i, fw_state = 0;
3652         unsigned long flags;
3653         struct qla_hw_data *ha = vha->hw;
3654
3655         /* Check if 82XX firmware is alive or not
3656          * We may have arrived here from NEED_RESET
3657          * detection only
3658          */
3659         if (!ha->flags.isp82xx_fw_hung) {
3660                 for (i = 0; i < 2; i++) {
3661                         msleep(1000);
3662                         if (IS_QLA82XX(ha))
3663                                 fw_state = qla82xx_check_fw_alive(vha);
3664                         else if (IS_QLA8044(ha))
3665                                 fw_state = qla8044_check_fw_alive(vha);
3666                         if (fw_state) {
3667                                 ha->flags.isp82xx_fw_hung = 1;
3668                                 qla82xx_clear_pending_mbx(vha);
3669                                 break;
3670                         }
3671                 }
3672         }
3673         ql_dbg(ql_dbg_init, vha, 0x00b0,
3674             "Entered %s fw_hung=%d.\n",
3675             __func__, ha->flags.isp82xx_fw_hung);
3676
3677         /* Abort all commands gracefully if fw NOT hung */
3678         if (!ha->flags.isp82xx_fw_hung) {
3679                 int cnt, que;
3680                 srb_t *sp;
3681                 struct req_que *req;
3682
3683                 spin_lock_irqsave(&ha->hardware_lock, flags);
3684                 for (que = 0; que < ha->max_req_queues; que++) {
3685                         req = ha->req_q_map[que];
3686                         if (!req)
3687                                 continue;
3688                         for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
3689                                 sp = req->outstanding_cmds[cnt];
3690                                 if (sp) {
3691                                         if ((!sp->u.scmd.crc_ctx ||
3692                                             (sp->flags &
3693                                                 SRB_FCP_CMND_DMA_VALID)) &&
3694                                                 !ha->flags.isp82xx_fw_hung) {
3695                                                 spin_unlock_irqrestore(
3696                                                     &ha->hardware_lock, flags);
3697                                                 if (ha->isp_ops->abort_command(sp)) {
3698                                                         ql_log(ql_log_info, vha,
3699                                                             0x00b1,
3700                                                             "mbx abort failed.\n");
3701                                                 } else {
3702                                                         ql_log(ql_log_info, vha,
3703                                                             0x00b2,
3704                                                             "mbx abort success.\n");
3705                                                 }
3706                                                 spin_lock_irqsave(&ha->hardware_lock, flags);
3707                                         }
3708                                 }
3709                         }
3710                 }
3711                 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3712
3713                 /* Wait for pending cmds (physical and virtual) to complete */
3714                 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0,
3715                     WAIT_HOST) == QLA_SUCCESS) {
3716                         ql_dbg(ql_dbg_init, vha, 0x00b3,
3717                             "Done wait for "
3718                             "pending commands.\n");
3719                 } else {
3720                         WARN_ON_ONCE(true);
3721                 }
3722         }
3723 }
3724
3725 /* Minidump related functions */
3726 static int
3727 qla82xx_minidump_process_control(scsi_qla_host_t *vha,
3728         qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3729 {
3730         struct qla_hw_data *ha = vha->hw;
3731         struct qla82xx_md_entry_crb *crb_entry;
3732         uint32_t read_value, opcode, poll_time;
3733         uint32_t addr, index, crb_addr;
3734         unsigned long wtime;
3735         struct qla82xx_md_template_hdr *tmplt_hdr;
3736         uint32_t rval = QLA_SUCCESS;
3737         int i;
3738
3739         tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
3740         crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr;
3741         crb_addr = crb_entry->addr;
3742
3743         for (i = 0; i < crb_entry->op_count; i++) {
3744                 opcode = crb_entry->crb_ctrl.opcode;
3745                 if (opcode & QLA82XX_DBG_OPCODE_WR) {
3746                         qla82xx_md_rw_32(ha, crb_addr,
3747                             crb_entry->value_1, 1);
3748                         opcode &= ~QLA82XX_DBG_OPCODE_WR;
3749                 }
3750
3751                 if (opcode & QLA82XX_DBG_OPCODE_RW) {
3752                         read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3753                         qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3754                         opcode &= ~QLA82XX_DBG_OPCODE_RW;
3755                 }
3756
3757                 if (opcode & QLA82XX_DBG_OPCODE_AND) {
3758                         read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3759                         read_value &= crb_entry->value_2;
3760                         opcode &= ~QLA82XX_DBG_OPCODE_AND;
3761                         if (opcode & QLA82XX_DBG_OPCODE_OR) {
3762                                 read_value |= crb_entry->value_3;
3763                                 opcode &= ~QLA82XX_DBG_OPCODE_OR;
3764                         }
3765                         qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3766                 }
3767
3768                 if (opcode & QLA82XX_DBG_OPCODE_OR) {
3769                         read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3770                         read_value |= crb_entry->value_3;
3771                         qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3772                         opcode &= ~QLA82XX_DBG_OPCODE_OR;
3773                 }
3774
3775                 if (opcode & QLA82XX_DBG_OPCODE_POLL) {
3776                         poll_time = crb_entry->crb_strd.poll_timeout;
3777                         wtime = jiffies + poll_time;
3778                         read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3779
3780                         do {
3781                                 if ((read_value & crb_entry->value_2)
3782                                     == crb_entry->value_1)
3783                                         break;
3784                                 else if (time_after_eq(jiffies, wtime)) {
3785                                         /* capturing dump failed */
3786                                         rval = QLA_FUNCTION_FAILED;
3787                                         break;
3788                                 } else
3789                                         read_value = qla82xx_md_rw_32(ha,
3790                                             crb_addr, 0, 0);
3791                         } while (1);
3792                         opcode &= ~QLA82XX_DBG_OPCODE_POLL;
3793                 }
3794
3795                 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) {
3796                         if (crb_entry->crb_strd.state_index_a) {
3797                                 index = crb_entry->crb_strd.state_index_a;
3798                                 addr = tmplt_hdr->saved_state_array[index];
3799                         } else
3800                                 addr = crb_addr;
3801
3802                         read_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3803                         index = crb_entry->crb_ctrl.state_index_v;
3804                         tmplt_hdr->saved_state_array[index] = read_value;
3805                         opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE;
3806                 }
3807
3808                 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) {
3809                         if (crb_entry->crb_strd.state_index_a) {
3810                                 index = crb_entry->crb_strd.state_index_a;
3811                                 addr = tmplt_hdr->saved_state_array[index];
3812                         } else
3813                                 addr = crb_addr;
3814
3815                         if (crb_entry->crb_ctrl.state_index_v) {
3816                                 index = crb_entry->crb_ctrl.state_index_v;
3817                                 read_value =
3818                                     tmplt_hdr->saved_state_array[index];
3819                         } else
3820                                 read_value = crb_entry->value_1;
3821
3822                         qla82xx_md_rw_32(ha, addr, read_value, 1);
3823                         opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE;
3824                 }
3825
3826                 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) {
3827                         index = crb_entry->crb_ctrl.state_index_v;
3828                         read_value = tmplt_hdr->saved_state_array[index];
3829                         read_value <<= crb_entry->crb_ctrl.shl;
3830                         read_value >>= crb_entry->crb_ctrl.shr;
3831                         if (crb_entry->value_2)
3832                                 read_value &= crb_entry->value_2;
3833                         read_value |= crb_entry->value_3;
3834                         read_value += crb_entry->value_1;
3835                         tmplt_hdr->saved_state_array[index] = read_value;
3836                         opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE;
3837                 }
3838                 crb_addr += crb_entry->crb_strd.addr_stride;
3839         }
3840         return rval;
3841 }
3842
3843 static void
3844 qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha,
3845         qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3846 {
3847         struct qla_hw_data *ha = vha->hw;
3848         uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3849         struct qla82xx_md_entry_rdocm *ocm_hdr;
3850         uint32_t *data_ptr = *d_ptr;
3851
3852         ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr;
3853         r_addr = ocm_hdr->read_addr;
3854         r_stride = ocm_hdr->read_addr_stride;
3855         loop_cnt = ocm_hdr->op_count;
3856
3857         for (i = 0; i < loop_cnt; i++) {
3858                 r_value = RD_REG_DWORD(r_addr + ha->nx_pcibase);
3859                 *data_ptr++ = cpu_to_le32(r_value);
3860                 r_addr += r_stride;
3861         }
3862         *d_ptr = data_ptr;
3863 }
3864
3865 static void
3866 qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha,
3867         qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3868 {
3869         struct qla_hw_data *ha = vha->hw;
3870         uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
3871         struct qla82xx_md_entry_mux *mux_hdr;
3872         uint32_t *data_ptr = *d_ptr;
3873
3874         mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr;
3875         r_addr = mux_hdr->read_addr;
3876         s_addr = mux_hdr->select_addr;
3877         s_stride = mux_hdr->select_value_stride;
3878         s_value = mux_hdr->select_value;
3879         loop_cnt = mux_hdr->op_count;
3880
3881         for (i = 0; i < loop_cnt; i++) {
3882                 qla82xx_md_rw_32(ha, s_addr, s_value, 1);
3883                 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3884                 *data_ptr++ = cpu_to_le32(s_value);
3885                 *data_ptr++ = cpu_to_le32(r_value);
3886                 s_value += s_stride;
3887         }
3888         *d_ptr = data_ptr;
3889 }
3890
3891 static void
3892 qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha,
3893         qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3894 {
3895         struct qla_hw_data *ha = vha->hw;
3896         uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3897         struct qla82xx_md_entry_crb *crb_hdr;
3898         uint32_t *data_ptr = *d_ptr;
3899
3900         crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr;
3901         r_addr = crb_hdr->addr;
3902         r_stride = crb_hdr->crb_strd.addr_stride;
3903         loop_cnt = crb_hdr->op_count;
3904
3905         for (i = 0; i < loop_cnt; i++) {
3906                 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3907                 *data_ptr++ = cpu_to_le32(r_addr);
3908                 *data_ptr++ = cpu_to_le32(r_value);
3909                 r_addr += r_stride;
3910         }
3911         *d_ptr = data_ptr;
3912 }
3913
3914 static int
3915 qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha,
3916         qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3917 {
3918         struct qla_hw_data *ha = vha->hw;
3919         uint32_t addr, r_addr, c_addr, t_r_addr;
3920         uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3921         unsigned long p_wait, w_time, p_mask;
3922         uint32_t c_value_w, c_value_r;
3923         struct qla82xx_md_entry_cache *cache_hdr;
3924         int rval = QLA_FUNCTION_FAILED;
3925         uint32_t *data_ptr = *d_ptr;
3926
3927         cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
3928         loop_count = cache_hdr->op_count;
3929         r_addr = cache_hdr->read_addr;
3930         c_addr = cache_hdr->control_addr;
3931         c_value_w = cache_hdr->cache_ctrl.write_value;
3932
3933         t_r_addr = cache_hdr->tag_reg_addr;
3934         t_value = cache_hdr->addr_ctrl.init_tag_value;
3935         r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
3936         p_wait = cache_hdr->cache_ctrl.poll_wait;
3937         p_mask = cache_hdr->cache_ctrl.poll_mask;
3938
3939         for (i = 0; i < loop_count; i++) {
3940                 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
3941                 if (c_value_w)
3942                         qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
3943
3944                 if (p_mask) {
3945                         w_time = jiffies + p_wait;
3946                         do {
3947                                 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0);
3948                                 if ((c_value_r & p_mask) == 0)
3949                                         break;
3950                                 else if (time_after_eq(jiffies, w_time)) {
3951                                         /* capturing dump failed */
3952                                         ql_dbg(ql_dbg_p3p, vha, 0xb032,
3953                                             "c_value_r: 0x%x, poll_mask: 0x%lx, "
3954                                             "w_time: 0x%lx\n",
3955                                             c_value_r, p_mask, w_time);
3956                                         return rval;
3957                                 }
3958                         } while (1);
3959                 }
3960
3961                 addr = r_addr;
3962                 for (k = 0; k < r_cnt; k++) {
3963                         r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3964                         *data_ptr++ = cpu_to_le32(r_value);
3965                         addr += cache_hdr->read_ctrl.read_addr_stride;
3966                 }
3967                 t_value += cache_hdr->addr_ctrl.tag_value_stride;
3968         }
3969         *d_ptr = data_ptr;
3970         return QLA_SUCCESS;
3971 }
3972
3973 static void
3974 qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha,
3975         qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3976 {
3977         struct qla_hw_data *ha = vha->hw;
3978         uint32_t addr, r_addr, c_addr, t_r_addr;
3979         uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3980         uint32_t c_value_w;
3981         struct qla82xx_md_entry_cache *cache_hdr;
3982         uint32_t *data_ptr = *d_ptr;
3983
3984         cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
3985         loop_count = cache_hdr->op_count;
3986         r_addr = cache_hdr->read_addr;
3987         c_addr = cache_hdr->control_addr;
3988         c_value_w = cache_hdr->cache_ctrl.write_value;
3989
3990         t_r_addr = cache_hdr->tag_reg_addr;
3991         t_value = cache_hdr->addr_ctrl.init_tag_value;
3992         r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
3993
3994         for (i = 0; i < loop_count; i++) {
3995                 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
3996                 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
3997                 addr = r_addr;
3998                 for (k = 0; k < r_cnt; k++) {
3999                         r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
4000                         *data_ptr++ = cpu_to_le32(r_value);
4001                         addr += cache_hdr->read_ctrl.read_addr_stride;
4002                 }
4003                 t_value += cache_hdr->addr_ctrl.tag_value_stride;
4004         }
4005         *d_ptr = data_ptr;
4006 }
4007
4008 static void
4009 qla82xx_minidump_process_queue(scsi_qla_host_t *vha,
4010         qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
4011 {
4012         struct qla_hw_data *ha = vha->hw;
4013         uint32_t s_addr, r_addr;
4014         uint32_t r_stride, r_value, r_cnt, qid = 0;
4015         uint32_t i, k, loop_cnt;
4016         struct qla82xx_md_entry_queue *q_hdr;
4017         uint32_t *data_ptr = *d_ptr;
4018
4019         q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr;
4020         s_addr = q_hdr->select_addr;
4021         r_cnt = q_hdr->rd_strd.read_addr_cnt;
4022         r_stride = q_hdr->rd_strd.read_addr_stride;
4023         loop_cnt = q_hdr->op_count;
4024
4025         for (i = 0; i < loop_cnt; i++) {
4026                 qla82xx_md_rw_32(ha, s_addr, qid, 1);
4027                 r_addr = q_hdr->read_addr;
4028                 for (k = 0; k < r_cnt; k++) {
4029                         r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
4030                         *data_ptr++ = cpu_to_le32(r_value);
4031                         r_addr += r_stride;
4032                 }
4033                 qid += q_hdr->q_strd.queue_id_stride;
4034         }
4035         *d_ptr = data_ptr;
4036 }
4037
4038 static void
4039 qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha,
4040         qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
4041 {
4042         struct qla_hw_data *ha = vha->hw;
4043         uint32_t r_addr, r_value;
4044         uint32_t i, loop_cnt;
4045         struct qla82xx_md_entry_rdrom *rom_hdr;
4046         uint32_t *data_ptr = *d_ptr;
4047
4048         rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr;
4049         r_addr = rom_hdr->read_addr;
4050         loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t);
4051
4052         for (i = 0; i < loop_cnt; i++) {
4053                 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW,
4054                     (r_addr & 0xFFFF0000), 1);
4055                 r_value = qla82xx_md_rw_32(ha,
4056                     MD_DIRECT_ROM_READ_BASE +
4057                     (r_addr & 0x0000FFFF), 0, 0);
4058                 *data_ptr++ = cpu_to_le32(r_value);
4059                 r_addr += sizeof(uint32_t);
4060         }
4061         *d_ptr = data_ptr;
4062 }
4063
4064 static int
4065 qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha,
4066         qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
4067 {
4068         struct qla_hw_data *ha = vha->hw;
4069         uint32_t r_addr, r_value, r_data;
4070         uint32_t i, j, loop_cnt;
4071         struct qla82xx_md_entry_rdmem *m_hdr;
4072         unsigned long flags;
4073         int rval = QLA_FUNCTION_FAILED;
4074         uint32_t *data_ptr = *d_ptr;
4075
4076         m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr;
4077         r_addr = m_hdr->read_addr;
4078         loop_cnt = m_hdr->read_data_size/16;
4079
4080         if (r_addr & 0xf) {
4081                 ql_log(ql_log_warn, vha, 0xb033,
4082                     "Read addr 0x%x not 16 bytes aligned\n", r_addr);
4083                 return rval;
4084         }
4085
4086         if (m_hdr->read_data_size % 16) {
4087                 ql_log(ql_log_warn, vha, 0xb034,
4088                     "Read data[0x%x] not multiple of 16 bytes\n",
4089                     m_hdr->read_data_size);
4090                 return rval;
4091         }
4092
4093         ql_dbg(ql_dbg_p3p, vha, 0xb035,
4094             "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
4095             __func__, r_addr, m_hdr->read_data_size, loop_cnt);
4096
4097         write_lock_irqsave(&ha->hw_lock, flags);
4098         for (i = 0; i < loop_cnt; i++) {
4099                 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1);
4100                 r_value = 0;
4101                 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1);
4102                 r_value = MIU_TA_CTL_ENABLE;
4103                 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
4104                 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
4105                 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
4106
4107                 for (j = 0; j < MAX_CTL_CHECK; j++) {
4108                         r_value = qla82xx_md_rw_32(ha,
4109                             MD_MIU_TEST_AGT_CTRL, 0, 0);
4110                         if ((r_value & MIU_TA_CTL_BUSY) == 0)
4111                                 break;
4112                 }
4113
4114                 if (j >= MAX_CTL_CHECK) {
4115                         printk_ratelimited(KERN_ERR
4116                             "failed to read through agent\n");
4117                         write_unlock_irqrestore(&ha->hw_lock, flags);
4118                         return rval;
4119                 }
4120
4121                 for (j = 0; j < 4; j++) {
4122                         r_data = qla82xx_md_rw_32(ha,
4123                             MD_MIU_TEST_AGT_RDDATA[j], 0, 0);
4124                         *data_ptr++ = cpu_to_le32(r_data);
4125                 }
4126                 r_addr += 16;
4127         }
4128         write_unlock_irqrestore(&ha->hw_lock, flags);
4129         *d_ptr = data_ptr;
4130         return QLA_SUCCESS;
4131 }
4132
4133 int
4134 qla82xx_validate_template_chksum(scsi_qla_host_t *vha)
4135 {
4136         struct qla_hw_data *ha = vha->hw;
4137         uint64_t chksum = 0;
4138         uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr;
4139         int count = ha->md_template_size/sizeof(uint32_t);
4140
4141         while (count-- > 0)
4142                 chksum += *d_ptr++;
4143         while (chksum >> 32)
4144                 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32);
4145         return ~chksum;
4146 }
4147
4148 static void
4149 qla82xx_mark_entry_skipped(scsi_qla_host_t *vha,
4150         qla82xx_md_entry_hdr_t *entry_hdr, int index)
4151 {
4152         entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG;
4153         ql_dbg(ql_dbg_p3p, vha, 0xb036,
4154             "Skipping entry[%d]: "
4155             "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4156             index, entry_hdr->entry_type,
4157             entry_hdr->d_ctrl.entry_capture_mask);
4158 }
4159
4160 int
4161 qla82xx_md_collect(scsi_qla_host_t *vha)
4162 {
4163         struct qla_hw_data *ha = vha->hw;
4164         int no_entry_hdr = 0;
4165         qla82xx_md_entry_hdr_t *entry_hdr;
4166         struct qla82xx_md_template_hdr *tmplt_hdr;
4167         uint32_t *data_ptr;
4168         uint32_t total_data_size = 0, f_capture_mask, data_collected = 0;
4169         int i = 0, rval = QLA_FUNCTION_FAILED;
4170
4171         tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
4172         data_ptr = (uint32_t *)ha->md_dump;
4173
4174         if (ha->fw_dumped) {
4175                 ql_log(ql_log_warn, vha, 0xb037,
4176                     "Firmware has been previously dumped (%p) "
4177                     "-- ignoring request.\n", ha->fw_dump);
4178                 goto md_failed;
4179         }
4180
4181         ha->fw_dumped = 0;
4182
4183         if (!ha->md_tmplt_hdr || !ha->md_dump) {
4184                 ql_log(ql_log_warn, vha, 0xb038,
4185                     "Memory not allocated for minidump capture\n");
4186                 goto md_failed;
4187         }
4188
4189         if (ha->flags.isp82xx_no_md_cap) {
4190                 ql_log(ql_log_warn, vha, 0xb054,
4191                     "Forced reset from application, "
4192                     "ignore minidump capture\n");
4193                 ha->flags.isp82xx_no_md_cap = 0;
4194                 goto md_failed;
4195         }
4196
4197         if (qla82xx_validate_template_chksum(vha)) {
4198                 ql_log(ql_log_info, vha, 0xb039,
4199                     "Template checksum validation error\n");
4200                 goto md_failed;
4201         }
4202
4203         no_entry_hdr = tmplt_hdr->num_of_entries;
4204         ql_dbg(ql_dbg_p3p, vha, 0xb03a,
4205             "No of entry headers in Template: 0x%x\n", no_entry_hdr);
4206
4207         ql_dbg(ql_dbg_p3p, vha, 0xb03b,
4208             "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level);
4209
4210         f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF;
4211
4212         /* Validate whether required debug level is set */
4213         if ((f_capture_mask & 0x3) != 0x3) {
4214                 ql_log(ql_log_warn, vha, 0xb03c,
4215                     "Minimum required capture mask[0x%x] level not set\n",
4216                     f_capture_mask);
4217                 goto md_failed;
4218         }
4219         tmplt_hdr->driver_capture_mask = ql2xmdcapmask;
4220
4221         tmplt_hdr->driver_info[0] = vha->host_no;
4222         tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) |
4223             (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) |
4224             QLA_DRIVER_BETA_VER;
4225
4226         total_data_size = ha->md_dump_size;
4227
4228         ql_dbg(ql_dbg_p3p, vha, 0xb03d,
4229             "Total minidump data_size 0x%x to be captured\n", total_data_size);
4230
4231         /* Check whether template obtained is valid */
4232         if (tmplt_hdr->entry_type != QLA82XX_TLHDR) {
4233                 ql_log(ql_log_warn, vha, 0xb04e,
4234                     "Bad template header entry type: 0x%x obtained\n",
4235                     tmplt_hdr->entry_type);
4236                 goto md_failed;
4237         }
4238
4239         entry_hdr = (qla82xx_md_entry_hdr_t *)
4240             (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset);
4241
4242         /* Walk through the entry headers */
4243         for (i = 0; i < no_entry_hdr; i++) {
4244
4245                 if (data_collected > total_data_size) {
4246                         ql_log(ql_log_warn, vha, 0xb03e,
4247                             "More MiniDump data collected: [0x%x]\n",
4248                             data_collected);
4249                         goto md_failed;
4250                 }
4251
4252                 if (!(entry_hdr->d_ctrl.entry_capture_mask &
4253                     ql2xmdcapmask)) {
4254                         entry_hdr->d_ctrl.driver_flags |=
4255                             QLA82XX_DBG_SKIPPED_FLAG;
4256                         ql_dbg(ql_dbg_p3p, vha, 0xb03f,
4257                             "Skipping entry[%d]: "
4258                             "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4259                             i, entry_hdr->entry_type,
4260                             entry_hdr->d_ctrl.entry_capture_mask);
4261                         goto skip_nxt_entry;
4262                 }
4263
4264                 ql_dbg(ql_dbg_p3p, vha, 0xb040,
4265                     "[%s]: data ptr[%d]: %p, entry_hdr: %p\n"
4266                     "entry_type: 0x%x, capture_mask: 0x%x\n",
4267                     __func__, i, data_ptr, entry_hdr,
4268                     entry_hdr->entry_type,
4269                     entry_hdr->d_ctrl.entry_capture_mask);
4270
4271                 ql_dbg(ql_dbg_p3p, vha, 0xb041,
4272                     "Data collected: [0x%x], Dump size left:[0x%x]\n",
4273                     data_collected, (ha->md_dump_size - data_collected));
4274
4275                 /* Decode the entry type and take
4276                  * required action to capture debug data */
4277                 switch (entry_hdr->entry_type) {
4278                 case QLA82XX_RDEND:
4279                         qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4280                         break;
4281                 case QLA82XX_CNTRL:
4282                         rval = qla82xx_minidump_process_control(vha,
4283                             entry_hdr, &data_ptr);
4284                         if (rval != QLA_SUCCESS) {
4285                                 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4286                                 goto md_failed;
4287                         }
4288                         break;
4289                 case QLA82XX_RDCRB:
4290                         qla82xx_minidump_process_rdcrb(vha,
4291                             entry_hdr, &data_ptr);
4292                         break;
4293                 case QLA82XX_RDMEM:
4294                         rval = qla82xx_minidump_process_rdmem(vha,
4295                             entry_hdr, &data_ptr);
4296                         if (rval != QLA_SUCCESS) {
4297                                 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4298                                 goto md_failed;
4299                         }
4300                         break;
4301                 case QLA82XX_BOARD:
4302                 case QLA82XX_RDROM:
4303                         qla82xx_minidump_process_rdrom(vha,
4304                             entry_hdr, &data_ptr);
4305                         break;
4306                 case QLA82XX_L2DTG:
4307                 case QLA82XX_L2ITG:
4308                 case QLA82XX_L2DAT:
4309                 case QLA82XX_L2INS:
4310                         rval = qla82xx_minidump_process_l2tag(vha,
4311                             entry_hdr, &data_ptr);
4312                         if (rval != QLA_SUCCESS) {
4313                                 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4314                                 goto md_failed;
4315                         }
4316                         break;
4317                 case QLA82XX_L1DAT:
4318                 case QLA82XX_L1INS:
4319                         qla82xx_minidump_process_l1cache(vha,
4320                             entry_hdr, &data_ptr);
4321                         break;
4322                 case QLA82XX_RDOCM:
4323                         qla82xx_minidump_process_rdocm(vha,
4324                             entry_hdr, &data_ptr);
4325                         break;
4326                 case QLA82XX_RDMUX:
4327                         qla82xx_minidump_process_rdmux(vha,
4328                             entry_hdr, &data_ptr);
4329                         break;
4330                 case QLA82XX_QUEUE:
4331                         qla82xx_minidump_process_queue(vha,
4332                             entry_hdr, &data_ptr);
4333                         break;
4334                 case QLA82XX_RDNOP:
4335                 default:
4336                         qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4337                         break;
4338                 }
4339
4340                 ql_dbg(ql_dbg_p3p, vha, 0xb042,
4341                     "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr);
4342
4343                 data_collected = (uint8_t *)data_ptr -
4344                     (uint8_t *)ha->md_dump;
4345 skip_nxt_entry:
4346                 entry_hdr = (qla82xx_md_entry_hdr_t *)
4347                     (((uint8_t *)entry_hdr) + entry_hdr->entry_size);
4348         }
4349
4350         if (data_collected != total_data_size) {
4351                 ql_dbg(ql_dbg_p3p, vha, 0xb043,
4352                     "MiniDump data mismatch: Data collected: [0x%x],"
4353                     "total_data_size:[0x%x]\n",
4354                     data_collected, total_data_size);
4355                 goto md_failed;
4356         }
4357
4358         ql_log(ql_log_info, vha, 0xb044,
4359             "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n",
4360             vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump);
4361         ha->fw_dumped = 1;
4362         qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
4363
4364 md_failed:
4365         return rval;
4366 }
4367
4368 int
4369 qla82xx_md_alloc(scsi_qla_host_t *vha)
4370 {
4371         struct qla_hw_data *ha = vha->hw;
4372         int i, k;
4373         struct qla82xx_md_template_hdr *tmplt_hdr;
4374
4375         tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
4376
4377         if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) {
4378                 ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF;
4379                 ql_log(ql_log_info, vha, 0xb045,
4380                     "Forcing driver capture mask to firmware default capture mask: 0x%x.\n",
4381                     ql2xmdcapmask);
4382         }
4383
4384         for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) {
4385                 if (i & ql2xmdcapmask)
4386                         ha->md_dump_size += tmplt_hdr->capture_size_array[k];
4387         }
4388
4389         if (ha->md_dump) {
4390                 ql_log(ql_log_warn, vha, 0xb046,
4391                     "Firmware dump previously allocated.\n");
4392                 return 1;
4393         }
4394
4395         ha->md_dump = vmalloc(ha->md_dump_size);
4396         if (ha->md_dump == NULL) {
4397                 ql_log(ql_log_warn, vha, 0xb047,
4398                     "Unable to allocate memory for Minidump size "
4399                     "(0x%x).\n", ha->md_dump_size);
4400                 return 1;
4401         }
4402         return 0;
4403 }
4404
4405 void
4406 qla82xx_md_free(scsi_qla_host_t *vha)
4407 {
4408         struct qla_hw_data *ha = vha->hw;
4409
4410         /* Release the template header allocated */
4411         if (ha->md_tmplt_hdr) {
4412                 ql_log(ql_log_info, vha, 0xb048,
4413                     "Free MiniDump template: %p, size (%d KB)\n",
4414                     ha->md_tmplt_hdr, ha->md_template_size / 1024);
4415                 dma_free_coherent(&ha->pdev->dev, ha->md_template_size,
4416                     ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
4417                 ha->md_tmplt_hdr = NULL;
4418         }
4419
4420         /* Release the template data buffer allocated */
4421         if (ha->md_dump) {
4422                 ql_log(ql_log_info, vha, 0xb049,
4423                     "Free MiniDump memory: %p, size (%d KB)\n",
4424                     ha->md_dump, ha->md_dump_size / 1024);
4425                 vfree(ha->md_dump);
4426                 ha->md_dump_size = 0;
4427                 ha->md_dump = NULL;
4428         }
4429 }
4430
4431 void
4432 qla82xx_md_prep(scsi_qla_host_t *vha)
4433 {
4434         struct qla_hw_data *ha = vha->hw;
4435         int rval;
4436
4437         /* Get Minidump template size */
4438         rval = qla82xx_md_get_template_size(vha);
4439         if (rval == QLA_SUCCESS) {
4440                 ql_log(ql_log_info, vha, 0xb04a,
4441                     "MiniDump Template size obtained (%d KB)\n",
4442                     ha->md_template_size / 1024);
4443
4444                 /* Get Minidump template */
4445                 if (IS_QLA8044(ha))
4446                         rval = qla8044_md_get_template(vha);
4447                 else
4448                         rval = qla82xx_md_get_template(vha);
4449
4450                 if (rval == QLA_SUCCESS) {
4451                         ql_dbg(ql_dbg_p3p, vha, 0xb04b,
4452                             "MiniDump Template obtained\n");
4453
4454                         /* Allocate memory for minidump */
4455                         rval = qla82xx_md_alloc(vha);
4456                         if (rval == QLA_SUCCESS)
4457                                 ql_log(ql_log_info, vha, 0xb04c,
4458                                     "MiniDump memory allocated (%d KB)\n",
4459                                     ha->md_dump_size / 1024);
4460                         else {
4461                                 ql_log(ql_log_info, vha, 0xb04d,
4462                                     "Free MiniDump template: %p, size: (%d KB)\n",
4463                                     ha->md_tmplt_hdr,
4464                                     ha->md_template_size / 1024);
4465                                 dma_free_coherent(&ha->pdev->dev,
4466                                     ha->md_template_size,
4467                                     ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
4468                                 ha->md_tmplt_hdr = NULL;
4469                         }
4470
4471                 }
4472         }
4473 }
4474
4475 int
4476 qla82xx_beacon_on(struct scsi_qla_host *vha)
4477 {
4478
4479         int rval;
4480         struct qla_hw_data *ha = vha->hw;
4481
4482         qla82xx_idc_lock(ha);
4483         rval = qla82xx_mbx_beacon_ctl(vha, 1);
4484
4485         if (rval) {
4486                 ql_log(ql_log_warn, vha, 0xb050,
4487                     "mbx set led config failed in %s\n", __func__);
4488                 goto exit;
4489         }
4490         ha->beacon_blink_led = 1;
4491 exit:
4492         qla82xx_idc_unlock(ha);
4493         return rval;
4494 }
4495
4496 int
4497 qla82xx_beacon_off(struct scsi_qla_host *vha)
4498 {
4499
4500         int rval;
4501         struct qla_hw_data *ha = vha->hw;
4502
4503         qla82xx_idc_lock(ha);
4504         rval = qla82xx_mbx_beacon_ctl(vha, 0);
4505
4506         if (rval) {
4507                 ql_log(ql_log_warn, vha, 0xb051,
4508                     "mbx set led config failed in %s\n", __func__);
4509                 goto exit;
4510         }
4511         ha->beacon_blink_led = 0;
4512 exit:
4513         qla82xx_idc_unlock(ha);
4514         return rval;
4515 }
4516
4517 void
4518 qla82xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
4519 {
4520         struct qla_hw_data *ha = vha->hw;
4521
4522         if (!ha->allow_cna_fw_dump)
4523                 return;
4524
4525         scsi_block_requests(vha->host);
4526         ha->flags.isp82xx_no_md_cap = 1;
4527         qla82xx_idc_lock(ha);
4528         qla82xx_set_reset_owner(vha);
4529         qla82xx_idc_unlock(ha);
4530         qla2x00_wait_for_chip_reset(vha);
4531         scsi_unblock_requests(vha->host);
4532 }