drivers/scsi/ufs/ufs-qcom.c

   1 /*
   2  * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  */
  14
  15 #include <linux/time.h>
  16 #include <linux/of.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/phy/phy.h>
  19 #include <linux/reset-controller.h>
  20
  21 #include "ufshcd.h"
  22 #include "ufshcd-pltfrm.h"
  23 #include "unipro.h"
  24 #include "ufs-qcom.h"
  25 #include "ufshci.h"
  26 #include "ufs_quirks.h"
  27 #define UFS_QCOM_DEFAULT_DBG_PRINT_EN   \
  28         (UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
  29
  30 enum {
  31         TSTBUS_UAWM,
  32         TSTBUS_UARM,
  33         TSTBUS_TXUC,
  34         TSTBUS_RXUC,
  35         TSTBUS_DFC,
  36         TSTBUS_TRLUT,
  37         TSTBUS_TMRLUT,
  38         TSTBUS_OCSC,
  39         TSTBUS_UTP_HCI,
  40         TSTBUS_COMBINED,
  41         TSTBUS_WRAPPER,
  42         TSTBUS_UNIPRO,
  43         TSTBUS_MAX,
  44 };
  45
  46 static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS];
  47
  48 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote);
  49 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
  50 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
  51                                                        u32 clk_cycles);
  52
  53 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd)
  54 {
  55         return container_of(rcd, struct ufs_qcom_host, rcdev);
  56 }
  57
  58 static void ufs_qcom_dump_regs_wrapper(struct ufs_hba *hba, int offset, int len,
  59                                        const char *prefix, void *priv)
  60 {
  61         ufshcd_dump_regs(hba, offset, len * 4, prefix);
  62 }
  63
  64 static int ufs_qcom_get_connected_tx_lanes(struct ufs_hba *hba, u32 *tx_lanes)
  65 {
  66         int err = 0;
  67
  68         err = ufshcd_dme_get(hba,
  69                         UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), tx_lanes);
  70         if (err)
  71                 dev_err(hba->dev, "%s: couldn't read PA_CONNECTEDTXDATALANES %d\n",
  72                                 __func__, err);
  73
  74         return err;
  75 }
  76
  77 static int ufs_qcom_host_clk_get(struct device *dev,
  78                 const char *name, struct clk **clk_out, bool optional)
  79 {
  80         struct clk *clk;
  81         int err = 0;
  82
  83         clk = devm_clk_get(dev, name);
  84         if (!IS_ERR(clk)) {
  85                 *clk_out = clk;
  86                 return 0;
  87         }
  88
  89         err = PTR_ERR(clk);
  90
  91         if (optional && err == -ENOENT) {
  92                 *clk_out = NULL;
  93                 return 0;
  94         }
  95
  96         if (err != -EPROBE_DEFER)
  97                 dev_err(dev, "failed to get %s err %d\n", name, err);
  98
  99         return err;
 100 }
 101
 102 static int ufs_qcom_host_clk_enable(struct device *dev,
 103                 const char *name, struct clk *clk)
 104 {
 105         int err = 0;
 106
 107         err = clk_prepare_enable(clk);
 108         if (err)
 109                 dev_err(dev, "%s: %s enable failed %d\n", __func__, name, err);
 110
 111         return err;
 112 }
 113
 114 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
 115 {
 116         if (!host->is_lane_clks_enabled)
 117                 return;
 118
 119         clk_disable_unprepare(host->tx_l1_sync_clk);
 120         clk_disable_unprepare(host->tx_l0_sync_clk);
 121         clk_disable_unprepare(host->rx_l1_sync_clk);
 122         clk_disable_unprepare(host->rx_l0_sync_clk);
 123
 124         host->is_lane_clks_enabled = false;
 125 }
 126
 127 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
 128 {
 129         int err = 0;
 130         struct device *dev = host->hba->dev;
 131
 132         if (host->is_lane_clks_enabled)
 133                 return 0;
 134
 135         err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk",
 136                 host->rx_l0_sync_clk);
 137         if (err)
 138                 goto out;
 139
 140         err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk",
 141                 host->tx_l0_sync_clk);
 142         if (err)
 143                 goto disable_rx_l0;
 144
 145         err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk",
 146                         host->rx_l1_sync_clk);
 147         if (err)
 148                 goto disable_tx_l0;
 149
 150         err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk",
 151                         host->tx_l1_sync_clk);
 152         if (err)
 153                 goto disable_rx_l1;
 154
 155         host->is_lane_clks_enabled = true;
 156         goto out;
 157
 158 disable_rx_l1:
 159         clk_disable_unprepare(host->rx_l1_sync_clk);
 160 disable_tx_l0:
 161         clk_disable_unprepare(host->tx_l0_sync_clk);
 162 disable_rx_l0:
 163         clk_disable_unprepare(host->rx_l0_sync_clk);
 164 out:
 165         return err;
 166 }
 167
 168 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
 169 {
 170         int err = 0;
 171         struct device *dev = host->hba->dev;
 172
 173         err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk",
 174                                         &host->rx_l0_sync_clk, false);
 175         if (err)
 176                 goto out;
 177
 178         err = ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk",
 179                                         &host->tx_l0_sync_clk, false);
 180         if (err)
 181                 goto out;
 182
 183         /* In case of single lane per direction, don't read lane1 clocks */
 184         if (host->hba->lanes_per_direction > 1) {
 185                 err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk",
 186                         &host->rx_l1_sync_clk, false);
 187                 if (err)
 188                         goto out;
 189
 190                 err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk",
 191                         &host->tx_l1_sync_clk, true);
 192         }
 193 out:
 194         return err;
 195 }
 196
 197 static int ufs_qcom_link_startup_post_change(struct ufs_hba *hba)
 198 {
 199         u32 tx_lanes;
 200
 201         return ufs_qcom_get_connected_tx_lanes(hba, &tx_lanes);
 202 }
 203
 204 static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
 205 {
 206         int err;
 207         u32 tx_fsm_val = 0;
 208         unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
 209
 210         do {
 211                 err = ufshcd_dme_get(hba,
 212                                 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
 213                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
 214                                 &tx_fsm_val);
 215                 if (err || tx_fsm_val == TX_FSM_HIBERN8)
 216                         break;
 217
 218                 /* sleep for max. 200us */
 219                 usleep_range(100, 200);
 220         } while (time_before(jiffies, timeout));
 221
 222         /*
 223          * we might have scheduled out for long during polling so
 224          * check the state again.
 225          */
 226         if (time_after(jiffies, timeout))
 227                 err = ufshcd_dme_get(hba,
 228                                 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
 229                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
 230                                 &tx_fsm_val);
 231
 232         if (err) {
 233                 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
 234                                 __func__, err);
 235         } else if (tx_fsm_val != TX_FSM_HIBERN8) {
 236                 err = tx_fsm_val;
 237                 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
 238                                 __func__, err);
 239         }
 240
 241         return err;
 242 }
 243
 244 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
 245 {
 246         ufshcd_rmwl(host->hba, QUNIPRO_SEL,
 247                    ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0,
 248                    REG_UFS_CFG1);
 249         /* make sure above configuration is applied before we return */
 250         mb();
 251 }
 252
 253 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
 254 {
 255         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 256         struct phy *phy = host->generic_phy;
 257         int ret = 0;
 258         bool is_rate_B = (UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B)
 259                                                         ? true : false;
 260
 261         if (is_rate_B)
 262                 phy_set_mode(phy, PHY_MODE_UFS_HS_B);
 263
 264         /* Assert PHY reset and apply PHY calibration values */
 265         ufs_qcom_assert_reset(hba);
 266         /* provide 1ms delay to let the reset pulse propagate */
 267         usleep_range(1000, 1100);
 268
 269         /* phy initialization - calibrate the phy */
 270         ret = phy_init(phy);
 271         if (ret) {
 272                 dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
 273                         __func__, ret);
 274                 goto out;
 275         }
 276
 277         /* De-assert PHY reset and start serdes */
 278         ufs_qcom_deassert_reset(hba);
 279
 280         /*
 281          * after reset deassertion, phy will need all ref clocks,
 282          * voltage, current to settle down before starting serdes.
 283          */
 284         usleep_range(1000, 1100);
 285
 286         /* power on phy - start serdes and phy's power and clocks */
 287         ret = phy_power_on(phy);
 288         if (ret) {
 289                 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n",
 290                         __func__, ret);
 291                 goto out_disable_phy;
 292         }
 293
 294         ufs_qcom_select_unipro_mode(host);
 295
 296         return 0;
 297
 298 out_disable_phy:
 299         ufs_qcom_assert_reset(hba);
 300         phy_exit(phy);
 301 out:
 302         return ret;
 303 }
 304
 305 /*
 306  * The UTP controller has a number of internal clock gating cells (CGCs).
 307  * Internal hardware sub-modules within the UTP controller control the CGCs.
 308  * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
 309  * in a specific operation, UTP controller CGCs are by default disabled and
 310  * this function enables them (after every UFS link startup) to save some power
 311  * leakage.
 312  */
 313 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
 314 {
 315         ufshcd_writel(hba,
 316                 ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL,
 317                 REG_UFS_CFG2);
 318
 319         /* Ensure that HW clock gating is enabled before next operations */
 320         mb();
 321 }
 322
 323 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
 324                                       enum ufs_notify_change_status status)
 325 {
 326         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 327         int err = 0;
 328
 329         switch (status) {
 330         case PRE_CHANGE:
 331                 ufs_qcom_power_up_sequence(hba);
 332                 /*
 333                  * The PHY PLL output is the source of tx/rx lane symbol
 334                  * clocks, hence, enable the lane clocks only after PHY
 335                  * is initialized.
 336                  */
 337                 err = ufs_qcom_enable_lane_clks(host);
 338                 break;
 339         case POST_CHANGE:
 340                 /* check if UFS PHY moved from DISABLED to HIBERN8 */
 341                 err = ufs_qcom_check_hibern8(hba);
 342                 ufs_qcom_enable_hw_clk_gating(hba);
 343
 344                 break;
 345         default:
 346                 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
 347                 err = -EINVAL;
 348                 break;
 349         }
 350         return err;
 351 }
 352
 353 /**
 354  * Returns zero for success and non-zero in case of a failure
 355  */
 356 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
 357                                u32 hs, u32 rate, bool update_link_startup_timer)
 358 {
 359         int ret = 0;
 360         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 361         struct ufs_clk_info *clki;
 362         u32 core_clk_period_in_ns;
 363         u32 tx_clk_cycles_per_us = 0;
 364         unsigned long core_clk_rate = 0;
 365         u32 core_clk_cycles_per_us = 0;
 366
 367         static u32 pwm_fr_table[][2] = {
 368                 {UFS_PWM_G1, 0x1},
 369                 {UFS_PWM_G2, 0x1},
 370                 {UFS_PWM_G3, 0x1},
 371                 {UFS_PWM_G4, 0x1},
 372         };
 373
 374         static u32 hs_fr_table_rA[][2] = {
 375                 {UFS_HS_G1, 0x1F},
 376                 {UFS_HS_G2, 0x3e},
 377                 {UFS_HS_G3, 0x7D},
 378         };
 379
 380         static u32 hs_fr_table_rB[][2] = {
 381                 {UFS_HS_G1, 0x24},
 382                 {UFS_HS_G2, 0x49},
 383                 {UFS_HS_G3, 0x92},
 384         };
 385
 386         /*
 387          * The Qunipro controller does not use following registers:
 388          * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG &
 389          * UFS_REG_PA_LINK_STARTUP_TIMER
 390          * But UTP controller uses SYS1CLK_1US_REG register for Interrupt
 391          * Aggregation logic.
 392         */
 393         if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba))
 394                 goto out;
 395
 396         if (gear == 0) {
 397                 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
 398                 goto out_error;
 399         }
 400
 401         list_for_each_entry(clki, &hba->clk_list_head, list) {
 402                 if (!strcmp(clki->name, "core_clk"))
 403                         core_clk_rate = clk_get_rate(clki->clk);
 404         }
 405
 406         /* If frequency is smaller than 1MHz, set to 1MHz */
 407         if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
 408                 core_clk_rate = DEFAULT_CLK_RATE_HZ;
 409
 410         core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
 411         if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
 412                 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
 413                 /*
 414                  * make sure above write gets applied before we return from
 415                  * this function.
 416                  */
 417                 mb();
 418         }
 419
 420         if (ufs_qcom_cap_qunipro(host))
 421                 goto out;
 422
 423         core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate;
 424         core_clk_period_in_ns <<= OFFSET_CLK_NS_REG;
 425         core_clk_period_in_ns &= MASK_CLK_NS_REG;
 426
 427         switch (hs) {
 428         case FASTAUTO_MODE:
 429         case FAST_MODE:
 430                 if (rate == PA_HS_MODE_A) {
 431                         if (gear > ARRAY_SIZE(hs_fr_table_rA)) {
 432                                 dev_err(hba->dev,
 433                                         "%s: index %d exceeds table size %zu\n",
 434                                         __func__, gear,
 435                                         ARRAY_SIZE(hs_fr_table_rA));
 436                                 goto out_error;
 437                         }
 438                         tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1];
 439                 } else if (rate == PA_HS_MODE_B) {
 440                         if (gear > ARRAY_SIZE(hs_fr_table_rB)) {
 441                                 dev_err(hba->dev,
 442                                         "%s: index %d exceeds table size %zu\n",
 443                                         __func__, gear,
 444                                         ARRAY_SIZE(hs_fr_table_rB));
 445                                 goto out_error;
 446                         }
 447                         tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1];
 448                 } else {
 449                         dev_err(hba->dev, "%s: invalid rate = %d\n",
 450                                 __func__, rate);
 451                         goto out_error;
 452                 }
 453                 break;
 454         case SLOWAUTO_MODE:
 455         case SLOW_MODE:
 456                 if (gear > ARRAY_SIZE(pwm_fr_table)) {
 457                         dev_err(hba->dev,
 458                                         "%s: index %d exceeds table size %zu\n",
 459                                         __func__, gear,
 460                                         ARRAY_SIZE(pwm_fr_table));
 461                         goto out_error;
 462                 }
 463                 tx_clk_cycles_per_us = pwm_fr_table[gear-1][1];
 464                 break;
 465         case UNCHANGED:
 466         default:
 467                 dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs);
 468                 goto out_error;
 469         }
 470
 471         if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) !=
 472             (core_clk_period_in_ns | tx_clk_cycles_per_us)) {
 473                 /* this register 2 fields shall be written at once */
 474                 ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us,
 475                               REG_UFS_TX_SYMBOL_CLK_NS_US);
 476                 /*
 477                  * make sure above write gets applied before we return from
 478                  * this function.
 479                  */
 480                 mb();
 481         }
 482
 483         if (update_link_startup_timer) {
 484                 ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100),
 485                               REG_UFS_PA_LINK_STARTUP_TIMER);
 486                 /*
 487                  * make sure that this configuration is applied before
 488                  * we return
 489                  */
 490                 mb();
 491         }
 492         goto out;
 493
 494 out_error:
 495         ret = -EINVAL;
 496 out:
 497         return ret;
 498 }
 499
 500 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
 501                                         enum ufs_notify_change_status status)
 502 {
 503         int err = 0;
 504         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 505
 506         switch (status) {
 507         case PRE_CHANGE:
 508                 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE,
 509                                         0, true)) {
 510                         dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
 511                                 __func__);
 512                         err = -EINVAL;
 513                         goto out;
 514                 }
 515
 516                 if (ufs_qcom_cap_qunipro(host))
 517                         /*
 518                          * set unipro core clock cycles to 150 & clear clock
 519                          * divider
 520                          */
 521                         err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba,
 522                                                                           150);
 523
 524                 /*
 525                  * Some UFS devices (and may be host) have issues if LCC is
 526                  * enabled. So we are setting PA_Local_TX_LCC_Enable to 0
 527                  * before link startup which will make sure that both host
 528                  * and device TX LCC are disabled once link startup is
 529                  * completed.
 530                  */
 531                 if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41)
 532                         err = ufshcd_dme_set(hba,
 533                                         UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE),
 534                                         0);
 535
 536                 break;
 537         case POST_CHANGE:
 538                 ufs_qcom_link_startup_post_change(hba);
 539                 break;
 540         default:
 541                 break;
 542         }
 543
 544 out:
 545         return err;
 546 }
 547
 548 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
 549 {
 550         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 551         struct phy *phy = host->generic_phy;
 552         int ret = 0;
 553
 554         if (ufs_qcom_is_link_off(hba)) {
 555                 /*
 556                  * Disable the tx/rx lane symbol clocks before PHY is
 557                  * powered down as the PLL source should be disabled
 558                  * after downstream clocks are disabled.
 559                  */
 560                 ufs_qcom_disable_lane_clks(host);
 561                 phy_power_off(phy);
 562
 563                 /* Assert PHY soft reset */
 564                 ufs_qcom_assert_reset(hba);
 565                 goto out;
 566         }
 567
 568         /*
 569          * If UniPro link is not active, PHY ref_clk, main PHY analog power
 570          * rail and low noise analog power rail for PLL can be switched off.
 571          */
 572         if (!ufs_qcom_is_link_active(hba)) {
 573                 ufs_qcom_disable_lane_clks(host);
 574                 phy_power_off(phy);
 575         }
 576
 577 out:
 578         return ret;
 579 }
 580
 581 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
 582 {
 583         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 584         struct phy *phy = host->generic_phy;
 585         int err;
 586
 587         err = phy_power_on(phy);
 588         if (err) {
 589                 dev_err(hba->dev, "%s: failed enabling regs, err = %d\n",
 590                         __func__, err);
 591                 goto out;
 592         }
 593
 594         err = ufs_qcom_enable_lane_clks(host);
 595         if (err)
 596                 goto out;
 597
 598         hba->is_sys_suspended = false;
 599
 600 out:
 601         return err;
 602 }
 603
 604 struct ufs_qcom_dev_params {
 605         u32 pwm_rx_gear;        /* pwm rx gear to work in */
 606         u32 pwm_tx_gear;        /* pwm tx gear to work in */
 607         u32 hs_rx_gear;         /* hs rx gear to work in */
 608         u32 hs_tx_gear;         /* hs tx gear to work in */
 609         u32 rx_lanes;           /* number of rx lanes */
 610         u32 tx_lanes;           /* number of tx lanes */
 611         u32 rx_pwr_pwm;         /* rx pwm working pwr */
 612         u32 tx_pwr_pwm;         /* tx pwm working pwr */
 613         u32 rx_pwr_hs;          /* rx hs working pwr */
 614         u32 tx_pwr_hs;          /* tx hs working pwr */
 615         u32 hs_rate;            /* rate A/B to work in HS */
 616         u32 desired_working_mode;
 617 };
 618
 619 static int ufs_qcom_get_pwr_dev_param(struct ufs_qcom_dev_params *qcom_param,
 620                                       struct ufs_pa_layer_attr *dev_max,
 621                                       struct ufs_pa_layer_attr *agreed_pwr)
 622 {
 623         int min_qcom_gear;
 624         int min_dev_gear;
 625         bool is_dev_sup_hs = false;
 626         bool is_qcom_max_hs = false;
 627
 628         if (dev_max->pwr_rx == FAST_MODE)
 629                 is_dev_sup_hs = true;
 630
 631         if (qcom_param->desired_working_mode == FAST) {
 632                 is_qcom_max_hs = true;
 633                 min_qcom_gear = min_t(u32, qcom_param->hs_rx_gear,
 634                                       qcom_param->hs_tx_gear);
 635         } else {
 636                 min_qcom_gear = min_t(u32, qcom_param->pwm_rx_gear,
 637                                       qcom_param->pwm_tx_gear);
 638         }
 639
 640         /*
 641          * device doesn't support HS but qcom_param->desired_working_mode is
 642          * HS, thus device and qcom_param don't agree
 643          */
 644         if (!is_dev_sup_hs && is_qcom_max_hs) {
 645                 pr_err("%s: failed to agree on power mode (device doesn't support HS but requested power is HS)\n",
 646                         __func__);
 647                 return -ENOTSUPP;
 648         } else if (is_dev_sup_hs && is_qcom_max_hs) {
 649                 /*
 650                  * since device supports HS, it supports FAST_MODE.
 651                  * since qcom_param->desired_working_mode is also HS
 652                  * then final decision (FAST/FASTAUTO) is done according
 653                  * to qcom_params as it is the restricting factor
 654                  */
 655                 agreed_pwr->pwr_rx = agreed_pwr->pwr_tx =
 656                                                 qcom_param->rx_pwr_hs;
 657         } else {
 658                 /*
 659                  * here qcom_param->desired_working_mode is PWM.
 660                  * it doesn't matter whether device supports HS or PWM,
 661                  * in both cases qcom_param->desired_working_mode will
 662                  * determine the mode
 663                  */
 664                  agreed_pwr->pwr_rx = agreed_pwr->pwr_tx =
 665                                                 qcom_param->rx_pwr_pwm;
 666         }
 667
 668         /*
 669          * we would like tx to work in the minimum number of lanes
 670          * between device capability and vendor preferences.
 671          * the same decision will be made for rx
 672          */
 673         agreed_pwr->lane_tx = min_t(u32, dev_max->lane_tx,
 674                                                 qcom_param->tx_lanes);
 675         agreed_pwr->lane_rx = min_t(u32, dev_max->lane_rx,
 676                                                 qcom_param->rx_lanes);
 677
 678         /* device maximum gear is the minimum between device rx and tx gears */
 679         min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx);
 680
 681         /*
 682          * if both device capabilities and vendor pre-defined preferences are
 683          * both HS or both PWM then set the minimum gear to be the chosen
 684          * working gear.
 685          * if one is PWM and one is HS then the one that is PWM get to decide
 686          * what is the gear, as it is the one that also decided previously what
 687          * pwr the device will be configured to.
 688          */
 689         if ((is_dev_sup_hs && is_qcom_max_hs) ||
 690             (!is_dev_sup_hs && !is_qcom_max_hs))
 691                 agreed_pwr->gear_rx = agreed_pwr->gear_tx =
 692                         min_t(u32, min_dev_gear, min_qcom_gear);
 693         else if (!is_dev_sup_hs)
 694                 agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_dev_gear;
 695         else
 696                 agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_qcom_gear;
 697
 698         agreed_pwr->hs_rate = qcom_param->hs_rate;
 699         return 0;
 700 }
 701
 702 #ifdef CONFIG_MSM_BUS_SCALING
 703 static int ufs_qcom_get_bus_vote(struct ufs_qcom_host *host,
 704                 const char *speed_mode)
 705 {
 706         struct device *dev = host->hba->dev;
 707         struct device_node *np = dev->of_node;
 708         int err;
 709         const char *key = "qcom,bus-vector-names";
 710
 711         if (!speed_mode) {
 712                 err = -EINVAL;
 713                 goto out;
 714         }
 715
 716         if (host->bus_vote.is_max_bw_needed && !!strcmp(speed_mode, "MIN"))
 717                 err = of_property_match_string(np, key, "MAX");
 718         else
 719                 err = of_property_match_string(np, key, speed_mode);
 720
 721 out:
 722         if (err < 0)
 723                 dev_err(dev, "%s: Invalid %s mode %d\n",
 724                                 __func__, speed_mode, err);
 725         return err;
 726 }
 727
 728 static void ufs_qcom_get_speed_mode(struct ufs_pa_layer_attr *p, char *result)
 729 {
 730         int gear = max_t(u32, p->gear_rx, p->gear_tx);
 731         int lanes = max_t(u32, p->lane_rx, p->lane_tx);
 732         int pwr;
 733
 734         /* default to PWM Gear 1, Lane 1 if power mode is not initialized */
 735         if (!gear)
 736                 gear = 1;
 737
 738         if (!lanes)
 739                 lanes = 1;
 740
 741         if (!p->pwr_rx && !p->pwr_tx) {
 742                 pwr = SLOWAUTO_MODE;
 743                 snprintf(result, BUS_VECTOR_NAME_LEN, "MIN");
 744         } else if (p->pwr_rx == FAST_MODE || p->pwr_rx == FASTAUTO_MODE ||
 745                  p->pwr_tx == FAST_MODE || p->pwr_tx == FASTAUTO_MODE) {
 746                 pwr = FAST_MODE;
 747                 snprintf(result, BUS_VECTOR_NAME_LEN, "%s_R%s_G%d_L%d", "HS",
 748                          p->hs_rate == PA_HS_MODE_B ? "B" : "A", gear, lanes);
 749         } else {
 750                 pwr = SLOW_MODE;
 751                 snprintf(result, BUS_VECTOR_NAME_LEN, "%s_G%d_L%d",
 752                          "PWM", gear, lanes);
 753         }
 754 }
 755
 756 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote)
 757 {
 758         int err = 0;
 759
 760         if (vote != host->bus_vote.curr_vote) {
 761                 err = msm_bus_scale_client_update_request(
 762                                 host->bus_vote.client_handle, vote);
 763                 if (err) {
 764                         dev_err(host->hba->dev,
 765                                 "%s: msm_bus_scale_client_update_request() failed: bus_client_handle=0x%x, vote=%d, err=%d\n",
 766                                 __func__, host->bus_vote.client_handle,
 767                                 vote, err);
 768                         goto out;
 769                 }
 770
 771                 host->bus_vote.curr_vote = vote;
 772         }
 773 out:
 774         return err;
 775 }
 776
 777 static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host)
 778 {
 779         int vote;
 780         int err = 0;
 781         char mode[BUS_VECTOR_NAME_LEN];
 782
 783         ufs_qcom_get_speed_mode(&host->dev_req_params, mode);
 784
 785         vote = ufs_qcom_get_bus_vote(host, mode);
 786         if (vote >= 0)
 787                 err = ufs_qcom_set_bus_vote(host, vote);
 788         else
 789                 err = vote;
 790
 791         if (err)
 792                 dev_err(host->hba->dev, "%s: failed %d\n", __func__, err);
 793         else
 794                 host->bus_vote.saved_vote = vote;
 795         return err;
 796 }
 797
 798 static ssize_t
 799 show_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
 800                         char *buf)
 801 {
 802         struct ufs_hba *hba = dev_get_drvdata(dev);
 803         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 804
 805         return snprintf(buf, PAGE_SIZE, "%u\n",
 806                         host->bus_vote.is_max_bw_needed);
 807 }
 808
 809 static ssize_t
 810 store_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
 811                 const char *buf, size_t count)
 812 {
 813         struct ufs_hba *hba = dev_get_drvdata(dev);
 814         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 815         uint32_t value;
 816
 817         if (!kstrtou32(buf, 0, &value)) {
 818                 host->bus_vote.is_max_bw_needed = !!value;
 819                 ufs_qcom_update_bus_bw_vote(host);
 820         }
 821
 822         return count;
 823 }
 824
 825 static int ufs_qcom_bus_register(struct ufs_qcom_host *host)
 826 {
 827         int err;
 828         struct msm_bus_scale_pdata *bus_pdata;
 829         struct device *dev = host->hba->dev;
 830         struct platform_device *pdev = to_platform_device(dev);
 831         struct device_node *np = dev->of_node;
 832
 833         bus_pdata = msm_bus_cl_get_pdata(pdev);
 834         if (!bus_pdata) {
 835                 dev_err(dev, "%s: failed to get bus vectors\n", __func__);
 836                 err = -ENODATA;
 837                 goto out;
 838         }
 839
 840         err = of_property_count_strings(np, "qcom,bus-vector-names");
 841         if (err < 0 || err != bus_pdata->num_usecases) {
 842                 dev_err(dev, "%s: qcom,bus-vector-names not specified correctly %d\n",
 843                                 __func__, err);
 844                 goto out;
 845         }
 846
 847         host->bus_vote.client_handle = msm_bus_scale_register_client(bus_pdata);
 848         if (!host->bus_vote.client_handle) {
 849                 dev_err(dev, "%s: msm_bus_scale_register_client failed\n",
 850                                 __func__);
 851                 err = -EFAULT;
 852                 goto out;
 853         }
 854
 855         /* cache the vote index for minimum and maximum bandwidth */
 856         host->bus_vote.min_bw_vote = ufs_qcom_get_bus_vote(host, "MIN");
 857         host->bus_vote.max_bw_vote = ufs_qcom_get_bus_vote(host, "MAX");
 858
 859         host->bus_vote.max_bus_bw.show = show_ufs_to_mem_max_bus_bw;
 860         host->bus_vote.max_bus_bw.store = store_ufs_to_mem_max_bus_bw;
 861         sysfs_attr_init(&host->bus_vote.max_bus_bw.attr);
 862         host->bus_vote.max_bus_bw.attr.name = "max_bus_bw";
 863         host->bus_vote.max_bus_bw.attr.mode = S_IRUGO | S_IWUSR;
 864         err = device_create_file(dev, &host->bus_vote.max_bus_bw);
 865 out:
 866         return err;
 867 }
 868 #else /* CONFIG_MSM_BUS_SCALING */
 869 static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host)
 870 {
 871         return 0;
 872 }
 873
 874 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote)
 875 {
 876         return 0;
 877 }
 878
 879 static int ufs_qcom_bus_register(struct ufs_qcom_host *host)
 880 {
 881         return 0;
 882 }
 883 #endif /* CONFIG_MSM_BUS_SCALING */
 884
 885 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
 886 {
 887         if (host->dev_ref_clk_ctrl_mmio &&
 888             (enable ^ host->is_dev_ref_clk_enabled)) {
 889                 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
 890
 891                 if (enable)
 892                         temp |= host->dev_ref_clk_en_mask;
 893                 else
 894                         temp &= ~host->dev_ref_clk_en_mask;
 895
 896                 /*
 897                  * If we are here to disable this clock it might be immediately
 898                  * after entering into hibern8 in which case we need to make
 899                  * sure that device ref_clk is active at least 1us after the
 900                  * hibern8 enter.
 901                  */
 902                 if (!enable)
 903                         udelay(1);
 904
 905                 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
 906
 907                 /* ensure that ref_clk is enabled/disabled before we return */
 908                 wmb();
 909
 910                 /*
 911                  * If we call hibern8 exit after this, we need to make sure that
 912                  * device ref_clk is stable for at least 1us before the hibern8
 913                  * exit command.
 914                  */
 915                 if (enable)
 916                         udelay(1);
 917
 918                 host->is_dev_ref_clk_enabled = enable;
 919         }
 920 }
 921
 922 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
 923                                 enum ufs_notify_change_status status,
 924                                 struct ufs_pa_layer_attr *dev_max_params,
 925                                 struct ufs_pa_layer_attr *dev_req_params)
 926 {
 927         u32 val;
 928         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 929         struct ufs_qcom_dev_params ufs_qcom_cap;
 930         int ret = 0;
 931
 932         if (!dev_req_params) {
 933                 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
 934                 ret = -EINVAL;
 935                 goto out;
 936         }
 937
 938         switch (status) {
 939         case PRE_CHANGE:
 940                 ufs_qcom_cap.tx_lanes = UFS_QCOM_LIMIT_NUM_LANES_TX;
 941                 ufs_qcom_cap.rx_lanes = UFS_QCOM_LIMIT_NUM_LANES_RX;
 942                 ufs_qcom_cap.hs_rx_gear = UFS_QCOM_LIMIT_HSGEAR_RX;
 943                 ufs_qcom_cap.hs_tx_gear = UFS_QCOM_LIMIT_HSGEAR_TX;
 944                 ufs_qcom_cap.pwm_rx_gear = UFS_QCOM_LIMIT_PWMGEAR_RX;
 945                 ufs_qcom_cap.pwm_tx_gear = UFS_QCOM_LIMIT_PWMGEAR_TX;
 946                 ufs_qcom_cap.rx_pwr_pwm = UFS_QCOM_LIMIT_RX_PWR_PWM;
 947                 ufs_qcom_cap.tx_pwr_pwm = UFS_QCOM_LIMIT_TX_PWR_PWM;
 948                 ufs_qcom_cap.rx_pwr_hs = UFS_QCOM_LIMIT_RX_PWR_HS;
 949                 ufs_qcom_cap.tx_pwr_hs = UFS_QCOM_LIMIT_TX_PWR_HS;
 950                 ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
 951                 ufs_qcom_cap.desired_working_mode =
 952                                         UFS_QCOM_LIMIT_DESIRED_MODE;
 953
 954                 if (host->hw_ver.major == 0x1) {
 955                         /*
 956                          * HS-G3 operations may not reliably work on legacy QCOM
 957                          * UFS host controller hardware even though capability
 958                          * exchange during link startup phase may end up
 959                          * negotiating maximum supported gear as G3.
 960                          * Hence downgrade the maximum supported gear to HS-G2.
 961                          */
 962                         if (ufs_qcom_cap.hs_tx_gear > UFS_HS_G2)
 963                                 ufs_qcom_cap.hs_tx_gear = UFS_HS_G2;
 964                         if (ufs_qcom_cap.hs_rx_gear > UFS_HS_G2)
 965                                 ufs_qcom_cap.hs_rx_gear = UFS_HS_G2;
 966                 }
 967
 968                 ret = ufs_qcom_get_pwr_dev_param(&ufs_qcom_cap,
 969                                                  dev_max_params,
 970                                                  dev_req_params);
 971                 if (ret) {
 972                         pr_err("%s: failed to determine capabilities\n",
 973                                         __func__);
 974                         goto out;
 975                 }
 976
 977                 /* enable the device ref clock before changing to HS mode */
 978                 if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
 979                         ufshcd_is_hs_mode(dev_req_params))
 980                         ufs_qcom_dev_ref_clk_ctrl(host, true);
 981                 break;
 982         case POST_CHANGE:
 983                 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
 984                                         dev_req_params->pwr_rx,
 985                                         dev_req_params->hs_rate, false)) {
 986                         dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
 987                                 __func__);
 988                         /*
 989                          * we return error code at the end of the routine,
 990                          * but continue to configure UFS_PHY_TX_LANE_ENABLE
 991                          * and bus voting as usual
 992                          */
 993                         ret = -EINVAL;
 994                 }
 995
 996                 val = ~(MAX_U32 << dev_req_params->lane_tx);
 997
 998                 /* cache the power mode parameters to use internally */
 999                 memcpy(&host->dev_req_params,
1000                                 dev_req_params, sizeof(*dev_req_params));
1001                 ufs_qcom_update_bus_bw_vote(host);
1002
1003                 /* disable the device ref clock if entered PWM mode */
1004                 if (ufshcd_is_hs_mode(&hba->pwr_info) &&
1005                         !ufshcd_is_hs_mode(dev_req_params))
1006                         ufs_qcom_dev_ref_clk_ctrl(host, false);
1007                 break;
1008         default:
1009                 ret = -EINVAL;
1010                 break;
1011         }
1012 out:
1013         return ret;
1014 }
1015
1016 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba)
1017 {
1018         int err;
1019         u32 pa_vs_config_reg1;
1020
1021         err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
1022                              &pa_vs_config_reg1);
1023         if (err)
1024                 goto out;
1025
1026         /* Allow extension of MSB bits of PA_SaveConfigTime attribute */
1027         err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
1028                             (pa_vs_config_reg1 | (1 << 12)));
1029
1030 out:
1031         return err;
1032 }
1033
1034 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba)
1035 {
1036         int err = 0;
1037
1038         if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME)
1039                 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba);
1040
1041         return err;
1042 }
1043
1044 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba)
1045 {
1046         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1047
1048         if (host->hw_ver.major == 0x1)
1049                 return UFSHCI_VERSION_11;
1050         else
1051                 return UFSHCI_VERSION_20;
1052 }
1053
1054 /**
1055  * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
1056  * @hba: host controller instance
1057  *
1058  * QCOM UFS host controller might have some non standard behaviours (quirks)
1059  * than what is specified by UFSHCI specification. Advertise all such
1060  * quirks to standard UFS host controller driver so standard takes them into
1061  * account.
1062  */
1063 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
1064 {
1065         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1066
1067         if (host->hw_ver.major == 0x01) {
1068                 hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
1069                             | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP
1070                             | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE;
1071
1072                 if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001)
1073                         hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR;
1074
1075                 hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC;
1076         }
1077
1078         if (host->hw_ver.major == 0x2) {
1079                 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
1080
1081                 if (!ufs_qcom_cap_qunipro(host))
1082                         /* Legacy UniPro mode still need following quirks */
1083                         hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
1084                                 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE
1085                                 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP);
1086         }
1087 }
1088
1089 static void ufs_qcom_set_caps(struct ufs_hba *hba)
1090 {
1091         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1092
1093         hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
1094         hba->caps |= UFSHCD_CAP_CLK_SCALING;
1095         hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
1096
1097         if (host->hw_ver.major >= 0x2) {
1098                 host->caps = UFS_QCOM_CAP_QUNIPRO |
1099                              UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE;
1100         }
1101 }
1102
1103 /**
1104  * ufs_qcom_setup_clocks - enables/disable clocks
1105  * @hba: host controller instance
1106  * @on: If true, enable clocks else disable them.
1107  * @status: PRE_CHANGE or POST_CHANGE notify
1108  *
1109  * Returns 0 on success, non-zero on failure.
1110  */
1111 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
1112                                  enum ufs_notify_change_status status)
1113 {
1114         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1115         int err;
1116         int vote = 0;
1117
1118         /*
1119          * In case ufs_qcom_init() is not yet done, simply ignore.
1120          * This ufs_qcom_setup_clocks() shall be called from
1121          * ufs_qcom_init() after init is done.
1122          */
1123         if (!host)
1124                 return 0;
1125
1126         if (on && (status == POST_CHANGE)) {
1127                 phy_power_on(host->generic_phy);
1128
1129                 /* enable the device ref clock for HS mode*/
1130                 if (ufshcd_is_hs_mode(&hba->pwr_info))
1131                         ufs_qcom_dev_ref_clk_ctrl(host, true);
1132                 vote = host->bus_vote.saved_vote;
1133                 if (vote == host->bus_vote.min_bw_vote)
1134                         ufs_qcom_update_bus_bw_vote(host);
1135
1136         } else if (!on && (status == PRE_CHANGE)) {
1137                 if (!ufs_qcom_is_link_active(hba)) {
1138                         /* disable device ref_clk */
1139                         ufs_qcom_dev_ref_clk_ctrl(host, false);
1140
1141                         /* powering off PHY during aggressive clk gating */
1142                         phy_power_off(host->generic_phy);
1143                 }
1144
1145                 vote = host->bus_vote.min_bw_vote;
1146         }
1147
1148         err = ufs_qcom_set_bus_vote(host, vote);
1149         if (err)
1150                 dev_err(hba->dev, "%s: set bus vote failed %d\n",
1151                                 __func__, err);
1152
1153         return err;
1154 }
1155
1156 static int
1157 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
1158 {
1159         struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
1160
1161         /* Currently this code only knows about a single reset. */
1162         WARN_ON(id);
1163         ufs_qcom_assert_reset(host->hba);
1164         /* provide 1ms delay to let the reset pulse propagate. */
1165         usleep_range(1000, 1100);
1166         return 0;
1167 }
1168
1169 static int
1170 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
1171 {
1172         struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
1173
1174         /* Currently this code only knows about a single reset. */
1175         WARN_ON(id);
1176         ufs_qcom_deassert_reset(host->hba);
1177
1178         /*
1179          * after reset deassertion, phy will need all ref clocks,
1180          * voltage, current to settle down before starting serdes.
1181          */
1182         usleep_range(1000, 1100);
1183         return 0;
1184 }
1185
1186 static const struct reset_control_ops ufs_qcom_reset_ops = {
1187         .assert = ufs_qcom_reset_assert,
1188         .deassert = ufs_qcom_reset_deassert,
1189 };
1190
1191 #define ANDROID_BOOT_DEV_MAX    30
1192 static char android_boot_dev[ANDROID_BOOT_DEV_MAX];
1193
1194 #ifndef MODULE
1195 static int __init get_android_boot_dev(char *str)
1196 {
1197         strlcpy(android_boot_dev, str, ANDROID_BOOT_DEV_MAX);
1198         return 1;
1199 }
1200 __setup("androidboot.bootdevice=", get_android_boot_dev);
1201 #endif
1202
1203 /**
1204  * ufs_qcom_init - bind phy with controller
1205  * @hba: host controller instance
1206  *
1207  * Binds PHY with controller and powers up PHY enabling clocks
1208  * and regulators.
1209  *
1210  * Returns -EPROBE_DEFER if binding fails, returns negative error
1211  * on phy power up failure and returns zero on success.
1212  */
1213 static int ufs_qcom_init(struct ufs_hba *hba)
1214 {
1215         int err;
1216         struct device *dev = hba->dev;
1217         struct platform_device *pdev = to_platform_device(dev);
1218         struct ufs_qcom_host *host;
1219         struct resource *res;
1220
1221         if (strlen(android_boot_dev) && strcmp(android_boot_dev, dev_name(dev)))
1222                 return -ENODEV;
1223
1224         host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
1225         if (!host) {
1226                 err = -ENOMEM;
1227                 dev_err(dev, "%s: no memory for qcom ufs host\n", __func__);
1228                 goto out;
1229         }
1230
1231         /* Make a two way bind between the qcom host and the hba */
1232         host->hba = hba;
1233         ufshcd_set_variant(hba, host);
1234
1235         /* Fire up the reset controller. Failure here is non-fatal. */
1236         host->rcdev.of_node = dev->of_node;
1237         host->rcdev.ops = &ufs_qcom_reset_ops;
1238         host->rcdev.owner = dev->driver->owner;
1239         host->rcdev.nr_resets = 1;
1240         err = devm_reset_controller_register(dev, &host->rcdev);
1241         if (err) {
1242                 dev_warn(dev, "Failed to register reset controller\n");
1243                 err = 0;
1244         }
1245
1246         /*
1247          * voting/devoting device ref_clk source is time consuming hence
1248          * skip devoting it during aggressive clock gating. This clock
1249          * will still be gated off during runtime suspend.
1250          */
1251         host->generic_phy = devm_phy_get(dev, "ufsphy");
1252
1253         if (host->generic_phy == ERR_PTR(-EPROBE_DEFER)) {
1254                 /*
1255                  * UFS driver might be probed before the phy driver does.
1256                  * In that case we would like to return EPROBE_DEFER code.
1257                  */
1258                 err = -EPROBE_DEFER;
1259                 dev_warn(dev, "%s: required phy device. hasn't probed yet. err = %d\n",
1260                         __func__, err);
1261                 goto out_variant_clear;
1262         } else if (IS_ERR(host->generic_phy)) {
1263                 err = PTR_ERR(host->generic_phy);
1264                 dev_err(dev, "%s: PHY get failed %d\n", __func__, err);
1265                 goto out_variant_clear;
1266         }
1267
1268         err = ufs_qcom_bus_register(host);
1269         if (err)
1270                 goto out_variant_clear;
1271
1272         ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
1273                 &host->hw_ver.minor, &host->hw_ver.step);
1274
1275         /*
1276          * for newer controllers, device reference clock control bit has
1277          * moved inside UFS controller register address space itself.
1278          */
1279         if (host->hw_ver.major >= 0x02) {
1280                 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;
1281                 host->dev_ref_clk_en_mask = BIT(26);
1282         } else {
1283                 /* "dev_ref_clk_ctrl_mem" is optional resource */
1284                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1285                 if (res) {
1286                         host->dev_ref_clk_ctrl_mmio =
1287                                         devm_ioremap_resource(dev, res);
1288                         if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) {
1289                                 dev_warn(dev,
1290                                         "%s: could not map dev_ref_clk_ctrl_mmio, err %ld\n",
1291                                         __func__,
1292                                         PTR_ERR(host->dev_ref_clk_ctrl_mmio));
1293                                 host->dev_ref_clk_ctrl_mmio = NULL;
1294                         }
1295                         host->dev_ref_clk_en_mask = BIT(5);
1296                 }
1297         }
1298
1299         err = ufs_qcom_init_lane_clks(host);
1300         if (err)
1301                 goto out_variant_clear;
1302
1303         ufs_qcom_set_caps(hba);
1304         ufs_qcom_advertise_quirks(hba);
1305
1306         ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
1307
1308         if (hba->dev->id < MAX_UFS_QCOM_HOSTS)
1309                 ufs_qcom_hosts[hba->dev->id] = host;
1310
1311         host->dbg_print_en |= UFS_QCOM_DEFAULT_DBG_PRINT_EN;
1312         ufs_qcom_get_default_testbus_cfg(host);
1313         err = ufs_qcom_testbus_config(host);
1314         if (err) {
1315                 dev_warn(dev, "%s: failed to configure the testbus %d\n",
1316                                 __func__, err);
1317                 err = 0;
1318         }
1319
1320         goto out;
1321
1322 out_variant_clear:
1323         ufshcd_set_variant(hba, NULL);
1324 out:
1325         return err;
1326 }
1327
1328 static void ufs_qcom_exit(struct ufs_hba *hba)
1329 {
1330         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1331
1332         ufs_qcom_disable_lane_clks(host);
1333         phy_power_off(host->generic_phy);
1334         phy_exit(host->generic_phy);
1335 }
1336
1337 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
1338                                                        u32 clk_cycles)
1339 {
1340         int err;
1341         u32 core_clk_ctrl_reg;
1342
1343         if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK)
1344                 return -EINVAL;
1345
1346         err = ufshcd_dme_get(hba,
1347                             UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1348                             &core_clk_ctrl_reg);
1349         if (err)
1350                 goto out;
1351
1352         core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK;
1353         core_clk_ctrl_reg |= clk_cycles;
1354
1355         /* Clear CORE_CLK_DIV_EN */
1356         core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1357
1358         err = ufshcd_dme_set(hba,
1359                             UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1360                             core_clk_ctrl_reg);
1361 out:
1362         return err;
1363 }
1364
1365 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)
1366 {
1367         /* nothing to do as of now */
1368         return 0;
1369 }
1370
1371 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)
1372 {
1373         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1374
1375         if (!ufs_qcom_cap_qunipro(host))
1376                 return 0;
1377
1378         /* set unipro core clock cycles to 150 and clear clock divider */
1379         return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150);
1380 }
1381
1382 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
1383 {
1384         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1385         int err;
1386         u32 core_clk_ctrl_reg;
1387
1388         if (!ufs_qcom_cap_qunipro(host))
1389                 return 0;
1390
1391         err = ufshcd_dme_get(hba,
1392                             UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1393                             &core_clk_ctrl_reg);
1394
1395         /* make sure CORE_CLK_DIV_EN is cleared */
1396         if (!err &&
1397             (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) {
1398                 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1399                 err = ufshcd_dme_set(hba,
1400                                     UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1401                                     core_clk_ctrl_reg);
1402         }
1403
1404         return err;
1405 }
1406
1407 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba)
1408 {
1409         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1410
1411         if (!ufs_qcom_cap_qunipro(host))
1412                 return 0;
1413
1414         /* set unipro core clock cycles to 75 and clear clock divider */
1415         return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75);
1416 }
1417
1418 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
1419                 bool scale_up, enum ufs_notify_change_status status)
1420 {
1421         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1422         struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params;
1423         int err = 0;
1424
1425         if (status == PRE_CHANGE) {
1426                 if (scale_up)
1427                         err = ufs_qcom_clk_scale_up_pre_change(hba);
1428                 else
1429                         err = ufs_qcom_clk_scale_down_pre_change(hba);
1430         } else {
1431                 if (scale_up)
1432                         err = ufs_qcom_clk_scale_up_post_change(hba);
1433                 else
1434                         err = ufs_qcom_clk_scale_down_post_change(hba);
1435
1436                 if (err || !dev_req_params)
1437                         goto out;
1438
1439                 ufs_qcom_cfg_timers(hba,
1440                                     dev_req_params->gear_rx,
1441                                     dev_req_params->pwr_rx,
1442                                     dev_req_params->hs_rate,
1443                                     false);
1444                 ufs_qcom_update_bus_bw_vote(host);
1445         }
1446
1447 out:
1448         return err;
1449 }
1450
1451 static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba,
1452                 void *priv, void (*print_fn)(struct ufs_hba *hba,
1453                 int offset, int num_regs, const char *str, void *priv))
1454 {
1455         u32 reg;
1456         struct ufs_qcom_host *host;
1457
1458         if (unlikely(!hba)) {
1459                 pr_err("%s: hba is NULL\n", __func__);
1460                 return;
1461         }
1462         if (unlikely(!print_fn)) {
1463                 dev_err(hba->dev, "%s: print_fn is NULL\n", __func__);
1464                 return;
1465         }
1466
1467         host = ufshcd_get_variant(hba);
1468         if (!(host->dbg_print_en & UFS_QCOM_DBG_PRINT_REGS_EN))
1469                 return;
1470
1471         reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
1472         print_fn(hba, reg, 44, "UFS_UFS_DBG_RD_REG_OCSC ", priv);
1473
1474         reg = ufshcd_readl(hba, REG_UFS_CFG1);
1475         reg |= UTP_DBG_RAMS_EN;
1476         ufshcd_writel(hba, reg, REG_UFS_CFG1);
1477
1478         reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
1479         print_fn(hba, reg, 32, "UFS_UFS_DBG_RD_EDTL_RAM ", priv);
1480
1481         reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
1482         print_fn(hba, reg, 128, "UFS_UFS_DBG_RD_DESC_RAM ", priv);
1483
1484         reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
1485         print_fn(hba, reg, 64, "UFS_UFS_DBG_RD_PRDT_RAM ", priv);
1486
1487         /* clear bit 17 - UTP_DBG_RAMS_EN */
1488         ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1);
1489
1490         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1491         print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UAWM ", priv);
1492
1493         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
1494         print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UARM ", priv);
1495
1496         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1497         print_fn(hba, reg, 48, "UFS_DBG_RD_REG_TXUC ", priv);
1498
1499         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1500         print_fn(hba, reg, 27, "UFS_DBG_RD_REG_RXUC ", priv);
1501
1502         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1503         print_fn(hba, reg, 19, "UFS_DBG_RD_REG_DFC ", priv);
1504
1505         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1506         print_fn(hba, reg, 34, "UFS_DBG_RD_REG_TRLUT ", priv);
1507
1508         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1509         print_fn(hba, reg, 9, "UFS_DBG_RD_REG_TMRLUT ", priv);
1510 }
1511
1512 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
1513 {
1514         if (host->dbg_print_en & UFS_QCOM_DBG_PRINT_TEST_BUS_EN) {
1515                 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,
1516                                 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1);
1517                 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1518         } else {
1519                 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 0, REG_UFS_CFG1);
1520                 ufshcd_rmwl(host->hba, TEST_BUS_EN, 0, REG_UFS_CFG1);
1521         }
1522 }
1523
1524 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
1525 {
1526         /* provide a legal default configuration */
1527         host->testbus.select_major = TSTBUS_UNIPRO;
1528         host->testbus.select_minor = 37;
1529 }
1530
1531 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host)
1532 {
1533         if (host->testbus.select_major >= TSTBUS_MAX) {
1534                 dev_err(host->hba->dev,
1535                         "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n",
1536                         __func__, host->testbus.select_major);
1537                 return false;
1538         }
1539
1540         return true;
1541 }
1542
1543 int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
1544 {
1545         int reg;
1546         int offset;
1547         u32 mask = TEST_BUS_SUB_SEL_MASK;
1548
1549         if (!host)
1550                 return -EINVAL;
1551
1552         if (!ufs_qcom_testbus_cfg_is_ok(host))
1553                 return -EPERM;
1554
1555         switch (host->testbus.select_major) {
1556         case TSTBUS_UAWM:
1557                 reg = UFS_TEST_BUS_CTRL_0;
1558                 offset = 24;
1559                 break;
1560         case TSTBUS_UARM:
1561                 reg = UFS_TEST_BUS_CTRL_0;
1562                 offset = 16;
1563                 break;
1564         case TSTBUS_TXUC:
1565                 reg = UFS_TEST_BUS_CTRL_0;
1566                 offset = 8;
1567                 break;
1568         case TSTBUS_RXUC:
1569                 reg = UFS_TEST_BUS_CTRL_0;
1570                 offset = 0;
1571                 break;
1572         case TSTBUS_DFC:
1573                 reg = UFS_TEST_BUS_CTRL_1;
1574                 offset = 24;
1575                 break;
1576         case TSTBUS_TRLUT:
1577                 reg = UFS_TEST_BUS_CTRL_1;
1578                 offset = 16;
1579                 break;
1580         case TSTBUS_TMRLUT:
1581                 reg = UFS_TEST_BUS_CTRL_1;
1582                 offset = 8;
1583                 break;
1584         case TSTBUS_OCSC:
1585                 reg = UFS_TEST_BUS_CTRL_1;
1586                 offset = 0;
1587                 break;
1588         case TSTBUS_WRAPPER:
1589                 reg = UFS_TEST_BUS_CTRL_2;
1590                 offset = 16;
1591                 break;
1592         case TSTBUS_COMBINED:
1593                 reg = UFS_TEST_BUS_CTRL_2;
1594                 offset = 8;
1595                 break;
1596         case TSTBUS_UTP_HCI:
1597                 reg = UFS_TEST_BUS_CTRL_2;
1598                 offset = 0;
1599                 break;
1600         case TSTBUS_UNIPRO:
1601                 reg = UFS_UNIPRO_CFG;
1602                 offset = 20;
1603                 mask = 0xFFF;
1604                 break;
1605         /*
1606          * No need for a default case, since
1607          * ufs_qcom_testbus_cfg_is_ok() checks that the configuration
1608          * is legal
1609          */
1610         }
1611         mask <<= offset;
1612
1613         pm_runtime_get_sync(host->hba->dev);
1614         ufshcd_hold(host->hba, false);
1615         ufshcd_rmwl(host->hba, TEST_BUS_SEL,
1616                     (u32)host->testbus.select_major << 19,
1617                     REG_UFS_CFG1);
1618         ufshcd_rmwl(host->hba, mask,
1619                     (u32)host->testbus.select_minor << offset,
1620                     reg);
1621         ufs_qcom_enable_test_bus(host);
1622         /*
1623          * Make sure the test bus configuration is
1624          * committed before returning.
1625          */
1626         mb();
1627         ufshcd_release(host->hba);
1628         pm_runtime_put_sync(host->hba->dev);
1629
1630         return 0;
1631 }
1632
1633 static void ufs_qcom_testbus_read(struct ufs_hba *hba)
1634 {
1635         ufshcd_dump_regs(hba, UFS_TEST_BUS, 4, "UFS_TEST_BUS ");
1636 }
1637
1638 static void ufs_qcom_print_unipro_testbus(struct ufs_hba *hba)
1639 {
1640         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1641         u32 *testbus = NULL;
1642         int i, nminor = 256, testbus_len = nminor * sizeof(u32);
1643
1644         testbus = kmalloc(testbus_len, GFP_KERNEL);
1645         if (!testbus)
1646                 return;
1647
1648         host->testbus.select_major = TSTBUS_UNIPRO;
1649         for (i = 0; i < nminor; i++) {
1650                 host->testbus.select_minor = i;
1651                 ufs_qcom_testbus_config(host);
1652                 testbus[i] = ufshcd_readl(hba, UFS_TEST_BUS);
1653         }
1654         print_hex_dump(KERN_ERR, "UNIPRO_TEST_BUS ", DUMP_PREFIX_OFFSET,
1655                         16, 4, testbus, testbus_len, false);
1656         kfree(testbus);
1657 }
1658
1659 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
1660 {
1661         ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4,
1662                          "HCI Vendor Specific Registers ");
1663
1664         /* sleep a bit intermittently as we are dumping too much data */
1665         ufs_qcom_print_hw_debug_reg_all(hba, NULL, ufs_qcom_dump_regs_wrapper);
1666         usleep_range(1000, 1100);
1667         ufs_qcom_testbus_read(hba);
1668         usleep_range(1000, 1100);
1669         ufs_qcom_print_unipro_testbus(hba);
1670         usleep_range(1000, 1100);
1671 }
1672
1673 /**
1674  * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1675  *
1676  * The variant operations configure the necessary controller and PHY
1677  * handshake during initialization.
1678  */
1679 static struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
1680         .name                   = "qcom",
1681         .init                   = ufs_qcom_init,
1682         .exit                   = ufs_qcom_exit,
1683         .get_ufs_hci_version    = ufs_qcom_get_ufs_hci_version,
1684         .clk_scale_notify       = ufs_qcom_clk_scale_notify,
1685         .setup_clocks           = ufs_qcom_setup_clocks,
1686         .hce_enable_notify      = ufs_qcom_hce_enable_notify,
1687         .link_startup_notify    = ufs_qcom_link_startup_notify,
1688         .pwr_change_notify      = ufs_qcom_pwr_change_notify,
1689         .apply_dev_quirks       = ufs_qcom_apply_dev_quirks,
1690         .suspend                = ufs_qcom_suspend,
1691         .resume                 = ufs_qcom_resume,
1692         .dbg_register_dump      = ufs_qcom_dump_dbg_regs,
1693 };
1694
1695 /**
1696  * ufs_qcom_probe - probe routine of the driver
1697  * @pdev: pointer to Platform device handle
1698  *
1699  * Return zero for success and non-zero for failure
1700  */
1701 static int ufs_qcom_probe(struct platform_device *pdev)
1702 {
1703         int err;
1704         struct device *dev = &pdev->dev;
1705
1706         /* Perform generic probe */
1707         err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops);
1708         if (err)
1709                 dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
1710
1711         return err;
1712 }
1713
1714 /**
1715  * ufs_qcom_remove - set driver_data of the device to NULL
1716  * @pdev: pointer to platform device handle
1717  *
1718  * Always returns 0
1719  */
1720 static int ufs_qcom_remove(struct platform_device *pdev)
1721 {
1722         struct ufs_hba *hba =  platform_get_drvdata(pdev);
1723
1724         pm_runtime_get_sync(&(pdev)->dev);
1725         ufshcd_remove(hba);
1726         return 0;
1727 }
1728
1729 static const struct of_device_id ufs_qcom_of_match[] = {
1730         { .compatible = "qcom,ufshc"},
1731         {},
1732 };
1733 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match);
1734
1735 static const struct dev_pm_ops ufs_qcom_pm_ops = {
1736         .suspend        = ufshcd_pltfrm_suspend,
1737         .resume         = ufshcd_pltfrm_resume,
1738         .runtime_suspend = ufshcd_pltfrm_runtime_suspend,
1739         .runtime_resume  = ufshcd_pltfrm_runtime_resume,
1740         .runtime_idle    = ufshcd_pltfrm_runtime_idle,
1741 };
1742
1743 static struct platform_driver ufs_qcom_pltform = {
1744         .probe  = ufs_qcom_probe,
1745         .remove = ufs_qcom_remove,
1746         .shutdown = ufshcd_pltfrm_shutdown,
1747         .driver = {
1748                 .name   = "ufshcd-qcom",
1749                 .pm     = &ufs_qcom_pm_ops,
1750                 .of_match_table = of_match_ptr(ufs_qcom_of_match),
1751         },
1752 };
1753 module_platform_driver(ufs_qcom_pltform);
1754
1755 MODULE_LICENSE("GPL v2");