drivers/scsi/ufs/ufs-qcom.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/acpi.h>
   7 #include <linux/time.h>
   8 #include <linux/of.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/phy/phy.h>
  11 #include <linux/gpio/consumer.h>
  12 #include <linux/reset-controller.h>
  13
  14 #include "ufshcd.h"
  15 #include "ufshcd-pltfrm.h"
  16 #include "unipro.h"
  17 #include "ufs-qcom.h"
  18 #include "ufshci.h"
  19 #include "ufs_quirks.h"
  20 #define UFS_QCOM_DEFAULT_DBG_PRINT_EN   \
  21         (UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
  22
  23 enum {
  24         TSTBUS_UAWM,
  25         TSTBUS_UARM,
  26         TSTBUS_TXUC,
  27         TSTBUS_RXUC,
  28         TSTBUS_DFC,
  29         TSTBUS_TRLUT,
  30         TSTBUS_TMRLUT,
  31         TSTBUS_OCSC,
  32         TSTBUS_UTP_HCI,
  33         TSTBUS_COMBINED,
  34         TSTBUS_WRAPPER,
  35         TSTBUS_UNIPRO,
  36         TSTBUS_MAX,
  37 };
  38
  39 static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS];
  40
  41 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote);
  42 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
  43 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
  44                                                        u32 clk_cycles);
  45
  46 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd)
  47 {
  48         return container_of(rcd, struct ufs_qcom_host, rcdev);
  49 }
  50
  51 static void ufs_qcom_dump_regs_wrapper(struct ufs_hba *hba, int offset, int len,
  52                                        const char *prefix, void *priv)
  53 {
  54         ufshcd_dump_regs(hba, offset, len * 4, prefix);
  55 }
  56
  57 static int ufs_qcom_get_connected_tx_lanes(struct ufs_hba *hba, u32 *tx_lanes)
  58 {
  59         int err = 0;
  60
  61         err = ufshcd_dme_get(hba,
  62                         UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), tx_lanes);
  63         if (err)
  64                 dev_err(hba->dev, "%s: couldn't read PA_CONNECTEDTXDATALANES %d\n",
  65                                 __func__, err);
  66
  67         return err;
  68 }
  69
  70 static int ufs_qcom_host_clk_get(struct device *dev,
  71                 const char *name, struct clk **clk_out, bool optional)
  72 {
  73         struct clk *clk;
  74         int err = 0;
  75
  76         clk = devm_clk_get(dev, name);
  77         if (!IS_ERR(clk)) {
  78                 *clk_out = clk;
  79                 return 0;
  80         }
  81
  82         err = PTR_ERR(clk);
  83
  84         if (optional && err == -ENOENT) {
  85                 *clk_out = NULL;
  86                 return 0;
  87         }
  88
  89         if (err != -EPROBE_DEFER)
  90                 dev_err(dev, "failed to get %s err %d\n", name, err);
  91
  92         return err;
  93 }
  94
  95 static int ufs_qcom_host_clk_enable(struct device *dev,
  96                 const char *name, struct clk *clk)
  97 {
  98         int err = 0;
  99
 100         err = clk_prepare_enable(clk);
 101         if (err)
 102                 dev_err(dev, "%s: %s enable failed %d\n", __func__, name, err);
 103
 104         return err;
 105 }
 106
 107 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
 108 {
 109         if (!host->is_lane_clks_enabled)
 110                 return;
 111
 112         clk_disable_unprepare(host->tx_l1_sync_clk);
 113         clk_disable_unprepare(host->tx_l0_sync_clk);
 114         clk_disable_unprepare(host->rx_l1_sync_clk);
 115         clk_disable_unprepare(host->rx_l0_sync_clk);
 116
 117         host->is_lane_clks_enabled = false;
 118 }
 119
 120 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
 121 {
 122         int err = 0;
 123         struct device *dev = host->hba->dev;
 124
 125         if (host->is_lane_clks_enabled)
 126                 return 0;
 127
 128         err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk",
 129                 host->rx_l0_sync_clk);
 130         if (err)
 131                 goto out;
 132
 133         err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk",
 134                 host->tx_l0_sync_clk);
 135         if (err)
 136                 goto disable_rx_l0;
 137
 138         err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk",
 139                         host->rx_l1_sync_clk);
 140         if (err)
 141                 goto disable_tx_l0;
 142
 143         err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk",
 144                         host->tx_l1_sync_clk);
 145         if (err)
 146                 goto disable_rx_l1;
 147
 148         host->is_lane_clks_enabled = true;
 149         goto out;
 150
 151 disable_rx_l1:
 152         clk_disable_unprepare(host->rx_l1_sync_clk);
 153 disable_tx_l0:
 154         clk_disable_unprepare(host->tx_l0_sync_clk);
 155 disable_rx_l0:
 156         clk_disable_unprepare(host->rx_l0_sync_clk);
 157 out:
 158         return err;
 159 }
 160
 161 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
 162 {
 163         int err = 0;
 164         struct device *dev = host->hba->dev;
 165
 166         if (has_acpi_companion(dev))
 167                 return 0;
 168
 169         err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk",
 170                                         &host->rx_l0_sync_clk, false);
 171         if (err)
 172                 goto out;
 173
 174         err = ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk",
 175                                         &host->tx_l0_sync_clk, false);
 176         if (err)
 177                 goto out;
 178
 179         /* In case of single lane per direction, don't read lane1 clocks */
 180         if (host->hba->lanes_per_direction > 1) {
 181                 err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk",
 182                         &host->rx_l1_sync_clk, false);
 183                 if (err)
 184                         goto out;
 185
 186                 err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk",
 187                         &host->tx_l1_sync_clk, true);
 188         }
 189 out:
 190         return err;
 191 }
 192
 193 static int ufs_qcom_link_startup_post_change(struct ufs_hba *hba)
 194 {
 195         u32 tx_lanes;
 196
 197         return ufs_qcom_get_connected_tx_lanes(hba, &tx_lanes);
 198 }
 199
 200 static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
 201 {
 202         int err;
 203         u32 tx_fsm_val = 0;
 204         unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
 205
 206         do {
 207                 err = ufshcd_dme_get(hba,
 208                                 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
 209                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
 210                                 &tx_fsm_val);
 211                 if (err || tx_fsm_val == TX_FSM_HIBERN8)
 212                         break;
 213
 214                 /* sleep for max. 200us */
 215                 usleep_range(100, 200);
 216         } while (time_before(jiffies, timeout));
 217
 218         /*
 219          * we might have scheduled out for long during polling so
 220          * check the state again.
 221          */
 222         if (time_after(jiffies, timeout))
 223                 err = ufshcd_dme_get(hba,
 224                                 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
 225                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
 226                                 &tx_fsm_val);
 227
 228         if (err) {
 229                 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
 230                                 __func__, err);
 231         } else if (tx_fsm_val != TX_FSM_HIBERN8) {
 232                 err = tx_fsm_val;
 233                 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
 234                                 __func__, err);
 235         }
 236
 237         return err;
 238 }
 239
 240 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
 241 {
 242         ufshcd_rmwl(host->hba, QUNIPRO_SEL,
 243                    ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0,
 244                    REG_UFS_CFG1);
 245         /* make sure above configuration is applied before we return */
 246         mb();
 247 }
 248
 249 /**
 250  * ufs_qcom_host_reset - reset host controller and PHY
 251  */
 252 static int ufs_qcom_host_reset(struct ufs_hba *hba)
 253 {
 254         int ret = 0;
 255         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 256
 257         if (!host->core_reset) {
 258                 dev_warn(hba->dev, "%s: reset control not set\n", __func__);
 259                 goto out;
 260         }
 261
 262         ret = reset_control_assert(host->core_reset);
 263         if (ret) {
 264                 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n",
 265                                  __func__, ret);
 266                 goto out;
 267         }
 268
 269         /*
 270          * The hardware requirement for delay between assert/deassert
 271          * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
 272          * ~125us (4/32768). To be on the safe side add 200us delay.
 273          */
 274         usleep_range(200, 210);
 275
 276         ret = reset_control_deassert(host->core_reset);
 277         if (ret)
 278                 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n",
 279                                  __func__, ret);
 280
 281         usleep_range(1000, 1100);
 282
 283 out:
 284         return ret;
 285 }
 286
 287 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
 288 {
 289         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 290         struct phy *phy = host->generic_phy;
 291         int ret = 0;
 292         bool is_rate_B = (UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B)
 293                                                         ? true : false;
 294
 295         /* Reset UFS Host Controller and PHY */
 296         ret = ufs_qcom_host_reset(hba);
 297         if (ret)
 298                 dev_warn(hba->dev, "%s: host reset returned %d\n",
 299                                   __func__, ret);
 300
 301         if (is_rate_B)
 302                 phy_set_mode(phy, PHY_MODE_UFS_HS_B);
 303
 304         /* phy initialization - calibrate the phy */
 305         ret = phy_init(phy);
 306         if (ret) {
 307                 dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
 308                         __func__, ret);
 309                 goto out;
 310         }
 311
 312         /* power on phy - start serdes and phy's power and clocks */
 313         ret = phy_power_on(phy);
 314         if (ret) {
 315                 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n",
 316                         __func__, ret);
 317                 goto out_disable_phy;
 318         }
 319
 320         ufs_qcom_select_unipro_mode(host);
 321
 322         return 0;
 323
 324 out_disable_phy:
 325         phy_exit(phy);
 326 out:
 327         return ret;
 328 }
 329
 330 /*
 331  * The UTP controller has a number of internal clock gating cells (CGCs).
 332  * Internal hardware sub-modules within the UTP controller control the CGCs.
 333  * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
 334  * in a specific operation, UTP controller CGCs are by default disabled and
 335  * this function enables them (after every UFS link startup) to save some power
 336  * leakage.
 337  */
 338 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
 339 {
 340         ufshcd_writel(hba,
 341                 ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL,
 342                 REG_UFS_CFG2);
 343
 344         /* Ensure that HW clock gating is enabled before next operations */
 345         mb();
 346 }
 347
 348 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
 349                                       enum ufs_notify_change_status status)
 350 {
 351         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 352         int err = 0;
 353
 354         switch (status) {
 355         case PRE_CHANGE:
 356                 ufs_qcom_power_up_sequence(hba);
 357                 /*
 358                  * The PHY PLL output is the source of tx/rx lane symbol
 359                  * clocks, hence, enable the lane clocks only after PHY
 360                  * is initialized.
 361                  */
 362                 err = ufs_qcom_enable_lane_clks(host);
 363                 break;
 364         case POST_CHANGE:
 365                 /* check if UFS PHY moved from DISABLED to HIBERN8 */
 366                 err = ufs_qcom_check_hibern8(hba);
 367                 ufs_qcom_enable_hw_clk_gating(hba);
 368
 369                 break;
 370         default:
 371                 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
 372                 err = -EINVAL;
 373                 break;
 374         }
 375         return err;
 376 }
 377
 378 /**
 379  * Returns zero for success and non-zero in case of a failure
 380  */
 381 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
 382                                u32 hs, u32 rate, bool update_link_startup_timer)
 383 {
 384         int ret = 0;
 385         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 386         struct ufs_clk_info *clki;
 387         u32 core_clk_period_in_ns;
 388         u32 tx_clk_cycles_per_us = 0;
 389         unsigned long core_clk_rate = 0;
 390         u32 core_clk_cycles_per_us = 0;
 391
 392         static u32 pwm_fr_table[][2] = {
 393                 {UFS_PWM_G1, 0x1},
 394                 {UFS_PWM_G2, 0x1},
 395                 {UFS_PWM_G3, 0x1},
 396                 {UFS_PWM_G4, 0x1},
 397         };
 398
 399         static u32 hs_fr_table_rA[][2] = {
 400                 {UFS_HS_G1, 0x1F},
 401                 {UFS_HS_G2, 0x3e},
 402                 {UFS_HS_G3, 0x7D},
 403         };
 404
 405         static u32 hs_fr_table_rB[][2] = {
 406                 {UFS_HS_G1, 0x24},
 407                 {UFS_HS_G2, 0x49},
 408                 {UFS_HS_G3, 0x92},
 409         };
 410
 411         /*
 412          * The Qunipro controller does not use following registers:
 413          * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG &
 414          * UFS_REG_PA_LINK_STARTUP_TIMER
 415          * But UTP controller uses SYS1CLK_1US_REG register for Interrupt
 416          * Aggregation logic.
 417         */
 418         if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba))
 419                 goto out;
 420
 421         if (gear == 0) {
 422                 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
 423                 goto out_error;
 424         }
 425
 426         list_for_each_entry(clki, &hba->clk_list_head, list) {
 427                 if (!strcmp(clki->name, "core_clk"))
 428                         core_clk_rate = clk_get_rate(clki->clk);
 429         }
 430
 431         /* If frequency is smaller than 1MHz, set to 1MHz */
 432         if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
 433                 core_clk_rate = DEFAULT_CLK_RATE_HZ;
 434
 435         core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
 436         if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
 437                 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
 438                 /*
 439                  * make sure above write gets applied before we return from
 440                  * this function.
 441                  */
 442                 mb();
 443         }
 444
 445         if (ufs_qcom_cap_qunipro(host))
 446                 goto out;
 447
 448         core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate;
 449         core_clk_period_in_ns <<= OFFSET_CLK_NS_REG;
 450         core_clk_period_in_ns &= MASK_CLK_NS_REG;
 451
 452         switch (hs) {
 453         case FASTAUTO_MODE:
 454         case FAST_MODE:
 455                 if (rate == PA_HS_MODE_A) {
 456                         if (gear > ARRAY_SIZE(hs_fr_table_rA)) {
 457                                 dev_err(hba->dev,
 458                                         "%s: index %d exceeds table size %zu\n",
 459                                         __func__, gear,
 460                                         ARRAY_SIZE(hs_fr_table_rA));
 461                                 goto out_error;
 462                         }
 463                         tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1];
 464                 } else if (rate == PA_HS_MODE_B) {
 465                         if (gear > ARRAY_SIZE(hs_fr_table_rB)) {
 466                                 dev_err(hba->dev,
 467                                         "%s: index %d exceeds table size %zu\n",
 468                                         __func__, gear,
 469                                         ARRAY_SIZE(hs_fr_table_rB));
 470                                 goto out_error;
 471                         }
 472                         tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1];
 473                 } else {
 474                         dev_err(hba->dev, "%s: invalid rate = %d\n",
 475                                 __func__, rate);
 476                         goto out_error;
 477                 }
 478                 break;
 479         case SLOWAUTO_MODE:
 480         case SLOW_MODE:
 481                 if (gear > ARRAY_SIZE(pwm_fr_table)) {
 482                         dev_err(hba->dev,
 483                                         "%s: index %d exceeds table size %zu\n",
 484                                         __func__, gear,
 485                                         ARRAY_SIZE(pwm_fr_table));
 486                         goto out_error;
 487                 }
 488                 tx_clk_cycles_per_us = pwm_fr_table[gear-1][1];
 489                 break;
 490         case UNCHANGED:
 491         default:
 492                 dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs);
 493                 goto out_error;
 494         }
 495
 496         if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) !=
 497             (core_clk_period_in_ns | tx_clk_cycles_per_us)) {
 498                 /* this register 2 fields shall be written at once */
 499                 ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us,
 500                               REG_UFS_TX_SYMBOL_CLK_NS_US);
 501                 /*
 502                  * make sure above write gets applied before we return from
 503                  * this function.
 504                  */
 505                 mb();
 506         }
 507
 508         if (update_link_startup_timer) {
 509                 ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100),
 510                               REG_UFS_PA_LINK_STARTUP_TIMER);
 511                 /*
 512                  * make sure that this configuration is applied before
 513                  * we return
 514                  */
 515                 mb();
 516         }
 517         goto out;
 518
 519 out_error:
 520         ret = -EINVAL;
 521 out:
 522         return ret;
 523 }
 524
 525 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
 526                                         enum ufs_notify_change_status status)
 527 {
 528         int err = 0;
 529         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 530
 531         switch (status) {
 532         case PRE_CHANGE:
 533                 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE,
 534                                         0, true)) {
 535                         dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
 536                                 __func__);
 537                         err = -EINVAL;
 538                         goto out;
 539                 }
 540
 541                 if (ufs_qcom_cap_qunipro(host))
 542                         /*
 543                          * set unipro core clock cycles to 150 & clear clock
 544                          * divider
 545                          */
 546                         err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba,
 547                                                                           150);
 548
 549                 /*
 550                  * Some UFS devices (and may be host) have issues if LCC is
 551                  * enabled. So we are setting PA_Local_TX_LCC_Enable to 0
 552                  * before link startup which will make sure that both host
 553                  * and device TX LCC are disabled once link startup is
 554                  * completed.
 555                  */
 556                 if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41)
 557                         err = ufshcd_dme_set(hba,
 558                                         UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE),
 559                                         0);
 560
 561                 break;
 562         case POST_CHANGE:
 563                 ufs_qcom_link_startup_post_change(hba);
 564                 break;
 565         default:
 566                 break;
 567         }
 568
 569 out:
 570         return err;
 571 }
 572
 573 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
 574 {
 575         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 576         struct phy *phy = host->generic_phy;
 577         int ret = 0;
 578
 579         if (ufs_qcom_is_link_off(hba)) {
 580                 /*
 581                  * Disable the tx/rx lane symbol clocks before PHY is
 582                  * powered down as the PLL source should be disabled
 583                  * after downstream clocks are disabled.
 584                  */
 585                 ufs_qcom_disable_lane_clks(host);
 586                 phy_power_off(phy);
 587
 588         } else if (!ufs_qcom_is_link_active(hba)) {
 589                 ufs_qcom_disable_lane_clks(host);
 590         }
 591
 592         return ret;
 593 }
 594
 595 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
 596 {
 597         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 598         struct phy *phy = host->generic_phy;
 599         int err;
 600
 601         if (ufs_qcom_is_link_off(hba)) {
 602                 err = phy_power_on(phy);
 603                 if (err) {
 604                         dev_err(hba->dev, "%s: failed PHY power on: %d\n",
 605                                 __func__, err);
 606                         return err;
 607                 }
 608
 609                 err = ufs_qcom_enable_lane_clks(host);
 610                 if (err)
 611                         return err;
 612
 613         } else if (!ufs_qcom_is_link_active(hba)) {
 614                 err = ufs_qcom_enable_lane_clks(host);
 615                 if (err)
 616                         return err;
 617         }
 618
 619         hba->is_sys_suspended = false;
 620         return 0;
 621 }
 622
 623 #ifdef CONFIG_MSM_BUS_SCALING
 624 static int ufs_qcom_get_bus_vote(struct ufs_qcom_host *host,
 625                 const char *speed_mode)
 626 {
 627         struct device *dev = host->hba->dev;
 628         struct device_node *np = dev->of_node;
 629         int err;
 630         const char *key = "qcom,bus-vector-names";
 631
 632         if (!speed_mode) {
 633                 err = -EINVAL;
 634                 goto out;
 635         }
 636
 637         if (host->bus_vote.is_max_bw_needed && !!strcmp(speed_mode, "MIN"))
 638                 err = of_property_match_string(np, key, "MAX");
 639         else
 640                 err = of_property_match_string(np, key, speed_mode);
 641
 642 out:
 643         if (err < 0)
 644                 dev_err(dev, "%s: Invalid %s mode %d\n",
 645                                 __func__, speed_mode, err);
 646         return err;
 647 }
 648
 649 static void ufs_qcom_get_speed_mode(struct ufs_pa_layer_attr *p, char *result)
 650 {
 651         int gear = max_t(u32, p->gear_rx, p->gear_tx);
 652         int lanes = max_t(u32, p->lane_rx, p->lane_tx);
 653         int pwr;
 654
 655         /* default to PWM Gear 1, Lane 1 if power mode is not initialized */
 656         if (!gear)
 657                 gear = 1;
 658
 659         if (!lanes)
 660                 lanes = 1;
 661
 662         if (!p->pwr_rx && !p->pwr_tx) {
 663                 pwr = SLOWAUTO_MODE;
 664                 snprintf(result, BUS_VECTOR_NAME_LEN, "MIN");
 665         } else if (p->pwr_rx == FAST_MODE || p->pwr_rx == FASTAUTO_MODE ||
 666                  p->pwr_tx == FAST_MODE || p->pwr_tx == FASTAUTO_MODE) {
 667                 pwr = FAST_MODE;
 668                 snprintf(result, BUS_VECTOR_NAME_LEN, "%s_R%s_G%d_L%d", "HS",
 669                          p->hs_rate == PA_HS_MODE_B ? "B" : "A", gear, lanes);
 670         } else {
 671                 pwr = SLOW_MODE;
 672                 snprintf(result, BUS_VECTOR_NAME_LEN, "%s_G%d_L%d",
 673                          "PWM", gear, lanes);
 674         }
 675 }
 676
 677 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote)
 678 {
 679         int err = 0;
 680
 681         if (vote != host->bus_vote.curr_vote) {
 682                 err = msm_bus_scale_client_update_request(
 683                                 host->bus_vote.client_handle, vote);
 684                 if (err) {
 685                         dev_err(host->hba->dev,
 686                                 "%s: msm_bus_scale_client_update_request() failed: bus_client_handle=0x%x, vote=%d, err=%d\n",
 687                                 __func__, host->bus_vote.client_handle,
 688                                 vote, err);
 689                         goto out;
 690                 }
 691
 692                 host->bus_vote.curr_vote = vote;
 693         }
 694 out:
 695         return err;
 696 }
 697
 698 static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host)
 699 {
 700         int vote;
 701         int err = 0;
 702         char mode[BUS_VECTOR_NAME_LEN];
 703
 704         ufs_qcom_get_speed_mode(&host->dev_req_params, mode);
 705
 706         vote = ufs_qcom_get_bus_vote(host, mode);
 707         if (vote >= 0)
 708                 err = ufs_qcom_set_bus_vote(host, vote);
 709         else
 710                 err = vote;
 711
 712         if (err)
 713                 dev_err(host->hba->dev, "%s: failed %d\n", __func__, err);
 714         else
 715                 host->bus_vote.saved_vote = vote;
 716         return err;
 717 }
 718
 719 static ssize_t
 720 show_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
 721                         char *buf)
 722 {
 723         struct ufs_hba *hba = dev_get_drvdata(dev);
 724         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 725
 726         return snprintf(buf, PAGE_SIZE, "%u\n",
 727                         host->bus_vote.is_max_bw_needed);
 728 }
 729
 730 static ssize_t
 731 store_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
 732                 const char *buf, size_t count)
 733 {
 734         struct ufs_hba *hba = dev_get_drvdata(dev);
 735         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 736         uint32_t value;
 737
 738         if (!kstrtou32(buf, 0, &value)) {
 739                 host->bus_vote.is_max_bw_needed = !!value;
 740                 ufs_qcom_update_bus_bw_vote(host);
 741         }
 742
 743         return count;
 744 }
 745
 746 static int ufs_qcom_bus_register(struct ufs_qcom_host *host)
 747 {
 748         int err;
 749         struct msm_bus_scale_pdata *bus_pdata;
 750         struct device *dev = host->hba->dev;
 751         struct platform_device *pdev = to_platform_device(dev);
 752         struct device_node *np = dev->of_node;
 753
 754         bus_pdata = msm_bus_cl_get_pdata(pdev);
 755         if (!bus_pdata) {
 756                 dev_err(dev, "%s: failed to get bus vectors\n", __func__);
 757                 err = -ENODATA;
 758                 goto out;
 759         }
 760
 761         err = of_property_count_strings(np, "qcom,bus-vector-names");
 762         if (err < 0 || err != bus_pdata->num_usecases) {
 763                 dev_err(dev, "%s: qcom,bus-vector-names not specified correctly %d\n",
 764                                 __func__, err);
 765                 goto out;
 766         }
 767
 768         host->bus_vote.client_handle = msm_bus_scale_register_client(bus_pdata);
 769         if (!host->bus_vote.client_handle) {
 770                 dev_err(dev, "%s: msm_bus_scale_register_client failed\n",
 771                                 __func__);
 772                 err = -EFAULT;
 773                 goto out;
 774         }
 775
 776         /* cache the vote index for minimum and maximum bandwidth */
 777         host->bus_vote.min_bw_vote = ufs_qcom_get_bus_vote(host, "MIN");
 778         host->bus_vote.max_bw_vote = ufs_qcom_get_bus_vote(host, "MAX");
 779
 780         host->bus_vote.max_bus_bw.show = show_ufs_to_mem_max_bus_bw;
 781         host->bus_vote.max_bus_bw.store = store_ufs_to_mem_max_bus_bw;
 782         sysfs_attr_init(&host->bus_vote.max_bus_bw.attr);
 783         host->bus_vote.max_bus_bw.attr.name = "max_bus_bw";
 784         host->bus_vote.max_bus_bw.attr.mode = S_IRUGO | S_IWUSR;
 785         err = device_create_file(dev, &host->bus_vote.max_bus_bw);
 786 out:
 787         return err;
 788 }
 789 #else /* CONFIG_MSM_BUS_SCALING */
 790 static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host)
 791 {
 792         return 0;
 793 }
 794
 795 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote)
 796 {
 797         return 0;
 798 }
 799
 800 static int ufs_qcom_bus_register(struct ufs_qcom_host *host)
 801 {
 802         return 0;
 803 }
 804 #endif /* CONFIG_MSM_BUS_SCALING */
 805
 806 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
 807 {
 808         if (host->dev_ref_clk_ctrl_mmio &&
 809             (enable ^ host->is_dev_ref_clk_enabled)) {
 810                 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
 811
 812                 if (enable)
 813                         temp |= host->dev_ref_clk_en_mask;
 814                 else
 815                         temp &= ~host->dev_ref_clk_en_mask;
 816
 817                 /*
 818                  * If we are here to disable this clock it might be immediately
 819                  * after entering into hibern8 in which case we need to make
 820                  * sure that device ref_clk is active at least 1us after the
 821                  * hibern8 enter.
 822                  */
 823                 if (!enable)
 824                         udelay(1);
 825
 826                 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
 827
 828                 /* ensure that ref_clk is enabled/disabled before we return */
 829                 wmb();
 830
 831                 /*
 832                  * If we call hibern8 exit after this, we need to make sure that
 833                  * device ref_clk is stable for at least 1us before the hibern8
 834                  * exit command.
 835                  */
 836                 if (enable)
 837                         udelay(1);
 838
 839                 host->is_dev_ref_clk_enabled = enable;
 840         }
 841 }
 842
 843 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
 844                                 enum ufs_notify_change_status status,
 845                                 struct ufs_pa_layer_attr *dev_max_params,
 846                                 struct ufs_pa_layer_attr *dev_req_params)
 847 {
 848         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 849         struct ufs_dev_params ufs_qcom_cap;
 850         int ret = 0;
 851
 852         if (!dev_req_params) {
 853                 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
 854                 ret = -EINVAL;
 855                 goto out;
 856         }
 857
 858         switch (status) {
 859         case PRE_CHANGE:
 860                 ufs_qcom_cap.tx_lanes = UFS_QCOM_LIMIT_NUM_LANES_TX;
 861                 ufs_qcom_cap.rx_lanes = UFS_QCOM_LIMIT_NUM_LANES_RX;
 862                 ufs_qcom_cap.hs_rx_gear = UFS_QCOM_LIMIT_HSGEAR_RX;
 863                 ufs_qcom_cap.hs_tx_gear = UFS_QCOM_LIMIT_HSGEAR_TX;
 864                 ufs_qcom_cap.pwm_rx_gear = UFS_QCOM_LIMIT_PWMGEAR_RX;
 865                 ufs_qcom_cap.pwm_tx_gear = UFS_QCOM_LIMIT_PWMGEAR_TX;
 866                 ufs_qcom_cap.rx_pwr_pwm = UFS_QCOM_LIMIT_RX_PWR_PWM;
 867                 ufs_qcom_cap.tx_pwr_pwm = UFS_QCOM_LIMIT_TX_PWR_PWM;
 868                 ufs_qcom_cap.rx_pwr_hs = UFS_QCOM_LIMIT_RX_PWR_HS;
 869                 ufs_qcom_cap.tx_pwr_hs = UFS_QCOM_LIMIT_TX_PWR_HS;
 870                 ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
 871                 ufs_qcom_cap.desired_working_mode =
 872                                         UFS_QCOM_LIMIT_DESIRED_MODE;
 873
 874                 if (host->hw_ver.major == 0x1) {
 875                         /*
 876                          * HS-G3 operations may not reliably work on legacy QCOM
 877                          * UFS host controller hardware even though capability
 878                          * exchange during link startup phase may end up
 879                          * negotiating maximum supported gear as G3.
 880                          * Hence downgrade the maximum supported gear to HS-G2.
 881                          */
 882                         if (ufs_qcom_cap.hs_tx_gear > UFS_HS_G2)
 883                                 ufs_qcom_cap.hs_tx_gear = UFS_HS_G2;
 884                         if (ufs_qcom_cap.hs_rx_gear > UFS_HS_G2)
 885                                 ufs_qcom_cap.hs_rx_gear = UFS_HS_G2;
 886                 }
 887
 888                 ret = ufshcd_get_pwr_dev_param(&ufs_qcom_cap,
 889                                                dev_max_params,
 890                                                dev_req_params);
 891                 if (ret) {
 892                         pr_err("%s: failed to determine capabilities\n",
 893                                         __func__);
 894                         goto out;
 895                 }
 896
 897                 /* enable the device ref clock before changing to HS mode */
 898                 if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
 899                         ufshcd_is_hs_mode(dev_req_params))
 900                         ufs_qcom_dev_ref_clk_ctrl(host, true);
 901                 break;
 902         case POST_CHANGE:
 903                 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
 904                                         dev_req_params->pwr_rx,
 905                                         dev_req_params->hs_rate, false)) {
 906                         dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
 907                                 __func__);
 908                         /*
 909                          * we return error code at the end of the routine,
 910                          * but continue to configure UFS_PHY_TX_LANE_ENABLE
 911                          * and bus voting as usual
 912                          */
 913                         ret = -EINVAL;
 914                 }
 915
 916                 /* cache the power mode parameters to use internally */
 917                 memcpy(&host->dev_req_params,
 918                                 dev_req_params, sizeof(*dev_req_params));
 919                 ufs_qcom_update_bus_bw_vote(host);
 920
 921                 /* disable the device ref clock if entered PWM mode */
 922                 if (ufshcd_is_hs_mode(&hba->pwr_info) &&
 923                         !ufshcd_is_hs_mode(dev_req_params))
 924                         ufs_qcom_dev_ref_clk_ctrl(host, false);
 925                 break;
 926         default:
 927                 ret = -EINVAL;
 928                 break;
 929         }
 930 out:
 931         return ret;
 932 }
 933
 934 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba)
 935 {
 936         int err;
 937         u32 pa_vs_config_reg1;
 938
 939         err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
 940                              &pa_vs_config_reg1);
 941         if (err)
 942                 goto out;
 943
 944         /* Allow extension of MSB bits of PA_SaveConfigTime attribute */
 945         err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
 946                             (pa_vs_config_reg1 | (1 << 12)));
 947
 948 out:
 949         return err;
 950 }
 951
 952 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba)
 953 {
 954         int err = 0;
 955
 956         if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME)
 957                 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba);
 958
 959         return err;
 960 }
 961
 962 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba)
 963 {
 964         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 965
 966         if (host->hw_ver.major == 0x1)
 967                 return UFSHCI_VERSION_11;
 968         else
 969                 return UFSHCI_VERSION_20;
 970 }
 971
 972 /**
 973  * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
 974  * @hba: host controller instance
 975  *
 976  * QCOM UFS host controller might have some non standard behaviours (quirks)
 977  * than what is specified by UFSHCI specification. Advertise all such
 978  * quirks to standard UFS host controller driver so standard takes them into
 979  * account.
 980  */
 981 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
 982 {
 983         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 984
 985         if (host->hw_ver.major == 0x01) {
 986                 hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
 987                             | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP
 988                             | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE;
 989
 990                 if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001)
 991                         hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR;
 992
 993                 hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC;
 994         }
 995
 996         if (host->hw_ver.major == 0x2) {
 997                 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
 998
 999                 if (!ufs_qcom_cap_qunipro(host))
1000                         /* Legacy UniPro mode still need following quirks */
1001                         hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
1002                                 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE
1003                                 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP);
1004         }
1005 }
1006
1007 static void ufs_qcom_set_caps(struct ufs_hba *hba)
1008 {
1009         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1010
1011         hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
1012         hba->caps |= UFSHCD_CAP_CLK_SCALING;
1013         hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
1014
1015         if (host->hw_ver.major >= 0x2) {
1016                 host->caps = UFS_QCOM_CAP_QUNIPRO |
1017                              UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE;
1018         }
1019 }
1020
1021 /**
1022  * ufs_qcom_setup_clocks - enables/disable clocks
1023  * @hba: host controller instance
1024  * @on: If true, enable clocks else disable them.
1025  * @status: PRE_CHANGE or POST_CHANGE notify
1026  *
1027  * Returns 0 on success, non-zero on failure.
1028  */
1029 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
1030                                  enum ufs_notify_change_status status)
1031 {
1032         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1033         int err;
1034         int vote = 0;
1035
1036         /*
1037          * In case ufs_qcom_init() is not yet done, simply ignore.
1038          * This ufs_qcom_setup_clocks() shall be called from
1039          * ufs_qcom_init() after init is done.
1040          */
1041         if (!host)
1042                 return 0;
1043
1044         if (on && (status == POST_CHANGE)) {
1045                 /* enable the device ref clock for HS mode*/
1046                 if (ufshcd_is_hs_mode(&hba->pwr_info))
1047                         ufs_qcom_dev_ref_clk_ctrl(host, true);
1048                 vote = host->bus_vote.saved_vote;
1049                 if (vote == host->bus_vote.min_bw_vote)
1050                         ufs_qcom_update_bus_bw_vote(host);
1051
1052         } else if (!on && (status == PRE_CHANGE)) {
1053                 if (!ufs_qcom_is_link_active(hba)) {
1054                         /* disable device ref_clk */
1055                         ufs_qcom_dev_ref_clk_ctrl(host, false);
1056                 }
1057
1058                 vote = host->bus_vote.min_bw_vote;
1059         }
1060
1061         err = ufs_qcom_set_bus_vote(host, vote);
1062         if (err)
1063                 dev_err(hba->dev, "%s: set bus vote failed %d\n",
1064                                 __func__, err);
1065
1066         return err;
1067 }
1068
1069 static int
1070 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
1071 {
1072         struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
1073
1074         /* Currently this code only knows about a single reset. */
1075         WARN_ON(id);
1076         ufs_qcom_assert_reset(host->hba);
1077         /* provide 1ms delay to let the reset pulse propagate. */
1078         usleep_range(1000, 1100);
1079         return 0;
1080 }
1081
1082 static int
1083 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
1084 {
1085         struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
1086
1087         /* Currently this code only knows about a single reset. */
1088         WARN_ON(id);
1089         ufs_qcom_deassert_reset(host->hba);
1090
1091         /*
1092          * after reset deassertion, phy will need all ref clocks,
1093          * voltage, current to settle down before starting serdes.
1094          */
1095         usleep_range(1000, 1100);
1096         return 0;
1097 }
1098
1099 static const struct reset_control_ops ufs_qcom_reset_ops = {
1100         .assert = ufs_qcom_reset_assert,
1101         .deassert = ufs_qcom_reset_deassert,
1102 };
1103
1104 #define ANDROID_BOOT_DEV_MAX    30
1105 static char android_boot_dev[ANDROID_BOOT_DEV_MAX];
1106
1107 #ifndef MODULE
1108 static int __init get_android_boot_dev(char *str)
1109 {
1110         strlcpy(android_boot_dev, str, ANDROID_BOOT_DEV_MAX);
1111         return 1;
1112 }
1113 __setup("androidboot.bootdevice=", get_android_boot_dev);
1114 #endif
1115
1116 /**
1117  * ufs_qcom_init - bind phy with controller
1118  * @hba: host controller instance
1119  *
1120  * Binds PHY with controller and powers up PHY enabling clocks
1121  * and regulators.
1122  *
1123  * Returns -EPROBE_DEFER if binding fails, returns negative error
1124  * on phy power up failure and returns zero on success.
1125  */
1126 static int ufs_qcom_init(struct ufs_hba *hba)
1127 {
1128         int err;
1129         struct device *dev = hba->dev;
1130         struct platform_device *pdev = to_platform_device(dev);
1131         struct ufs_qcom_host *host;
1132         struct resource *res;
1133
1134         if (strlen(android_boot_dev) && strcmp(android_boot_dev, dev_name(dev)))
1135                 return -ENODEV;
1136
1137         host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
1138         if (!host) {
1139                 err = -ENOMEM;
1140                 dev_err(dev, "%s: no memory for qcom ufs host\n", __func__);
1141                 goto out;
1142         }
1143
1144         /* Make a two way bind between the qcom host and the hba */
1145         host->hba = hba;
1146         ufshcd_set_variant(hba, host);
1147
1148         /* Setup the reset control of HCI */
1149         host->core_reset = devm_reset_control_get(hba->dev, "rst");
1150         if (IS_ERR(host->core_reset)) {
1151                 err = PTR_ERR(host->core_reset);
1152                 dev_warn(dev, "Failed to get reset control %d\n", err);
1153                 host->core_reset = NULL;
1154                 err = 0;
1155         }
1156
1157         /* Fire up the reset controller. Failure here is non-fatal. */
1158         host->rcdev.of_node = dev->of_node;
1159         host->rcdev.ops = &ufs_qcom_reset_ops;
1160         host->rcdev.owner = dev->driver->owner;
1161         host->rcdev.nr_resets = 1;
1162         err = devm_reset_controller_register(dev, &host->rcdev);
1163         if (err) {
1164                 dev_warn(dev, "Failed to register reset controller\n");
1165                 err = 0;
1166         }
1167
1168         /*
1169          * voting/devoting device ref_clk source is time consuming hence
1170          * skip devoting it during aggressive clock gating. This clock
1171          * will still be gated off during runtime suspend.
1172          */
1173         host->generic_phy = devm_phy_get(dev, "ufsphy");
1174
1175         if (host->generic_phy == ERR_PTR(-EPROBE_DEFER)) {
1176                 /*
1177                  * UFS driver might be probed before the phy driver does.
1178                  * In that case we would like to return EPROBE_DEFER code.
1179                  */
1180                 err = -EPROBE_DEFER;
1181                 dev_warn(dev, "%s: required phy device. hasn't probed yet. err = %d\n",
1182                         __func__, err);
1183                 goto out_variant_clear;
1184         } else if (IS_ERR(host->generic_phy)) {
1185                 if (has_acpi_companion(dev)) {
1186                         host->generic_phy = NULL;
1187                 } else {
1188                         err = PTR_ERR(host->generic_phy);
1189                         dev_err(dev, "%s: PHY get failed %d\n", __func__, err);
1190                         goto out_variant_clear;
1191                 }
1192         }
1193
1194         host->device_reset = devm_gpiod_get_optional(dev, "reset",
1195                                                      GPIOD_OUT_HIGH);
1196         if (IS_ERR(host->device_reset)) {
1197                 err = PTR_ERR(host->device_reset);
1198                 if (err != -EPROBE_DEFER)
1199                         dev_err(dev, "failed to acquire reset gpio: %d\n", err);
1200                 goto out_variant_clear;
1201         }
1202
1203         err = ufs_qcom_bus_register(host);
1204         if (err)
1205                 goto out_variant_clear;
1206
1207         ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
1208                 &host->hw_ver.minor, &host->hw_ver.step);
1209
1210         /*
1211          * for newer controllers, device reference clock control bit has
1212          * moved inside UFS controller register address space itself.
1213          */
1214         if (host->hw_ver.major >= 0x02) {
1215                 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;
1216                 host->dev_ref_clk_en_mask = BIT(26);
1217         } else {
1218                 /* "dev_ref_clk_ctrl_mem" is optional resource */
1219                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1220                 if (res) {
1221                         host->dev_ref_clk_ctrl_mmio =
1222                                         devm_ioremap_resource(dev, res);
1223                         if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) {
1224                                 dev_warn(dev,
1225                                         "%s: could not map dev_ref_clk_ctrl_mmio, err %ld\n",
1226                                         __func__,
1227                                         PTR_ERR(host->dev_ref_clk_ctrl_mmio));
1228                                 host->dev_ref_clk_ctrl_mmio = NULL;
1229                         }
1230                         host->dev_ref_clk_en_mask = BIT(5);
1231                 }
1232         }
1233
1234         err = ufs_qcom_init_lane_clks(host);
1235         if (err)
1236                 goto out_variant_clear;
1237
1238         ufs_qcom_set_caps(hba);
1239         ufs_qcom_advertise_quirks(hba);
1240
1241         ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
1242
1243         if (hba->dev->id < MAX_UFS_QCOM_HOSTS)
1244                 ufs_qcom_hosts[hba->dev->id] = host;
1245
1246         host->dbg_print_en |= UFS_QCOM_DEFAULT_DBG_PRINT_EN;
1247         ufs_qcom_get_default_testbus_cfg(host);
1248         err = ufs_qcom_testbus_config(host);
1249         if (err) {
1250                 dev_warn(dev, "%s: failed to configure the testbus %d\n",
1251                                 __func__, err);
1252                 err = 0;
1253         }
1254
1255         goto out;
1256
1257 out_variant_clear:
1258         ufshcd_set_variant(hba, NULL);
1259 out:
1260         return err;
1261 }
1262
1263 static void ufs_qcom_exit(struct ufs_hba *hba)
1264 {
1265         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1266
1267         ufs_qcom_disable_lane_clks(host);
1268         phy_power_off(host->generic_phy);
1269         phy_exit(host->generic_phy);
1270 }
1271
1272 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
1273                                                        u32 clk_cycles)
1274 {
1275         int err;
1276         u32 core_clk_ctrl_reg;
1277
1278         if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK)
1279                 return -EINVAL;
1280
1281         err = ufshcd_dme_get(hba,
1282                             UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1283                             &core_clk_ctrl_reg);
1284         if (err)
1285                 goto out;
1286
1287         core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK;
1288         core_clk_ctrl_reg |= clk_cycles;
1289
1290         /* Clear CORE_CLK_DIV_EN */
1291         core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1292
1293         err = ufshcd_dme_set(hba,
1294                             UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1295                             core_clk_ctrl_reg);
1296 out:
1297         return err;
1298 }
1299
1300 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)
1301 {
1302         /* nothing to do as of now */
1303         return 0;
1304 }
1305
1306 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)
1307 {
1308         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1309
1310         if (!ufs_qcom_cap_qunipro(host))
1311                 return 0;
1312
1313         /* set unipro core clock cycles to 150 and clear clock divider */
1314         return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150);
1315 }
1316
1317 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
1318 {
1319         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1320         int err;
1321         u32 core_clk_ctrl_reg;
1322
1323         if (!ufs_qcom_cap_qunipro(host))
1324                 return 0;
1325
1326         err = ufshcd_dme_get(hba,
1327                             UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1328                             &core_clk_ctrl_reg);
1329
1330         /* make sure CORE_CLK_DIV_EN is cleared */
1331         if (!err &&
1332             (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) {
1333                 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1334                 err = ufshcd_dme_set(hba,
1335                                     UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1336                                     core_clk_ctrl_reg);
1337         }
1338
1339         return err;
1340 }
1341
1342 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba)
1343 {
1344         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1345
1346         if (!ufs_qcom_cap_qunipro(host))
1347                 return 0;
1348
1349         /* set unipro core clock cycles to 75 and clear clock divider */
1350         return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75);
1351 }
1352
1353 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
1354                 bool scale_up, enum ufs_notify_change_status status)
1355 {
1356         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1357         struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params;
1358         int err = 0;
1359
1360         if (status == PRE_CHANGE) {
1361                 if (scale_up)
1362                         err = ufs_qcom_clk_scale_up_pre_change(hba);
1363                 else
1364                         err = ufs_qcom_clk_scale_down_pre_change(hba);
1365         } else {
1366                 if (scale_up)
1367                         err = ufs_qcom_clk_scale_up_post_change(hba);
1368                 else
1369                         err = ufs_qcom_clk_scale_down_post_change(hba);
1370
1371                 if (err || !dev_req_params)
1372                         goto out;
1373
1374                 ufs_qcom_cfg_timers(hba,
1375                                     dev_req_params->gear_rx,
1376                                     dev_req_params->pwr_rx,
1377                                     dev_req_params->hs_rate,
1378                                     false);
1379                 ufs_qcom_update_bus_bw_vote(host);
1380         }
1381
1382 out:
1383         return err;
1384 }
1385
1386 static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba,
1387                 void *priv, void (*print_fn)(struct ufs_hba *hba,
1388                 int offset, int num_regs, const char *str, void *priv))
1389 {
1390         u32 reg;
1391         struct ufs_qcom_host *host;
1392
1393         if (unlikely(!hba)) {
1394                 pr_err("%s: hba is NULL\n", __func__);
1395                 return;
1396         }
1397         if (unlikely(!print_fn)) {
1398                 dev_err(hba->dev, "%s: print_fn is NULL\n", __func__);
1399                 return;
1400         }
1401
1402         host = ufshcd_get_variant(hba);
1403         if (!(host->dbg_print_en & UFS_QCOM_DBG_PRINT_REGS_EN))
1404                 return;
1405
1406         reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
1407         print_fn(hba, reg, 44, "UFS_UFS_DBG_RD_REG_OCSC ", priv);
1408
1409         reg = ufshcd_readl(hba, REG_UFS_CFG1);
1410         reg |= UTP_DBG_RAMS_EN;
1411         ufshcd_writel(hba, reg, REG_UFS_CFG1);
1412
1413         reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
1414         print_fn(hba, reg, 32, "UFS_UFS_DBG_RD_EDTL_RAM ", priv);
1415
1416         reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
1417         print_fn(hba, reg, 128, "UFS_UFS_DBG_RD_DESC_RAM ", priv);
1418
1419         reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
1420         print_fn(hba, reg, 64, "UFS_UFS_DBG_RD_PRDT_RAM ", priv);
1421
1422         /* clear bit 17 - UTP_DBG_RAMS_EN */
1423         ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1);
1424
1425         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1426         print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UAWM ", priv);
1427
1428         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
1429         print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UARM ", priv);
1430
1431         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1432         print_fn(hba, reg, 48, "UFS_DBG_RD_REG_TXUC ", priv);
1433
1434         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1435         print_fn(hba, reg, 27, "UFS_DBG_RD_REG_RXUC ", priv);
1436
1437         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1438         print_fn(hba, reg, 19, "UFS_DBG_RD_REG_DFC ", priv);
1439
1440         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1441         print_fn(hba, reg, 34, "UFS_DBG_RD_REG_TRLUT ", priv);
1442
1443         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1444         print_fn(hba, reg, 9, "UFS_DBG_RD_REG_TMRLUT ", priv);
1445 }
1446
1447 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
1448 {
1449         if (host->dbg_print_en & UFS_QCOM_DBG_PRINT_TEST_BUS_EN) {
1450                 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,
1451                                 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1);
1452                 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1453         } else {
1454                 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 0, REG_UFS_CFG1);
1455                 ufshcd_rmwl(host->hba, TEST_BUS_EN, 0, REG_UFS_CFG1);
1456         }
1457 }
1458
1459 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
1460 {
1461         /* provide a legal default configuration */
1462         host->testbus.select_major = TSTBUS_UNIPRO;
1463         host->testbus.select_minor = 37;
1464 }
1465
1466 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host)
1467 {
1468         if (host->testbus.select_major >= TSTBUS_MAX) {
1469                 dev_err(host->hba->dev,
1470                         "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n",
1471                         __func__, host->testbus.select_major);
1472                 return false;
1473         }
1474
1475         return true;
1476 }
1477
1478 int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
1479 {
1480         int reg;
1481         int offset;
1482         u32 mask = TEST_BUS_SUB_SEL_MASK;
1483
1484         if (!host)
1485                 return -EINVAL;
1486
1487         if (!ufs_qcom_testbus_cfg_is_ok(host))
1488                 return -EPERM;
1489
1490         switch (host->testbus.select_major) {
1491         case TSTBUS_UAWM:
1492                 reg = UFS_TEST_BUS_CTRL_0;
1493                 offset = 24;
1494                 break;
1495         case TSTBUS_UARM:
1496                 reg = UFS_TEST_BUS_CTRL_0;
1497                 offset = 16;
1498                 break;
1499         case TSTBUS_TXUC:
1500                 reg = UFS_TEST_BUS_CTRL_0;
1501                 offset = 8;
1502                 break;
1503         case TSTBUS_RXUC:
1504                 reg = UFS_TEST_BUS_CTRL_0;
1505                 offset = 0;
1506                 break;
1507         case TSTBUS_DFC:
1508                 reg = UFS_TEST_BUS_CTRL_1;
1509                 offset = 24;
1510                 break;
1511         case TSTBUS_TRLUT:
1512                 reg = UFS_TEST_BUS_CTRL_1;
1513                 offset = 16;
1514                 break;
1515         case TSTBUS_TMRLUT:
1516                 reg = UFS_TEST_BUS_CTRL_1;
1517                 offset = 8;
1518                 break;
1519         case TSTBUS_OCSC:
1520                 reg = UFS_TEST_BUS_CTRL_1;
1521                 offset = 0;
1522                 break;
1523         case TSTBUS_WRAPPER:
1524                 reg = UFS_TEST_BUS_CTRL_2;
1525                 offset = 16;
1526                 break;
1527         case TSTBUS_COMBINED:
1528                 reg = UFS_TEST_BUS_CTRL_2;
1529                 offset = 8;
1530                 break;
1531         case TSTBUS_UTP_HCI:
1532                 reg = UFS_TEST_BUS_CTRL_2;
1533                 offset = 0;
1534                 break;
1535         case TSTBUS_UNIPRO:
1536                 reg = UFS_UNIPRO_CFG;
1537                 offset = 20;
1538                 mask = 0xFFF;
1539                 break;
1540         /*
1541          * No need for a default case, since
1542          * ufs_qcom_testbus_cfg_is_ok() checks that the configuration
1543          * is legal
1544          */
1545         }
1546         mask <<= offset;
1547
1548         pm_runtime_get_sync(host->hba->dev);
1549         ufshcd_hold(host->hba, false);
1550         ufshcd_rmwl(host->hba, TEST_BUS_SEL,
1551                     (u32)host->testbus.select_major << 19,
1552                     REG_UFS_CFG1);
1553         ufshcd_rmwl(host->hba, mask,
1554                     (u32)host->testbus.select_minor << offset,
1555                     reg);
1556         ufs_qcom_enable_test_bus(host);
1557         /*
1558          * Make sure the test bus configuration is
1559          * committed before returning.
1560          */
1561         mb();
1562         ufshcd_release(host->hba);
1563         pm_runtime_put_sync(host->hba->dev);
1564
1565         return 0;
1566 }
1567
1568 static void ufs_qcom_testbus_read(struct ufs_hba *hba)
1569 {
1570         ufshcd_dump_regs(hba, UFS_TEST_BUS, 4, "UFS_TEST_BUS ");
1571 }
1572
1573 static void ufs_qcom_print_unipro_testbus(struct ufs_hba *hba)
1574 {
1575         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1576         u32 *testbus = NULL;
1577         int i, nminor = 256, testbus_len = nminor * sizeof(u32);
1578
1579         testbus = kmalloc(testbus_len, GFP_KERNEL);
1580         if (!testbus)
1581                 return;
1582
1583         host->testbus.select_major = TSTBUS_UNIPRO;
1584         for (i = 0; i < nminor; i++) {
1585                 host->testbus.select_minor = i;
1586                 ufs_qcom_testbus_config(host);
1587                 testbus[i] = ufshcd_readl(hba, UFS_TEST_BUS);
1588         }
1589         print_hex_dump(KERN_ERR, "UNIPRO_TEST_BUS ", DUMP_PREFIX_OFFSET,
1590                         16, 4, testbus, testbus_len, false);
1591         kfree(testbus);
1592 }
1593
1594 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
1595 {
1596         ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4,
1597                          "HCI Vendor Specific Registers ");
1598
1599         /* sleep a bit intermittently as we are dumping too much data */
1600         ufs_qcom_print_hw_debug_reg_all(hba, NULL, ufs_qcom_dump_regs_wrapper);
1601         usleep_range(1000, 1100);
1602         ufs_qcom_testbus_read(hba);
1603         usleep_range(1000, 1100);
1604         ufs_qcom_print_unipro_testbus(hba);
1605         usleep_range(1000, 1100);
1606 }
1607
1608 /**
1609  * ufs_qcom_device_reset() - toggle the (optional) device reset line
1610  * @hba: per-adapter instance
1611  *
1612  * Toggles the (optional) reset line to reset the attached device.
1613  */
1614 static void ufs_qcom_device_reset(struct ufs_hba *hba)
1615 {
1616         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1617
1618         /* reset gpio is optional */
1619         if (!host->device_reset)
1620                 return;
1621
1622         /*
1623          * The UFS device shall detect reset pulses of 1us, sleep for 10us to
1624          * be on the safe side.
1625          */
1626         gpiod_set_value_cansleep(host->device_reset, 1);
1627         usleep_range(10, 15);
1628
1629         gpiod_set_value_cansleep(host->device_reset, 0);
1630         usleep_range(10, 15);
1631 }
1632
1633 /**
1634  * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1635  *
1636  * The variant operations configure the necessary controller and PHY
1637  * handshake during initialization.
1638  */
1639 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
1640         .name                   = "qcom",
1641         .init                   = ufs_qcom_init,
1642         .exit                   = ufs_qcom_exit,
1643         .get_ufs_hci_version    = ufs_qcom_get_ufs_hci_version,
1644         .clk_scale_notify       = ufs_qcom_clk_scale_notify,
1645         .setup_clocks           = ufs_qcom_setup_clocks,
1646         .hce_enable_notify      = ufs_qcom_hce_enable_notify,
1647         .link_startup_notify    = ufs_qcom_link_startup_notify,
1648         .pwr_change_notify      = ufs_qcom_pwr_change_notify,
1649         .apply_dev_quirks       = ufs_qcom_apply_dev_quirks,
1650         .suspend                = ufs_qcom_suspend,
1651         .resume                 = ufs_qcom_resume,
1652         .dbg_register_dump      = ufs_qcom_dump_dbg_regs,
1653         .device_reset           = ufs_qcom_device_reset,
1654 };
1655
1656 /**
1657  * ufs_qcom_probe - probe routine of the driver
1658  * @pdev: pointer to Platform device handle
1659  *
1660  * Return zero for success and non-zero for failure
1661  */
1662 static int ufs_qcom_probe(struct platform_device *pdev)
1663 {
1664         int err;
1665         struct device *dev = &pdev->dev;
1666
1667         /* Perform generic probe */
1668         err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops);
1669         if (err)
1670                 dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
1671
1672         return err;
1673 }
1674
1675 /**
1676  * ufs_qcom_remove - set driver_data of the device to NULL
1677  * @pdev: pointer to platform device handle
1678  *
1679  * Always returns 0
1680  */
1681 static int ufs_qcom_remove(struct platform_device *pdev)
1682 {
1683         struct ufs_hba *hba =  platform_get_drvdata(pdev);
1684
1685         pm_runtime_get_sync(&(pdev)->dev);
1686         ufshcd_remove(hba);
1687         return 0;
1688 }
1689
1690 static const struct of_device_id ufs_qcom_of_match[] = {
1691         { .compatible = "qcom,ufshc"},
1692         {},
1693 };
1694 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match);
1695
1696 #ifdef CONFIG_ACPI
1697 static const struct acpi_device_id ufs_qcom_acpi_match[] = {
1698         { "QCOM24A5" },
1699         { },
1700 };
1701 MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match);
1702 #endif
1703
1704 static const struct dev_pm_ops ufs_qcom_pm_ops = {
1705         .suspend        = ufshcd_pltfrm_suspend,
1706         .resume         = ufshcd_pltfrm_resume,
1707         .runtime_suspend = ufshcd_pltfrm_runtime_suspend,
1708         .runtime_resume  = ufshcd_pltfrm_runtime_resume,
1709         .runtime_idle    = ufshcd_pltfrm_runtime_idle,
1710 };
1711
1712 static struct platform_driver ufs_qcom_pltform = {
1713         .probe  = ufs_qcom_probe,
1714         .remove = ufs_qcom_remove,
1715         .shutdown = ufshcd_pltfrm_shutdown,
1716         .driver = {
1717                 .name   = "ufshcd-qcom",
1718                 .pm     = &ufs_qcom_pm_ops,
1719                 .of_match_table = of_match_ptr(ufs_qcom_of_match),
1720                 .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match),
1721         },
1722 };
1723 module_platform_driver(ufs_qcom_pltform);
1724
1725 MODULE_LICENSE("GPL v2");