1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2 // Copyright(c) 2015-17 Intel Corporation.
5 * Soundwire Intel Master Driver
8 #include <linux/acpi.h>
9 #include <linux/debugfs.h>
10 #include <linux/delay.h>
11 #include <linux/module.h>
12 #include <linux/interrupt.h>
14 #include <linux/platform_device.h>
15 #include <sound/pcm_params.h>
16 #include <sound/soc.h>
17 #include <linux/soundwire/sdw_registers.h>
18 #include <linux/soundwire/sdw.h>
19 #include <linux/soundwire/sdw_intel.h>
20 #include "cadence_master.h"
24 /* Intel SHIM Registers Definition */
25 #define SDW_SHIM_LCAP 0x0
26 #define SDW_SHIM_LCTL 0x4
27 #define SDW_SHIM_IPPTR 0x8
28 #define SDW_SHIM_SYNC 0xC
30 #define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x))
31 #define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x))
32 #define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x))
33 #define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x))
34 #define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x))
35 #define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x))
37 #define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y)))
38 #define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y)))
39 #define SDW_SHIM_PDMSCAP(x) (0x062 + 0x60 * (x))
40 #define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x))
41 #define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x))
43 #define SDW_SHIM_WAKEEN 0x190
44 #define SDW_SHIM_WAKESTS 0x192
46 #define SDW_SHIM_LCTL_SPA BIT(0)
47 #define SDW_SHIM_LCTL_CPA BIT(8)
49 #define SDW_SHIM_SYNC_SYNCPRD_VAL 0x176F
50 #define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0)
51 #define SDW_SHIM_SYNC_SYNCCPU BIT(15)
52 #define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16)
53 #define SDW_SHIM_SYNC_CMDSYNC BIT(16)
54 #define SDW_SHIM_SYNC_SYNCGO BIT(24)
56 #define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0)
57 #define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4)
58 #define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8)
60 #define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0)
61 #define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4)
62 #define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8)
63 #define SDW_SHIM_PCMSYCM_DIR BIT(15)
65 #define SDW_SHIM_PDMSCAP_ISS GENMASK(3, 0)
66 #define SDW_SHIM_PDMSCAP_OSS GENMASK(7, 4)
67 #define SDW_SHIM_PDMSCAP_BSS GENMASK(12, 8)
68 #define SDW_SHIM_PDMSCAP_CPSS GENMASK(15, 13)
70 #define SDW_SHIM_IOCTL_MIF BIT(0)
71 #define SDW_SHIM_IOCTL_CO BIT(1)
72 #define SDW_SHIM_IOCTL_COE BIT(2)
73 #define SDW_SHIM_IOCTL_DO BIT(3)
74 #define SDW_SHIM_IOCTL_DOE BIT(4)
75 #define SDW_SHIM_IOCTL_BKE BIT(5)
76 #define SDW_SHIM_IOCTL_WPDD BIT(6)
77 #define SDW_SHIM_IOCTL_CIBD BIT(8)
78 #define SDW_SHIM_IOCTL_DIBD BIT(9)
80 #define SDW_SHIM_CTMCTL_DACTQE BIT(0)
81 #define SDW_SHIM_CTMCTL_DODS BIT(1)
82 #define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3)
84 #define SDW_SHIM_WAKEEN_ENABLE BIT(0)
85 #define SDW_SHIM_WAKESTS_STATUS BIT(0)
87 /* Intel ALH Register definitions */
88 #define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x)))
89 #define SDW_ALH_NUM_STREAMS 64
91 #define SDW_ALH_STRMZCFG_DMAT_VAL 0x3
92 #define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0)
93 #define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16)
95 #define SDW_INTEL_QUIRK_MASK_BUS_DISABLE BIT(1)
104 struct sdw_cdns cdns;
106 struct sdw_intel_link_res *res;
107 #ifdef CONFIG_DEBUG_FS
108 struct dentry *debugfs;
112 #define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns)
115 * Read, write helpers for HW registers
117 static inline int intel_readl(void __iomem *base, int offset)
119 return readl(base + offset);
122 static inline void intel_writel(void __iomem *base, int offset, int value)
124 writel(value, base + offset);
127 static inline u16 intel_readw(void __iomem *base, int offset)
129 return readw(base + offset);
132 static inline void intel_writew(void __iomem *base, int offset, u16 value)
134 writew(value, base + offset);
137 static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask)
142 writel(value, base + offset);
144 reg_read = readl(base + offset);
145 if (!(reg_read & mask))
150 } while (timeout != 0);
155 static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask)
160 writel(value, base + offset);
162 reg_read = readl(base + offset);
168 } while (timeout != 0);
176 #ifdef CONFIG_DEBUG_FS
178 #define RD_BUF (2 * PAGE_SIZE)
180 static ssize_t intel_sprintf(void __iomem *mem, bool l,
181 char *buf, size_t pos, unsigned int reg)
186 value = intel_readl(mem, reg);
188 value = intel_readw(mem, reg);
190 return scnprintf(buf + pos, RD_BUF - pos, "%4x\t%4x\n", reg, value);
193 static int intel_reg_show(struct seq_file *s_file, void *data)
195 struct sdw_intel *sdw = s_file->private;
196 void __iomem *s = sdw->res->shim;
197 void __iomem *a = sdw->res->alh;
201 unsigned int links, reg;
203 buf = kzalloc(RD_BUF, GFP_KERNEL);
207 links = intel_readl(s, SDW_SHIM_LCAP) & GENMASK(2, 0);
209 ret = scnprintf(buf, RD_BUF, "Register Value\n");
210 ret += scnprintf(buf + ret, RD_BUF - ret, "\nShim\n");
212 for (i = 0; i < links; i++) {
213 reg = SDW_SHIM_LCAP + i * 4;
214 ret += intel_sprintf(s, true, buf, ret, reg);
217 for (i = 0; i < links; i++) {
218 ret += scnprintf(buf + ret, RD_BUF - ret, "\nLink%d\n", i);
219 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLSCAP(i));
220 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS0CM(i));
221 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS1CM(i));
222 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS2CM(i));
223 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS3CM(i));
224 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PCMSCAP(i));
226 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PCMSyCH registers\n");
229 * the value 10 is the number of PDIs. We will need a
230 * cleanup to remove hard-coded Intel configurations
231 * from cadence_master.c
233 for (j = 0; j < 10; j++) {
234 ret += intel_sprintf(s, false, buf, ret,
235 SDW_SHIM_PCMSYCHM(i, j));
236 ret += intel_sprintf(s, false, buf, ret,
237 SDW_SHIM_PCMSYCHC(i, j));
239 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PDMSCAP, IOCTL, CTMCTL\n");
241 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PDMSCAP(i));
242 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_IOCTL(i));
243 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTMCTL(i));
246 ret += scnprintf(buf + ret, RD_BUF - ret, "\nWake registers\n");
247 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKEEN);
248 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKESTS);
250 ret += scnprintf(buf + ret, RD_BUF - ret, "\nALH STRMzCFG\n");
251 for (i = 0; i < SDW_ALH_NUM_STREAMS; i++)
252 ret += intel_sprintf(a, true, buf, ret, SDW_ALH_STRMZCFG(i));
254 seq_printf(s_file, "%s", buf);
259 DEFINE_SHOW_ATTRIBUTE(intel_reg);
261 static void intel_debugfs_init(struct sdw_intel *sdw)
263 struct dentry *root = sdw->cdns.bus.debugfs;
268 sdw->debugfs = debugfs_create_dir("intel-sdw", root);
270 debugfs_create_file("intel-registers", 0400, sdw->debugfs, sdw,
273 sdw_cdns_debugfs_init(&sdw->cdns, sdw->debugfs);
276 static void intel_debugfs_exit(struct sdw_intel *sdw)
278 debugfs_remove_recursive(sdw->debugfs);
281 static void intel_debugfs_init(struct sdw_intel *sdw) {}
282 static void intel_debugfs_exit(struct sdw_intel *sdw) {}
283 #endif /* CONFIG_DEBUG_FS */
289 static int intel_link_power_up(struct sdw_intel *sdw)
291 unsigned int link_id = sdw->instance;
292 void __iomem *shim = sdw->res->shim;
293 int spa_mask, cpa_mask;
294 int link_control, ret;
296 /* Link power up sequence */
297 link_control = intel_readl(shim, SDW_SHIM_LCTL);
298 spa_mask = (SDW_SHIM_LCTL_SPA << link_id);
299 cpa_mask = (SDW_SHIM_LCTL_CPA << link_id);
300 link_control |= spa_mask;
302 ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);
306 sdw->cdns.link_up = true;
310 static int intel_shim_init(struct sdw_intel *sdw)
312 void __iomem *shim = sdw->res->shim;
313 unsigned int link_id = sdw->instance;
315 u16 ioctl = 0, act = 0;
317 /* Initialize Shim */
318 ioctl |= SDW_SHIM_IOCTL_BKE;
319 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
321 ioctl |= SDW_SHIM_IOCTL_WPDD;
322 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
324 ioctl |= SDW_SHIM_IOCTL_DO;
325 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
327 ioctl |= SDW_SHIM_IOCTL_DOE;
328 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
330 /* Switch to MIP from Glue logic */
331 ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id));
333 ioctl &= ~(SDW_SHIM_IOCTL_DOE);
334 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
336 ioctl &= ~(SDW_SHIM_IOCTL_DO);
337 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
339 ioctl |= (SDW_SHIM_IOCTL_MIF);
340 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
342 ioctl &= ~(SDW_SHIM_IOCTL_BKE);
343 ioctl &= ~(SDW_SHIM_IOCTL_COE);
345 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
347 act |= 0x1 << SDW_REG_SHIFT(SDW_SHIM_CTMCTL_DOAIS);
348 act |= SDW_SHIM_CTMCTL_DACTQE;
349 act |= SDW_SHIM_CTMCTL_DODS;
350 intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act);
352 /* Now set SyncPRD period */
353 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
354 sync_reg |= (SDW_SHIM_SYNC_SYNCPRD_VAL <<
355 SDW_REG_SHIFT(SDW_SHIM_SYNC_SYNCPRD));
357 /* Set SyncCPU bit */
358 sync_reg |= SDW_SHIM_SYNC_SYNCCPU;
359 ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg,
360 SDW_SHIM_SYNC_SYNCCPU);
362 dev_err(sdw->cdns.dev, "Failed to set sync period: %d\n", ret);
370 static void intel_pdi_init(struct sdw_intel *sdw,
371 struct sdw_cdns_stream_config *config)
373 void __iomem *shim = sdw->res->shim;
374 unsigned int link_id = sdw->instance;
375 int pcm_cap, pdm_cap;
377 /* PCM Stream Capability */
378 pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id));
380 config->pcm_bd = (pcm_cap & SDW_SHIM_PCMSCAP_BSS) >>
381 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_BSS);
382 config->pcm_in = (pcm_cap & SDW_SHIM_PCMSCAP_ISS) >>
383 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_ISS);
384 config->pcm_out = (pcm_cap & SDW_SHIM_PCMSCAP_OSS) >>
385 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_OSS);
387 dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n",
388 config->pcm_bd, config->pcm_in, config->pcm_out);
390 /* PDM Stream Capability */
391 pdm_cap = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
393 config->pdm_bd = (pdm_cap & SDW_SHIM_PDMSCAP_BSS) >>
394 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_BSS);
395 config->pdm_in = (pdm_cap & SDW_SHIM_PDMSCAP_ISS) >>
396 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_ISS);
397 config->pdm_out = (pdm_cap & SDW_SHIM_PDMSCAP_OSS) >>
398 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_OSS);
400 dev_dbg(sdw->cdns.dev, "PDM cap bd:%d in:%d out:%d\n",
401 config->pdm_bd, config->pdm_in, config->pdm_out);
405 intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num, bool pcm)
407 void __iomem *shim = sdw->res->shim;
408 unsigned int link_id = sdw->instance;
412 count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num));
415 * WORKAROUND: on all existing Intel controllers, pdi
416 * number 2 reports channel count as 1 even though it
417 * supports 8 channels. Performing hardcoding for pdi
424 count = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
425 count = ((count & SDW_SHIM_PDMSCAP_CPSS) >>
426 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_CPSS));
429 /* zero based values for channel count in register */
435 static int intel_pdi_get_ch_update(struct sdw_intel *sdw,
436 struct sdw_cdns_pdi *pdi,
437 unsigned int num_pdi,
438 unsigned int *num_ch, bool pcm)
442 for (i = 0; i < num_pdi; i++) {
443 pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num, pcm);
444 ch_count += pdi->ch_count;
452 static int intel_pdi_stream_ch_update(struct sdw_intel *sdw,
453 struct sdw_cdns_streams *stream, bool pcm)
455 intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd,
456 &stream->num_ch_bd, pcm);
458 intel_pdi_get_ch_update(sdw, stream->in, stream->num_in,
459 &stream->num_ch_in, pcm);
461 intel_pdi_get_ch_update(sdw, stream->out, stream->num_out,
462 &stream->num_ch_out, pcm);
467 static int intel_pdi_ch_update(struct sdw_intel *sdw)
469 /* First update PCM streams followed by PDM streams */
470 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm, true);
471 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pdm, false);
477 intel_pdi_shim_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
479 void __iomem *shim = sdw->res->shim;
480 unsigned int link_id = sdw->instance;
483 /* the Bulk and PCM streams are not contiguous */
484 pdi->intel_alh_id = (link_id * 16) + pdi->num + 3;
486 pdi->intel_alh_id += 2;
489 * Program stream parameters to stream SHIM register
490 * This is applicable for PCM stream only.
492 if (pdi->type != SDW_STREAM_PCM)
495 if (pdi->dir == SDW_DATA_DIR_RX)
496 pdi_conf |= SDW_SHIM_PCMSYCM_DIR;
498 pdi_conf &= ~(SDW_SHIM_PCMSYCM_DIR);
500 pdi_conf |= (pdi->intel_alh_id <<
501 SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_STREAM));
502 pdi_conf |= (pdi->l_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_LCHN));
503 pdi_conf |= (pdi->h_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_HCHN));
505 intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf);
509 intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
511 void __iomem *alh = sdw->res->alh;
512 unsigned int link_id = sdw->instance;
515 /* the Bulk and PCM streams are not contiguous */
516 pdi->intel_alh_id = (link_id * 16) + pdi->num + 3;
518 pdi->intel_alh_id += 2;
520 /* Program Stream config ALH register */
521 conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id));
523 conf |= (SDW_ALH_STRMZCFG_DMAT_VAL <<
524 SDW_REG_SHIFT(SDW_ALH_STRMZCFG_DMAT));
526 conf |= ((pdi->ch_count - 1) <<
527 SDW_REG_SHIFT(SDW_ALH_STRMZCFG_CHN));
529 intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf);
532 static int intel_config_stream(struct sdw_intel *sdw,
533 struct snd_pcm_substream *substream,
534 struct snd_soc_dai *dai,
535 struct snd_pcm_hw_params *hw_params, int link_id)
537 struct sdw_intel_link_res *res = sdw->res;
539 if (res->ops && res->ops->config_stream && res->arg)
540 return res->ops->config_stream(res->arg,
541 substream, dai, hw_params, link_id);
547 * bank switch routines
550 static int intel_pre_bank_switch(struct sdw_bus *bus)
552 struct sdw_cdns *cdns = bus_to_cdns(bus);
553 struct sdw_intel *sdw = cdns_to_intel(cdns);
554 void __iomem *shim = sdw->res->shim;
557 /* Write to register only for multi-link */
558 if (!bus->multi_link)
561 /* Read SYNC register */
562 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
563 sync_reg |= SDW_SHIM_SYNC_CMDSYNC << sdw->instance;
564 intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
569 static int intel_post_bank_switch(struct sdw_bus *bus)
571 struct sdw_cdns *cdns = bus_to_cdns(bus);
572 struct sdw_intel *sdw = cdns_to_intel(cdns);
573 void __iomem *shim = sdw->res->shim;
576 /* Write to register only for multi-link */
577 if (!bus->multi_link)
580 /* Read SYNC register */
581 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
584 * post_bank_switch() ops is called from the bus in loop for
585 * all the Masters in the steam with the expectation that
586 * we trigger the bankswitch for the only first Master in the list
587 * and do nothing for the other Masters
589 * So, set the SYNCGO bit only if CMDSYNC bit is set for any Master.
591 if (!(sync_reg & SDW_SHIM_SYNC_CMDSYNC_MASK))
595 * Set SyncGO bit to synchronously trigger a bank switch for
596 * all the masters. A write to SYNCGO bit clears CMDSYNC bit for all
599 sync_reg |= SDW_SHIM_SYNC_SYNCGO;
601 ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg,
602 SDW_SHIM_SYNC_SYNCGO);
604 dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret);
613 static int intel_hw_params(struct snd_pcm_substream *substream,
614 struct snd_pcm_hw_params *params,
615 struct snd_soc_dai *dai)
617 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
618 struct sdw_intel *sdw = cdns_to_intel(cdns);
619 struct sdw_cdns_dma_data *dma;
620 struct sdw_cdns_pdi *pdi;
621 struct sdw_stream_config sconfig;
622 struct sdw_port_config *pconfig;
627 dma = snd_soc_dai_get_dma_data(dai, substream);
631 ch = params_channels(params);
632 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
633 dir = SDW_DATA_DIR_RX;
635 dir = SDW_DATA_DIR_TX;
637 if (dma->stream_type == SDW_STREAM_PDM)
641 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, ch, dir, dai->id);
643 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pdm, ch, dir, dai->id);
650 /* do run-time configurations for SHIM, ALH and PDI/PORT */
651 intel_pdi_shim_configure(sdw, pdi);
652 intel_pdi_alh_configure(sdw, pdi);
653 sdw_cdns_config_stream(cdns, ch, dir, pdi);
656 /* Inform DSP about PDI stream number */
657 ret = intel_config_stream(sdw, substream, dai, params,
662 sconfig.direction = dir;
663 sconfig.ch_count = ch;
664 sconfig.frame_rate = params_rate(params);
665 sconfig.type = dma->stream_type;
667 if (dma->stream_type == SDW_STREAM_PDM) {
668 sconfig.frame_rate *= 50;
671 sconfig.bps = snd_pcm_format_width(params_format(params));
674 /* Port configuration */
675 pconfig = kcalloc(1, sizeof(*pconfig), GFP_KERNEL);
681 pconfig->num = pdi->num;
682 pconfig->ch_mask = (1 << ch) - 1;
684 ret = sdw_stream_add_master(&cdns->bus, &sconfig,
685 pconfig, 1, dma->stream);
687 dev_err(cdns->dev, "add master to stream failed:%d\n", ret);
695 intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
697 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
698 struct sdw_cdns_dma_data *dma;
701 dma = snd_soc_dai_get_dma_data(dai, substream);
705 ret = sdw_stream_remove_master(&cdns->bus, dma->stream);
707 dev_err(dai->dev, "remove master from stream %s failed: %d\n",
708 dma->stream->name, ret);
713 static void intel_shutdown(struct snd_pcm_substream *substream,
714 struct snd_soc_dai *dai)
716 struct sdw_cdns_dma_data *dma;
718 dma = snd_soc_dai_get_dma_data(dai, substream);
722 snd_soc_dai_set_dma_data(dai, substream, NULL);
726 static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai,
727 void *stream, int direction)
729 return cdns_set_sdw_stream(dai, stream, true, direction);
732 static int intel_pdm_set_sdw_stream(struct snd_soc_dai *dai,
733 void *stream, int direction)
735 return cdns_set_sdw_stream(dai, stream, false, direction);
738 static const struct snd_soc_dai_ops intel_pcm_dai_ops = {
739 .hw_params = intel_hw_params,
740 .hw_free = intel_hw_free,
741 .shutdown = intel_shutdown,
742 .set_sdw_stream = intel_pcm_set_sdw_stream,
745 static const struct snd_soc_dai_ops intel_pdm_dai_ops = {
746 .hw_params = intel_hw_params,
747 .hw_free = intel_hw_free,
748 .shutdown = intel_shutdown,
749 .set_sdw_stream = intel_pdm_set_sdw_stream,
752 static const struct snd_soc_component_driver dai_component = {
756 static int intel_create_dai(struct sdw_cdns *cdns,
757 struct snd_soc_dai_driver *dais,
758 enum intel_pdi_type type,
759 u32 num, u32 off, u32 max_ch, bool pcm)
766 /* TODO: Read supported rates/formats from hardware */
767 for (i = off; i < (off + num); i++) {
768 dais[i].name = kasprintf(GFP_KERNEL, "SDW%d Pin%d",
773 if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) {
774 dais[i].playback.channels_min = 1;
775 dais[i].playback.channels_max = max_ch;
776 dais[i].playback.rates = SNDRV_PCM_RATE_48000;
777 dais[i].playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
780 if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) {
781 dais[i].capture.channels_min = 1;
782 dais[i].capture.channels_max = max_ch;
783 dais[i].capture.rates = SNDRV_PCM_RATE_48000;
784 dais[i].capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
788 dais[i].ops = &intel_pcm_dai_ops;
790 dais[i].ops = &intel_pdm_dai_ops;
796 static int intel_register_dai(struct sdw_intel *sdw)
798 struct sdw_cdns *cdns = &sdw->cdns;
799 struct sdw_cdns_streams *stream;
800 struct snd_soc_dai_driver *dais;
801 int num_dai, ret, off = 0;
803 /* DAIs are created based on total number of PDIs supported */
804 num_dai = cdns->pcm.num_pdi + cdns->pdm.num_pdi;
806 dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL);
810 /* Create PCM DAIs */
813 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pcm.num_in,
814 off, stream->num_ch_in, true);
818 off += cdns->pcm.num_in;
819 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out,
820 off, stream->num_ch_out, true);
824 off += cdns->pcm.num_out;
825 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd,
826 off, stream->num_ch_bd, true);
830 /* Create PDM DAIs */
832 off += cdns->pcm.num_bd;
833 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pdm.num_in,
834 off, stream->num_ch_in, false);
838 off += cdns->pdm.num_in;
839 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pdm.num_out,
840 off, stream->num_ch_out, false);
844 off += cdns->pdm.num_out;
845 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pdm.num_bd,
846 off, stream->num_ch_bd, false);
850 return snd_soc_register_component(cdns->dev, &dai_component,
854 static int sdw_master_read_intel_prop(struct sdw_bus *bus)
856 struct sdw_master_prop *prop = &bus->prop;
857 struct fwnode_handle *link;
861 /* Find master handle */
862 snprintf(name, sizeof(name),
863 "mipi-sdw-link-%d-subproperties", bus->link_id);
865 link = device_get_named_child_node(bus->dev, name);
867 dev_err(bus->dev, "Master node %s not found\n", name);
871 fwnode_property_read_u32(link,
872 "intel-sdw-ip-clock",
875 fwnode_property_read_u32(link,
879 if (quirk_mask & SDW_INTEL_QUIRK_MASK_BUS_DISABLE)
880 prop->hw_disabled = true;
885 static int intel_prop_read(struct sdw_bus *bus)
887 /* Initialize with default handler to read all DisCo properties */
888 sdw_master_read_prop(bus);
890 /* read Intel-specific properties */
891 sdw_master_read_intel_prop(bus);
896 static struct sdw_master_ops sdw_intel_ops = {
897 .read_prop = sdw_master_read_prop,
898 .xfer_msg = cdns_xfer_msg,
899 .xfer_msg_defer = cdns_xfer_msg_defer,
900 .reset_page_addr = cdns_reset_page_addr,
901 .set_bus_conf = cdns_bus_conf,
902 .pre_bank_switch = intel_pre_bank_switch,
903 .post_bank_switch = intel_post_bank_switch,
906 static int intel_init(struct sdw_intel *sdw)
908 /* Initialize shim and controller */
909 intel_link_power_up(sdw);
910 intel_shim_init(sdw);
912 return sdw_cdns_init(&sdw->cdns, false);
918 static int intel_probe(struct platform_device *pdev)
920 struct sdw_cdns_stream_config config;
921 struct sdw_intel *sdw;
924 sdw = devm_kzalloc(&pdev->dev, sizeof(*sdw), GFP_KERNEL);
928 sdw->instance = pdev->id;
929 sdw->res = dev_get_platdata(&pdev->dev);
930 sdw->cdns.dev = &pdev->dev;
931 sdw->cdns.registers = sdw->res->registers;
932 sdw->cdns.instance = sdw->instance;
933 sdw->cdns.msg_count = 0;
934 sdw->cdns.bus.dev = &pdev->dev;
935 sdw->cdns.bus.link_id = pdev->id;
937 sdw_cdns_probe(&sdw->cdns);
939 /* Set property read ops */
940 sdw_intel_ops.read_prop = intel_prop_read;
941 sdw->cdns.bus.ops = &sdw_intel_ops;
943 platform_set_drvdata(pdev, sdw);
945 ret = sdw_add_bus_master(&sdw->cdns.bus);
947 dev_err(&pdev->dev, "sdw_add_bus_master fail: %d\n", ret);
951 if (sdw->cdns.bus.prop.hw_disabled) {
952 dev_info(&pdev->dev, "SoundWire master %d is disabled, ignoring\n",
953 sdw->cdns.bus.link_id);
957 /* Initialize shim, controller and Cadence IP */
958 ret = intel_init(sdw);
962 /* Read the PDI config and initialize cadence PDI */
963 intel_pdi_init(sdw, &config);
964 ret = sdw_cdns_pdi_init(&sdw->cdns, config);
968 intel_pdi_ch_update(sdw);
971 ret = request_threaded_irq(sdw->res->irq, sdw_cdns_irq, sdw_cdns_thread,
972 IRQF_SHARED, KBUILD_MODNAME, &sdw->cdns);
974 dev_err(sdw->cdns.dev, "unable to grab IRQ %d, disabling device\n",
979 ret = sdw_cdns_enable_interrupt(&sdw->cdns, true);
981 dev_err(sdw->cdns.dev, "cannot enable interrupts\n");
985 ret = sdw_cdns_exit_reset(&sdw->cdns);
987 dev_err(sdw->cdns.dev, "unable to exit bus reset sequence\n");
992 ret = intel_register_dai(sdw);
994 dev_err(sdw->cdns.dev, "DAI registration failed: %d\n", ret);
995 snd_soc_unregister_component(sdw->cdns.dev);
999 intel_debugfs_init(sdw);
1004 sdw_cdns_enable_interrupt(&sdw->cdns, false);
1005 free_irq(sdw->res->irq, sdw);
1007 sdw_delete_bus_master(&sdw->cdns.bus);
1011 static int intel_remove(struct platform_device *pdev)
1013 struct sdw_intel *sdw;
1015 sdw = platform_get_drvdata(pdev);
1017 if (!sdw->cdns.bus.prop.hw_disabled) {
1018 intel_debugfs_exit(sdw);
1019 sdw_cdns_enable_interrupt(&sdw->cdns, false);
1020 free_irq(sdw->res->irq, sdw);
1021 snd_soc_unregister_component(sdw->cdns.dev);
1023 sdw_delete_bus_master(&sdw->cdns.bus);
1028 static struct platform_driver sdw_intel_drv = {
1029 .probe = intel_probe,
1030 .remove = intel_remove,
1037 module_platform_driver(sdw_intel_drv);
1039 MODULE_LICENSE("Dual BSD/GPL");
1040 MODULE_ALIAS("platform:int-sdw");
1041 MODULE_DESCRIPTION("Intel Soundwire Master Driver");