1 // SPDX-License-Identifier: GPL-2.0-only
3 * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
5 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
7 * This driver has been based on the spi-gpio.c:
8 * Copyright (C) 2006,2008 David Brownell
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/spinlock.h>
15 #include <linux/platform_device.h>
17 #include <linux/spi/spi.h>
18 #include <linux/spi/spi_bitbang.h>
19 #include <linux/bitops.h>
20 #include <linux/clk.h>
21 #include <linux/err.h>
22 #include <linux/platform_data/spi-ath79.h>
24 #define DRV_NAME "ath79-spi"
26 #define ATH79_SPI_RRW_DELAY_FACTOR 12000
27 #define MHZ (1000 * 1000)
29 #define AR71XX_SPI_REG_FS 0x00 /* Function Select */
30 #define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */
31 #define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */
32 #define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */
34 #define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
36 #define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */
37 #define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */
38 #define AR71XX_SPI_IOC_CS(n) BIT(16 + (n))
41 struct spi_bitbang bitbang;
46 unsigned int rrw_delay;
49 static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned int reg)
51 return ioread32(sp->base + reg);
54 static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned int reg, u32 val)
56 iowrite32(val, sp->base + reg);
59 static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
61 return spi_master_get_devdata(spi->master);
64 static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned int nsecs)
66 if (nsecs > sp->rrw_delay)
67 ndelay(nsecs - sp->rrw_delay);
70 static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
72 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
73 int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
74 u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
77 sp->ioc_base |= cs_bit;
79 sp->ioc_base &= ~cs_bit;
81 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
84 static void ath79_spi_enable(struct ath79_spi *sp)
86 /* enable GPIO mode */
87 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
89 /* save CTRL register */
90 sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
91 sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
93 /* clear clk and mosi in the base state */
94 sp->ioc_base &= ~(AR71XX_SPI_IOC_DO | AR71XX_SPI_IOC_CLK);
96 /* TODO: setup speed? */
97 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
100 static void ath79_spi_disable(struct ath79_spi *sp)
102 /* restore CTRL register */
103 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
104 /* disable GPIO mode */
105 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
108 static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned int nsecs,
109 u32 word, u8 bits, unsigned flags)
111 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
112 u32 ioc = sp->ioc_base;
114 /* clock starts at inactive polarity */
115 for (word <<= (32 - bits); likely(bits); bits--) {
118 if (word & (1 << 31))
119 out = ioc | AR71XX_SPI_IOC_DO;
121 out = ioc & ~AR71XX_SPI_IOC_DO;
123 /* setup MSB (to slave) on trailing edge */
124 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
125 ath79_spi_delay(sp, nsecs);
126 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
127 ath79_spi_delay(sp, nsecs);
129 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
134 return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
137 static int ath79_spi_probe(struct platform_device *pdev)
139 struct spi_master *master;
140 struct ath79_spi *sp;
141 struct ath79_spi_platform_data *pdata;
146 master = spi_alloc_master(&pdev->dev, sizeof(*sp));
147 if (master == NULL) {
148 dev_err(&pdev->dev, "failed to allocate spi master\n");
152 sp = spi_master_get_devdata(master);
153 master->dev.of_node = pdev->dev.of_node;
154 platform_set_drvdata(pdev, sp);
156 pdata = dev_get_platdata(&pdev->dev);
158 master->use_gpio_descriptors = true;
159 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
160 master->setup = spi_bitbang_setup;
161 master->cleanup = spi_bitbang_cleanup;
163 master->bus_num = pdata->bus_num;
164 master->num_chipselect = pdata->num_chipselect;
167 sp->bitbang.master = master;
168 sp->bitbang.chipselect = ath79_spi_chipselect;
169 sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
170 sp->bitbang.flags = SPI_CS_HIGH;
172 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
173 sp->base = devm_ioremap_resource(&pdev->dev, r);
174 if (IS_ERR(sp->base)) {
175 ret = PTR_ERR(sp->base);
179 sp->clk = devm_clk_get(&pdev->dev, "ahb");
180 if (IS_ERR(sp->clk)) {
181 ret = PTR_ERR(sp->clk);
185 ret = clk_prepare_enable(sp->clk);
189 rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
192 goto err_clk_disable;
195 sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
196 dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
199 ath79_spi_enable(sp);
200 ret = spi_bitbang_start(&sp->bitbang);
207 ath79_spi_disable(sp);
209 clk_disable_unprepare(sp->clk);
211 spi_master_put(sp->bitbang.master);
216 static int ath79_spi_remove(struct platform_device *pdev)
218 struct ath79_spi *sp = platform_get_drvdata(pdev);
220 spi_bitbang_stop(&sp->bitbang);
221 ath79_spi_disable(sp);
222 clk_disable_unprepare(sp->clk);
223 spi_master_put(sp->bitbang.master);
228 static void ath79_spi_shutdown(struct platform_device *pdev)
230 ath79_spi_remove(pdev);
233 static const struct of_device_id ath79_spi_of_match[] = {
234 { .compatible = "qca,ar7100-spi", },
237 MODULE_DEVICE_TABLE(of, ath79_spi_of_match);
239 static struct platform_driver ath79_spi_driver = {
240 .probe = ath79_spi_probe,
241 .remove = ath79_spi_remove,
242 .shutdown = ath79_spi_shutdown,
245 .of_match_table = ath79_spi_of_match,
248 module_platform_driver(ath79_spi_driver);
250 MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
251 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
252 MODULE_LICENSE("GPL v2");
253 MODULE_ALIAS("platform:" DRV_NAME);