1 // SPDX-License-Identifier: GPL-2.0-only
3 * PCI interface driver for DW SPI Core
5 * Copyright (c) 2009, 2014 Intel Corporation.
8 #include <linux/interrupt.h>
10 #include <linux/slab.h>
11 #include <linux/spi/spi.h>
12 #include <linux/module.h>
16 #define DRIVER_NAME "dw_spi_pci"
19 int (*setup)(struct dw_spi *);
25 static struct spi_pci_desc spi_pci_mid_desc_1 = {
26 .setup = dw_spi_mid_init,
31 static struct spi_pci_desc spi_pci_mid_desc_2 = {
32 .setup = dw_spi_mid_init,
37 static struct spi_pci_desc spi_pci_ehl_desc = {
40 .max_freq = 100000000,
43 static int spi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
46 struct spi_pci_desc *desc = (struct spi_pci_desc *)ent->driver_data;
50 ret = pcim_enable_device(pdev);
54 dws = devm_kzalloc(&pdev->dev, sizeof(*dws), GFP_KERNEL);
58 /* Get basic io resource and map it */
59 dws->paddr = pci_resource_start(pdev, pci_bar);
61 ret = pcim_iomap_regions(pdev, 1 << pci_bar, pci_name(pdev));
65 dws->regs = pcim_iomap_table(pdev)[pci_bar];
69 * Specific handling for platforms, like dma setup,
70 * clock rate, FIFO depth.
73 dws->num_cs = desc->num_cs;
74 dws->bus_num = desc->bus_num;
75 dws->max_freq = desc->max_freq;
78 ret = desc->setup(dws);
86 ret = dw_spi_add_host(&pdev->dev, dws);
90 /* PCI hook and SPI hook use the same drv data */
91 pci_set_drvdata(pdev, dws);
93 dev_info(&pdev->dev, "found PCI SPI controller(ID: %04x:%04x)\n",
94 pdev->vendor, pdev->device);
99 static void spi_pci_remove(struct pci_dev *pdev)
101 struct dw_spi *dws = pci_get_drvdata(pdev);
103 dw_spi_remove_host(dws);
106 #ifdef CONFIG_PM_SLEEP
107 static int spi_suspend(struct device *dev)
109 struct dw_spi *dws = dev_get_drvdata(dev);
111 return dw_spi_suspend_host(dws);
114 static int spi_resume(struct device *dev)
116 struct dw_spi *dws = dev_get_drvdata(dev);
118 return dw_spi_resume_host(dws);
122 static SIMPLE_DEV_PM_OPS(dw_spi_pm_ops, spi_suspend, spi_resume);
124 static const struct pci_device_id pci_ids[] = {
125 /* Intel MID platform SPI controller 0 */
127 * The access to the device 8086:0801 is disabled by HW, since it's
128 * exclusively used by SCU to communicate with MSIC.
130 /* Intel MID platform SPI controller 1 */
131 { PCI_VDEVICE(INTEL, 0x0800), (kernel_ulong_t)&spi_pci_mid_desc_1},
132 /* Intel MID platform SPI controller 2 */
133 { PCI_VDEVICE(INTEL, 0x0812), (kernel_ulong_t)&spi_pci_mid_desc_2},
134 /* Intel Elkhart Lake PSE SPI controllers */
135 { PCI_VDEVICE(INTEL, 0x4b84), (kernel_ulong_t)&spi_pci_ehl_desc},
136 { PCI_VDEVICE(INTEL, 0x4b85), (kernel_ulong_t)&spi_pci_ehl_desc},
137 { PCI_VDEVICE(INTEL, 0x4b86), (kernel_ulong_t)&spi_pci_ehl_desc},
138 { PCI_VDEVICE(INTEL, 0x4b87), (kernel_ulong_t)&spi_pci_ehl_desc},
141 MODULE_DEVICE_TABLE(pci, pci_ids);
143 static struct pci_driver dw_spi_driver = {
146 .probe = spi_pci_probe,
147 .remove = spi_pci_remove,
149 .pm = &dw_spi_pm_ops,
153 module_pci_driver(dw_spi_driver);
155 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
156 MODULE_DESCRIPTION("PCI interface driver for DW SPI Core");
157 MODULE_LICENSE("GPL v2");