drivers/spi/spi-fsl-dspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Copyright 2013 Freescale Semiconductor, Inc.
   4 //
   5 // Freescale DSPI driver
   6 // This file contains a driver for the Freescale DSPI
   7
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/dmaengine.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/of_device.h>
  16 #include <linux/pinctrl/consumer.h>
  17 #include <linux/regmap.h>
  18 #include <linux/spi/spi.h>
  19 #include <linux/spi/spi-fsl-dspi.h>
  20
  21 #define DRIVER_NAME                     "fsl-dspi"
  22
  23 #ifdef CONFIG_M5441x
  24 #define DSPI_FIFO_SIZE                  16
  25 #else
  26 #define DSPI_FIFO_SIZE                  4
  27 #endif
  28 #define DSPI_DMA_BUFSIZE                (DSPI_FIFO_SIZE * 1024)
  29
  30 #define SPI_MCR                         0x00
  31 #define SPI_MCR_MASTER                  BIT(31)
  32 #define SPI_MCR_PCSIS                   (0x3F << 16)
  33 #define SPI_MCR_CLR_TXF                 BIT(11)
  34 #define SPI_MCR_CLR_RXF                 BIT(10)
  35 #define SPI_MCR_XSPI                    BIT(3)
  36
  37 #define SPI_TCR                         0x08
  38 #define SPI_TCR_GET_TCNT(x)             (((x) & GENMASK(31, 16)) >> 16)
  39
  40 #define SPI_CTAR(x)                     (0x0c + (((x) & GENMASK(1, 0)) * 4))
  41 #define SPI_CTAR_FMSZ(x)                (((x) << 27) & GENMASK(30, 27))
  42 #define SPI_CTAR_CPOL                   BIT(26)
  43 #define SPI_CTAR_CPHA                   BIT(25)
  44 #define SPI_CTAR_LSBFE                  BIT(24)
  45 #define SPI_CTAR_PCSSCK(x)              (((x) << 22) & GENMASK(23, 22))
  46 #define SPI_CTAR_PASC(x)                (((x) << 20) & GENMASK(21, 20))
  47 #define SPI_CTAR_PDT(x)                 (((x) << 18) & GENMASK(19, 18))
  48 #define SPI_CTAR_PBR(x)                 (((x) << 16) & GENMASK(17, 16))
  49 #define SPI_CTAR_CSSCK(x)               (((x) << 12) & GENMASK(15, 12))
  50 #define SPI_CTAR_ASC(x)                 (((x) << 8) & GENMASK(11, 8))
  51 #define SPI_CTAR_DT(x)                  (((x) << 4) & GENMASK(7, 4))
  52 #define SPI_CTAR_BR(x)                  ((x) & GENMASK(3, 0))
  53 #define SPI_CTAR_SCALE_BITS             0xf
  54
  55 #define SPI_CTAR0_SLAVE                 0x0c
  56
  57 #define SPI_SR                          0x2c
  58 #define SPI_SR_TCFQF                    BIT(31)
  59 #define SPI_SR_EOQF                     BIT(28)
  60 #define SPI_SR_TFUF                     BIT(27)
  61 #define SPI_SR_TFFF                     BIT(25)
  62 #define SPI_SR_CMDTCF                   BIT(23)
  63 #define SPI_SR_SPEF                     BIT(21)
  64 #define SPI_SR_RFOF                     BIT(19)
  65 #define SPI_SR_TFIWF                    BIT(18)
  66 #define SPI_SR_RFDF                     BIT(17)
  67 #define SPI_SR_CMDFFF                   BIT(16)
  68 #define SPI_SR_CLEAR                    (SPI_SR_TCFQF | SPI_SR_EOQF | \
  69                                         SPI_SR_TFUF | SPI_SR_TFFF | \
  70                                         SPI_SR_CMDTCF | SPI_SR_SPEF | \
  71                                         SPI_SR_RFOF | SPI_SR_TFIWF | \
  72                                         SPI_SR_RFDF | SPI_SR_CMDFFF)
  73
  74 #define SPI_RSER_TFFFE                  BIT(25)
  75 #define SPI_RSER_TFFFD                  BIT(24)
  76 #define SPI_RSER_RFDFE                  BIT(17)
  77 #define SPI_RSER_RFDFD                  BIT(16)
  78
  79 #define SPI_RSER                        0x30
  80 #define SPI_RSER_TCFQE                  BIT(31)
  81 #define SPI_RSER_EOQFE                  BIT(28)
  82
  83 #define SPI_PUSHR                       0x34
  84 #define SPI_PUSHR_CMD_CONT              BIT(15)
  85 #define SPI_PUSHR_CMD_CTAS(x)           (((x) << 12 & GENMASK(14, 12)))
  86 #define SPI_PUSHR_CMD_EOQ               BIT(11)
  87 #define SPI_PUSHR_CMD_CTCNT             BIT(10)
  88 #define SPI_PUSHR_CMD_PCS(x)            (BIT(x) & GENMASK(5, 0))
  89
  90 #define SPI_PUSHR_SLAVE                 0x34
  91
  92 #define SPI_POPR                        0x38
  93
  94 #define SPI_TXFR0                       0x3c
  95 #define SPI_TXFR1                       0x40
  96 #define SPI_TXFR2                       0x44
  97 #define SPI_TXFR3                       0x48
  98 #define SPI_RXFR0                       0x7c
  99 #define SPI_RXFR1                       0x80
 100 #define SPI_RXFR2                       0x84
 101 #define SPI_RXFR3                       0x88
 102
 103 #define SPI_CTARE(x)                    (0x11c + (((x) & GENMASK(1, 0)) * 4))
 104 #define SPI_CTARE_FMSZE(x)              (((x) & 0x1) << 16)
 105 #define SPI_CTARE_DTCP(x)               ((x) & 0x7ff)
 106
 107 #define SPI_SREX                        0x13c
 108
 109 #define SPI_FRAME_BITS(bits)            SPI_CTAR_FMSZ((bits) - 1)
 110 #define SPI_FRAME_EBITS(bits)           SPI_CTARE_FMSZE(((bits) - 1) >> 4)
 111
 112 /* Register offsets for regmap_pushr */
 113 #define PUSHR_CMD                       0x0
 114 #define PUSHR_TX                        0x2
 115
 116 #define DMA_COMPLETION_TIMEOUT          msecs_to_jiffies(3000)
 117
 118 struct chip_data {
 119         u32                     ctar_val;
 120         u16                     void_write_data;
 121 };
 122
 123 enum dspi_trans_mode {
 124         DSPI_EOQ_MODE = 0,
 125         DSPI_TCFQ_MODE,
 126         DSPI_DMA_MODE,
 127 };
 128
 129 struct fsl_dspi_devtype_data {
 130         enum dspi_trans_mode    trans_mode;
 131         u8                      max_clock_factor;
 132         bool                    ptp_sts_supported;
 133         bool                    xspi_mode;
 134 };
 135
 136 static const struct fsl_dspi_devtype_data vf610_data = {
 137         .trans_mode             = DSPI_DMA_MODE,
 138         .max_clock_factor       = 2,
 139 };
 140
 141 static const struct fsl_dspi_devtype_data ls1021a_v1_data = {
 142         .trans_mode             = DSPI_TCFQ_MODE,
 143         .max_clock_factor       = 8,
 144         .ptp_sts_supported      = true,
 145         .xspi_mode              = true,
 146 };
 147
 148 static const struct fsl_dspi_devtype_data ls2085a_data = {
 149         .trans_mode             = DSPI_TCFQ_MODE,
 150         .max_clock_factor       = 8,
 151         .ptp_sts_supported      = true,
 152 };
 153
 154 static const struct fsl_dspi_devtype_data coldfire_data = {
 155         .trans_mode             = DSPI_EOQ_MODE,
 156         .max_clock_factor       = 8,
 157 };
 158
 159 struct fsl_dspi_dma {
 160         /* Length of transfer in words of DSPI_FIFO_SIZE */
 161         u32                                     curr_xfer_len;
 162
 163         u32                                     *tx_dma_buf;
 164         struct dma_chan                         *chan_tx;
 165         dma_addr_t                              tx_dma_phys;
 166         struct completion                       cmd_tx_complete;
 167         struct dma_async_tx_descriptor          *tx_desc;
 168
 169         u32                                     *rx_dma_buf;
 170         struct dma_chan                         *chan_rx;
 171         dma_addr_t                              rx_dma_phys;
 172         struct completion                       cmd_rx_complete;
 173         struct dma_async_tx_descriptor          *rx_desc;
 174 };
 175
 176 struct fsl_dspi {
 177         struct spi_controller                   *ctlr;
 178         struct platform_device                  *pdev;
 179
 180         struct regmap                           *regmap;
 181         struct regmap                           *regmap_pushr;
 182         int                                     irq;
 183         struct clk                              *clk;
 184
 185         struct spi_transfer                     *cur_transfer;
 186         struct spi_message                      *cur_msg;
 187         struct chip_data                        *cur_chip;
 188         size_t                                  len;
 189         const void                              *tx;
 190         void                                    *rx;
 191         void                                    *rx_end;
 192         u16                                     void_write_data;
 193         u16                                     tx_cmd;
 194         u8                                      bits_per_word;
 195         u8                                      bytes_per_word;
 196         const struct fsl_dspi_devtype_data      *devtype_data;
 197
 198         wait_queue_head_t                       waitq;
 199         u32                                     waitflags;
 200
 201         struct fsl_dspi_dma                     *dma;
 202 };
 203
 204 static u32 dspi_pop_tx(struct fsl_dspi *dspi)
 205 {
 206         u32 txdata = 0;
 207
 208         if (dspi->tx) {
 209                 if (dspi->bytes_per_word == 1)
 210                         txdata = *(u8 *)dspi->tx;
 211                 else if (dspi->bytes_per_word == 2)
 212                         txdata = *(u16 *)dspi->tx;
 213                 else  /* dspi->bytes_per_word == 4 */
 214                         txdata = *(u32 *)dspi->tx;
 215                 dspi->tx += dspi->bytes_per_word;
 216         }
 217         dspi->len -= dspi->bytes_per_word;
 218         return txdata;
 219 }
 220
 221 static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi)
 222 {
 223         u16 cmd = dspi->tx_cmd, data = dspi_pop_tx(dspi);
 224
 225         if (spi_controller_is_slave(dspi->ctlr))
 226                 return data;
 227
 228         if (dspi->len > 0)
 229                 cmd |= SPI_PUSHR_CMD_CONT;
 230         return cmd << 16 | data;
 231 }
 232
 233 static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata)
 234 {
 235         if (!dspi->rx)
 236                 return;
 237
 238         /* Mask off undefined bits */
 239         rxdata &= (1 << dspi->bits_per_word) - 1;
 240
 241         if (dspi->bytes_per_word == 1)
 242                 *(u8 *)dspi->rx = rxdata;
 243         else if (dspi->bytes_per_word == 2)
 244                 *(u16 *)dspi->rx = rxdata;
 245         else /* dspi->bytes_per_word == 4 */
 246                 *(u32 *)dspi->rx = rxdata;
 247         dspi->rx += dspi->bytes_per_word;
 248 }
 249
 250 static void dspi_tx_dma_callback(void *arg)
 251 {
 252         struct fsl_dspi *dspi = arg;
 253         struct fsl_dspi_dma *dma = dspi->dma;
 254
 255         complete(&dma->cmd_tx_complete);
 256 }
 257
 258 static void dspi_rx_dma_callback(void *arg)
 259 {
 260         struct fsl_dspi *dspi = arg;
 261         struct fsl_dspi_dma *dma = dspi->dma;
 262         int i;
 263
 264         if (dspi->rx) {
 265                 for (i = 0; i < dma->curr_xfer_len; i++)
 266                         dspi_push_rx(dspi, dspi->dma->rx_dma_buf[i]);
 267         }
 268
 269         complete(&dma->cmd_rx_complete);
 270 }
 271
 272 static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
 273 {
 274         struct device *dev = &dspi->pdev->dev;
 275         struct fsl_dspi_dma *dma = dspi->dma;
 276         int time_left;
 277         int i;
 278
 279         for (i = 0; i < dma->curr_xfer_len; i++)
 280                 dspi->dma->tx_dma_buf[i] = dspi_pop_tx_pushr(dspi);
 281
 282         dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx,
 283                                         dma->tx_dma_phys,
 284                                         dma->curr_xfer_len *
 285                                         DMA_SLAVE_BUSWIDTH_4_BYTES,
 286                                         DMA_MEM_TO_DEV,
 287                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 288         if (!dma->tx_desc) {
 289                 dev_err(dev, "Not able to get desc for DMA xfer\n");
 290                 return -EIO;
 291         }
 292
 293         dma->tx_desc->callback = dspi_tx_dma_callback;
 294         dma->tx_desc->callback_param = dspi;
 295         if (dma_submit_error(dmaengine_submit(dma->tx_desc))) {
 296                 dev_err(dev, "DMA submit failed\n");
 297                 return -EINVAL;
 298         }
 299
 300         dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx,
 301                                         dma->rx_dma_phys,
 302                                         dma->curr_xfer_len *
 303                                         DMA_SLAVE_BUSWIDTH_4_BYTES,
 304                                         DMA_DEV_TO_MEM,
 305                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 306         if (!dma->rx_desc) {
 307                 dev_err(dev, "Not able to get desc for DMA xfer\n");
 308                 return -EIO;
 309         }
 310
 311         dma->rx_desc->callback = dspi_rx_dma_callback;
 312         dma->rx_desc->callback_param = dspi;
 313         if (dma_submit_error(dmaengine_submit(dma->rx_desc))) {
 314                 dev_err(dev, "DMA submit failed\n");
 315                 return -EINVAL;
 316         }
 317
 318         reinit_completion(&dspi->dma->cmd_rx_complete);
 319         reinit_completion(&dspi->dma->cmd_tx_complete);
 320
 321         dma_async_issue_pending(dma->chan_rx);
 322         dma_async_issue_pending(dma->chan_tx);
 323
 324         if (spi_controller_is_slave(dspi->ctlr)) {
 325                 wait_for_completion_interruptible(&dspi->dma->cmd_rx_complete);
 326                 return 0;
 327         }
 328
 329         time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete,
 330                                                 DMA_COMPLETION_TIMEOUT);
 331         if (time_left == 0) {
 332                 dev_err(dev, "DMA tx timeout\n");
 333                 dmaengine_terminate_all(dma->chan_tx);
 334                 dmaengine_terminate_all(dma->chan_rx);
 335                 return -ETIMEDOUT;
 336         }
 337
 338         time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete,
 339                                                 DMA_COMPLETION_TIMEOUT);
 340         if (time_left == 0) {
 341                 dev_err(dev, "DMA rx timeout\n");
 342                 dmaengine_terminate_all(dma->chan_tx);
 343                 dmaengine_terminate_all(dma->chan_rx);
 344                 return -ETIMEDOUT;
 345         }
 346
 347         return 0;
 348 }
 349
 350 static int dspi_dma_xfer(struct fsl_dspi *dspi)
 351 {
 352         struct spi_message *message = dspi->cur_msg;
 353         struct device *dev = &dspi->pdev->dev;
 354         struct fsl_dspi_dma *dma = dspi->dma;
 355         int curr_remaining_bytes;
 356         int bytes_per_buffer;
 357         int ret = 0;
 358
 359         curr_remaining_bytes = dspi->len;
 360         bytes_per_buffer = DSPI_DMA_BUFSIZE / DSPI_FIFO_SIZE;
 361         while (curr_remaining_bytes) {
 362                 /* Check if current transfer fits the DMA buffer */
 363                 dma->curr_xfer_len = curr_remaining_bytes
 364                         / dspi->bytes_per_word;
 365                 if (dma->curr_xfer_len > bytes_per_buffer)
 366                         dma->curr_xfer_len = bytes_per_buffer;
 367
 368                 ret = dspi_next_xfer_dma_submit(dspi);
 369                 if (ret) {
 370                         dev_err(dev, "DMA transfer failed\n");
 371                         goto exit;
 372
 373                 } else {
 374                         const int len =
 375                                 dma->curr_xfer_len * dspi->bytes_per_word;
 376                         curr_remaining_bytes -= len;
 377                         message->actual_length += len;
 378                         if (curr_remaining_bytes < 0)
 379                                 curr_remaining_bytes = 0;
 380                 }
 381         }
 382
 383 exit:
 384         return ret;
 385 }
 386
 387 static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr)
 388 {
 389         struct device *dev = &dspi->pdev->dev;
 390         struct dma_slave_config cfg;
 391         struct fsl_dspi_dma *dma;
 392         int ret;
 393
 394         dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
 395         if (!dma)
 396                 return -ENOMEM;
 397
 398         dma->chan_rx = dma_request_slave_channel(dev, "rx");
 399         if (!dma->chan_rx) {
 400                 dev_err(dev, "rx dma channel not available\n");
 401                 ret = -ENODEV;
 402                 return ret;
 403         }
 404
 405         dma->chan_tx = dma_request_slave_channel(dev, "tx");
 406         if (!dma->chan_tx) {
 407                 dev_err(dev, "tx dma channel not available\n");
 408                 ret = -ENODEV;
 409                 goto err_tx_channel;
 410         }
 411
 412         dma->tx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
 413                                              &dma->tx_dma_phys, GFP_KERNEL);
 414         if (!dma->tx_dma_buf) {
 415                 ret = -ENOMEM;
 416                 goto err_tx_dma_buf;
 417         }
 418
 419         dma->rx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
 420                                              &dma->rx_dma_phys, GFP_KERNEL);
 421         if (!dma->rx_dma_buf) {
 422                 ret = -ENOMEM;
 423                 goto err_rx_dma_buf;
 424         }
 425
 426         cfg.src_addr = phy_addr + SPI_POPR;
 427         cfg.dst_addr = phy_addr + SPI_PUSHR;
 428         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 429         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 430         cfg.src_maxburst = 1;
 431         cfg.dst_maxburst = 1;
 432
 433         cfg.direction = DMA_DEV_TO_MEM;
 434         ret = dmaengine_slave_config(dma->chan_rx, &cfg);
 435         if (ret) {
 436                 dev_err(dev, "can't configure rx dma channel\n");
 437                 ret = -EINVAL;
 438                 goto err_slave_config;
 439         }
 440
 441         cfg.direction = DMA_MEM_TO_DEV;
 442         ret = dmaengine_slave_config(dma->chan_tx, &cfg);
 443         if (ret) {
 444                 dev_err(dev, "can't configure tx dma channel\n");
 445                 ret = -EINVAL;
 446                 goto err_slave_config;
 447         }
 448
 449         dspi->dma = dma;
 450         init_completion(&dma->cmd_tx_complete);
 451         init_completion(&dma->cmd_rx_complete);
 452
 453         return 0;
 454
 455 err_slave_config:
 456         dma_free_coherent(dev, DSPI_DMA_BUFSIZE,
 457                         dma->rx_dma_buf, dma->rx_dma_phys);
 458 err_rx_dma_buf:
 459         dma_free_coherent(dev, DSPI_DMA_BUFSIZE,
 460                         dma->tx_dma_buf, dma->tx_dma_phys);
 461 err_tx_dma_buf:
 462         dma_release_channel(dma->chan_tx);
 463 err_tx_channel:
 464         dma_release_channel(dma->chan_rx);
 465
 466         devm_kfree(dev, dma);
 467         dspi->dma = NULL;
 468
 469         return ret;
 470 }
 471
 472 static void dspi_release_dma(struct fsl_dspi *dspi)
 473 {
 474         struct fsl_dspi_dma *dma = dspi->dma;
 475         struct device *dev = &dspi->pdev->dev;
 476
 477         if (!dma)
 478                 return;
 479
 480         if (dma->chan_tx) {
 481                 dma_unmap_single(dev, dma->tx_dma_phys,
 482                                  DSPI_DMA_BUFSIZE, DMA_TO_DEVICE);
 483                 dma_release_channel(dma->chan_tx);
 484         }
 485
 486         if (dma->chan_rx) {
 487                 dma_unmap_single(dev, dma->rx_dma_phys,
 488                                  DSPI_DMA_BUFSIZE, DMA_FROM_DEVICE);
 489                 dma_release_channel(dma->chan_rx);
 490         }
 491 }
 492
 493 static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
 494                            unsigned long clkrate)
 495 {
 496         /* Valid baud rate pre-scaler values */
 497         int pbr_tbl[4] = {2, 3, 5, 7};
 498         int brs[16] = { 2,      4,      6,      8,
 499                         16,     32,     64,     128,
 500                         256,    512,    1024,   2048,
 501                         4096,   8192,   16384,  32768 };
 502         int scale_needed, scale, minscale = INT_MAX;
 503         int i, j;
 504
 505         scale_needed = clkrate / speed_hz;
 506         if (clkrate % speed_hz)
 507                 scale_needed++;
 508
 509         for (i = 0; i < ARRAY_SIZE(brs); i++)
 510                 for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) {
 511                         scale = brs[i] * pbr_tbl[j];
 512                         if (scale >= scale_needed) {
 513                                 if (scale < minscale) {
 514                                         minscale = scale;
 515                                         *br = i;
 516                                         *pbr = j;
 517                                 }
 518                                 break;
 519                         }
 520                 }
 521
 522         if (minscale == INT_MAX) {
 523                 pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n",
 524                         speed_hz, clkrate);
 525                 *pbr = ARRAY_SIZE(pbr_tbl) - 1;
 526                 *br =  ARRAY_SIZE(brs) - 1;
 527         }
 528 }
 529
 530 static void ns_delay_scale(char *psc, char *sc, int delay_ns,
 531                            unsigned long clkrate)
 532 {
 533         int scale_needed, scale, minscale = INT_MAX;
 534         int pscale_tbl[4] = {1, 3, 5, 7};
 535         u32 remainder;
 536         int i, j;
 537
 538         scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
 539                                    &remainder);
 540         if (remainder)
 541                 scale_needed++;
 542
 543         for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
 544                 for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) {
 545                         scale = pscale_tbl[i] * (2 << j);
 546                         if (scale >= scale_needed) {
 547                                 if (scale < minscale) {
 548                                         minscale = scale;
 549                                         *psc = i;
 550                                         *sc = j;
 551                                 }
 552                                 break;
 553                         }
 554                 }
 555
 556         if (minscale == INT_MAX) {
 557                 pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
 558                         delay_ns, clkrate);
 559                 *psc = ARRAY_SIZE(pscale_tbl) - 1;
 560                 *sc = SPI_CTAR_SCALE_BITS;
 561         }
 562 }
 563
 564 static void fifo_write(struct fsl_dspi *dspi)
 565 {
 566         regmap_write(dspi->regmap, SPI_PUSHR, dspi_pop_tx_pushr(dspi));
 567 }
 568
 569 static void cmd_fifo_write(struct fsl_dspi *dspi)
 570 {
 571         u16 cmd = dspi->tx_cmd;
 572
 573         if (dspi->len > 0)
 574                 cmd |= SPI_PUSHR_CMD_CONT;
 575         regmap_write(dspi->regmap_pushr, PUSHR_CMD, cmd);
 576 }
 577
 578 static void tx_fifo_write(struct fsl_dspi *dspi, u16 txdata)
 579 {
 580         regmap_write(dspi->regmap_pushr, PUSHR_TX, txdata);
 581 }
 582
 583 static void dspi_tcfq_write(struct fsl_dspi *dspi)
 584 {
 585         /* Clear transfer count */
 586         dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT;
 587
 588         if (dspi->devtype_data->xspi_mode && dspi->bits_per_word > 16) {
 589                 /* Write two TX FIFO entries first, and then the corresponding
 590                  * CMD FIFO entry.
 591                  */
 592                 u32 data = dspi_pop_tx(dspi);
 593
 594                 if (dspi->cur_chip->ctar_val & SPI_CTAR_LSBFE) {
 595                         /* LSB */
 596                         tx_fifo_write(dspi, data & 0xFFFF);
 597                         tx_fifo_write(dspi, data >> 16);
 598                 } else {
 599                         /* MSB */
 600                         tx_fifo_write(dspi, data >> 16);
 601                         tx_fifo_write(dspi, data & 0xFFFF);
 602                 }
 603                 cmd_fifo_write(dspi);
 604         } else {
 605                 /* Write one entry to both TX FIFO and CMD FIFO
 606                  * simultaneously.
 607                  */
 608                 fifo_write(dspi);
 609         }
 610 }
 611
 612 static u32 fifo_read(struct fsl_dspi *dspi)
 613 {
 614         u32 rxdata = 0;
 615
 616         regmap_read(dspi->regmap, SPI_POPR, &rxdata);
 617         return rxdata;
 618 }
 619
 620 static void dspi_tcfq_read(struct fsl_dspi *dspi)
 621 {
 622         dspi_push_rx(dspi, fifo_read(dspi));
 623 }
 624
 625 static void dspi_eoq_write(struct fsl_dspi *dspi)
 626 {
 627         int fifo_size = DSPI_FIFO_SIZE;
 628         u16 xfer_cmd = dspi->tx_cmd;
 629
 630         /* Fill TX FIFO with as many transfers as possible */
 631         while (dspi->len && fifo_size--) {
 632                 dspi->tx_cmd = xfer_cmd;
 633                 /* Request EOQF for last transfer in FIFO */
 634                 if (dspi->len == dspi->bytes_per_word || fifo_size == 0)
 635                         dspi->tx_cmd |= SPI_PUSHR_CMD_EOQ;
 636                 /* Clear transfer count for first transfer in FIFO */
 637                 if (fifo_size == (DSPI_FIFO_SIZE - 1))
 638                         dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT;
 639                 /* Write combined TX FIFO and CMD FIFO entry */
 640                 fifo_write(dspi);
 641         }
 642 }
 643
 644 static void dspi_eoq_read(struct fsl_dspi *dspi)
 645 {
 646         int fifo_size = DSPI_FIFO_SIZE;
 647
 648         /* Read one FIFO entry and push to rx buffer */
 649         while ((dspi->rx < dspi->rx_end) && fifo_size--)
 650                 dspi_push_rx(dspi, fifo_read(dspi));
 651 }
 652
 653 static int dspi_rxtx(struct fsl_dspi *dspi)
 654 {
 655         struct spi_message *msg = dspi->cur_msg;
 656         enum dspi_trans_mode trans_mode;
 657         u16 spi_tcnt;
 658         u32 spi_tcr;
 659
 660         spi_take_timestamp_post(dspi->ctlr, dspi->cur_transfer,
 661                                 dspi->tx - dspi->bytes_per_word, !dspi->irq);
 662
 663         /* Get transfer counter (in number of SPI transfers). It was
 664          * reset to 0 when transfer(s) were started.
 665          */
 666         regmap_read(dspi->regmap, SPI_TCR, &spi_tcr);
 667         spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr);
 668         /* Update total number of bytes that were transferred */
 669         msg->actual_length += spi_tcnt * dspi->bytes_per_word;
 670
 671         trans_mode = dspi->devtype_data->trans_mode;
 672         if (trans_mode == DSPI_EOQ_MODE)
 673                 dspi_eoq_read(dspi);
 674         else if (trans_mode == DSPI_TCFQ_MODE)
 675                 dspi_tcfq_read(dspi);
 676
 677         if (!dspi->len)
 678                 /* Success! */
 679                 return 0;
 680
 681         spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer,
 682                                dspi->tx, !dspi->irq);
 683
 684         if (trans_mode == DSPI_EOQ_MODE)
 685                 dspi_eoq_write(dspi);
 686         else if (trans_mode == DSPI_TCFQ_MODE)
 687                 dspi_tcfq_write(dspi);
 688
 689         return -EINPROGRESS;
 690 }
 691
 692 static int dspi_poll(struct fsl_dspi *dspi)
 693 {
 694         int tries = 1000;
 695         u32 spi_sr;
 696
 697         do {
 698                 regmap_read(dspi->regmap, SPI_SR, &spi_sr);
 699                 regmap_write(dspi->regmap, SPI_SR, spi_sr);
 700
 701                 if (spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF))
 702                         break;
 703         } while (--tries);
 704
 705         if (!tries)
 706                 return -ETIMEDOUT;
 707
 708         return dspi_rxtx(dspi);
 709 }
 710
 711 static irqreturn_t dspi_interrupt(int irq, void *dev_id)
 712 {
 713         struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
 714         u32 spi_sr;
 715
 716         regmap_read(dspi->regmap, SPI_SR, &spi_sr);
 717         regmap_write(dspi->regmap, SPI_SR, spi_sr);
 718
 719         if (!(spi_sr & SPI_SR_EOQF))
 720                 return IRQ_NONE;
 721
 722         if (dspi_rxtx(dspi) == 0) {
 723                 dspi->waitflags = 1;
 724                 wake_up_interruptible(&dspi->waitq);
 725         }
 726
 727         return IRQ_HANDLED;
 728 }
 729
 730 static int dspi_transfer_one_message(struct spi_controller *ctlr,
 731                                      struct spi_message *message)
 732 {
 733         struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
 734         struct spi_device *spi = message->spi;
 735         enum dspi_trans_mode trans_mode;
 736         struct spi_transfer *transfer;
 737         int status = 0;
 738
 739         message->actual_length = 0;
 740
 741         list_for_each_entry(transfer, &message->transfers, transfer_list) {
 742                 dspi->cur_transfer = transfer;
 743                 dspi->cur_msg = message;
 744                 dspi->cur_chip = spi_get_ctldata(spi);
 745                 /* Prepare command word for CMD FIFO */
 746                 dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0) |
 747                                SPI_PUSHR_CMD_PCS(spi->chip_select);
 748                 if (list_is_last(&dspi->cur_transfer->transfer_list,
 749                                  &dspi->cur_msg->transfers)) {
 750                         /* Leave PCS activated after last transfer when
 751                          * cs_change is set.
 752                          */
 753                         if (transfer->cs_change)
 754                                 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
 755                 } else {
 756                         /* Keep PCS active between transfers in same message
 757                          * when cs_change is not set, and de-activate PCS
 758                          * between transfers in the same message when
 759                          * cs_change is set.
 760                          */
 761                         if (!transfer->cs_change)
 762                                 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
 763                 }
 764
 765                 dspi->void_write_data = dspi->cur_chip->void_write_data;
 766
 767                 dspi->tx = transfer->tx_buf;
 768                 dspi->rx = transfer->rx_buf;
 769                 dspi->rx_end = dspi->rx + transfer->len;
 770                 dspi->len = transfer->len;
 771                 /* Validated transfer specific frame size (defaults applied) */
 772                 dspi->bits_per_word = transfer->bits_per_word;
 773                 if (transfer->bits_per_word <= 8)
 774                         dspi->bytes_per_word = 1;
 775                 else if (transfer->bits_per_word <= 16)
 776                         dspi->bytes_per_word = 2;
 777                 else
 778                         dspi->bytes_per_word = 4;
 779
 780                 regmap_update_bits(dspi->regmap, SPI_MCR,
 781                                    SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
 782                                    SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
 783                 regmap_write(dspi->regmap, SPI_CTAR(0),
 784                              dspi->cur_chip->ctar_val |
 785                              SPI_FRAME_BITS(transfer->bits_per_word));
 786                 if (dspi->devtype_data->xspi_mode)
 787                         regmap_write(dspi->regmap, SPI_CTARE(0),
 788                                      SPI_FRAME_EBITS(transfer->bits_per_word) |
 789                                      SPI_CTARE_DTCP(1));
 790
 791                 spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer,
 792                                        dspi->tx, !dspi->irq);
 793
 794                 trans_mode = dspi->devtype_data->trans_mode;
 795                 switch (trans_mode) {
 796                 case DSPI_EOQ_MODE:
 797                         regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
 798                         dspi_eoq_write(dspi);
 799                         break;
 800                 case DSPI_TCFQ_MODE:
 801                         regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TCFQE);
 802                         dspi_tcfq_write(dspi);
 803                         break;
 804                 case DSPI_DMA_MODE:
 805                         regmap_write(dspi->regmap, SPI_RSER,
 806                                      SPI_RSER_TFFFE | SPI_RSER_TFFFD |
 807                                      SPI_RSER_RFDFE | SPI_RSER_RFDFD);
 808                         status = dspi_dma_xfer(dspi);
 809                         break;
 810                 default:
 811                         dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
 812                                 trans_mode);
 813                         status = -EINVAL;
 814                         goto out;
 815                 }
 816
 817                 if (!dspi->irq) {
 818                         do {
 819                                 status = dspi_poll(dspi);
 820                         } while (status == -EINPROGRESS);
 821                 } else if (trans_mode != DSPI_DMA_MODE) {
 822                         status = wait_event_interruptible(dspi->waitq,
 823                                                           dspi->waitflags);
 824                         dspi->waitflags = 0;
 825                 }
 826                 if (status)
 827                         dev_err(&dspi->pdev->dev,
 828                                 "Waiting for transfer to complete failed!\n");
 829
 830                 if (transfer->delay_usecs)
 831                         udelay(transfer->delay_usecs);
 832         }
 833
 834 out:
 835         message->status = status;
 836         spi_finalize_current_message(ctlr);
 837
 838         return status;
 839 }
 840
 841 static int dspi_setup(struct spi_device *spi)
 842 {
 843         struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller);
 844         unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
 845         u32 cs_sck_delay = 0, sck_cs_delay = 0;
 846         struct fsl_dspi_platform_data *pdata;
 847         unsigned char pasc = 0, asc = 0;
 848         struct chip_data *chip;
 849         unsigned long clkrate;
 850
 851         /* Only alloc on first setup */
 852         chip = spi_get_ctldata(spi);
 853         if (chip == NULL) {
 854                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 855                 if (!chip)
 856                         return -ENOMEM;
 857         }
 858
 859         pdata = dev_get_platdata(&dspi->pdev->dev);
 860
 861         if (!pdata) {
 862                 of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
 863                                      &cs_sck_delay);
 864
 865                 of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
 866                                      &sck_cs_delay);
 867         } else {
 868                 cs_sck_delay = pdata->cs_sck_delay;
 869                 sck_cs_delay = pdata->sck_cs_delay;
 870         }
 871
 872         chip->void_write_data = 0;
 873
 874         clkrate = clk_get_rate(dspi->clk);
 875         hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);
 876
 877         /* Set PCS to SCK delay scale values */
 878         ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate);
 879
 880         /* Set After SCK delay scale values */
 881         ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);
 882
 883         chip->ctar_val = 0;
 884         if (spi->mode & SPI_CPOL)
 885                 chip->ctar_val |= SPI_CTAR_CPOL;
 886         if (spi->mode & SPI_CPHA)
 887                 chip->ctar_val |= SPI_CTAR_CPHA;
 888
 889         if (!spi_controller_is_slave(dspi->ctlr)) {
 890                 chip->ctar_val |= SPI_CTAR_PCSSCK(pcssck) |
 891                                   SPI_CTAR_CSSCK(cssck) |
 892                                   SPI_CTAR_PASC(pasc) |
 893                                   SPI_CTAR_ASC(asc) |
 894                                   SPI_CTAR_PBR(pbr) |
 895                                   SPI_CTAR_BR(br);
 896
 897                 if (spi->mode & SPI_LSB_FIRST)
 898                         chip->ctar_val |= SPI_CTAR_LSBFE;
 899         }
 900
 901         spi_set_ctldata(spi, chip);
 902
 903         return 0;
 904 }
 905
 906 static void dspi_cleanup(struct spi_device *spi)
 907 {
 908         struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
 909
 910         dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
 911                 spi->controller->bus_num, spi->chip_select);
 912
 913         kfree(chip);
 914 }
 915
 916 static const struct of_device_id fsl_dspi_dt_ids[] = {
 917         { .compatible = "fsl,vf610-dspi", .data = &vf610_data, },
 918         { .compatible = "fsl,ls1021a-v1.0-dspi", .data = &ls1021a_v1_data, },
 919         { .compatible = "fsl,ls2085a-dspi", .data = &ls2085a_data, },
 920         { /* sentinel */ }
 921 };
 922 MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
 923
 924 #ifdef CONFIG_PM_SLEEP
 925 static int dspi_suspend(struct device *dev)
 926 {
 927         struct spi_controller *ctlr = dev_get_drvdata(dev);
 928         struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
 929
 930         spi_controller_suspend(ctlr);
 931         clk_disable_unprepare(dspi->clk);
 932
 933         pinctrl_pm_select_sleep_state(dev);
 934
 935         return 0;
 936 }
 937
 938 static int dspi_resume(struct device *dev)
 939 {
 940         struct spi_controller *ctlr = dev_get_drvdata(dev);
 941         struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
 942         int ret;
 943
 944         pinctrl_pm_select_default_state(dev);
 945
 946         ret = clk_prepare_enable(dspi->clk);
 947         if (ret)
 948                 return ret;
 949         spi_controller_resume(ctlr);
 950
 951         return 0;
 952 }
 953 #endif /* CONFIG_PM_SLEEP */
 954
 955 static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
 956
 957 static const struct regmap_range dspi_volatile_ranges[] = {
 958         regmap_reg_range(SPI_MCR, SPI_TCR),
 959         regmap_reg_range(SPI_SR, SPI_SR),
 960         regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
 961 };
 962
 963 static const struct regmap_access_table dspi_volatile_table = {
 964         .yes_ranges     = dspi_volatile_ranges,
 965         .n_yes_ranges   = ARRAY_SIZE(dspi_volatile_ranges),
 966 };
 967
 968 static const struct regmap_config dspi_regmap_config = {
 969         .reg_bits       = 32,
 970         .val_bits       = 32,
 971         .reg_stride     = 4,
 972         .max_register   = 0x88,
 973         .volatile_table = &dspi_volatile_table,
 974 };
 975
 976 static const struct regmap_range dspi_xspi_volatile_ranges[] = {
 977         regmap_reg_range(SPI_MCR, SPI_TCR),
 978         regmap_reg_range(SPI_SR, SPI_SR),
 979         regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
 980         regmap_reg_range(SPI_SREX, SPI_SREX),
 981 };
 982
 983 static const struct regmap_access_table dspi_xspi_volatile_table = {
 984         .yes_ranges     = dspi_xspi_volatile_ranges,
 985         .n_yes_ranges   = ARRAY_SIZE(dspi_xspi_volatile_ranges),
 986 };
 987
 988 static const struct regmap_config dspi_xspi_regmap_config[] = {
 989         {
 990                 .reg_bits       = 32,
 991                 .val_bits       = 32,
 992                 .reg_stride     = 4,
 993                 .max_register   = 0x13c,
 994                 .volatile_table = &dspi_xspi_volatile_table,
 995         },
 996         {
 997                 .name           = "pushr",
 998                 .reg_bits       = 16,
 999                 .val_bits       = 16,
1000                 .reg_stride     = 2,
1001                 .max_register   = 0x2,
1002         },
1003 };
1004
1005 static void dspi_init(struct fsl_dspi *dspi)
1006 {
1007         unsigned int mcr = SPI_MCR_PCSIS;
1008
1009         if (dspi->devtype_data->xspi_mode)
1010                 mcr |= SPI_MCR_XSPI;
1011         if (!spi_controller_is_slave(dspi->ctlr))
1012                 mcr |= SPI_MCR_MASTER;
1013
1014         regmap_write(dspi->regmap, SPI_MCR, mcr);
1015         regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR);
1016         if (dspi->devtype_data->xspi_mode)
1017                 regmap_write(dspi->regmap, SPI_CTARE(0),
1018                              SPI_CTARE_FMSZE(0) | SPI_CTARE_DTCP(1));
1019 }
1020
1021 static int dspi_slave_abort(struct spi_master *master)
1022 {
1023         struct fsl_dspi *dspi = spi_master_get_devdata(master);
1024
1025         /*
1026          * Terminate all pending DMA transactions for the SPI working
1027          * in SLAVE mode.
1028          */
1029         dmaengine_terminate_sync(dspi->dma->chan_rx);
1030         dmaengine_terminate_sync(dspi->dma->chan_tx);
1031
1032         /* Clear the internal DSPI RX and TX FIFO buffers */
1033         regmap_update_bits(dspi->regmap, SPI_MCR,
1034                            SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
1035                            SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
1036
1037         return 0;
1038 }
1039
1040 static int dspi_probe(struct platform_device *pdev)
1041 {
1042         struct device_node *np = pdev->dev.of_node;
1043         const struct regmap_config *regmap_config;
1044         struct fsl_dspi_platform_data *pdata;
1045         struct spi_controller *ctlr;
1046         int ret, cs_num, bus_num;
1047         struct fsl_dspi *dspi;
1048         struct resource *res;
1049         void __iomem *base;
1050
1051         ctlr = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
1052         if (!ctlr)
1053                 return -ENOMEM;
1054
1055         dspi = spi_controller_get_devdata(ctlr);
1056         dspi->pdev = pdev;
1057         dspi->ctlr = ctlr;
1058
1059         ctlr->setup = dspi_setup;
1060         ctlr->transfer_one_message = dspi_transfer_one_message;
1061         ctlr->dev.of_node = pdev->dev.of_node;
1062
1063         ctlr->cleanup = dspi_cleanup;
1064         ctlr->slave_abort = dspi_slave_abort;
1065         ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1066
1067         pdata = dev_get_platdata(&pdev->dev);
1068         if (pdata) {
1069                 ctlr->num_chipselect = pdata->cs_num;
1070                 ctlr->bus_num = pdata->bus_num;
1071
1072                 dspi->devtype_data = &coldfire_data;
1073         } else {
1074
1075                 ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
1076                 if (ret < 0) {
1077                         dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
1078                         goto out_ctlr_put;
1079                 }
1080                 ctlr->num_chipselect = cs_num;
1081
1082                 ret = of_property_read_u32(np, "bus-num", &bus_num);
1083                 if (ret < 0) {
1084                         dev_err(&pdev->dev, "can't get bus-num\n");
1085                         goto out_ctlr_put;
1086                 }
1087                 ctlr->bus_num = bus_num;
1088
1089                 if (of_property_read_bool(np, "spi-slave"))
1090                         ctlr->slave = true;
1091
1092                 dspi->devtype_data = of_device_get_match_data(&pdev->dev);
1093                 if (!dspi->devtype_data) {
1094                         dev_err(&pdev->dev, "can't get devtype_data\n");
1095                         ret = -EFAULT;
1096                         goto out_ctlr_put;
1097                 }
1098         }
1099
1100         if (dspi->devtype_data->xspi_mode)
1101                 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1102         else
1103                 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1104
1105         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1106         base = devm_ioremap_resource(&pdev->dev, res);
1107         if (IS_ERR(base)) {
1108                 ret = PTR_ERR(base);
1109                 goto out_ctlr_put;
1110         }
1111
1112         if (dspi->devtype_data->xspi_mode)
1113                 regmap_config = &dspi_xspi_regmap_config[0];
1114         else
1115                 regmap_config = &dspi_regmap_config;
1116         dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base, regmap_config);
1117         if (IS_ERR(dspi->regmap)) {
1118                 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
1119                                 PTR_ERR(dspi->regmap));
1120                 ret = PTR_ERR(dspi->regmap);
1121                 goto out_ctlr_put;
1122         }
1123
1124         if (dspi->devtype_data->xspi_mode) {
1125                 dspi->regmap_pushr = devm_regmap_init_mmio(
1126                         &pdev->dev, base + SPI_PUSHR,
1127                         &dspi_xspi_regmap_config[1]);
1128                 if (IS_ERR(dspi->regmap_pushr)) {
1129                         dev_err(&pdev->dev,
1130                                 "failed to init pushr regmap: %ld\n",
1131                                 PTR_ERR(dspi->regmap_pushr));
1132                         ret = PTR_ERR(dspi->regmap_pushr);
1133                         goto out_ctlr_put;
1134                 }
1135         }
1136
1137         dspi->clk = devm_clk_get(&pdev->dev, "dspi");
1138         if (IS_ERR(dspi->clk)) {
1139                 ret = PTR_ERR(dspi->clk);
1140                 dev_err(&pdev->dev, "unable to get clock\n");
1141                 goto out_ctlr_put;
1142         }
1143         ret = clk_prepare_enable(dspi->clk);
1144         if (ret)
1145                 goto out_ctlr_put;
1146
1147         dspi_init(dspi);
1148
1149         if (dspi->devtype_data->trans_mode == DSPI_TCFQ_MODE)
1150                 goto poll_mode;
1151
1152         dspi->irq = platform_get_irq(pdev, 0);
1153         if (dspi->irq <= 0) {
1154                 dev_info(&pdev->dev,
1155                          "can't get platform irq, using poll mode\n");
1156                 dspi->irq = 0;
1157                 goto poll_mode;
1158         }
1159
1160         ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt,
1161                                IRQF_SHARED, pdev->name, dspi);
1162         if (ret < 0) {
1163                 dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
1164                 goto out_clk_put;
1165         }
1166
1167         init_waitqueue_head(&dspi->waitq);
1168
1169 poll_mode:
1170
1171         if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
1172                 ret = dspi_request_dma(dspi, res->start);
1173                 if (ret < 0) {
1174                         dev_err(&pdev->dev, "can't get dma channels\n");
1175                         goto out_clk_put;
1176                 }
1177         }
1178
1179         ctlr->max_speed_hz =
1180                 clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
1181
1182         ctlr->ptp_sts_supported = dspi->devtype_data->ptp_sts_supported;
1183
1184         platform_set_drvdata(pdev, ctlr);
1185
1186         ret = spi_register_controller(ctlr);
1187         if (ret != 0) {
1188                 dev_err(&pdev->dev, "Problem registering DSPI ctlr\n");
1189                 goto out_clk_put;
1190         }
1191
1192         return ret;
1193
1194 out_clk_put:
1195         clk_disable_unprepare(dspi->clk);
1196 out_ctlr_put:
1197         spi_controller_put(ctlr);
1198
1199         return ret;
1200 }
1201
1202 static int dspi_remove(struct platform_device *pdev)
1203 {
1204         struct spi_controller *ctlr = platform_get_drvdata(pdev);
1205         struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
1206
1207         /* Disconnect from the SPI framework */
1208         dspi_release_dma(dspi);
1209         clk_disable_unprepare(dspi->clk);
1210         spi_unregister_controller(dspi->ctlr);
1211
1212         return 0;
1213 }
1214
1215 static struct platform_driver fsl_dspi_driver = {
1216         .driver.name            = DRIVER_NAME,
1217         .driver.of_match_table  = fsl_dspi_dt_ids,
1218         .driver.owner           = THIS_MODULE,
1219         .driver.pm              = &dspi_pm,
1220         .probe                  = dspi_probe,
1221         .remove                 = dspi_remove,
1222 };
1223 module_platform_driver(fsl_dspi_driver);
1224
1225 MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
1226 MODULE_LICENSE("GPL");
1227 MODULE_ALIAS("platform:" DRIVER_NAME);