drivers/spi/spi-fsl-dspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Copyright 2013 Freescale Semiconductor, Inc.
   4 //
   5 // Freescale DSPI driver
   6 // This file contains a driver for the Freescale DSPI
   7
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/dmaengine.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/of_device.h>
  16 #include <linux/pinctrl/consumer.h>
  17 #include <linux/regmap.h>
  18 #include <linux/spi/spi.h>
  19 #include <linux/spi/spi-fsl-dspi.h>
  20
  21 #define DRIVER_NAME                     "fsl-dspi"
  22
  23 #ifdef CONFIG_M5441x
  24 #define DSPI_FIFO_SIZE                  16
  25 #else
  26 #define DSPI_FIFO_SIZE                  4
  27 #endif
  28 #define DSPI_DMA_BUFSIZE                (DSPI_FIFO_SIZE * 1024)
  29
  30 #define SPI_MCR                         0x00
  31 #define SPI_MCR_MASTER                  BIT(31)
  32 #define SPI_MCR_PCSIS                   (0x3F << 16)
  33 #define SPI_MCR_CLR_TXF                 BIT(11)
  34 #define SPI_MCR_CLR_RXF                 BIT(10)
  35 #define SPI_MCR_XSPI                    BIT(3)
  36
  37 #define SPI_TCR                         0x08
  38 #define SPI_TCR_GET_TCNT(x)             (((x) & GENMASK(31, 16)) >> 16)
  39
  40 #define SPI_CTAR(x)                     (0x0c + (((x) & GENMASK(1, 0)) * 4))
  41 #define SPI_CTAR_FMSZ(x)                (((x) << 27) & GENMASK(30, 27))
  42 #define SPI_CTAR_CPOL                   BIT(26)
  43 #define SPI_CTAR_CPHA                   BIT(25)
  44 #define SPI_CTAR_LSBFE                  BIT(24)
  45 #define SPI_CTAR_PCSSCK(x)              (((x) << 22) & GENMASK(23, 22))
  46 #define SPI_CTAR_PASC(x)                (((x) << 20) & GENMASK(21, 20))
  47 #define SPI_CTAR_PDT(x)                 (((x) << 18) & GENMASK(19, 18))
  48 #define SPI_CTAR_PBR(x)                 (((x) << 16) & GENMASK(17, 16))
  49 #define SPI_CTAR_CSSCK(x)               (((x) << 12) & GENMASK(15, 12))
  50 #define SPI_CTAR_ASC(x)                 (((x) << 8) & GENMASK(11, 8))
  51 #define SPI_CTAR_DT(x)                  (((x) << 4) & GENMASK(7, 4))
  52 #define SPI_CTAR_BR(x)                  ((x) & GENMASK(3, 0))
  53 #define SPI_CTAR_SCALE_BITS             0xf
  54
  55 #define SPI_CTAR0_SLAVE                 0x0c
  56
  57 #define SPI_SR                          0x2c
  58 #define SPI_SR_TCFQF                    BIT(31)
  59 #define SPI_SR_EOQF                     BIT(28)
  60 #define SPI_SR_TFUF                     BIT(27)
  61 #define SPI_SR_TFFF                     BIT(25)
  62 #define SPI_SR_CMDTCF                   BIT(23)
  63 #define SPI_SR_SPEF                     BIT(21)
  64 #define SPI_SR_RFOF                     BIT(19)
  65 #define SPI_SR_TFIWF                    BIT(18)
  66 #define SPI_SR_RFDF                     BIT(17)
  67 #define SPI_SR_CMDFFF                   BIT(16)
  68 #define SPI_SR_CLEAR                    (SPI_SR_TCFQF | SPI_SR_EOQF | \
  69                                         SPI_SR_TFUF | SPI_SR_TFFF | \
  70                                         SPI_SR_CMDTCF | SPI_SR_SPEF | \
  71                                         SPI_SR_RFOF | SPI_SR_TFIWF | \
  72                                         SPI_SR_RFDF | SPI_SR_CMDFFF)
  73
  74 #define SPI_RSER_TFFFE                  BIT(25)
  75 #define SPI_RSER_TFFFD                  BIT(24)
  76 #define SPI_RSER_RFDFE                  BIT(17)
  77 #define SPI_RSER_RFDFD                  BIT(16)
  78
  79 #define SPI_RSER                        0x30
  80 #define SPI_RSER_TCFQE                  BIT(31)
  81 #define SPI_RSER_EOQFE                  BIT(28)
  82
  83 #define SPI_PUSHR                       0x34
  84 #define SPI_PUSHR_CMD_CONT              BIT(15)
  85 #define SPI_PUSHR_CMD_CTAS(x)           (((x) << 12 & GENMASK(14, 12)))
  86 #define SPI_PUSHR_CMD_EOQ               BIT(11)
  87 #define SPI_PUSHR_CMD_CTCNT             BIT(10)
  88 #define SPI_PUSHR_CMD_PCS(x)            (BIT(x) & GENMASK(5, 0))
  89
  90 #define SPI_PUSHR_SLAVE                 0x34
  91
  92 #define SPI_POPR                        0x38
  93
  94 #define SPI_TXFR0                       0x3c
  95 #define SPI_TXFR1                       0x40
  96 #define SPI_TXFR2                       0x44
  97 #define SPI_TXFR3                       0x48
  98 #define SPI_RXFR0                       0x7c
  99 #define SPI_RXFR1                       0x80
 100 #define SPI_RXFR2                       0x84
 101 #define SPI_RXFR3                       0x88
 102
 103 #define SPI_CTARE(x)                    (0x11c + (((x) & GENMASK(1, 0)) * 4))
 104 #define SPI_CTARE_FMSZE(x)              (((x) & 0x1) << 16)
 105 #define SPI_CTARE_DTCP(x)               ((x) & 0x7ff)
 106
 107 #define SPI_SREX                        0x13c
 108
 109 #define SPI_FRAME_BITS(bits)            SPI_CTAR_FMSZ((bits) - 1)
 110 #define SPI_FRAME_EBITS(bits)           SPI_CTARE_FMSZE(((bits) - 1) >> 4)
 111
 112 /* Register offsets for regmap_pushr */
 113 #define PUSHR_CMD                       0x0
 114 #define PUSHR_TX                        0x2
 115
 116 #define DMA_COMPLETION_TIMEOUT          msecs_to_jiffies(3000)
 117
 118 struct chip_data {
 119         u32                     ctar_val;
 120         u16                     void_write_data;
 121 };
 122
 123 enum dspi_trans_mode {
 124         DSPI_EOQ_MODE = 0,
 125         DSPI_TCFQ_MODE,
 126         DSPI_DMA_MODE,
 127 };
 128
 129 struct fsl_dspi_devtype_data {
 130         enum dspi_trans_mode    trans_mode;
 131         u8                      max_clock_factor;
 132         bool                    xspi_mode;
 133 };
 134
 135 static const struct fsl_dspi_devtype_data vf610_data = {
 136         .trans_mode             = DSPI_DMA_MODE,
 137         .max_clock_factor       = 2,
 138 };
 139
 140 static const struct fsl_dspi_devtype_data ls1021a_v1_data = {
 141         .trans_mode             = DSPI_TCFQ_MODE,
 142         .max_clock_factor       = 8,
 143         .xspi_mode              = true,
 144 };
 145
 146 static const struct fsl_dspi_devtype_data ls2085a_data = {
 147         .trans_mode             = DSPI_TCFQ_MODE,
 148         .max_clock_factor       = 8,
 149 };
 150
 151 static const struct fsl_dspi_devtype_data coldfire_data = {
 152         .trans_mode             = DSPI_EOQ_MODE,
 153         .max_clock_factor       = 8,
 154 };
 155
 156 struct fsl_dspi_dma {
 157         /* Length of transfer in words of DSPI_FIFO_SIZE */
 158         u32                                     curr_xfer_len;
 159
 160         u32                                     *tx_dma_buf;
 161         struct dma_chan                         *chan_tx;
 162         dma_addr_t                              tx_dma_phys;
 163         struct completion                       cmd_tx_complete;
 164         struct dma_async_tx_descriptor          *tx_desc;
 165
 166         u32                                     *rx_dma_buf;
 167         struct dma_chan                         *chan_rx;
 168         dma_addr_t                              rx_dma_phys;
 169         struct completion                       cmd_rx_complete;
 170         struct dma_async_tx_descriptor          *rx_desc;
 171 };
 172
 173 struct fsl_dspi {
 174         struct spi_master                       *master;
 175         struct platform_device                  *pdev;
 176
 177         struct regmap                           *regmap;
 178         struct regmap                           *regmap_pushr;
 179         int                                     irq;
 180         struct clk                              *clk;
 181
 182         struct spi_transfer                     *cur_transfer;
 183         struct spi_message                      *cur_msg;
 184         struct chip_data                        *cur_chip;
 185         size_t                                  len;
 186         const void                              *tx;
 187         void                                    *rx;
 188         void                                    *rx_end;
 189         u16                                     void_write_data;
 190         u16                                     tx_cmd;
 191         u8                                      bits_per_word;
 192         u8                                      bytes_per_word;
 193         const struct fsl_dspi_devtype_data      *devtype_data;
 194
 195         wait_queue_head_t                       waitq;
 196         u32                                     waitflags;
 197
 198         struct fsl_dspi_dma                     *dma;
 199 };
 200
 201 static u32 dspi_pop_tx(struct fsl_dspi *dspi)
 202 {
 203         u32 txdata = 0;
 204
 205         if (dspi->tx) {
 206                 if (dspi->bytes_per_word == 1)
 207                         txdata = *(u8 *)dspi->tx;
 208                 else if (dspi->bytes_per_word == 2)
 209                         txdata = *(u16 *)dspi->tx;
 210                 else  /* dspi->bytes_per_word == 4 */
 211                         txdata = *(u32 *)dspi->tx;
 212                 dspi->tx += dspi->bytes_per_word;
 213         }
 214         dspi->len -= dspi->bytes_per_word;
 215         return txdata;
 216 }
 217
 218 static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi)
 219 {
 220         u16 cmd = dspi->tx_cmd, data = dspi_pop_tx(dspi);
 221
 222         if (spi_controller_is_slave(dspi->master))
 223                 return data;
 224
 225         if (dspi->len > 0)
 226                 cmd |= SPI_PUSHR_CMD_CONT;
 227         return cmd << 16 | data;
 228 }
 229
 230 static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata)
 231 {
 232         if (!dspi->rx)
 233                 return;
 234
 235         /* Mask of undefined bits */
 236         rxdata &= (1 << dspi->bits_per_word) - 1;
 237
 238         if (dspi->bytes_per_word == 1)
 239                 *(u8 *)dspi->rx = rxdata;
 240         else if (dspi->bytes_per_word == 2)
 241                 *(u16 *)dspi->rx = rxdata;
 242         else /* dspi->bytes_per_word == 4 */
 243                 *(u32 *)dspi->rx = rxdata;
 244         dspi->rx += dspi->bytes_per_word;
 245 }
 246
 247 static void dspi_tx_dma_callback(void *arg)
 248 {
 249         struct fsl_dspi *dspi = arg;
 250         struct fsl_dspi_dma *dma = dspi->dma;
 251
 252         complete(&dma->cmd_tx_complete);
 253 }
 254
 255 static void dspi_rx_dma_callback(void *arg)
 256 {
 257         struct fsl_dspi *dspi = arg;
 258         struct fsl_dspi_dma *dma = dspi->dma;
 259         int i;
 260
 261         if (dspi->rx) {
 262                 for (i = 0; i < dma->curr_xfer_len; i++)
 263                         dspi_push_rx(dspi, dspi->dma->rx_dma_buf[i]);
 264         }
 265
 266         complete(&dma->cmd_rx_complete);
 267 }
 268
 269 static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
 270 {
 271         struct fsl_dspi_dma *dma = dspi->dma;
 272         struct device *dev = &dspi->pdev->dev;
 273         int time_left;
 274         int i;
 275
 276         for (i = 0; i < dma->curr_xfer_len; i++)
 277                 dspi->dma->tx_dma_buf[i] = dspi_pop_tx_pushr(dspi);
 278
 279         dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx,
 280                                         dma->tx_dma_phys,
 281                                         dma->curr_xfer_len *
 282                                         DMA_SLAVE_BUSWIDTH_4_BYTES,
 283                                         DMA_MEM_TO_DEV,
 284                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 285         if (!dma->tx_desc) {
 286                 dev_err(dev, "Not able to get desc for DMA xfer\n");
 287                 return -EIO;
 288         }
 289
 290         dma->tx_desc->callback = dspi_tx_dma_callback;
 291         dma->tx_desc->callback_param = dspi;
 292         if (dma_submit_error(dmaengine_submit(dma->tx_desc))) {
 293                 dev_err(dev, "DMA submit failed\n");
 294                 return -EINVAL;
 295         }
 296
 297         dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx,
 298                                         dma->rx_dma_phys,
 299                                         dma->curr_xfer_len *
 300                                         DMA_SLAVE_BUSWIDTH_4_BYTES,
 301                                         DMA_DEV_TO_MEM,
 302                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 303         if (!dma->rx_desc) {
 304                 dev_err(dev, "Not able to get desc for DMA xfer\n");
 305                 return -EIO;
 306         }
 307
 308         dma->rx_desc->callback = dspi_rx_dma_callback;
 309         dma->rx_desc->callback_param = dspi;
 310         if (dma_submit_error(dmaengine_submit(dma->rx_desc))) {
 311                 dev_err(dev, "DMA submit failed\n");
 312                 return -EINVAL;
 313         }
 314
 315         reinit_completion(&dspi->dma->cmd_rx_complete);
 316         reinit_completion(&dspi->dma->cmd_tx_complete);
 317
 318         dma_async_issue_pending(dma->chan_rx);
 319         dma_async_issue_pending(dma->chan_tx);
 320
 321         if (spi_controller_is_slave(dspi->master)) {
 322                 wait_for_completion_interruptible(&dspi->dma->cmd_rx_complete);
 323                 return 0;
 324         }
 325
 326         time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete,
 327                                                 DMA_COMPLETION_TIMEOUT);
 328         if (time_left == 0) {
 329                 dev_err(dev, "DMA tx timeout\n");
 330                 dmaengine_terminate_all(dma->chan_tx);
 331                 dmaengine_terminate_all(dma->chan_rx);
 332                 return -ETIMEDOUT;
 333         }
 334
 335         time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete,
 336                                                 DMA_COMPLETION_TIMEOUT);
 337         if (time_left == 0) {
 338                 dev_err(dev, "DMA rx timeout\n");
 339                 dmaengine_terminate_all(dma->chan_tx);
 340                 dmaengine_terminate_all(dma->chan_rx);
 341                 return -ETIMEDOUT;
 342         }
 343
 344         return 0;
 345 }
 346
 347 static int dspi_dma_xfer(struct fsl_dspi *dspi)
 348 {
 349         struct fsl_dspi_dma *dma = dspi->dma;
 350         struct device *dev = &dspi->pdev->dev;
 351         struct spi_message *message = dspi->cur_msg;
 352         int curr_remaining_bytes;
 353         int bytes_per_buffer;
 354         int ret = 0;
 355
 356         curr_remaining_bytes = dspi->len;
 357         bytes_per_buffer = DSPI_DMA_BUFSIZE / DSPI_FIFO_SIZE;
 358         while (curr_remaining_bytes) {
 359                 /* Check if current transfer fits the DMA buffer */
 360                 dma->curr_xfer_len = curr_remaining_bytes
 361                         / dspi->bytes_per_word;
 362                 if (dma->curr_xfer_len > bytes_per_buffer)
 363                         dma->curr_xfer_len = bytes_per_buffer;
 364
 365                 ret = dspi_next_xfer_dma_submit(dspi);
 366                 if (ret) {
 367                         dev_err(dev, "DMA transfer failed\n");
 368                         goto exit;
 369
 370                 } else {
 371                         const int len =
 372                                 dma->curr_xfer_len * dspi->bytes_per_word;
 373                         curr_remaining_bytes -= len;
 374                         message->actual_length += len;
 375                         if (curr_remaining_bytes < 0)
 376                                 curr_remaining_bytes = 0;
 377                 }
 378         }
 379
 380 exit:
 381         return ret;
 382 }
 383
 384 static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr)
 385 {
 386         struct fsl_dspi_dma *dma;
 387         struct dma_slave_config cfg;
 388         struct device *dev = &dspi->pdev->dev;
 389         int ret;
 390
 391         dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
 392         if (!dma)
 393                 return -ENOMEM;
 394
 395         dma->chan_rx = dma_request_slave_channel(dev, "rx");
 396         if (!dma->chan_rx) {
 397                 dev_err(dev, "rx dma channel not available\n");
 398                 ret = -ENODEV;
 399                 return ret;
 400         }
 401
 402         dma->chan_tx = dma_request_slave_channel(dev, "tx");
 403         if (!dma->chan_tx) {
 404                 dev_err(dev, "tx dma channel not available\n");
 405                 ret = -ENODEV;
 406                 goto err_tx_channel;
 407         }
 408
 409         dma->tx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
 410                                              &dma->tx_dma_phys, GFP_KERNEL);
 411         if (!dma->tx_dma_buf) {
 412                 ret = -ENOMEM;
 413                 goto err_tx_dma_buf;
 414         }
 415
 416         dma->rx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
 417                                              &dma->rx_dma_phys, GFP_KERNEL);
 418         if (!dma->rx_dma_buf) {
 419                 ret = -ENOMEM;
 420                 goto err_rx_dma_buf;
 421         }
 422
 423         cfg.src_addr = phy_addr + SPI_POPR;
 424         cfg.dst_addr = phy_addr + SPI_PUSHR;
 425         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 426         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 427         cfg.src_maxburst = 1;
 428         cfg.dst_maxburst = 1;
 429
 430         cfg.direction = DMA_DEV_TO_MEM;
 431         ret = dmaengine_slave_config(dma->chan_rx, &cfg);
 432         if (ret) {
 433                 dev_err(dev, "can't configure rx dma channel\n");
 434                 ret = -EINVAL;
 435                 goto err_slave_config;
 436         }
 437
 438         cfg.direction = DMA_MEM_TO_DEV;
 439         ret = dmaengine_slave_config(dma->chan_tx, &cfg);
 440         if (ret) {
 441                 dev_err(dev, "can't configure tx dma channel\n");
 442                 ret = -EINVAL;
 443                 goto err_slave_config;
 444         }
 445
 446         dspi->dma = dma;
 447         init_completion(&dma->cmd_tx_complete);
 448         init_completion(&dma->cmd_rx_complete);
 449
 450         return 0;
 451
 452 err_slave_config:
 453         dma_free_coherent(dev, DSPI_DMA_BUFSIZE,
 454                         dma->rx_dma_buf, dma->rx_dma_phys);
 455 err_rx_dma_buf:
 456         dma_free_coherent(dev, DSPI_DMA_BUFSIZE,
 457                         dma->tx_dma_buf, dma->tx_dma_phys);
 458 err_tx_dma_buf:
 459         dma_release_channel(dma->chan_tx);
 460 err_tx_channel:
 461         dma_release_channel(dma->chan_rx);
 462
 463         devm_kfree(dev, dma);
 464         dspi->dma = NULL;
 465
 466         return ret;
 467 }
 468
 469 static void dspi_release_dma(struct fsl_dspi *dspi)
 470 {
 471         struct fsl_dspi_dma *dma = dspi->dma;
 472         struct device *dev = &dspi->pdev->dev;
 473
 474         if (!dma)
 475                 return;
 476
 477         if (dma->chan_tx) {
 478                 dma_unmap_single(dev, dma->tx_dma_phys,
 479                                  DSPI_DMA_BUFSIZE, DMA_TO_DEVICE);
 480                 dma_release_channel(dma->chan_tx);
 481         }
 482
 483         if (dma->chan_rx) {
 484                 dma_unmap_single(dev, dma->rx_dma_phys,
 485                                  DSPI_DMA_BUFSIZE, DMA_FROM_DEVICE);
 486                 dma_release_channel(dma->chan_rx);
 487         }
 488 }
 489
 490 static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
 491                            unsigned long clkrate)
 492 {
 493         /* Valid baud rate pre-scaler values */
 494         int pbr_tbl[4] = {2, 3, 5, 7};
 495         int brs[16] = { 2,      4,      6,      8,
 496                         16,     32,     64,     128,
 497                         256,    512,    1024,   2048,
 498                         4096,   8192,   16384,  32768 };
 499         int scale_needed, scale, minscale = INT_MAX;
 500         int i, j;
 501
 502         scale_needed = clkrate / speed_hz;
 503         if (clkrate % speed_hz)
 504                 scale_needed++;
 505
 506         for (i = 0; i < ARRAY_SIZE(brs); i++)
 507                 for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) {
 508                         scale = brs[i] * pbr_tbl[j];
 509                         if (scale >= scale_needed) {
 510                                 if (scale < minscale) {
 511                                         minscale = scale;
 512                                         *br = i;
 513                                         *pbr = j;
 514                                 }
 515                                 break;
 516                         }
 517                 }
 518
 519         if (minscale == INT_MAX) {
 520                 pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n",
 521                         speed_hz, clkrate);
 522                 *pbr = ARRAY_SIZE(pbr_tbl) - 1;
 523                 *br =  ARRAY_SIZE(brs) - 1;
 524         }
 525 }
 526
 527 static void ns_delay_scale(char *psc, char *sc, int delay_ns,
 528                            unsigned long clkrate)
 529 {
 530         int pscale_tbl[4] = {1, 3, 5, 7};
 531         int scale_needed, scale, minscale = INT_MAX;
 532         int i, j;
 533         u32 remainder;
 534
 535         scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
 536                                    &remainder);
 537         if (remainder)
 538                 scale_needed++;
 539
 540         for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
 541                 for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) {
 542                         scale = pscale_tbl[i] * (2 << j);
 543                         if (scale >= scale_needed) {
 544                                 if (scale < minscale) {
 545                                         minscale = scale;
 546                                         *psc = i;
 547                                         *sc = j;
 548                                 }
 549                                 break;
 550                         }
 551                 }
 552
 553         if (minscale == INT_MAX) {
 554                 pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
 555                         delay_ns, clkrate);
 556                 *psc = ARRAY_SIZE(pscale_tbl) - 1;
 557                 *sc = SPI_CTAR_SCALE_BITS;
 558         }
 559 }
 560
 561 static void fifo_write(struct fsl_dspi *dspi)
 562 {
 563         regmap_write(dspi->regmap, SPI_PUSHR, dspi_pop_tx_pushr(dspi));
 564 }
 565
 566 static void cmd_fifo_write(struct fsl_dspi *dspi)
 567 {
 568         u16 cmd = dspi->tx_cmd;
 569
 570         if (dspi->len > 0)
 571                 cmd |= SPI_PUSHR_CMD_CONT;
 572         regmap_write(dspi->regmap_pushr, PUSHR_CMD, cmd);
 573 }
 574
 575 static void tx_fifo_write(struct fsl_dspi *dspi, u16 txdata)
 576 {
 577         regmap_write(dspi->regmap_pushr, PUSHR_TX, txdata);
 578 }
 579
 580 static void dspi_tcfq_write(struct fsl_dspi *dspi)
 581 {
 582         /* Clear transfer count */
 583         dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT;
 584
 585         if (dspi->devtype_data->xspi_mode && dspi->bits_per_word > 16) {
 586                 /* Write two TX FIFO entries first, and then the corresponding
 587                  * CMD FIFO entry.
 588                  */
 589                 u32 data = dspi_pop_tx(dspi);
 590
 591                 if (dspi->cur_chip->ctar_val & SPI_CTAR_LSBFE) {
 592                         /* LSB */
 593                         tx_fifo_write(dspi, data & 0xFFFF);
 594                         tx_fifo_write(dspi, data >> 16);
 595                 } else {
 596                         /* MSB */
 597                         tx_fifo_write(dspi, data >> 16);
 598                         tx_fifo_write(dspi, data & 0xFFFF);
 599                 }
 600                 cmd_fifo_write(dspi);
 601         } else {
 602                 /* Write one entry to both TX FIFO and CMD FIFO
 603                  * simultaneously.
 604                  */
 605                 fifo_write(dspi);
 606         }
 607 }
 608
 609 static u32 fifo_read(struct fsl_dspi *dspi)
 610 {
 611         u32 rxdata = 0;
 612
 613         regmap_read(dspi->regmap, SPI_POPR, &rxdata);
 614         return rxdata;
 615 }
 616
 617 static void dspi_tcfq_read(struct fsl_dspi *dspi)
 618 {
 619         dspi_push_rx(dspi, fifo_read(dspi));
 620 }
 621
 622 static void dspi_eoq_write(struct fsl_dspi *dspi)
 623 {
 624         int fifo_size = DSPI_FIFO_SIZE;
 625         u16 xfer_cmd = dspi->tx_cmd;
 626
 627         /* Fill TX FIFO with as many transfers as possible */
 628         while (dspi->len && fifo_size--) {
 629                 dspi->tx_cmd = xfer_cmd;
 630                 /* Request EOQF for last transfer in FIFO */
 631                 if (dspi->len == dspi->bytes_per_word || fifo_size == 0)
 632                         dspi->tx_cmd |= SPI_PUSHR_CMD_EOQ;
 633                 /* Clear transfer count for first transfer in FIFO */
 634                 if (fifo_size == (DSPI_FIFO_SIZE - 1))
 635                         dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT;
 636                 /* Write combined TX FIFO and CMD FIFO entry */
 637                 fifo_write(dspi);
 638         }
 639 }
 640
 641 static void dspi_eoq_read(struct fsl_dspi *dspi)
 642 {
 643         int fifo_size = DSPI_FIFO_SIZE;
 644
 645         /* Read one FIFO entry at and push to rx buffer */
 646         while ((dspi->rx < dspi->rx_end) && fifo_size--)
 647                 dspi_push_rx(dspi, fifo_read(dspi));
 648 }
 649
 650 static int dspi_transfer_one_message(struct spi_master *master,
 651                                      struct spi_message *message)
 652 {
 653         struct fsl_dspi *dspi = spi_master_get_devdata(master);
 654         struct spi_device *spi = message->spi;
 655         struct spi_transfer *transfer;
 656         int status = 0;
 657         enum dspi_trans_mode trans_mode;
 658
 659         message->actual_length = 0;
 660
 661         list_for_each_entry(transfer, &message->transfers, transfer_list) {
 662                 dspi->cur_transfer = transfer;
 663                 dspi->cur_msg = message;
 664                 dspi->cur_chip = spi_get_ctldata(spi);
 665                 /* Prepare command word for CMD FIFO */
 666                 dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0) |
 667                                SPI_PUSHR_CMD_PCS(spi->chip_select);
 668                 if (list_is_last(&dspi->cur_transfer->transfer_list,
 669                                  &dspi->cur_msg->transfers)) {
 670                         /* Leave PCS activated after last transfer when
 671                          * cs_change is set.
 672                          */
 673                         if (transfer->cs_change)
 674                                 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
 675                 } else {
 676                         /* Keep PCS active between transfers in same message
 677                          * when cs_change is not set, and de-activate PCS
 678                          * between transfers in the same message when
 679                          * cs_change is set.
 680                          */
 681                         if (!transfer->cs_change)
 682                                 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
 683                 }
 684
 685                 dspi->void_write_data = dspi->cur_chip->void_write_data;
 686
 687                 dspi->tx = transfer->tx_buf;
 688                 dspi->rx = transfer->rx_buf;
 689                 dspi->rx_end = dspi->rx + transfer->len;
 690                 dspi->len = transfer->len;
 691                 /* Validated transfer specific frame size (defaults applied) */
 692                 dspi->bits_per_word = transfer->bits_per_word;
 693                 if (transfer->bits_per_word <= 8)
 694                         dspi->bytes_per_word = 1;
 695                 else if (transfer->bits_per_word <= 16)
 696                         dspi->bytes_per_word = 2;
 697                 else
 698                         dspi->bytes_per_word = 4;
 699
 700                 regmap_update_bits(dspi->regmap, SPI_MCR,
 701                                    SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
 702                                    SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
 703                 regmap_write(dspi->regmap, SPI_CTAR(0),
 704                              dspi->cur_chip->ctar_val |
 705                              SPI_FRAME_BITS(transfer->bits_per_word));
 706                 if (dspi->devtype_data->xspi_mode)
 707                         regmap_write(dspi->regmap, SPI_CTARE(0),
 708                                      SPI_FRAME_EBITS(transfer->bits_per_word) |
 709                                      SPI_CTARE_DTCP(1));
 710
 711                 trans_mode = dspi->devtype_data->trans_mode;
 712                 switch (trans_mode) {
 713                 case DSPI_EOQ_MODE:
 714                         regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
 715                         dspi_eoq_write(dspi);
 716                         break;
 717                 case DSPI_TCFQ_MODE:
 718                         regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TCFQE);
 719                         dspi_tcfq_write(dspi);
 720                         break;
 721                 case DSPI_DMA_MODE:
 722                         regmap_write(dspi->regmap, SPI_RSER,
 723                                      SPI_RSER_TFFFE | SPI_RSER_TFFFD |
 724                                      SPI_RSER_RFDFE | SPI_RSER_RFDFD);
 725                         status = dspi_dma_xfer(dspi);
 726                         break;
 727                 default:
 728                         dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
 729                                 trans_mode);
 730                         status = -EINVAL;
 731                         goto out;
 732                 }
 733
 734                 if (trans_mode != DSPI_DMA_MODE) {
 735                         if (wait_event_interruptible(dspi->waitq,
 736                                                      dspi->waitflags))
 737                                 dev_err(&dspi->pdev->dev,
 738                                         "wait transfer complete fail!\n");
 739                         dspi->waitflags = 0;
 740                 }
 741
 742                 if (transfer->delay_usecs)
 743                         udelay(transfer->delay_usecs);
 744         }
 745
 746 out:
 747         message->status = status;
 748         spi_finalize_current_message(master);
 749
 750         return status;
 751 }
 752
 753 static int dspi_setup(struct spi_device *spi)
 754 {
 755         struct chip_data *chip;
 756         struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
 757         struct fsl_dspi_platform_data *pdata;
 758         u32 cs_sck_delay = 0, sck_cs_delay = 0;
 759         unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
 760         unsigned char pasc = 0, asc = 0;
 761         unsigned long clkrate;
 762
 763         /* Only alloc on first setup */
 764         chip = spi_get_ctldata(spi);
 765         if (chip == NULL) {
 766                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 767                 if (!chip)
 768                         return -ENOMEM;
 769         }
 770
 771         pdata = dev_get_platdata(&dspi->pdev->dev);
 772
 773         if (!pdata) {
 774                 of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
 775                                      &cs_sck_delay);
 776
 777                 of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
 778                                      &sck_cs_delay);
 779         } else {
 780                 cs_sck_delay = pdata->cs_sck_delay;
 781                 sck_cs_delay = pdata->sck_cs_delay;
 782         }
 783
 784         chip->void_write_data = 0;
 785
 786         clkrate = clk_get_rate(dspi->clk);
 787         hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);
 788
 789         /* Set PCS to SCK delay scale values */
 790         ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate);
 791
 792         /* Set After SCK delay scale values */
 793         ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);
 794
 795         chip->ctar_val = 0;
 796         if (spi->mode & SPI_CPOL)
 797                 chip->ctar_val |= SPI_CTAR_CPOL;
 798         if (spi->mode & SPI_CPHA)
 799                 chip->ctar_val |= SPI_CTAR_CPHA;
 800
 801         if (!spi_controller_is_slave(dspi->master)) {
 802                 chip->ctar_val |= SPI_CTAR_PCSSCK(pcssck) |
 803                                   SPI_CTAR_CSSCK(cssck) |
 804                                   SPI_CTAR_PASC(pasc) |
 805                                   SPI_CTAR_ASC(asc) |
 806                                   SPI_CTAR_PBR(pbr) |
 807                                   SPI_CTAR_BR(br);
 808
 809                 if (spi->mode & SPI_LSB_FIRST)
 810                         chip->ctar_val |= SPI_CTAR_LSBFE;
 811         }
 812
 813         spi_set_ctldata(spi, chip);
 814
 815         return 0;
 816 }
 817
 818 static void dspi_cleanup(struct spi_device *spi)
 819 {
 820         struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
 821
 822         dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
 823                 spi->master->bus_num, spi->chip_select);
 824
 825         kfree(chip);
 826 }
 827
 828 static irqreturn_t dspi_interrupt(int irq, void *dev_id)
 829 {
 830         struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
 831         struct spi_message *msg = dspi->cur_msg;
 832         enum dspi_trans_mode trans_mode;
 833         u32 spi_sr, spi_tcr;
 834         u16 spi_tcnt;
 835
 836         regmap_read(dspi->regmap, SPI_SR, &spi_sr);
 837         regmap_write(dspi->regmap, SPI_SR, spi_sr);
 838
 839
 840         if (spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF)) {
 841                 /* Get transfer counter (in number of SPI transfers). It was
 842                  * reset to 0 when transfer(s) were started.
 843                  */
 844                 regmap_read(dspi->regmap, SPI_TCR, &spi_tcr);
 845                 spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr);
 846                 /* Update total number of bytes that were transferred */
 847                 msg->actual_length += spi_tcnt * dspi->bytes_per_word;
 848
 849                 trans_mode = dspi->devtype_data->trans_mode;
 850                 switch (trans_mode) {
 851                 case DSPI_EOQ_MODE:
 852                         dspi_eoq_read(dspi);
 853                         break;
 854                 case DSPI_TCFQ_MODE:
 855                         dspi_tcfq_read(dspi);
 856                         break;
 857                 default:
 858                         dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
 859                                 trans_mode);
 860                                 return IRQ_HANDLED;
 861                 }
 862
 863                 if (!dspi->len) {
 864                         dspi->waitflags = 1;
 865                         wake_up_interruptible(&dspi->waitq);
 866                 } else {
 867                         switch (trans_mode) {
 868                         case DSPI_EOQ_MODE:
 869                                 dspi_eoq_write(dspi);
 870                                 break;
 871                         case DSPI_TCFQ_MODE:
 872                                 dspi_tcfq_write(dspi);
 873                                 break;
 874                         default:
 875                                 dev_err(&dspi->pdev->dev,
 876                                         "unsupported trans_mode %u\n",
 877                                         trans_mode);
 878                         }
 879                 }
 880         }
 881
 882         return IRQ_HANDLED;
 883 }
 884
 885 static const struct of_device_id fsl_dspi_dt_ids[] = {
 886         { .compatible = "fsl,vf610-dspi", .data = &vf610_data, },
 887         { .compatible = "fsl,ls1021a-v1.0-dspi", .data = &ls1021a_v1_data, },
 888         { .compatible = "fsl,ls2085a-dspi", .data = &ls2085a_data, },
 889         { /* sentinel */ }
 890 };
 891 MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
 892
 893 #ifdef CONFIG_PM_SLEEP
 894 static int dspi_suspend(struct device *dev)
 895 {
 896         struct spi_master *master = dev_get_drvdata(dev);
 897         struct fsl_dspi *dspi = spi_master_get_devdata(master);
 898
 899         spi_master_suspend(master);
 900         clk_disable_unprepare(dspi->clk);
 901
 902         pinctrl_pm_select_sleep_state(dev);
 903
 904         return 0;
 905 }
 906
 907 static int dspi_resume(struct device *dev)
 908 {
 909         struct spi_master *master = dev_get_drvdata(dev);
 910         struct fsl_dspi *dspi = spi_master_get_devdata(master);
 911         int ret;
 912
 913         pinctrl_pm_select_default_state(dev);
 914
 915         ret = clk_prepare_enable(dspi->clk);
 916         if (ret)
 917                 return ret;
 918         spi_master_resume(master);
 919
 920         return 0;
 921 }
 922 #endif /* CONFIG_PM_SLEEP */
 923
 924 static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
 925
 926 static const struct regmap_range dspi_volatile_ranges[] = {
 927         regmap_reg_range(SPI_MCR, SPI_TCR),
 928         regmap_reg_range(SPI_SR, SPI_SR),
 929         regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
 930 };
 931
 932 static const struct regmap_access_table dspi_volatile_table = {
 933         .yes_ranges     = dspi_volatile_ranges,
 934         .n_yes_ranges   = ARRAY_SIZE(dspi_volatile_ranges),
 935 };
 936
 937 static const struct regmap_config dspi_regmap_config = {
 938         .reg_bits       = 32,
 939         .val_bits       = 32,
 940         .reg_stride     = 4,
 941         .max_register   = 0x88,
 942         .volatile_table = &dspi_volatile_table,
 943 };
 944
 945 static const struct regmap_range dspi_xspi_volatile_ranges[] = {
 946         regmap_reg_range(SPI_MCR, SPI_TCR),
 947         regmap_reg_range(SPI_SR, SPI_SR),
 948         regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
 949         regmap_reg_range(SPI_SREX, SPI_SREX),
 950 };
 951
 952 static const struct regmap_access_table dspi_xspi_volatile_table = {
 953         .yes_ranges     = dspi_xspi_volatile_ranges,
 954         .n_yes_ranges   = ARRAY_SIZE(dspi_xspi_volatile_ranges),
 955 };
 956
 957 static const struct regmap_config dspi_xspi_regmap_config[] = {
 958         {
 959                 .reg_bits       = 32,
 960                 .val_bits       = 32,
 961                 .reg_stride     = 4,
 962                 .max_register   = 0x13c,
 963                 .volatile_table = &dspi_xspi_volatile_table,
 964         },
 965         {
 966                 .name           = "pushr",
 967                 .reg_bits       = 16,
 968                 .val_bits       = 16,
 969                 .reg_stride     = 2,
 970                 .max_register   = 0x2,
 971         },
 972 };
 973
 974 static void dspi_init(struct fsl_dspi *dspi)
 975 {
 976         unsigned int mcr = SPI_MCR_PCSIS;
 977
 978         if (dspi->devtype_data->xspi_mode)
 979                 mcr |= SPI_MCR_XSPI;
 980         if (!spi_controller_is_slave(dspi->master))
 981                 mcr |= SPI_MCR_MASTER;
 982
 983         regmap_write(dspi->regmap, SPI_MCR, mcr);
 984         regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR);
 985         if (dspi->devtype_data->xspi_mode)
 986                 regmap_write(dspi->regmap, SPI_CTARE(0),
 987                              SPI_CTARE_FMSZE(0) | SPI_CTARE_DTCP(1));
 988 }
 989
 990 static int dspi_probe(struct platform_device *pdev)
 991 {
 992         struct device_node *np = pdev->dev.of_node;
 993         struct spi_master *master;
 994         struct fsl_dspi *dspi;
 995         struct resource *res;
 996         const struct regmap_config *regmap_config;
 997         void __iomem *base;
 998         struct fsl_dspi_platform_data *pdata;
 999         int ret, cs_num, bus_num;
1000
1001         master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
1002         if (!master)
1003                 return -ENOMEM;
1004
1005         dspi = spi_master_get_devdata(master);
1006         dspi->pdev = pdev;
1007         dspi->master = master;
1008
1009         master->setup = dspi_setup;
1010         master->transfer_one_message = dspi_transfer_one_message;
1011         master->dev.of_node = pdev->dev.of_node;
1012
1013         master->cleanup = dspi_cleanup;
1014         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1015
1016         pdata = dev_get_platdata(&pdev->dev);
1017         if (pdata) {
1018                 master->num_chipselect = pdata->cs_num;
1019                 master->bus_num = pdata->bus_num;
1020
1021                 dspi->devtype_data = &coldfire_data;
1022         } else {
1023
1024                 ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
1025                 if (ret < 0) {
1026                         dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
1027                         goto out_master_put;
1028                 }
1029                 master->num_chipselect = cs_num;
1030
1031                 ret = of_property_read_u32(np, "bus-num", &bus_num);
1032                 if (ret < 0) {
1033                         dev_err(&pdev->dev, "can't get bus-num\n");
1034                         goto out_master_put;
1035                 }
1036                 master->bus_num = bus_num;
1037
1038                 if (of_property_read_bool(np, "spi-slave"))
1039                         master->slave = true;
1040
1041                 dspi->devtype_data = of_device_get_match_data(&pdev->dev);
1042                 if (!dspi->devtype_data) {
1043                         dev_err(&pdev->dev, "can't get devtype_data\n");
1044                         ret = -EFAULT;
1045                         goto out_master_put;
1046                 }
1047         }
1048
1049         if (dspi->devtype_data->xspi_mode)
1050                 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1051         else
1052                 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1053
1054         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1055         base = devm_ioremap_resource(&pdev->dev, res);
1056         if (IS_ERR(base)) {
1057                 ret = PTR_ERR(base);
1058                 goto out_master_put;
1059         }
1060
1061         if (dspi->devtype_data->xspi_mode)
1062                 regmap_config = &dspi_xspi_regmap_config[0];
1063         else
1064                 regmap_config = &dspi_regmap_config;
1065         dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base, regmap_config);
1066         if (IS_ERR(dspi->regmap)) {
1067                 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
1068                                 PTR_ERR(dspi->regmap));
1069                 ret = PTR_ERR(dspi->regmap);
1070                 goto out_master_put;
1071         }
1072
1073         if (dspi->devtype_data->xspi_mode) {
1074                 dspi->regmap_pushr = devm_regmap_init_mmio(
1075                         &pdev->dev, base + SPI_PUSHR,
1076                         &dspi_xspi_regmap_config[1]);
1077                 if (IS_ERR(dspi->regmap_pushr)) {
1078                         dev_err(&pdev->dev,
1079                                 "failed to init pushr regmap: %ld\n",
1080                                 PTR_ERR(dspi->regmap_pushr));
1081                         ret = PTR_ERR(dspi->regmap_pushr);
1082                         goto out_master_put;
1083                 }
1084         }
1085
1086         dspi->clk = devm_clk_get(&pdev->dev, "dspi");
1087         if (IS_ERR(dspi->clk)) {
1088                 ret = PTR_ERR(dspi->clk);
1089                 dev_err(&pdev->dev, "unable to get clock\n");
1090                 goto out_master_put;
1091         }
1092         ret = clk_prepare_enable(dspi->clk);
1093         if (ret)
1094                 goto out_master_put;
1095
1096         dspi_init(dspi);
1097         dspi->irq = platform_get_irq(pdev, 0);
1098         if (dspi->irq < 0) {
1099                 ret = dspi->irq;
1100                 goto out_clk_put;
1101         }
1102
1103         ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt,
1104                                IRQF_SHARED, pdev->name, dspi);
1105         if (ret < 0) {
1106                 dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
1107                 goto out_clk_put;
1108         }
1109
1110         if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
1111                 ret = dspi_request_dma(dspi, res->start);
1112                 if (ret < 0) {
1113                         dev_err(&pdev->dev, "can't get dma channels\n");
1114                         goto out_clk_put;
1115                 }
1116         }
1117
1118         master->max_speed_hz =
1119                 clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
1120
1121         init_waitqueue_head(&dspi->waitq);
1122         platform_set_drvdata(pdev, master);
1123
1124         ret = spi_register_master(master);
1125         if (ret != 0) {
1126                 dev_err(&pdev->dev, "Problem registering DSPI master\n");
1127                 goto out_clk_put;
1128         }
1129
1130         return ret;
1131
1132 out_clk_put:
1133         clk_disable_unprepare(dspi->clk);
1134 out_master_put:
1135         spi_master_put(master);
1136
1137         return ret;
1138 }
1139
1140 static int dspi_remove(struct platform_device *pdev)
1141 {
1142         struct spi_master *master = platform_get_drvdata(pdev);
1143         struct fsl_dspi *dspi = spi_master_get_devdata(master);
1144
1145         /* Disconnect from the SPI framework */
1146         dspi_release_dma(dspi);
1147         clk_disable_unprepare(dspi->clk);
1148         spi_unregister_master(dspi->master);
1149
1150         return 0;
1151 }
1152
1153 static struct platform_driver fsl_dspi_driver = {
1154         .driver.name            = DRIVER_NAME,
1155         .driver.of_match_table  = fsl_dspi_dt_ids,
1156         .driver.owner           = THIS_MODULE,
1157         .driver.pm              = &dspi_pm,
1158         .probe                  = dspi_probe,
1159         .remove                 = dspi_remove,
1160 };
1161 module_platform_driver(fsl_dspi_driver);
1162
1163 MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
1164 MODULE_LICENSE("GPL");
1165 MODULE_ALIAS("platform:" DRIVER_NAME);