1 // SPDX-License-Identifier: GPL-2.0+
3 // Freescale i.MX7ULP LPSPI driver
5 // Copyright 2016 Freescale Semiconductor, Inc.
6 // Copyright 2018 NXP Semiconductors
9 #include <linux/completion.h>
10 #include <linux/delay.h>
11 #include <linux/err.h>
12 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/slab.h>
21 #include <linux/spi/spi.h>
22 #include <linux/spi/spi_bitbang.h>
23 #include <linux/types.h>
25 #define DRIVER_NAME "fsl_lpspi"
27 /* i.MX7ULP LPSPI registers */
28 #define IMX7ULP_VERID 0x0
29 #define IMX7ULP_PARAM 0x4
30 #define IMX7ULP_CR 0x10
31 #define IMX7ULP_SR 0x14
32 #define IMX7ULP_IER 0x18
33 #define IMX7ULP_DER 0x1c
34 #define IMX7ULP_CFGR0 0x20
35 #define IMX7ULP_CFGR1 0x24
36 #define IMX7ULP_DMR0 0x30
37 #define IMX7ULP_DMR1 0x34
38 #define IMX7ULP_CCR 0x40
39 #define IMX7ULP_FCR 0x58
40 #define IMX7ULP_FSR 0x5c
41 #define IMX7ULP_TCR 0x60
42 #define IMX7ULP_TDR 0x64
43 #define IMX7ULP_RSR 0x70
44 #define IMX7ULP_RDR 0x74
46 /* General control register field define */
51 #define SR_TCF BIT(10)
54 #define IER_TCIE BIT(10)
55 #define IER_RDIE BIT(1)
56 #define IER_TDIE BIT(0)
57 #define CFGR1_PCSCFG BIT(27)
58 #define CFGR1_PINCFG (BIT(24)|BIT(25))
59 #define CFGR1_PCSPOL BIT(8)
60 #define CFGR1_NOSTALL BIT(3)
61 #define CFGR1_MASTER BIT(0)
62 #define RSR_RXEMPTY BIT(1)
63 #define TCR_CPOL BIT(31)
64 #define TCR_CPHA BIT(30)
65 #define TCR_CONT BIT(21)
66 #define TCR_CONTC BIT(20)
67 #define TCR_RXMSK BIT(19)
68 #define TCR_TXMSK BIT(18)
70 static int clkdivs[] = {1, 2, 4, 8, 16, 32, 64, 128};
80 struct fsl_lpspi_data {
88 void (*tx)(struct fsl_lpspi_data *);
89 void (*rx)(struct fsl_lpspi_data *);
96 struct lpspi_config config;
97 struct completion xfer_done;
102 static const struct of_device_id fsl_lpspi_dt_ids[] = {
103 { .compatible = "fsl,imx7ulp-spi", },
106 MODULE_DEVICE_TABLE(of, fsl_lpspi_dt_ids);
108 #define LPSPI_BUF_RX(type) \
109 static void fsl_lpspi_buf_rx_##type(struct fsl_lpspi_data *fsl_lpspi) \
111 unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \
113 if (fsl_lpspi->rx_buf) { \
114 *(type *)fsl_lpspi->rx_buf = val; \
115 fsl_lpspi->rx_buf += sizeof(type); \
119 #define LPSPI_BUF_TX(type) \
120 static void fsl_lpspi_buf_tx_##type(struct fsl_lpspi_data *fsl_lpspi) \
124 if (fsl_lpspi->tx_buf) { \
125 val = *(type *)fsl_lpspi->tx_buf; \
126 fsl_lpspi->tx_buf += sizeof(type); \
129 fsl_lpspi->remain -= sizeof(type); \
130 writel(val, fsl_lpspi->base + IMX7ULP_TDR); \
140 static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi,
143 writel(enable, fsl_lpspi->base + IMX7ULP_IER);
146 static int lpspi_prepare_xfer_hardware(struct spi_controller *controller)
148 struct fsl_lpspi_data *fsl_lpspi =
149 spi_controller_get_devdata(controller);
151 return clk_prepare_enable(fsl_lpspi->clk);
154 static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller)
156 struct fsl_lpspi_data *fsl_lpspi =
157 spi_controller_get_devdata(controller);
159 clk_disable_unprepare(fsl_lpspi->clk);
164 static int fsl_lpspi_txfifo_empty(struct fsl_lpspi_data *fsl_lpspi)
167 unsigned long orig_jiffies = jiffies;
170 txcnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
172 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
173 dev_dbg(fsl_lpspi->dev, "txfifo empty timeout\n");
183 static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi)
187 txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
189 while (txfifo_cnt < fsl_lpspi->txfifosize) {
190 if (!fsl_lpspi->remain)
192 fsl_lpspi->tx(fsl_lpspi);
196 if (!fsl_lpspi->remain && (txfifo_cnt < fsl_lpspi->txfifosize))
197 writel(0, fsl_lpspi->base + IMX7ULP_TDR);
199 fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE);
202 static void fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data *fsl_lpspi)
204 while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY))
205 fsl_lpspi->rx(fsl_lpspi);
208 static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi,
213 temp |= fsl_lpspi->config.bpw - 1;
214 temp |= (fsl_lpspi->config.mode & 0x3) << 30;
215 if (!fsl_lpspi->is_slave) {
216 temp |= fsl_lpspi->config.prescale << 27;
217 temp |= (fsl_lpspi->config.chip_select & 0x3) << 24;
220 * Set TCR_CONT will keep SS asserted after current transfer.
221 * For the first transfer, clear TCR_CONTC to assert SS.
222 * For subsequent transfer, set TCR_CONTC to keep SS asserted.
230 writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
232 dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp);
235 static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi)
239 temp = fsl_lpspi->watermark >> 1 | (fsl_lpspi->watermark >> 1) << 16;
241 writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
243 dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp);
246 static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
248 struct lpspi_config config = fsl_lpspi->config;
249 unsigned int perclk_rate, scldiv;
252 perclk_rate = clk_get_rate(fsl_lpspi->clk);
253 for (prescale = 0; prescale < 8; prescale++) {
254 scldiv = perclk_rate /
255 (clkdivs[prescale] * config.speed_hz) - 2;
257 fsl_lpspi->config.prescale = prescale;
262 if (prescale == 8 && scldiv >= 256)
265 writel(scldiv | (scldiv << 8) | ((scldiv >> 1) << 16),
266 fsl_lpspi->base + IMX7ULP_CCR);
268 dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale =%d, scldiv=%d\n",
269 perclk_rate, config.speed_hz, prescale, scldiv);
274 static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
280 writel(temp, fsl_lpspi->base + IMX7ULP_CR);
281 writel(0, fsl_lpspi->base + IMX7ULP_CR);
283 if (!fsl_lpspi->is_slave) {
284 ret = fsl_lpspi_set_bitrate(fsl_lpspi);
289 fsl_lpspi_set_watermark(fsl_lpspi);
291 if (!fsl_lpspi->is_slave)
295 if (fsl_lpspi->config.mode & SPI_CS_HIGH)
296 temp |= CFGR1_PCSPOL;
297 writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
299 temp = readl(fsl_lpspi->base + IMX7ULP_CR);
300 temp |= CR_RRF | CR_RTF | CR_MEN;
301 writel(temp, fsl_lpspi->base + IMX7ULP_CR);
306 static void fsl_lpspi_setup_transfer(struct spi_device *spi,
307 struct spi_transfer *t)
309 struct fsl_lpspi_data *fsl_lpspi =
310 spi_controller_get_devdata(spi->controller);
312 fsl_lpspi->config.mode = spi->mode;
313 fsl_lpspi->config.bpw = t ? t->bits_per_word : spi->bits_per_word;
314 fsl_lpspi->config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
315 fsl_lpspi->config.chip_select = spi->chip_select;
317 if (!fsl_lpspi->config.speed_hz)
318 fsl_lpspi->config.speed_hz = spi->max_speed_hz;
319 if (!fsl_lpspi->config.bpw)
320 fsl_lpspi->config.bpw = spi->bits_per_word;
322 /* Initialize the functions for transfer */
323 if (fsl_lpspi->config.bpw <= 8) {
324 fsl_lpspi->rx = fsl_lpspi_buf_rx_u8;
325 fsl_lpspi->tx = fsl_lpspi_buf_tx_u8;
326 } else if (fsl_lpspi->config.bpw <= 16) {
327 fsl_lpspi->rx = fsl_lpspi_buf_rx_u16;
328 fsl_lpspi->tx = fsl_lpspi_buf_tx_u16;
330 fsl_lpspi->rx = fsl_lpspi_buf_rx_u32;
331 fsl_lpspi->tx = fsl_lpspi_buf_tx_u32;
334 if (t->len <= fsl_lpspi->txfifosize)
335 fsl_lpspi->watermark = t->len;
337 fsl_lpspi->watermark = fsl_lpspi->txfifosize;
339 fsl_lpspi_config(fsl_lpspi);
342 static int fsl_lpspi_slave_abort(struct spi_controller *controller)
344 struct fsl_lpspi_data *fsl_lpspi =
345 spi_controller_get_devdata(controller);
347 fsl_lpspi->slave_aborted = true;
348 complete(&fsl_lpspi->xfer_done);
352 static int fsl_lpspi_wait_for_completion(struct spi_controller *controller)
354 struct fsl_lpspi_data *fsl_lpspi =
355 spi_controller_get_devdata(controller);
357 if (fsl_lpspi->is_slave) {
358 if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) ||
359 fsl_lpspi->slave_aborted) {
360 dev_dbg(fsl_lpspi->dev, "interrupted\n");
364 if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) {
365 dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n");
373 static int fsl_lpspi_transfer_one(struct spi_controller *controller,
374 struct spi_device *spi,
375 struct spi_transfer *t)
377 struct fsl_lpspi_data *fsl_lpspi =
378 spi_controller_get_devdata(controller);
381 fsl_lpspi->tx_buf = t->tx_buf;
382 fsl_lpspi->rx_buf = t->rx_buf;
383 fsl_lpspi->remain = t->len;
385 reinit_completion(&fsl_lpspi->xfer_done);
386 fsl_lpspi->slave_aborted = false;
388 fsl_lpspi_write_tx_fifo(fsl_lpspi);
390 ret = fsl_lpspi_wait_for_completion(controller);
394 ret = fsl_lpspi_txfifo_empty(fsl_lpspi);
398 fsl_lpspi_read_rx_fifo(fsl_lpspi);
403 static int fsl_lpspi_transfer_one_msg(struct spi_controller *controller,
404 struct spi_message *msg)
406 struct fsl_lpspi_data *fsl_lpspi =
407 spi_controller_get_devdata(controller);
408 struct spi_device *spi = msg->spi;
409 struct spi_transfer *xfer;
410 bool is_first_xfer = true;
415 msg->actual_length = 0;
417 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
418 fsl_lpspi_setup_transfer(spi, xfer);
419 fsl_lpspi_set_cmd(fsl_lpspi, is_first_xfer);
421 is_first_xfer = false;
423 ret = fsl_lpspi_transfer_one(controller, spi, xfer);
427 msg->actual_length += xfer->len;
431 if (!fsl_lpspi->is_slave) {
432 /* de-assert SS, then finalize current message */
433 temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
435 writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
439 spi_finalize_current_message(controller);
444 static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id)
446 struct fsl_lpspi_data *fsl_lpspi = dev_id;
449 fsl_lpspi_intctrl(fsl_lpspi, 0);
450 temp = readl(fsl_lpspi->base + IMX7ULP_SR);
452 fsl_lpspi_read_rx_fifo(fsl_lpspi);
455 fsl_lpspi_write_tx_fifo(fsl_lpspi);
457 if (!fsl_lpspi->remain)
458 complete(&fsl_lpspi->xfer_done);
466 static int fsl_lpspi_probe(struct platform_device *pdev)
468 struct fsl_lpspi_data *fsl_lpspi;
469 struct spi_controller *controller;
470 struct resource *res;
474 if (of_property_read_bool((&pdev->dev)->of_node, "spi-slave"))
475 controller = spi_alloc_slave(&pdev->dev,
476 sizeof(struct fsl_lpspi_data));
478 controller = spi_alloc_master(&pdev->dev,
479 sizeof(struct fsl_lpspi_data));
484 platform_set_drvdata(pdev, controller);
486 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
487 controller->bus_num = pdev->id;
489 fsl_lpspi = spi_controller_get_devdata(controller);
490 fsl_lpspi->dev = &pdev->dev;
491 fsl_lpspi->is_slave = of_property_read_bool((&pdev->dev)->of_node,
494 controller->transfer_one_message = fsl_lpspi_transfer_one_msg;
495 controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware;
496 controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware;
497 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
498 controller->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
499 controller->dev.of_node = pdev->dev.of_node;
500 controller->bus_num = pdev->id;
501 controller->slave_abort = fsl_lpspi_slave_abort;
503 init_completion(&fsl_lpspi->xfer_done);
505 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
506 fsl_lpspi->base = devm_ioremap_resource(&pdev->dev, res);
507 if (IS_ERR(fsl_lpspi->base)) {
508 ret = PTR_ERR(fsl_lpspi->base);
509 goto out_controller_put;
512 irq = platform_get_irq(pdev, 0);
515 goto out_controller_put;
518 ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, 0,
519 dev_name(&pdev->dev), fsl_lpspi);
521 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
522 goto out_controller_put;
525 fsl_lpspi->clk = devm_clk_get(&pdev->dev, "ipg");
526 if (IS_ERR(fsl_lpspi->clk)) {
527 ret = PTR_ERR(fsl_lpspi->clk);
528 goto out_controller_put;
531 ret = clk_prepare_enable(fsl_lpspi->clk);
533 dev_err(&pdev->dev, "can't enable lpspi clock, ret=%d\n", ret);
534 goto out_controller_put;
537 temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
538 fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
539 fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
541 clk_disable_unprepare(fsl_lpspi->clk);
543 ret = devm_spi_register_controller(&pdev->dev, controller);
545 dev_err(&pdev->dev, "spi_register_controller error.\n");
546 goto out_controller_put;
552 spi_controller_put(controller);
557 static int fsl_lpspi_remove(struct platform_device *pdev)
559 struct spi_controller *controller = platform_get_drvdata(pdev);
560 struct fsl_lpspi_data *fsl_lpspi =
561 spi_controller_get_devdata(controller);
563 clk_disable_unprepare(fsl_lpspi->clk);
568 static struct platform_driver fsl_lpspi_driver = {
571 .of_match_table = fsl_lpspi_dt_ids,
573 .probe = fsl_lpspi_probe,
574 .remove = fsl_lpspi_remove,
576 module_platform_driver(fsl_lpspi_driver);
578 MODULE_DESCRIPTION("LPSPI Controller driver");
579 MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>");
580 MODULE_LICENSE("GPL");