1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Leilk Liu <leilk.liu@mediatek.com>
8 #include <linux/device.h>
10 #include <linux/interrupt.h>
12 #include <linux/ioport.h>
13 #include <linux/module.h>
15 #include <linux/of_gpio.h>
16 #include <linux/platform_device.h>
17 #include <linux/platform_data/spi-mt65xx.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/spi/spi.h>
20 #include <linux/dma-mapping.h>
22 #define SPI_CFG0_REG 0x0000
23 #define SPI_CFG1_REG 0x0004
24 #define SPI_TX_SRC_REG 0x0008
25 #define SPI_RX_DST_REG 0x000c
26 #define SPI_TX_DATA_REG 0x0010
27 #define SPI_RX_DATA_REG 0x0014
28 #define SPI_CMD_REG 0x0018
29 #define SPI_STATUS0_REG 0x001c
30 #define SPI_PAD_SEL_REG 0x0024
31 #define SPI_CFG2_REG 0x0028
32 #define SPI_TX_SRC_REG_64 0x002c
33 #define SPI_RX_DST_REG_64 0x0030
35 #define SPI_CFG0_SCK_HIGH_OFFSET 0
36 #define SPI_CFG0_SCK_LOW_OFFSET 8
37 #define SPI_CFG0_CS_HOLD_OFFSET 16
38 #define SPI_CFG0_CS_SETUP_OFFSET 24
39 #define SPI_ADJUST_CFG0_SCK_LOW_OFFSET 16
40 #define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0
41 #define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16
43 #define SPI_CFG1_CS_IDLE_OFFSET 0
44 #define SPI_CFG1_PACKET_LOOP_OFFSET 8
45 #define SPI_CFG1_PACKET_LENGTH_OFFSET 16
46 #define SPI_CFG1_GET_TICK_DLY_OFFSET 30
48 #define SPI_CFG1_CS_IDLE_MASK 0xff
49 #define SPI_CFG1_PACKET_LOOP_MASK 0xff00
50 #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
52 #define SPI_CMD_ACT BIT(0)
53 #define SPI_CMD_RESUME BIT(1)
54 #define SPI_CMD_RST BIT(2)
55 #define SPI_CMD_PAUSE_EN BIT(4)
56 #define SPI_CMD_DEASSERT BIT(5)
57 #define SPI_CMD_SAMPLE_SEL BIT(6)
58 #define SPI_CMD_CS_POL BIT(7)
59 #define SPI_CMD_CPHA BIT(8)
60 #define SPI_CMD_CPOL BIT(9)
61 #define SPI_CMD_RX_DMA BIT(10)
62 #define SPI_CMD_TX_DMA BIT(11)
63 #define SPI_CMD_TXMSBF BIT(12)
64 #define SPI_CMD_RXMSBF BIT(13)
65 #define SPI_CMD_RX_ENDIAN BIT(14)
66 #define SPI_CMD_TX_ENDIAN BIT(15)
67 #define SPI_CMD_FINISH_IE BIT(16)
68 #define SPI_CMD_PAUSE_IE BIT(17)
70 #define MT8173_SPI_MAX_PAD_SEL 3
72 #define MTK_SPI_PAUSE_INT_STATUS 0x2
74 #define MTK_SPI_IDLE 0
75 #define MTK_SPI_PAUSED 1
77 #define MTK_SPI_MAX_FIFO_SIZE 32U
78 #define MTK_SPI_PACKET_SIZE 1024
79 #define MTK_SPI_32BITS_MASK (0xffffffff)
81 #define DMA_ADDR_EXT_BITS (36)
82 #define DMA_ADDR_DEF_BITS (32)
84 struct mtk_spi_compatible {
86 /* Must explicitly send dummy Tx bytes to do Rx only transfer */
88 /* some IC design adjust cfg register to enhance time accuracy */
90 /* some IC support DMA addr extension */
99 struct clk *parent_clk, *sel_clk, *spi_clk;
100 struct spi_transfer *cur_transfer;
103 struct scatterlist *tx_sgl, *rx_sgl;
104 u32 tx_sgl_len, rx_sgl_len;
105 const struct mtk_spi_compatible *dev_comp;
108 static const struct mtk_spi_compatible mtk_common_compat;
110 static const struct mtk_spi_compatible mt2712_compat = {
114 static const struct mtk_spi_compatible mt6765_compat = {
115 .need_pad_sel = true,
117 .enhance_timing = true,
121 static const struct mtk_spi_compatible mt7622_compat = {
123 .enhance_timing = true,
126 static const struct mtk_spi_compatible mt8173_compat = {
127 .need_pad_sel = true,
131 static const struct mtk_spi_compatible mt8183_compat = {
132 .need_pad_sel = true,
134 .enhance_timing = true,
138 * A piece of default chip info unless the platform
141 static const struct mtk_chip_config mtk_default_chip_info = {
146 static const struct of_device_id mtk_spi_of_match[] = {
147 { .compatible = "mediatek,mt2701-spi",
148 .data = (void *)&mtk_common_compat,
150 { .compatible = "mediatek,mt2712-spi",
151 .data = (void *)&mt2712_compat,
153 { .compatible = "mediatek,mt6589-spi",
154 .data = (void *)&mtk_common_compat,
156 { .compatible = "mediatek,mt6765-spi",
157 .data = (void *)&mt6765_compat,
159 { .compatible = "mediatek,mt7622-spi",
160 .data = (void *)&mt7622_compat,
162 { .compatible = "mediatek,mt7629-spi",
163 .data = (void *)&mt7622_compat,
165 { .compatible = "mediatek,mt8135-spi",
166 .data = (void *)&mtk_common_compat,
168 { .compatible = "mediatek,mt8173-spi",
169 .data = (void *)&mt8173_compat,
171 { .compatible = "mediatek,mt8183-spi",
172 .data = (void *)&mt8183_compat,
176 MODULE_DEVICE_TABLE(of, mtk_spi_of_match);
178 static void mtk_spi_reset(struct mtk_spi *mdata)
182 /* set the software reset bit in SPI_CMD_REG. */
183 reg_val = readl(mdata->base + SPI_CMD_REG);
184 reg_val |= SPI_CMD_RST;
185 writel(reg_val, mdata->base + SPI_CMD_REG);
187 reg_val = readl(mdata->base + SPI_CMD_REG);
188 reg_val &= ~SPI_CMD_RST;
189 writel(reg_val, mdata->base + SPI_CMD_REG);
192 static int mtk_spi_prepare_message(struct spi_master *master,
193 struct spi_message *msg)
197 struct spi_device *spi = msg->spi;
198 struct mtk_chip_config *chip_config = spi->controller_data;
199 struct mtk_spi *mdata = spi_master_get_devdata(master);
201 cpha = spi->mode & SPI_CPHA ? 1 : 0;
202 cpol = spi->mode & SPI_CPOL ? 1 : 0;
204 reg_val = readl(mdata->base + SPI_CMD_REG);
206 reg_val |= SPI_CMD_CPHA;
208 reg_val &= ~SPI_CMD_CPHA;
210 reg_val |= SPI_CMD_CPOL;
212 reg_val &= ~SPI_CMD_CPOL;
214 /* set the mlsbx and mlsbtx */
215 if (spi->mode & SPI_LSB_FIRST) {
216 reg_val &= ~SPI_CMD_TXMSBF;
217 reg_val &= ~SPI_CMD_RXMSBF;
219 reg_val |= SPI_CMD_TXMSBF;
220 reg_val |= SPI_CMD_RXMSBF;
223 /* set the tx/rx endian */
224 #ifdef __LITTLE_ENDIAN
225 reg_val &= ~SPI_CMD_TX_ENDIAN;
226 reg_val &= ~SPI_CMD_RX_ENDIAN;
228 reg_val |= SPI_CMD_TX_ENDIAN;
229 reg_val |= SPI_CMD_RX_ENDIAN;
232 if (mdata->dev_comp->enhance_timing) {
233 if (chip_config->cs_pol)
234 reg_val |= SPI_CMD_CS_POL;
236 reg_val &= ~SPI_CMD_CS_POL;
237 if (chip_config->sample_sel)
238 reg_val |= SPI_CMD_SAMPLE_SEL;
240 reg_val &= ~SPI_CMD_SAMPLE_SEL;
243 /* set finish and pause interrupt always enable */
244 reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE;
246 /* disable dma mode */
247 reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
249 /* disable deassert mode */
250 reg_val &= ~SPI_CMD_DEASSERT;
252 writel(reg_val, mdata->base + SPI_CMD_REG);
255 if (mdata->dev_comp->need_pad_sel)
256 writel(mdata->pad_sel[spi->chip_select],
257 mdata->base + SPI_PAD_SEL_REG);
262 static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
265 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
267 reg_val = readl(mdata->base + SPI_CMD_REG);
269 reg_val |= SPI_CMD_PAUSE_EN;
270 writel(reg_val, mdata->base + SPI_CMD_REG);
272 reg_val &= ~SPI_CMD_PAUSE_EN;
273 writel(reg_val, mdata->base + SPI_CMD_REG);
274 mdata->state = MTK_SPI_IDLE;
275 mtk_spi_reset(mdata);
279 static void mtk_spi_prepare_transfer(struct spi_master *master,
280 struct spi_transfer *xfer)
282 u32 spi_clk_hz, div, sck_time, cs_time, reg_val = 0;
283 struct mtk_spi *mdata = spi_master_get_devdata(master);
285 spi_clk_hz = clk_get_rate(mdata->spi_clk);
286 if (xfer->speed_hz < spi_clk_hz / 2)
287 div = DIV_ROUND_UP(spi_clk_hz, xfer->speed_hz);
291 sck_time = (div + 1) / 2;
292 cs_time = sck_time * 2;
294 if (mdata->dev_comp->enhance_timing) {
295 reg_val |= (((sck_time - 1) & 0xffff)
296 << SPI_CFG0_SCK_HIGH_OFFSET);
297 reg_val |= (((sck_time - 1) & 0xffff)
298 << SPI_ADJUST_CFG0_SCK_LOW_OFFSET);
299 writel(reg_val, mdata->base + SPI_CFG2_REG);
300 reg_val |= (((cs_time - 1) & 0xffff)
301 << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
302 reg_val |= (((cs_time - 1) & 0xffff)
303 << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
304 writel(reg_val, mdata->base + SPI_CFG0_REG);
306 reg_val |= (((sck_time - 1) & 0xff)
307 << SPI_CFG0_SCK_HIGH_OFFSET);
308 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
309 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
310 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET);
311 writel(reg_val, mdata->base + SPI_CFG0_REG);
314 reg_val = readl(mdata->base + SPI_CFG1_REG);
315 reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
316 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
317 writel(reg_val, mdata->base + SPI_CFG1_REG);
320 static void mtk_spi_setup_packet(struct spi_master *master)
322 u32 packet_size, packet_loop, reg_val;
323 struct mtk_spi *mdata = spi_master_get_devdata(master);
325 packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE);
326 packet_loop = mdata->xfer_len / packet_size;
328 reg_val = readl(mdata->base + SPI_CFG1_REG);
329 reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK);
330 reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
331 reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
332 writel(reg_val, mdata->base + SPI_CFG1_REG);
335 static void mtk_spi_enable_transfer(struct spi_master *master)
338 struct mtk_spi *mdata = spi_master_get_devdata(master);
340 cmd = readl(mdata->base + SPI_CMD_REG);
341 if (mdata->state == MTK_SPI_IDLE)
344 cmd |= SPI_CMD_RESUME;
345 writel(cmd, mdata->base + SPI_CMD_REG);
348 static int mtk_spi_get_mult_delta(u32 xfer_len)
352 if (xfer_len > MTK_SPI_PACKET_SIZE)
353 mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
360 static void mtk_spi_update_mdata_len(struct spi_master *master)
363 struct mtk_spi *mdata = spi_master_get_devdata(master);
365 if (mdata->tx_sgl_len && mdata->rx_sgl_len) {
366 if (mdata->tx_sgl_len > mdata->rx_sgl_len) {
367 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
368 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
369 mdata->rx_sgl_len = mult_delta;
370 mdata->tx_sgl_len -= mdata->xfer_len;
372 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
373 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
374 mdata->tx_sgl_len = mult_delta;
375 mdata->rx_sgl_len -= mdata->xfer_len;
377 } else if (mdata->tx_sgl_len) {
378 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
379 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
380 mdata->tx_sgl_len = mult_delta;
381 } else if (mdata->rx_sgl_len) {
382 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
383 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
384 mdata->rx_sgl_len = mult_delta;
388 static void mtk_spi_setup_dma_addr(struct spi_master *master,
389 struct spi_transfer *xfer)
391 struct mtk_spi *mdata = spi_master_get_devdata(master);
394 writel((u32)(xfer->tx_dma & MTK_SPI_32BITS_MASK),
395 mdata->base + SPI_TX_SRC_REG);
396 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
397 if (mdata->dev_comp->dma_ext)
398 writel((u32)(xfer->tx_dma >> 32),
399 mdata->base + SPI_TX_SRC_REG_64);
404 writel((u32)(xfer->rx_dma & MTK_SPI_32BITS_MASK),
405 mdata->base + SPI_RX_DST_REG);
406 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
407 if (mdata->dev_comp->dma_ext)
408 writel((u32)(xfer->rx_dma >> 32),
409 mdata->base + SPI_RX_DST_REG_64);
414 static int mtk_spi_fifo_transfer(struct spi_master *master,
415 struct spi_device *spi,
416 struct spi_transfer *xfer)
420 struct mtk_spi *mdata = spi_master_get_devdata(master);
422 mdata->cur_transfer = xfer;
423 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len);
424 mdata->num_xfered = 0;
425 mtk_spi_prepare_transfer(master, xfer);
426 mtk_spi_setup_packet(master);
429 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
431 remainder = xfer->len % 4;
434 memcpy(®_val, xfer->tx_buf + (cnt * 4), remainder);
435 writel(reg_val, mdata->base + SPI_TX_DATA_REG);
438 mtk_spi_enable_transfer(master);
443 static int mtk_spi_dma_transfer(struct spi_master *master,
444 struct spi_device *spi,
445 struct spi_transfer *xfer)
448 struct mtk_spi *mdata = spi_master_get_devdata(master);
450 mdata->tx_sgl = NULL;
451 mdata->rx_sgl = NULL;
452 mdata->tx_sgl_len = 0;
453 mdata->rx_sgl_len = 0;
454 mdata->cur_transfer = xfer;
455 mdata->num_xfered = 0;
457 mtk_spi_prepare_transfer(master, xfer);
459 cmd = readl(mdata->base + SPI_CMD_REG);
461 cmd |= SPI_CMD_TX_DMA;
463 cmd |= SPI_CMD_RX_DMA;
464 writel(cmd, mdata->base + SPI_CMD_REG);
467 mdata->tx_sgl = xfer->tx_sg.sgl;
469 mdata->rx_sgl = xfer->rx_sg.sgl;
472 xfer->tx_dma = sg_dma_address(mdata->tx_sgl);
473 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
476 xfer->rx_dma = sg_dma_address(mdata->rx_sgl);
477 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
480 mtk_spi_update_mdata_len(master);
481 mtk_spi_setup_packet(master);
482 mtk_spi_setup_dma_addr(master, xfer);
483 mtk_spi_enable_transfer(master);
488 static int mtk_spi_transfer_one(struct spi_master *master,
489 struct spi_device *spi,
490 struct spi_transfer *xfer)
492 if (master->can_dma(master, spi, xfer))
493 return mtk_spi_dma_transfer(master, spi, xfer);
495 return mtk_spi_fifo_transfer(master, spi, xfer);
498 static bool mtk_spi_can_dma(struct spi_master *master,
499 struct spi_device *spi,
500 struct spi_transfer *xfer)
502 /* Buffers for DMA transactions must be 4-byte aligned */
503 return (xfer->len > MTK_SPI_MAX_FIFO_SIZE &&
504 (unsigned long)xfer->tx_buf % 4 == 0 &&
505 (unsigned long)xfer->rx_buf % 4 == 0);
508 static int mtk_spi_setup(struct spi_device *spi)
510 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
512 if (!spi->controller_data)
513 spi->controller_data = (void *)&mtk_default_chip_info;
515 if (mdata->dev_comp->need_pad_sel && gpio_is_valid(spi->cs_gpio))
516 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
521 static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
523 u32 cmd, reg_val, cnt, remainder, len;
524 struct spi_master *master = dev_id;
525 struct mtk_spi *mdata = spi_master_get_devdata(master);
526 struct spi_transfer *trans = mdata->cur_transfer;
528 reg_val = readl(mdata->base + SPI_STATUS0_REG);
529 if (reg_val & MTK_SPI_PAUSE_INT_STATUS)
530 mdata->state = MTK_SPI_PAUSED;
532 mdata->state = MTK_SPI_IDLE;
534 if (!master->can_dma(master, master->cur_msg->spi, trans)) {
536 cnt = mdata->xfer_len / 4;
537 ioread32_rep(mdata->base + SPI_RX_DATA_REG,
538 trans->rx_buf + mdata->num_xfered, cnt);
539 remainder = mdata->xfer_len % 4;
541 reg_val = readl(mdata->base + SPI_RX_DATA_REG);
542 memcpy(trans->rx_buf +
550 mdata->num_xfered += mdata->xfer_len;
551 if (mdata->num_xfered == trans->len) {
552 spi_finalize_current_transfer(master);
556 len = trans->len - mdata->num_xfered;
557 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, len);
558 mtk_spi_setup_packet(master);
560 cnt = mdata->xfer_len / 4;
561 iowrite32_rep(mdata->base + SPI_TX_DATA_REG,
562 trans->tx_buf + mdata->num_xfered, cnt);
564 remainder = mdata->xfer_len % 4;
568 trans->tx_buf + (cnt * 4) + mdata->num_xfered,
570 writel(reg_val, mdata->base + SPI_TX_DATA_REG);
573 mtk_spi_enable_transfer(master);
579 trans->tx_dma += mdata->xfer_len;
581 trans->rx_dma += mdata->xfer_len;
583 if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) {
584 mdata->tx_sgl = sg_next(mdata->tx_sgl);
586 trans->tx_dma = sg_dma_address(mdata->tx_sgl);
587 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
590 if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) {
591 mdata->rx_sgl = sg_next(mdata->rx_sgl);
593 trans->rx_dma = sg_dma_address(mdata->rx_sgl);
594 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
598 if (!mdata->tx_sgl && !mdata->rx_sgl) {
599 /* spi disable dma */
600 cmd = readl(mdata->base + SPI_CMD_REG);
601 cmd &= ~SPI_CMD_TX_DMA;
602 cmd &= ~SPI_CMD_RX_DMA;
603 writel(cmd, mdata->base + SPI_CMD_REG);
605 spi_finalize_current_transfer(master);
609 mtk_spi_update_mdata_len(master);
610 mtk_spi_setup_packet(master);
611 mtk_spi_setup_dma_addr(master, trans);
612 mtk_spi_enable_transfer(master);
617 static int mtk_spi_probe(struct platform_device *pdev)
619 struct spi_master *master;
620 struct mtk_spi *mdata;
621 const struct of_device_id *of_id;
622 int i, irq, ret, addr_bits;
624 master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
626 dev_err(&pdev->dev, "failed to alloc spi master\n");
630 master->auto_runtime_pm = true;
631 master->dev.of_node = pdev->dev.of_node;
632 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
634 master->set_cs = mtk_spi_set_cs;
635 master->prepare_message = mtk_spi_prepare_message;
636 master->transfer_one = mtk_spi_transfer_one;
637 master->can_dma = mtk_spi_can_dma;
638 master->setup = mtk_spi_setup;
640 of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
642 dev_err(&pdev->dev, "failed to probe of_node\n");
647 mdata = spi_master_get_devdata(master);
648 mdata->dev_comp = of_id->data;
649 if (mdata->dev_comp->must_tx)
650 master->flags = SPI_MASTER_MUST_TX;
652 if (mdata->dev_comp->need_pad_sel) {
653 mdata->pad_num = of_property_count_u32_elems(
655 "mediatek,pad-select");
656 if (mdata->pad_num < 0) {
658 "No 'mediatek,pad-select' property\n");
663 mdata->pad_sel = devm_kmalloc_array(&pdev->dev, mdata->pad_num,
664 sizeof(u32), GFP_KERNEL);
665 if (!mdata->pad_sel) {
670 for (i = 0; i < mdata->pad_num; i++) {
671 of_property_read_u32_index(pdev->dev.of_node,
672 "mediatek,pad-select",
673 i, &mdata->pad_sel[i]);
674 if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) {
675 dev_err(&pdev->dev, "wrong pad-sel[%d]: %u\n",
676 i, mdata->pad_sel[i]);
683 platform_set_drvdata(pdev, master);
684 mdata->base = devm_platform_ioremap_resource(pdev, 0);
685 if (IS_ERR(mdata->base)) {
686 ret = PTR_ERR(mdata->base);
690 irq = platform_get_irq(pdev, 0);
696 if (!pdev->dev.dma_mask)
697 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
699 ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt,
700 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master);
702 dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
706 mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk");
707 if (IS_ERR(mdata->parent_clk)) {
708 ret = PTR_ERR(mdata->parent_clk);
709 dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret);
713 mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk");
714 if (IS_ERR(mdata->sel_clk)) {
715 ret = PTR_ERR(mdata->sel_clk);
716 dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret);
720 mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk");
721 if (IS_ERR(mdata->spi_clk)) {
722 ret = PTR_ERR(mdata->spi_clk);
723 dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
727 ret = clk_prepare_enable(mdata->spi_clk);
729 dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
733 ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
735 dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
736 clk_disable_unprepare(mdata->spi_clk);
740 clk_disable_unprepare(mdata->spi_clk);
742 pm_runtime_enable(&pdev->dev);
744 ret = devm_spi_register_master(&pdev->dev, master);
746 dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
747 goto err_disable_runtime_pm;
750 if (mdata->dev_comp->need_pad_sel) {
751 if (mdata->pad_num != master->num_chipselect) {
753 "pad_num does not match num_chipselect(%d != %d)\n",
754 mdata->pad_num, master->num_chipselect);
756 goto err_disable_runtime_pm;
759 if (!master->cs_gpios && master->num_chipselect > 1) {
761 "cs_gpios not specified and num_chipselect > 1\n");
763 goto err_disable_runtime_pm;
766 if (master->cs_gpios) {
767 for (i = 0; i < master->num_chipselect; i++) {
768 ret = devm_gpio_request(&pdev->dev,
770 dev_name(&pdev->dev));
773 "can't get CS GPIO %i\n", i);
774 goto err_disable_runtime_pm;
780 if (mdata->dev_comp->dma_ext)
781 addr_bits = DMA_ADDR_EXT_BITS;
783 addr_bits = DMA_ADDR_DEF_BITS;
784 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(addr_bits));
786 dev_notice(&pdev->dev, "SPI dma_set_mask(%d) failed, ret:%d\n",
791 err_disable_runtime_pm:
792 pm_runtime_disable(&pdev->dev);
794 spi_master_put(master);
799 static int mtk_spi_remove(struct platform_device *pdev)
801 struct spi_master *master = platform_get_drvdata(pdev);
802 struct mtk_spi *mdata = spi_master_get_devdata(master);
804 pm_runtime_disable(&pdev->dev);
806 mtk_spi_reset(mdata);
811 #ifdef CONFIG_PM_SLEEP
812 static int mtk_spi_suspend(struct device *dev)
815 struct spi_master *master = dev_get_drvdata(dev);
816 struct mtk_spi *mdata = spi_master_get_devdata(master);
818 ret = spi_master_suspend(master);
822 if (!pm_runtime_suspended(dev))
823 clk_disable_unprepare(mdata->spi_clk);
828 static int mtk_spi_resume(struct device *dev)
831 struct spi_master *master = dev_get_drvdata(dev);
832 struct mtk_spi *mdata = spi_master_get_devdata(master);
834 if (!pm_runtime_suspended(dev)) {
835 ret = clk_prepare_enable(mdata->spi_clk);
837 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
842 ret = spi_master_resume(master);
844 clk_disable_unprepare(mdata->spi_clk);
848 #endif /* CONFIG_PM_SLEEP */
851 static int mtk_spi_runtime_suspend(struct device *dev)
853 struct spi_master *master = dev_get_drvdata(dev);
854 struct mtk_spi *mdata = spi_master_get_devdata(master);
856 clk_disable_unprepare(mdata->spi_clk);
861 static int mtk_spi_runtime_resume(struct device *dev)
863 struct spi_master *master = dev_get_drvdata(dev);
864 struct mtk_spi *mdata = spi_master_get_devdata(master);
867 ret = clk_prepare_enable(mdata->spi_clk);
869 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
875 #endif /* CONFIG_PM */
877 static const struct dev_pm_ops mtk_spi_pm = {
878 SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume)
879 SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend,
880 mtk_spi_runtime_resume, NULL)
883 static struct platform_driver mtk_spi_driver = {
887 .of_match_table = mtk_spi_of_match,
889 .probe = mtk_spi_probe,
890 .remove = mtk_spi_remove,
893 module_platform_driver(mtk_spi_driver);
895 MODULE_DESCRIPTION("MTK SPI Controller driver");
896 MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
897 MODULE_LICENSE("GPL v2");
898 MODULE_ALIAS("platform:mtk-spi");