1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Leilk Liu <leilk.liu@mediatek.com>
8 #include <linux/device.h>
10 #include <linux/interrupt.h>
12 #include <linux/ioport.h>
13 #include <linux/module.h>
15 #include <linux/of_gpio.h>
16 #include <linux/platform_device.h>
17 #include <linux/platform_data/spi-mt65xx.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/spi/spi.h>
21 #define SPI_CFG0_REG 0x0000
22 #define SPI_CFG1_REG 0x0004
23 #define SPI_TX_SRC_REG 0x0008
24 #define SPI_RX_DST_REG 0x000c
25 #define SPI_TX_DATA_REG 0x0010
26 #define SPI_RX_DATA_REG 0x0014
27 #define SPI_CMD_REG 0x0018
28 #define SPI_STATUS0_REG 0x001c
29 #define SPI_PAD_SEL_REG 0x0024
30 #define SPI_CFG2_REG 0x0028
32 #define SPI_CFG0_SCK_HIGH_OFFSET 0
33 #define SPI_CFG0_SCK_LOW_OFFSET 8
34 #define SPI_CFG0_CS_HOLD_OFFSET 16
35 #define SPI_CFG0_CS_SETUP_OFFSET 24
36 #define SPI_ADJUST_CFG0_SCK_LOW_OFFSET 16
37 #define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0
38 #define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16
40 #define SPI_CFG1_CS_IDLE_OFFSET 0
41 #define SPI_CFG1_PACKET_LOOP_OFFSET 8
42 #define SPI_CFG1_PACKET_LENGTH_OFFSET 16
43 #define SPI_CFG1_GET_TICK_DLY_OFFSET 30
45 #define SPI_CFG1_CS_IDLE_MASK 0xff
46 #define SPI_CFG1_PACKET_LOOP_MASK 0xff00
47 #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
49 #define SPI_CMD_ACT BIT(0)
50 #define SPI_CMD_RESUME BIT(1)
51 #define SPI_CMD_RST BIT(2)
52 #define SPI_CMD_PAUSE_EN BIT(4)
53 #define SPI_CMD_DEASSERT BIT(5)
54 #define SPI_CMD_SAMPLE_SEL BIT(6)
55 #define SPI_CMD_CS_POL BIT(7)
56 #define SPI_CMD_CPHA BIT(8)
57 #define SPI_CMD_CPOL BIT(9)
58 #define SPI_CMD_RX_DMA BIT(10)
59 #define SPI_CMD_TX_DMA BIT(11)
60 #define SPI_CMD_TXMSBF BIT(12)
61 #define SPI_CMD_RXMSBF BIT(13)
62 #define SPI_CMD_RX_ENDIAN BIT(14)
63 #define SPI_CMD_TX_ENDIAN BIT(15)
64 #define SPI_CMD_FINISH_IE BIT(16)
65 #define SPI_CMD_PAUSE_IE BIT(17)
67 #define MT8173_SPI_MAX_PAD_SEL 3
69 #define MTK_SPI_PAUSE_INT_STATUS 0x2
71 #define MTK_SPI_IDLE 0
72 #define MTK_SPI_PAUSED 1
74 #define MTK_SPI_MAX_FIFO_SIZE 32U
75 #define MTK_SPI_PACKET_SIZE 1024
77 struct mtk_spi_compatible {
79 /* Must explicitly send dummy Tx bytes to do Rx only transfer */
81 /* some IC design adjust cfg register to enhance time accuracy */
90 struct clk *parent_clk, *sel_clk, *spi_clk;
91 struct spi_transfer *cur_transfer;
94 struct scatterlist *tx_sgl, *rx_sgl;
95 u32 tx_sgl_len, rx_sgl_len;
96 const struct mtk_spi_compatible *dev_comp;
99 static const struct mtk_spi_compatible mtk_common_compat;
101 static const struct mtk_spi_compatible mt2712_compat = {
105 static const struct mtk_spi_compatible mt7622_compat = {
107 .enhance_timing = true,
110 static const struct mtk_spi_compatible mt8173_compat = {
111 .need_pad_sel = true,
115 static const struct mtk_spi_compatible mt8183_compat = {
116 .need_pad_sel = true,
118 .enhance_timing = true,
122 * A piece of default chip info unless the platform
125 static const struct mtk_chip_config mtk_default_chip_info = {
130 static const struct of_device_id mtk_spi_of_match[] = {
131 { .compatible = "mediatek,mt2701-spi",
132 .data = (void *)&mtk_common_compat,
134 { .compatible = "mediatek,mt2712-spi",
135 .data = (void *)&mt2712_compat,
137 { .compatible = "mediatek,mt6589-spi",
138 .data = (void *)&mtk_common_compat,
140 { .compatible = "mediatek,mt7622-spi",
141 .data = (void *)&mt7622_compat,
143 { .compatible = "mediatek,mt7629-spi",
144 .data = (void *)&mt7622_compat,
146 { .compatible = "mediatek,mt8135-spi",
147 .data = (void *)&mtk_common_compat,
149 { .compatible = "mediatek,mt8173-spi",
150 .data = (void *)&mt8173_compat,
152 { .compatible = "mediatek,mt8183-spi",
153 .data = (void *)&mt8183_compat,
157 MODULE_DEVICE_TABLE(of, mtk_spi_of_match);
159 static void mtk_spi_reset(struct mtk_spi *mdata)
163 /* set the software reset bit in SPI_CMD_REG. */
164 reg_val = readl(mdata->base + SPI_CMD_REG);
165 reg_val |= SPI_CMD_RST;
166 writel(reg_val, mdata->base + SPI_CMD_REG);
168 reg_val = readl(mdata->base + SPI_CMD_REG);
169 reg_val &= ~SPI_CMD_RST;
170 writel(reg_val, mdata->base + SPI_CMD_REG);
173 static int mtk_spi_prepare_message(struct spi_master *master,
174 struct spi_message *msg)
178 struct spi_device *spi = msg->spi;
179 struct mtk_chip_config *chip_config = spi->controller_data;
180 struct mtk_spi *mdata = spi_master_get_devdata(master);
182 cpha = spi->mode & SPI_CPHA ? 1 : 0;
183 cpol = spi->mode & SPI_CPOL ? 1 : 0;
185 reg_val = readl(mdata->base + SPI_CMD_REG);
187 reg_val |= SPI_CMD_CPHA;
189 reg_val &= ~SPI_CMD_CPHA;
191 reg_val |= SPI_CMD_CPOL;
193 reg_val &= ~SPI_CMD_CPOL;
195 /* set the mlsbx and mlsbtx */
196 if (spi->mode & SPI_LSB_FIRST) {
197 reg_val &= ~SPI_CMD_TXMSBF;
198 reg_val &= ~SPI_CMD_RXMSBF;
200 reg_val |= SPI_CMD_TXMSBF;
201 reg_val |= SPI_CMD_RXMSBF;
204 /* set the tx/rx endian */
205 #ifdef __LITTLE_ENDIAN
206 reg_val &= ~SPI_CMD_TX_ENDIAN;
207 reg_val &= ~SPI_CMD_RX_ENDIAN;
209 reg_val |= SPI_CMD_TX_ENDIAN;
210 reg_val |= SPI_CMD_RX_ENDIAN;
213 if (mdata->dev_comp->enhance_timing) {
214 if (chip_config->cs_pol)
215 reg_val |= SPI_CMD_CS_POL;
217 reg_val &= ~SPI_CMD_CS_POL;
218 if (chip_config->sample_sel)
219 reg_val |= SPI_CMD_SAMPLE_SEL;
221 reg_val &= ~SPI_CMD_SAMPLE_SEL;
224 /* set finish and pause interrupt always enable */
225 reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE;
227 /* disable dma mode */
228 reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
230 /* disable deassert mode */
231 reg_val &= ~SPI_CMD_DEASSERT;
233 writel(reg_val, mdata->base + SPI_CMD_REG);
236 if (mdata->dev_comp->need_pad_sel)
237 writel(mdata->pad_sel[spi->chip_select],
238 mdata->base + SPI_PAD_SEL_REG);
243 static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
246 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
248 reg_val = readl(mdata->base + SPI_CMD_REG);
250 reg_val |= SPI_CMD_PAUSE_EN;
251 writel(reg_val, mdata->base + SPI_CMD_REG);
253 reg_val &= ~SPI_CMD_PAUSE_EN;
254 writel(reg_val, mdata->base + SPI_CMD_REG);
255 mdata->state = MTK_SPI_IDLE;
256 mtk_spi_reset(mdata);
260 static void mtk_spi_prepare_transfer(struct spi_master *master,
261 struct spi_transfer *xfer)
263 u32 spi_clk_hz, div, sck_time, cs_time, reg_val = 0;
264 struct mtk_spi *mdata = spi_master_get_devdata(master);
266 spi_clk_hz = clk_get_rate(mdata->spi_clk);
267 if (xfer->speed_hz < spi_clk_hz / 2)
268 div = DIV_ROUND_UP(spi_clk_hz, xfer->speed_hz);
272 sck_time = (div + 1) / 2;
273 cs_time = sck_time * 2;
275 if (mdata->dev_comp->enhance_timing) {
276 reg_val |= (((sck_time - 1) & 0xffff)
277 << SPI_CFG0_SCK_HIGH_OFFSET);
278 reg_val |= (((sck_time - 1) & 0xffff)
279 << SPI_ADJUST_CFG0_SCK_LOW_OFFSET);
280 writel(reg_val, mdata->base + SPI_CFG2_REG);
281 reg_val |= (((cs_time - 1) & 0xffff)
282 << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
283 reg_val |= (((cs_time - 1) & 0xffff)
284 << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
285 writel(reg_val, mdata->base + SPI_CFG0_REG);
287 reg_val |= (((sck_time - 1) & 0xff)
288 << SPI_CFG0_SCK_HIGH_OFFSET);
289 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
290 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
291 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET);
292 writel(reg_val, mdata->base + SPI_CFG0_REG);
295 reg_val = readl(mdata->base + SPI_CFG1_REG);
296 reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
297 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
298 writel(reg_val, mdata->base + SPI_CFG1_REG);
301 static void mtk_spi_setup_packet(struct spi_master *master)
303 u32 packet_size, packet_loop, reg_val;
304 struct mtk_spi *mdata = spi_master_get_devdata(master);
306 packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE);
307 packet_loop = mdata->xfer_len / packet_size;
309 reg_val = readl(mdata->base + SPI_CFG1_REG);
310 reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK);
311 reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
312 reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
313 writel(reg_val, mdata->base + SPI_CFG1_REG);
316 static void mtk_spi_enable_transfer(struct spi_master *master)
319 struct mtk_spi *mdata = spi_master_get_devdata(master);
321 cmd = readl(mdata->base + SPI_CMD_REG);
322 if (mdata->state == MTK_SPI_IDLE)
325 cmd |= SPI_CMD_RESUME;
326 writel(cmd, mdata->base + SPI_CMD_REG);
329 static int mtk_spi_get_mult_delta(u32 xfer_len)
333 if (xfer_len > MTK_SPI_PACKET_SIZE)
334 mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
341 static void mtk_spi_update_mdata_len(struct spi_master *master)
344 struct mtk_spi *mdata = spi_master_get_devdata(master);
346 if (mdata->tx_sgl_len && mdata->rx_sgl_len) {
347 if (mdata->tx_sgl_len > mdata->rx_sgl_len) {
348 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
349 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
350 mdata->rx_sgl_len = mult_delta;
351 mdata->tx_sgl_len -= mdata->xfer_len;
353 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
354 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
355 mdata->tx_sgl_len = mult_delta;
356 mdata->rx_sgl_len -= mdata->xfer_len;
358 } else if (mdata->tx_sgl_len) {
359 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
360 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
361 mdata->tx_sgl_len = mult_delta;
362 } else if (mdata->rx_sgl_len) {
363 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
364 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
365 mdata->rx_sgl_len = mult_delta;
369 static void mtk_spi_setup_dma_addr(struct spi_master *master,
370 struct spi_transfer *xfer)
372 struct mtk_spi *mdata = spi_master_get_devdata(master);
375 writel(xfer->tx_dma, mdata->base + SPI_TX_SRC_REG);
377 writel(xfer->rx_dma, mdata->base + SPI_RX_DST_REG);
380 static int mtk_spi_fifo_transfer(struct spi_master *master,
381 struct spi_device *spi,
382 struct spi_transfer *xfer)
386 struct mtk_spi *mdata = spi_master_get_devdata(master);
388 mdata->cur_transfer = xfer;
389 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len);
390 mdata->num_xfered = 0;
391 mtk_spi_prepare_transfer(master, xfer);
392 mtk_spi_setup_packet(master);
395 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
397 remainder = xfer->len % 4;
400 memcpy(®_val, xfer->tx_buf + (cnt * 4), remainder);
401 writel(reg_val, mdata->base + SPI_TX_DATA_REG);
404 mtk_spi_enable_transfer(master);
409 static int mtk_spi_dma_transfer(struct spi_master *master,
410 struct spi_device *spi,
411 struct spi_transfer *xfer)
414 struct mtk_spi *mdata = spi_master_get_devdata(master);
416 mdata->tx_sgl = NULL;
417 mdata->rx_sgl = NULL;
418 mdata->tx_sgl_len = 0;
419 mdata->rx_sgl_len = 0;
420 mdata->cur_transfer = xfer;
421 mdata->num_xfered = 0;
423 mtk_spi_prepare_transfer(master, xfer);
425 cmd = readl(mdata->base + SPI_CMD_REG);
427 cmd |= SPI_CMD_TX_DMA;
429 cmd |= SPI_CMD_RX_DMA;
430 writel(cmd, mdata->base + SPI_CMD_REG);
433 mdata->tx_sgl = xfer->tx_sg.sgl;
435 mdata->rx_sgl = xfer->rx_sg.sgl;
438 xfer->tx_dma = sg_dma_address(mdata->tx_sgl);
439 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
442 xfer->rx_dma = sg_dma_address(mdata->rx_sgl);
443 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
446 mtk_spi_update_mdata_len(master);
447 mtk_spi_setup_packet(master);
448 mtk_spi_setup_dma_addr(master, xfer);
449 mtk_spi_enable_transfer(master);
454 static int mtk_spi_transfer_one(struct spi_master *master,
455 struct spi_device *spi,
456 struct spi_transfer *xfer)
458 if (master->can_dma(master, spi, xfer))
459 return mtk_spi_dma_transfer(master, spi, xfer);
461 return mtk_spi_fifo_transfer(master, spi, xfer);
464 static bool mtk_spi_can_dma(struct spi_master *master,
465 struct spi_device *spi,
466 struct spi_transfer *xfer)
468 /* Buffers for DMA transactions must be 4-byte aligned */
469 return (xfer->len > MTK_SPI_MAX_FIFO_SIZE &&
470 (unsigned long)xfer->tx_buf % 4 == 0 &&
471 (unsigned long)xfer->rx_buf % 4 == 0);
474 static int mtk_spi_setup(struct spi_device *spi)
476 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
478 if (!spi->controller_data)
479 spi->controller_data = (void *)&mtk_default_chip_info;
481 if (mdata->dev_comp->need_pad_sel && gpio_is_valid(spi->cs_gpio))
482 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
487 static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
489 u32 cmd, reg_val, cnt, remainder, len;
490 struct spi_master *master = dev_id;
491 struct mtk_spi *mdata = spi_master_get_devdata(master);
492 struct spi_transfer *trans = mdata->cur_transfer;
494 reg_val = readl(mdata->base + SPI_STATUS0_REG);
495 if (reg_val & MTK_SPI_PAUSE_INT_STATUS)
496 mdata->state = MTK_SPI_PAUSED;
498 mdata->state = MTK_SPI_IDLE;
500 if (!master->can_dma(master, master->cur_msg->spi, trans)) {
502 cnt = mdata->xfer_len / 4;
503 ioread32_rep(mdata->base + SPI_RX_DATA_REG,
504 trans->rx_buf + mdata->num_xfered, cnt);
505 remainder = mdata->xfer_len % 4;
507 reg_val = readl(mdata->base + SPI_RX_DATA_REG);
508 memcpy(trans->rx_buf +
516 mdata->num_xfered += mdata->xfer_len;
517 if (mdata->num_xfered == trans->len) {
518 spi_finalize_current_transfer(master);
522 len = trans->len - mdata->num_xfered;
523 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, len);
524 mtk_spi_setup_packet(master);
526 cnt = mdata->xfer_len / 4;
527 iowrite32_rep(mdata->base + SPI_TX_DATA_REG,
528 trans->tx_buf + mdata->num_xfered, cnt);
530 remainder = mdata->xfer_len % 4;
534 trans->tx_buf + (cnt * 4) + mdata->num_xfered,
536 writel(reg_val, mdata->base + SPI_TX_DATA_REG);
539 mtk_spi_enable_transfer(master);
545 trans->tx_dma += mdata->xfer_len;
547 trans->rx_dma += mdata->xfer_len;
549 if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) {
550 mdata->tx_sgl = sg_next(mdata->tx_sgl);
552 trans->tx_dma = sg_dma_address(mdata->tx_sgl);
553 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
556 if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) {
557 mdata->rx_sgl = sg_next(mdata->rx_sgl);
559 trans->rx_dma = sg_dma_address(mdata->rx_sgl);
560 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
564 if (!mdata->tx_sgl && !mdata->rx_sgl) {
565 /* spi disable dma */
566 cmd = readl(mdata->base + SPI_CMD_REG);
567 cmd &= ~SPI_CMD_TX_DMA;
568 cmd &= ~SPI_CMD_RX_DMA;
569 writel(cmd, mdata->base + SPI_CMD_REG);
571 spi_finalize_current_transfer(master);
575 mtk_spi_update_mdata_len(master);
576 mtk_spi_setup_packet(master);
577 mtk_spi_setup_dma_addr(master, trans);
578 mtk_spi_enable_transfer(master);
583 static int mtk_spi_probe(struct platform_device *pdev)
585 struct spi_master *master;
586 struct mtk_spi *mdata;
587 const struct of_device_id *of_id;
588 struct resource *res;
591 master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
593 dev_err(&pdev->dev, "failed to alloc spi master\n");
597 master->auto_runtime_pm = true;
598 master->dev.of_node = pdev->dev.of_node;
599 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
601 master->set_cs = mtk_spi_set_cs;
602 master->prepare_message = mtk_spi_prepare_message;
603 master->transfer_one = mtk_spi_transfer_one;
604 master->can_dma = mtk_spi_can_dma;
605 master->setup = mtk_spi_setup;
607 of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
609 dev_err(&pdev->dev, "failed to probe of_node\n");
614 mdata = spi_master_get_devdata(master);
615 mdata->dev_comp = of_id->data;
616 if (mdata->dev_comp->must_tx)
617 master->flags = SPI_MASTER_MUST_TX;
619 if (mdata->dev_comp->need_pad_sel) {
620 mdata->pad_num = of_property_count_u32_elems(
622 "mediatek,pad-select");
623 if (mdata->pad_num < 0) {
625 "No 'mediatek,pad-select' property\n");
630 mdata->pad_sel = devm_kmalloc_array(&pdev->dev, mdata->pad_num,
631 sizeof(u32), GFP_KERNEL);
632 if (!mdata->pad_sel) {
637 for (i = 0; i < mdata->pad_num; i++) {
638 of_property_read_u32_index(pdev->dev.of_node,
639 "mediatek,pad-select",
640 i, &mdata->pad_sel[i]);
641 if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) {
642 dev_err(&pdev->dev, "wrong pad-sel[%d]: %u\n",
643 i, mdata->pad_sel[i]);
650 platform_set_drvdata(pdev, master);
652 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
655 dev_err(&pdev->dev, "failed to determine base address\n");
659 mdata->base = devm_ioremap_resource(&pdev->dev, res);
660 if (IS_ERR(mdata->base)) {
661 ret = PTR_ERR(mdata->base);
665 irq = platform_get_irq(pdev, 0);
667 dev_err(&pdev->dev, "failed to get irq (%d)\n", irq);
672 if (!pdev->dev.dma_mask)
673 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
675 ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt,
676 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master);
678 dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
682 mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk");
683 if (IS_ERR(mdata->parent_clk)) {
684 ret = PTR_ERR(mdata->parent_clk);
685 dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret);
689 mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk");
690 if (IS_ERR(mdata->sel_clk)) {
691 ret = PTR_ERR(mdata->sel_clk);
692 dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret);
696 mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk");
697 if (IS_ERR(mdata->spi_clk)) {
698 ret = PTR_ERR(mdata->spi_clk);
699 dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
703 ret = clk_prepare_enable(mdata->spi_clk);
705 dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
709 ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
711 dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
712 clk_disable_unprepare(mdata->spi_clk);
716 clk_disable_unprepare(mdata->spi_clk);
718 pm_runtime_enable(&pdev->dev);
720 ret = devm_spi_register_master(&pdev->dev, master);
722 dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
723 goto err_disable_runtime_pm;
726 if (mdata->dev_comp->need_pad_sel) {
727 if (mdata->pad_num != master->num_chipselect) {
729 "pad_num does not match num_chipselect(%d != %d)\n",
730 mdata->pad_num, master->num_chipselect);
732 goto err_disable_runtime_pm;
735 if (!master->cs_gpios && master->num_chipselect > 1) {
737 "cs_gpios not specified and num_chipselect > 1\n");
739 goto err_disable_runtime_pm;
742 if (master->cs_gpios) {
743 for (i = 0; i < master->num_chipselect; i++) {
744 ret = devm_gpio_request(&pdev->dev,
746 dev_name(&pdev->dev));
749 "can't get CS GPIO %i\n", i);
750 goto err_disable_runtime_pm;
758 err_disable_runtime_pm:
759 pm_runtime_disable(&pdev->dev);
761 spi_master_put(master);
766 static int mtk_spi_remove(struct platform_device *pdev)
768 struct spi_master *master = platform_get_drvdata(pdev);
769 struct mtk_spi *mdata = spi_master_get_devdata(master);
771 pm_runtime_disable(&pdev->dev);
773 mtk_spi_reset(mdata);
778 #ifdef CONFIG_PM_SLEEP
779 static int mtk_spi_suspend(struct device *dev)
782 struct spi_master *master = dev_get_drvdata(dev);
783 struct mtk_spi *mdata = spi_master_get_devdata(master);
785 ret = spi_master_suspend(master);
789 if (!pm_runtime_suspended(dev))
790 clk_disable_unprepare(mdata->spi_clk);
795 static int mtk_spi_resume(struct device *dev)
798 struct spi_master *master = dev_get_drvdata(dev);
799 struct mtk_spi *mdata = spi_master_get_devdata(master);
801 if (!pm_runtime_suspended(dev)) {
802 ret = clk_prepare_enable(mdata->spi_clk);
804 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
809 ret = spi_master_resume(master);
811 clk_disable_unprepare(mdata->spi_clk);
815 #endif /* CONFIG_PM_SLEEP */
818 static int mtk_spi_runtime_suspend(struct device *dev)
820 struct spi_master *master = dev_get_drvdata(dev);
821 struct mtk_spi *mdata = spi_master_get_devdata(master);
823 clk_disable_unprepare(mdata->spi_clk);
828 static int mtk_spi_runtime_resume(struct device *dev)
830 struct spi_master *master = dev_get_drvdata(dev);
831 struct mtk_spi *mdata = spi_master_get_devdata(master);
834 ret = clk_prepare_enable(mdata->spi_clk);
836 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
842 #endif /* CONFIG_PM */
844 static const struct dev_pm_ops mtk_spi_pm = {
845 SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume)
846 SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend,
847 mtk_spi_runtime_resume, NULL)
850 static struct platform_driver mtk_spi_driver = {
854 .of_match_table = mtk_spi_of_match,
856 .probe = mtk_spi_probe,
857 .remove = mtk_spi_remove,
860 module_platform_driver(mtk_spi_driver);
862 MODULE_DESCRIPTION("MTK SPI Controller driver");
863 MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
864 MODULE_LICENSE("GPL v2");
865 MODULE_ALIAS("platform:mtk-spi");