drivers/spi/spi-npcm-pspi.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2018 Nuvoton Technology corporation.
   3
   4 #include <linux/kernel.h>
   5 #include <linux/bitfield.h>
   6 #include <linux/bitops.h>
   7 #include <linux/clk.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/io.h>
  10 #include <linux/module.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/spi/spi.h>
  13 #include <linux/gpio.h>
  14 #include <linux/of_gpio.h>
  15
  16 #include <asm/unaligned.h>
  17
  18 #include <linux/regmap.h>
  19 #include <linux/mfd/syscon.h>
  20
  21 struct npcm_pspi {
  22         struct completion xfer_done;
  23         struct regmap *rst_regmap;
  24         struct spi_master *master;
  25         unsigned int tx_bytes;
  26         unsigned int rx_bytes;
  27         void __iomem *base;
  28         bool is_save_param;
  29         u8 bits_per_word;
  30         const u8 *tx_buf;
  31         struct clk *clk;
  32         u32 speed_hz;
  33         u8 *rx_buf;
  34         u16 mode;
  35         u32 id;
  36 };
  37
  38 #define DRIVER_NAME "npcm-pspi"
  39
  40 #define NPCM_PSPI_DATA          0x00
  41 #define NPCM_PSPI_CTL1          0x02
  42 #define NPCM_PSPI_STAT          0x04
  43
  44 /* definitions for control and status register */
  45 #define NPCM_PSPI_CTL1_SPIEN    BIT(0)
  46 #define NPCM_PSPI_CTL1_MOD      BIT(2)
  47 #define NPCM_PSPI_CTL1_EIR      BIT(5)
  48 #define NPCM_PSPI_CTL1_EIW      BIT(6)
  49 #define NPCM_PSPI_CTL1_SCM      BIT(7)
  50 #define NPCM_PSPI_CTL1_SCIDL    BIT(8)
  51 #define NPCM_PSPI_CTL1_SCDV6_0  GENMASK(15, 9)
  52
  53 #define NPCM_PSPI_STAT_BSY      BIT(0)
  54 #define NPCM_PSPI_STAT_RBF      BIT(1)
  55
  56 /* general definitions */
  57 #define NPCM_PSPI_TIMEOUT_MS            2000
  58 #define NPCM_PSPI_MAX_CLK_DIVIDER       256
  59 #define NPCM_PSPI_MIN_CLK_DIVIDER       4
  60 #define NPCM_PSPI_DEFAULT_CLK           25000000
  61
  62 /* reset register */
  63 #define NPCM7XX_IPSRST2_OFFSET  0x24
  64
  65 #define NPCM7XX_PSPI1_RESET     BIT(22)
  66 #define NPCM7XX_PSPI2_RESET     BIT(23)
  67
  68 static inline unsigned int bytes_per_word(unsigned int bits)
  69 {
  70         return bits <= 8 ? 1 : 2;
  71 }
  72
  73 static inline void npcm_pspi_irq_enable(struct npcm_pspi *priv, u16 mask)
  74 {
  75         u16 val;
  76
  77         val = ioread16(priv->base + NPCM_PSPI_CTL1);
  78         val |= mask;
  79         iowrite16(val, priv->base + NPCM_PSPI_CTL1);
  80 }
  81
  82 static inline void npcm_pspi_irq_disable(struct npcm_pspi *priv, u16 mask)
  83 {
  84         u16 val;
  85
  86         val = ioread16(priv->base + NPCM_PSPI_CTL1);
  87         val &= ~mask;
  88         iowrite16(val, priv->base + NPCM_PSPI_CTL1);
  89 }
  90
  91 static inline void npcm_pspi_enable(struct npcm_pspi *priv)
  92 {
  93         u16 val;
  94
  95         val = ioread16(priv->base + NPCM_PSPI_CTL1);
  96         val |= NPCM_PSPI_CTL1_SPIEN;
  97         iowrite16(val, priv->base + NPCM_PSPI_CTL1);
  98 }
  99
 100 static inline void npcm_pspi_disable(struct npcm_pspi *priv)
 101 {
 102         u16 val;
 103
 104         val = ioread16(priv->base + NPCM_PSPI_CTL1);
 105         val &= ~NPCM_PSPI_CTL1_SPIEN;
 106         iowrite16(val, priv->base + NPCM_PSPI_CTL1);
 107 }
 108
 109 static void npcm_pspi_set_mode(struct spi_device *spi)
 110 {
 111         struct npcm_pspi *priv = spi_master_get_devdata(spi->master);
 112         u16 regtemp;
 113         u16 mode_val;
 114
 115         switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
 116         case SPI_MODE_0:
 117                 mode_val = 0;
 118                 break;
 119         case SPI_MODE_1:
 120                 mode_val = NPCM_PSPI_CTL1_SCIDL;
 121                 break;
 122         case SPI_MODE_2:
 123                 mode_val = NPCM_PSPI_CTL1_SCM;
 124                 break;
 125         case SPI_MODE_3:
 126                 mode_val = NPCM_PSPI_CTL1_SCIDL | NPCM_PSPI_CTL1_SCM;
 127                 break;
 128         }
 129
 130         regtemp = ioread16(priv->base + NPCM_PSPI_CTL1);
 131         regtemp &= ~(NPCM_PSPI_CTL1_SCM | NPCM_PSPI_CTL1_SCIDL);
 132         iowrite16(regtemp | mode_val, priv->base + NPCM_PSPI_CTL1);
 133 }
 134
 135 static void npcm_pspi_set_transfer_size(struct npcm_pspi *priv, int size)
 136 {
 137         u16 regtemp;
 138
 139         regtemp = ioread16(NPCM_PSPI_CTL1 + priv->base);
 140
 141         switch (size) {
 142         case 8:
 143                 regtemp &= ~NPCM_PSPI_CTL1_MOD;
 144                 break;
 145         case 16:
 146                 regtemp |= NPCM_PSPI_CTL1_MOD;
 147                 break;
 148         }
 149
 150         iowrite16(regtemp, NPCM_PSPI_CTL1 + priv->base);
 151 }
 152
 153 static void npcm_pspi_set_baudrate(struct npcm_pspi *priv, unsigned int speed)
 154 {
 155         u32 ckdiv;
 156         u16 regtemp;
 157
 158         /* the supported rates are numbers from 4 to 256. */
 159         ckdiv = DIV_ROUND_CLOSEST(clk_get_rate(priv->clk), (2 * speed)) - 1;
 160
 161         regtemp = ioread16(NPCM_PSPI_CTL1 + priv->base);
 162         regtemp &= ~NPCM_PSPI_CTL1_SCDV6_0;
 163         iowrite16(regtemp | (ckdiv << 9), NPCM_PSPI_CTL1 + priv->base);
 164 }
 165
 166 static void npcm_pspi_setup_transfer(struct spi_device *spi,
 167                                      struct spi_transfer *t)
 168 {
 169         struct npcm_pspi *priv = spi_master_get_devdata(spi->master);
 170
 171         priv->tx_buf = t->tx_buf;
 172         priv->rx_buf = t->rx_buf;
 173         priv->tx_bytes = t->len;
 174         priv->rx_bytes = t->len;
 175
 176         if (!priv->is_save_param || priv->mode != spi->mode) {
 177                 npcm_pspi_set_mode(spi);
 178                 priv->mode = spi->mode;
 179         }
 180
 181         if (!priv->is_save_param || priv->bits_per_word != t->bits_per_word) {
 182                 npcm_pspi_set_transfer_size(priv, t->bits_per_word);
 183                 priv->bits_per_word = t->bits_per_word;
 184         }
 185
 186         if (!priv->is_save_param || priv->speed_hz != t->speed_hz) {
 187                 npcm_pspi_set_baudrate(priv, t->speed_hz);
 188                 priv->speed_hz = t->speed_hz;
 189         }
 190
 191         if (!priv->is_save_param)
 192                 priv->is_save_param = true;
 193 }
 194
 195 static void npcm_pspi_send(struct npcm_pspi *priv)
 196 {
 197         int wsize;
 198
 199         wsize = min(bytes_per_word(priv->bits_per_word), priv->tx_bytes);
 200         priv->tx_bytes -= wsize;
 201
 202         if (priv->tx_buf) {
 203                 if (wsize == 1)
 204                         iowrite8(*priv->tx_buf, NPCM_PSPI_DATA + priv->base);
 205                 if (wsize == 2)
 206                         iowrite16(*priv->tx_buf, NPCM_PSPI_DATA + priv->base);
 207
 208                 priv->tx_buf += wsize;
 209         }
 210 }
 211
 212 static void npcm_pspi_recv(struct npcm_pspi *priv)
 213 {
 214         int rsize;
 215         u16 val;
 216
 217         rsize = min(bytes_per_word(priv->bits_per_word), priv->rx_bytes);
 218         priv->rx_bytes -= rsize;
 219
 220         if (priv->rx_buf) {
 221                 if (rsize == 1)
 222                         val = ioread8(priv->base + NPCM_PSPI_DATA);
 223                 if (rsize == 2)
 224                         val = ioread16(priv->base + NPCM_PSPI_DATA);
 225
 226                 *priv->rx_buf = val;
 227                 priv->rx_buf += rsize;
 228         }
 229 }
 230
 231 static int npcm_pspi_transfer_one(struct spi_master *master,
 232                                   struct spi_device *spi,
 233                                   struct spi_transfer *t)
 234 {
 235         struct npcm_pspi *priv = spi_master_get_devdata(master);
 236         int status;
 237
 238         npcm_pspi_setup_transfer(spi, t);
 239         reinit_completion(&priv->xfer_done);
 240         npcm_pspi_enable(priv);
 241         status = wait_for_completion_timeout(&priv->xfer_done,
 242                                              msecs_to_jiffies
 243                                              (NPCM_PSPI_TIMEOUT_MS));
 244         if (status == 0) {
 245                 npcm_pspi_disable(priv);
 246                 return -ETIMEDOUT;
 247         }
 248
 249         return 0;
 250 }
 251
 252 static int npcm_pspi_prepare_transfer_hardware(struct spi_master *master)
 253 {
 254         struct npcm_pspi *priv = spi_master_get_devdata(master);
 255
 256         npcm_pspi_irq_enable(priv, NPCM_PSPI_CTL1_EIR | NPCM_PSPI_CTL1_EIW);
 257
 258         return 0;
 259 }
 260
 261 static int npcm_pspi_unprepare_transfer_hardware(struct spi_master *master)
 262 {
 263         struct npcm_pspi *priv = spi_master_get_devdata(master);
 264
 265         npcm_pspi_irq_disable(priv, NPCM_PSPI_CTL1_EIR | NPCM_PSPI_CTL1_EIW);
 266
 267         return 0;
 268 }
 269
 270 static void npcm_pspi_reset_hw(struct npcm_pspi *priv)
 271 {
 272         regmap_write(priv->rst_regmap, NPCM7XX_IPSRST2_OFFSET,
 273                      NPCM7XX_PSPI1_RESET << priv->id);
 274         regmap_write(priv->rst_regmap, NPCM7XX_IPSRST2_OFFSET, 0x0);
 275 }
 276
 277 static irqreturn_t npcm_pspi_handler(int irq, void *dev_id)
 278 {
 279         struct npcm_pspi *priv = dev_id;
 280         u16 val;
 281         u8 stat;
 282
 283         stat = ioread8(priv->base + NPCM_PSPI_STAT);
 284
 285         if (!priv->tx_buf && !priv->rx_buf)
 286                 return IRQ_NONE;
 287
 288         if (priv->tx_buf) {
 289                 if (stat & NPCM_PSPI_STAT_RBF) {
 290                         val = ioread8(NPCM_PSPI_DATA + priv->base);
 291                         if (priv->tx_bytes == 0) {
 292                                 npcm_pspi_disable(priv);
 293                                 complete(&priv->xfer_done);
 294                                 return IRQ_HANDLED;
 295                         }
 296                 }
 297
 298                 if ((stat & NPCM_PSPI_STAT_BSY) == 0)
 299                         if (priv->tx_bytes)
 300                                 npcm_pspi_send(priv);
 301         }
 302
 303         if (priv->rx_buf) {
 304                 if (stat & NPCM_PSPI_STAT_RBF) {
 305                         if (!priv->rx_bytes)
 306                                 return IRQ_NONE;
 307
 308                         npcm_pspi_recv(priv);
 309
 310                         if (!priv->rx_bytes) {
 311                                 npcm_pspi_disable(priv);
 312                                 complete(&priv->xfer_done);
 313                                 return IRQ_HANDLED;
 314                         }
 315                 }
 316
 317                 if (((stat & NPCM_PSPI_STAT_BSY) == 0) && !priv->tx_buf)
 318                         iowrite8(0x0, NPCM_PSPI_DATA + priv->base);
 319         }
 320
 321         return IRQ_HANDLED;
 322 }
 323
 324 static int npcm_pspi_probe(struct platform_device *pdev)
 325 {
 326         struct npcm_pspi *priv;
 327         struct spi_master *master;
 328         struct resource *res;
 329         unsigned long clk_hz;
 330         struct device_node *np = pdev->dev.of_node;
 331         int num_cs, i;
 332         int csgpio;
 333         int irq;
 334         int ret;
 335
 336         num_cs = of_gpio_named_count(np, "cs-gpios");
 337         if (num_cs < 0)
 338                 return num_cs;
 339
 340         pdev->id = of_alias_get_id(np, "spi");
 341         if (pdev->id < 0)
 342                 pdev->id = 0;
 343
 344         master = spi_alloc_master(&pdev->dev, sizeof(*priv));
 345         if (!master)
 346                 return -ENOMEM;
 347
 348         platform_set_drvdata(pdev, master);
 349
 350         priv = spi_master_get_devdata(master);
 351         priv->master = master;
 352         priv->is_save_param = false;
 353         priv->id = pdev->id;
 354
 355         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 356         priv->base = devm_ioremap_resource(&pdev->dev, res);
 357         if (IS_ERR(priv->base)) {
 358                 ret = PTR_ERR(priv->base);
 359                 goto out_master_put;
 360         }
 361
 362         priv->clk = devm_clk_get(&pdev->dev, NULL);
 363         if (IS_ERR(priv->clk)) {
 364                 dev_err(&pdev->dev, "failed to get clock\n");
 365                 ret = PTR_ERR(priv->clk);
 366                 goto out_master_put;
 367         }
 368
 369         ret = clk_prepare_enable(priv->clk);
 370         if (ret)
 371                 goto out_master_put;
 372
 373         irq = platform_get_irq(pdev, 0);
 374         if (irq < 0) {
 375                 dev_err(&pdev->dev, "failed to get IRQ\n");
 376                 ret = irq;
 377                 goto out_disable_clk;
 378         }
 379
 380         priv->rst_regmap =
 381                 syscon_regmap_lookup_by_compatible("nuvoton,npcm750-rst");
 382         if (IS_ERR(priv->rst_regmap)) {
 383                 dev_err(&pdev->dev, "failed to find nuvoton,npcm750-rst\n");
 384                 return IS_ERR(priv->rst_regmap);
 385         }
 386
 387         /* reset SPI-HW block */
 388         npcm_pspi_reset_hw(priv);
 389
 390         ret = devm_request_irq(&pdev->dev, irq, npcm_pspi_handler, 0,
 391                                "npcm-pspi", priv);
 392         if (ret) {
 393                 dev_err(&pdev->dev, "failed to request IRQ\n");
 394                 goto out_disable_clk;
 395         }
 396
 397         init_completion(&priv->xfer_done);
 398
 399         clk_hz = clk_get_rate(priv->clk);
 400
 401         master->max_speed_hz = DIV_ROUND_UP(clk_hz, NPCM_PSPI_MIN_CLK_DIVIDER);
 402         master->min_speed_hz = DIV_ROUND_UP(clk_hz, NPCM_PSPI_MAX_CLK_DIVIDER);
 403         master->mode_bits = SPI_CPHA | SPI_CPOL;
 404         master->dev.of_node = pdev->dev.of_node;
 405         master->bus_num = pdev->id;
 406         master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
 407         master->transfer_one = npcm_pspi_transfer_one;
 408         master->prepare_transfer_hardware =
 409                 npcm_pspi_prepare_transfer_hardware;
 410         master->unprepare_transfer_hardware =
 411                 npcm_pspi_unprepare_transfer_hardware;
 412         master->num_chipselect = num_cs;
 413
 414         for (i = 0; i < num_cs; i++) {
 415                 csgpio = of_get_named_gpio(np, "cs-gpios", i);
 416                 if (csgpio < 0) {
 417                         dev_err(&pdev->dev, "failed to get csgpio#%u\n", i);
 418                         goto out_disable_clk;
 419                 }
 420                 dev_dbg(&pdev->dev, "csgpio#%u = %d\n", i, csgpio);
 421                 ret = devm_gpio_request_one(&pdev->dev, csgpio,
 422                                             GPIOF_OUT_INIT_HIGH, DRIVER_NAME);
 423                 if (ret < 0) {
 424                         dev_err(&pdev->dev,
 425                                 "failed to configure csgpio#%u %d\n"
 426                                 , i, csgpio);
 427                         goto out_disable_clk;
 428                 }
 429         }
 430
 431         /* set to default clock rate */
 432         npcm_pspi_set_baudrate(priv, NPCM_PSPI_DEFAULT_CLK);
 433
 434         ret = devm_spi_register_master(&pdev->dev, master);
 435         if (ret)
 436                 goto out_disable_clk;
 437
 438         pr_info("NPCM Peripheral SPI %d probed\n", pdev->id);
 439
 440         return 0;
 441
 442 out_disable_clk:
 443         clk_disable_unprepare(priv->clk);
 444
 445 out_master_put:
 446         spi_master_put(master);
 447         return ret;
 448 }
 449
 450 static int npcm_pspi_remove(struct platform_device *pdev)
 451 {
 452         struct npcm_pspi *priv = platform_get_drvdata(pdev);
 453
 454         npcm_pspi_reset_hw(priv);
 455         clk_disable_unprepare(priv->clk);
 456
 457         return 0;
 458 }
 459
 460 static const struct of_device_id npcm_pspi_match[] = {
 461         { .compatible = "nuvoton,npcm750-pspi", .data = NULL },
 462         {}
 463 };
 464 MODULE_DEVICE_TABLE(of, npcm_pspi_match);
 465
 466 static struct platform_driver npcm_pspi_driver = {
 467         .driver         = {
 468                 .name           = DRIVER_NAME,
 469                 .of_match_table = npcm_pspi_match,
 470         },
 471         .probe          = npcm_pspi_probe,
 472         .remove         = npcm_pspi_remove,
 473 };
 474 module_platform_driver(npcm_pspi_driver);
 475
 476 MODULE_DESCRIPTION("NPCM peripheral SPI Controller driver");
 477 MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>");
 478 MODULE_LICENSE("GPL v2");
 479