drivers/spi/spi-omap2-mcspi.c

   1 /*
   2  * OMAP2 McSPI controller driver
   3  *
   4  * Copyright (C) 2005, 2006 Nokia Corporation
   5  * Author:      Samuel Ortiz <samuel.ortiz@nokia.com> and
   6  *              Juha Yrj�l� <juha.yrjola@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/module.h>
  22 #include <linux/device.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/dmaengine.h>
  26 #include <linux/pinctrl/consumer.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/err.h>
  29 #include <linux/clk.h>
  30 #include <linux/io.h>
  31 #include <linux/slab.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/of.h>
  34 #include <linux/of_device.h>
  35 #include <linux/gcd.h>
  36
  37 #include <linux/spi/spi.h>
  38 #include <linux/gpio.h>
  39
  40 #include <linux/platform_data/spi-omap2-mcspi.h>
  41
  42 #define OMAP2_MCSPI_MAX_FREQ            48000000
  43 #define OMAP2_MCSPI_MAX_DIVIDER         4096
  44 #define OMAP2_MCSPI_MAX_FIFODEPTH       64
  45 #define OMAP2_MCSPI_MAX_FIFOWCNT        0xFFFF
  46 #define SPI_AUTOSUSPEND_TIMEOUT         2000
  47
  48 #define OMAP2_MCSPI_REVISION            0x00
  49 #define OMAP2_MCSPI_SYSSTATUS           0x14
  50 #define OMAP2_MCSPI_IRQSTATUS           0x18
  51 #define OMAP2_MCSPI_IRQENABLE           0x1c
  52 #define OMAP2_MCSPI_WAKEUPENABLE        0x20
  53 #define OMAP2_MCSPI_SYST                0x24
  54 #define OMAP2_MCSPI_MODULCTRL           0x28
  55 #define OMAP2_MCSPI_XFERLEVEL           0x7c
  56
  57 /* per-channel banks, 0x14 bytes each, first is: */
  58 #define OMAP2_MCSPI_CHCONF0             0x2c
  59 #define OMAP2_MCSPI_CHSTAT0             0x30
  60 #define OMAP2_MCSPI_CHCTRL0             0x34
  61 #define OMAP2_MCSPI_TX0                 0x38
  62 #define OMAP2_MCSPI_RX0                 0x3c
  63
  64 /* per-register bitmasks: */
  65 #define OMAP2_MCSPI_IRQSTATUS_EOW       BIT(17)
  66
  67 #define OMAP2_MCSPI_MODULCTRL_SINGLE    BIT(0)
  68 #define OMAP2_MCSPI_MODULCTRL_MS        BIT(2)
  69 #define OMAP2_MCSPI_MODULCTRL_STEST     BIT(3)
  70
  71 #define OMAP2_MCSPI_CHCONF_PHA          BIT(0)
  72 #define OMAP2_MCSPI_CHCONF_POL          BIT(1)
  73 #define OMAP2_MCSPI_CHCONF_CLKD_MASK    (0x0f << 2)
  74 #define OMAP2_MCSPI_CHCONF_EPOL         BIT(6)
  75 #define OMAP2_MCSPI_CHCONF_WL_MASK      (0x1f << 7)
  76 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY  BIT(12)
  77 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY  BIT(13)
  78 #define OMAP2_MCSPI_CHCONF_TRM_MASK     (0x03 << 12)
  79 #define OMAP2_MCSPI_CHCONF_DMAW         BIT(14)
  80 #define OMAP2_MCSPI_CHCONF_DMAR         BIT(15)
  81 #define OMAP2_MCSPI_CHCONF_DPE0         BIT(16)
  82 #define OMAP2_MCSPI_CHCONF_DPE1         BIT(17)
  83 #define OMAP2_MCSPI_CHCONF_IS           BIT(18)
  84 #define OMAP2_MCSPI_CHCONF_TURBO        BIT(19)
  85 #define OMAP2_MCSPI_CHCONF_FORCE        BIT(20)
  86 #define OMAP2_MCSPI_CHCONF_FFET         BIT(27)
  87 #define OMAP2_MCSPI_CHCONF_FFER         BIT(28)
  88 #define OMAP2_MCSPI_CHCONF_CLKG         BIT(29)
  89
  90 #define OMAP2_MCSPI_CHSTAT_RXS          BIT(0)
  91 #define OMAP2_MCSPI_CHSTAT_TXS          BIT(1)
  92 #define OMAP2_MCSPI_CHSTAT_EOT          BIT(2)
  93 #define OMAP2_MCSPI_CHSTAT_TXFFE        BIT(3)
  94
  95 #define OMAP2_MCSPI_CHCTRL_EN           BIT(0)
  96 #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK  (0xff << 8)
  97
  98 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN   BIT(0)
  99
 100 /* We have 2 DMA channels per CS, one for RX and one for TX */
 101 struct omap2_mcspi_dma {
 102         struct dma_chan *dma_tx;
 103         struct dma_chan *dma_rx;
 104
 105         struct completion dma_tx_completion;
 106         struct completion dma_rx_completion;
 107
 108         char dma_rx_ch_name[14];
 109         char dma_tx_ch_name[14];
 110 };
 111
 112 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
 113  * cache operations; better heuristics consider wordsize and bitrate.
 114  */
 115 #define DMA_MIN_BYTES                   160
 116
 117
 118 /*
 119  * Used for context save and restore, structure members to be updated whenever
 120  * corresponding registers are modified.
 121  */
 122 struct omap2_mcspi_regs {
 123         u32 modulctrl;
 124         u32 wakeupenable;
 125         struct list_head cs;
 126 };
 127
 128 struct omap2_mcspi {
 129         struct spi_master       *master;
 130         /* Virtual base address of the controller */
 131         void __iomem            *base;
 132         unsigned long           phys;
 133         /* SPI1 has 4 channels, while SPI2 has 2 */
 134         struct omap2_mcspi_dma  *dma_channels;
 135         struct device           *dev;
 136         struct omap2_mcspi_regs ctx;
 137         int                     fifo_depth;
 138         unsigned int            pin_dir:1;
 139 };
 140
 141 struct omap2_mcspi_cs {
 142         void __iomem            *base;
 143         unsigned long           phys;
 144         int                     word_len;
 145         u16                     mode;
 146         struct list_head        node;
 147         /* Context save and restore shadow register */
 148         u32                     chconf0, chctrl0;
 149 };
 150
 151 static inline void mcspi_write_reg(struct spi_master *master,
 152                 int idx, u32 val)
 153 {
 154         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 155
 156         writel_relaxed(val, mcspi->base + idx);
 157 }
 158
 159 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
 160 {
 161         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 162
 163         return readl_relaxed(mcspi->base + idx);
 164 }
 165
 166 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
 167                 int idx, u32 val)
 168 {
 169         struct omap2_mcspi_cs   *cs = spi->controller_state;
 170
 171         writel_relaxed(val, cs->base +  idx);
 172 }
 173
 174 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
 175 {
 176         struct omap2_mcspi_cs   *cs = spi->controller_state;
 177
 178         return readl_relaxed(cs->base + idx);
 179 }
 180
 181 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
 182 {
 183         struct omap2_mcspi_cs *cs = spi->controller_state;
 184
 185         return cs->chconf0;
 186 }
 187
 188 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
 189 {
 190         struct omap2_mcspi_cs *cs = spi->controller_state;
 191
 192         cs->chconf0 = val;
 193         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
 194         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 195 }
 196
 197 static inline int mcspi_bytes_per_word(int word_len)
 198 {
 199         if (word_len <= 8)
 200                 return 1;
 201         else if (word_len <= 16)
 202                 return 2;
 203         else /* word_len <= 32 */
 204                 return 4;
 205 }
 206
 207 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
 208                 int is_read, int enable)
 209 {
 210         u32 l, rw;
 211
 212         l = mcspi_cached_chconf0(spi);
 213
 214         if (is_read) /* 1 is read, 0 write */
 215                 rw = OMAP2_MCSPI_CHCONF_DMAR;
 216         else
 217                 rw = OMAP2_MCSPI_CHCONF_DMAW;
 218
 219         if (enable)
 220                 l |= rw;
 221         else
 222                 l &= ~rw;
 223
 224         mcspi_write_chconf0(spi, l);
 225 }
 226
 227 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
 228 {
 229         struct omap2_mcspi_cs *cs = spi->controller_state;
 230         u32 l;
 231
 232         l = cs->chctrl0;
 233         if (enable)
 234                 l |= OMAP2_MCSPI_CHCTRL_EN;
 235         else
 236                 l &= ~OMAP2_MCSPI_CHCTRL_EN;
 237         cs->chctrl0 = l;
 238         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
 239         /* Flash post-writes */
 240         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
 241 }
 242
 243 static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable)
 244 {
 245         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 246         u32 l;
 247
 248         /* The controller handles the inverted chip selects
 249          * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert
 250          * the inversion from the core spi_set_cs function.
 251          */
 252         if (spi->mode & SPI_CS_HIGH)
 253                 enable = !enable;
 254
 255         if (spi->controller_state) {
 256                 int err = pm_runtime_get_sync(mcspi->dev);
 257                 if (err < 0) {
 258                         dev_err(mcspi->dev, "failed to get sync: %d\n", err);
 259                         return;
 260                 }
 261
 262                 l = mcspi_cached_chconf0(spi);
 263
 264                 if (enable)
 265                         l &= ~OMAP2_MCSPI_CHCONF_FORCE;
 266                 else
 267                         l |= OMAP2_MCSPI_CHCONF_FORCE;
 268
 269                 mcspi_write_chconf0(spi, l);
 270
 271                 pm_runtime_mark_last_busy(mcspi->dev);
 272                 pm_runtime_put_autosuspend(mcspi->dev);
 273         }
 274 }
 275
 276 static void omap2_mcspi_set_master_mode(struct spi_master *master)
 277 {
 278         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
 279         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 280         u32 l;
 281
 282         /*
 283          * Setup when switching from (reset default) slave mode
 284          * to single-channel master mode
 285          */
 286         l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
 287         l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
 288         l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
 289         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
 290
 291         ctx->modulctrl = l;
 292 }
 293
 294 static void omap2_mcspi_set_fifo(const struct spi_device *spi,
 295                                 struct spi_transfer *t, int enable)
 296 {
 297         struct spi_master *master = spi->master;
 298         struct omap2_mcspi_cs *cs = spi->controller_state;
 299         struct omap2_mcspi *mcspi;
 300         unsigned int wcnt;
 301         int max_fifo_depth, fifo_depth, bytes_per_word;
 302         u32 chconf, xferlevel;
 303
 304         mcspi = spi_master_get_devdata(master);
 305
 306         chconf = mcspi_cached_chconf0(spi);
 307         if (enable) {
 308                 bytes_per_word = mcspi_bytes_per_word(cs->word_len);
 309                 if (t->len % bytes_per_word != 0)
 310                         goto disable_fifo;
 311
 312                 if (t->rx_buf != NULL && t->tx_buf != NULL)
 313                         max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2;
 314                 else
 315                         max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH;
 316
 317                 fifo_depth = gcd(t->len, max_fifo_depth);
 318                 if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0)
 319                         goto disable_fifo;
 320
 321                 wcnt = t->len / bytes_per_word;
 322                 if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
 323                         goto disable_fifo;
 324
 325                 xferlevel = wcnt << 16;
 326                 if (t->rx_buf != NULL) {
 327                         chconf |= OMAP2_MCSPI_CHCONF_FFER;
 328                         xferlevel |= (fifo_depth - 1) << 8;
 329                 }
 330                 if (t->tx_buf != NULL) {
 331                         chconf |= OMAP2_MCSPI_CHCONF_FFET;
 332                         xferlevel |= fifo_depth - 1;
 333                 }
 334
 335                 mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel);
 336                 mcspi_write_chconf0(spi, chconf);
 337                 mcspi->fifo_depth = fifo_depth;
 338
 339                 return;
 340         }
 341
 342 disable_fifo:
 343         if (t->rx_buf != NULL)
 344                 chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
 345
 346         if (t->tx_buf != NULL)
 347                 chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
 348
 349         mcspi_write_chconf0(spi, chconf);
 350         mcspi->fifo_depth = 0;
 351 }
 352
 353 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
 354 {
 355         struct spi_master       *spi_cntrl = mcspi->master;
 356         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 357         struct omap2_mcspi_cs   *cs;
 358
 359         /* McSPI: context restore */
 360         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
 361         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
 362
 363         list_for_each_entry(cs, &ctx->cs, node)
 364                 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
 365 }
 366
 367 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
 368 {
 369         unsigned long timeout;
 370
 371         timeout = jiffies + msecs_to_jiffies(1000);
 372         while (!(readl_relaxed(reg) & bit)) {
 373                 if (time_after(jiffies, timeout)) {
 374                         if (!(readl_relaxed(reg) & bit))
 375                                 return -ETIMEDOUT;
 376                         else
 377                                 return 0;
 378                 }
 379                 cpu_relax();
 380         }
 381         return 0;
 382 }
 383
 384 static void omap2_mcspi_rx_callback(void *data)
 385 {
 386         struct spi_device *spi = data;
 387         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 388         struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 389
 390         /* We must disable the DMA RX request */
 391         omap2_mcspi_set_dma_req(spi, 1, 0);
 392
 393         complete(&mcspi_dma->dma_rx_completion);
 394 }
 395
 396 static void omap2_mcspi_tx_callback(void *data)
 397 {
 398         struct spi_device *spi = data;
 399         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 400         struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 401
 402         /* We must disable the DMA TX request */
 403         omap2_mcspi_set_dma_req(spi, 0, 0);
 404
 405         complete(&mcspi_dma->dma_tx_completion);
 406 }
 407
 408 static void omap2_mcspi_tx_dma(struct spi_device *spi,
 409                                 struct spi_transfer *xfer,
 410                                 struct dma_slave_config cfg)
 411 {
 412         struct omap2_mcspi      *mcspi;
 413         struct omap2_mcspi_dma  *mcspi_dma;
 414         unsigned int            count;
 415
 416         mcspi = spi_master_get_devdata(spi->master);
 417         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 418         count = xfer->len;
 419
 420         if (mcspi_dma->dma_tx) {
 421                 struct dma_async_tx_descriptor *tx;
 422                 struct scatterlist sg;
 423
 424                 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
 425
 426                 sg_init_table(&sg, 1);
 427                 sg_dma_address(&sg) = xfer->tx_dma;
 428                 sg_dma_len(&sg) = xfer->len;
 429
 430                 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
 431                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 432                 if (tx) {
 433                         tx->callback = omap2_mcspi_tx_callback;
 434                         tx->callback_param = spi;
 435                         dmaengine_submit(tx);
 436                 } else {
 437                         /* FIXME: fall back to PIO? */
 438                 }
 439         }
 440         dma_async_issue_pending(mcspi_dma->dma_tx);
 441         omap2_mcspi_set_dma_req(spi, 0, 1);
 442
 443 }
 444
 445 static unsigned
 446 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
 447                                 struct dma_slave_config cfg,
 448                                 unsigned es)
 449 {
 450         struct omap2_mcspi      *mcspi;
 451         struct omap2_mcspi_dma  *mcspi_dma;
 452         unsigned int            count, dma_count;
 453         u32                     l;
 454         int                     elements = 0;
 455         int                     word_len, element_count;
 456         struct omap2_mcspi_cs   *cs = spi->controller_state;
 457         mcspi = spi_master_get_devdata(spi->master);
 458         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 459         count = xfer->len;
 460         dma_count = xfer->len;
 461
 462         /*
 463          *  In the "End-of-Transfer Procedure" section for DMA RX in OMAP35x TRM
 464          *  it mentions reducing DMA transfer length by one element in master
 465          *  normal mode.
 466          */
 467         if (mcspi->fifo_depth == 0)
 468                 dma_count -= es;
 469
 470         word_len = cs->word_len;
 471         l = mcspi_cached_chconf0(spi);
 472
 473         if (word_len <= 8)
 474                 element_count = count;
 475         else if (word_len <= 16)
 476                 element_count = count >> 1;
 477         else /* word_len <= 32 */
 478                 element_count = count >> 2;
 479
 480         if (mcspi_dma->dma_rx) {
 481                 struct dma_async_tx_descriptor *tx;
 482                 struct scatterlist sg;
 483
 484                 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
 485
 486                 /*
 487                  *  Reduce DMA transfer length by one more if McSPI is
 488                  *  configured in turbo mode.
 489                  */
 490                 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
 491                         dma_count -= es;
 492
 493                 sg_init_table(&sg, 1);
 494                 sg_dma_address(&sg) = xfer->rx_dma;
 495                 sg_dma_len(&sg) = dma_count;
 496
 497                 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
 498                                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT |
 499                                 DMA_CTRL_ACK);
 500                 if (tx) {
 501                         tx->callback = omap2_mcspi_rx_callback;
 502                         tx->callback_param = spi;
 503                         dmaengine_submit(tx);
 504                 } else {
 505                                 /* FIXME: fall back to PIO? */
 506                 }
 507         }
 508
 509         dma_async_issue_pending(mcspi_dma->dma_rx);
 510         omap2_mcspi_set_dma_req(spi, 1, 1);
 511
 512         wait_for_completion(&mcspi_dma->dma_rx_completion);
 513         dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
 514                          DMA_FROM_DEVICE);
 515
 516         if (mcspi->fifo_depth > 0)
 517                 return count;
 518
 519         /*
 520          *  Due to the DMA transfer length reduction the missing bytes must
 521          *  be read manually to receive all of the expected data.
 522          */
 523         omap2_mcspi_set_enable(spi, 0);
 524
 525         elements = element_count - 1;
 526
 527         if (l & OMAP2_MCSPI_CHCONF_TURBO) {
 528                 elements--;
 529
 530                 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
 531                                    & OMAP2_MCSPI_CHSTAT_RXS)) {
 532                         u32 w;
 533
 534                         w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 535                         if (word_len <= 8)
 536                                 ((u8 *)xfer->rx_buf)[elements++] = w;
 537                         else if (word_len <= 16)
 538                                 ((u16 *)xfer->rx_buf)[elements++] = w;
 539                         else /* word_len <= 32 */
 540                                 ((u32 *)xfer->rx_buf)[elements++] = w;
 541                 } else {
 542                         int bytes_per_word = mcspi_bytes_per_word(word_len);
 543                         dev_err(&spi->dev, "DMA RX penultimate word empty\n");
 544                         count -= (bytes_per_word << 1);
 545                         omap2_mcspi_set_enable(spi, 1);
 546                         return count;
 547                 }
 548         }
 549         if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
 550                                 & OMAP2_MCSPI_CHSTAT_RXS)) {
 551                 u32 w;
 552
 553                 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 554                 if (word_len <= 8)
 555                         ((u8 *)xfer->rx_buf)[elements] = w;
 556                 else if (word_len <= 16)
 557                         ((u16 *)xfer->rx_buf)[elements] = w;
 558                 else /* word_len <= 32 */
 559                         ((u32 *)xfer->rx_buf)[elements] = w;
 560         } else {
 561                 dev_err(&spi->dev, "DMA RX last word empty\n");
 562                 count -= mcspi_bytes_per_word(word_len);
 563         }
 564         omap2_mcspi_set_enable(spi, 1);
 565         return count;
 566 }
 567
 568 static unsigned
 569 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
 570 {
 571         struct omap2_mcspi      *mcspi;
 572         struct omap2_mcspi_cs   *cs = spi->controller_state;
 573         struct omap2_mcspi_dma  *mcspi_dma;
 574         unsigned int            count;
 575         u32                     l;
 576         u8                      *rx;
 577         const u8                *tx;
 578         struct dma_slave_config cfg;
 579         enum dma_slave_buswidth width;
 580         unsigned es;
 581         u32                     burst;
 582         void __iomem            *chstat_reg;
 583         void __iomem            *irqstat_reg;
 584         int                     wait_res;
 585
 586         mcspi = spi_master_get_devdata(spi->master);
 587         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 588         l = mcspi_cached_chconf0(spi);
 589
 590
 591         if (cs->word_len <= 8) {
 592                 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 593                 es = 1;
 594         } else if (cs->word_len <= 16) {
 595                 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 596                 es = 2;
 597         } else {
 598                 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 599                 es = 4;
 600         }
 601
 602         count = xfer->len;
 603         burst = 1;
 604
 605         if (mcspi->fifo_depth > 0) {
 606                 if (count > mcspi->fifo_depth)
 607                         burst = mcspi->fifo_depth / es;
 608                 else
 609                         burst = count / es;
 610         }
 611
 612         memset(&cfg, 0, sizeof(cfg));
 613         cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
 614         cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
 615         cfg.src_addr_width = width;
 616         cfg.dst_addr_width = width;
 617         cfg.src_maxburst = burst;
 618         cfg.dst_maxburst = burst;
 619
 620         rx = xfer->rx_buf;
 621         tx = xfer->tx_buf;
 622
 623         if (tx != NULL)
 624                 omap2_mcspi_tx_dma(spi, xfer, cfg);
 625
 626         if (rx != NULL)
 627                 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
 628
 629         if (tx != NULL) {
 630                 wait_for_completion(&mcspi_dma->dma_tx_completion);
 631                 dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len,
 632                                  DMA_TO_DEVICE);
 633
 634                 if (mcspi->fifo_depth > 0) {
 635                         irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
 636
 637                         if (mcspi_wait_for_reg_bit(irqstat_reg,
 638                                                 OMAP2_MCSPI_IRQSTATUS_EOW) < 0)
 639                                 dev_err(&spi->dev, "EOW timed out\n");
 640
 641                         mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS,
 642                                         OMAP2_MCSPI_IRQSTATUS_EOW);
 643                 }
 644
 645                 /* for TX_ONLY mode, be sure all words have shifted out */
 646                 if (rx == NULL) {
 647                         chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
 648                         if (mcspi->fifo_depth > 0) {
 649                                 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
 650                                                 OMAP2_MCSPI_CHSTAT_TXFFE);
 651                                 if (wait_res < 0)
 652                                         dev_err(&spi->dev, "TXFFE timed out\n");
 653                         } else {
 654                                 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
 655                                                 OMAP2_MCSPI_CHSTAT_TXS);
 656                                 if (wait_res < 0)
 657                                         dev_err(&spi->dev, "TXS timed out\n");
 658                         }
 659                         if (wait_res >= 0 &&
 660                                 (mcspi_wait_for_reg_bit(chstat_reg,
 661                                         OMAP2_MCSPI_CHSTAT_EOT) < 0))
 662                                 dev_err(&spi->dev, "EOT timed out\n");
 663                 }
 664         }
 665         return count;
 666 }
 667
 668 static unsigned
 669 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 670 {
 671         struct omap2_mcspi      *mcspi;
 672         struct omap2_mcspi_cs   *cs = spi->controller_state;
 673         unsigned int            count, c;
 674         u32                     l;
 675         void __iomem            *base = cs->base;
 676         void __iomem            *tx_reg;
 677         void __iomem            *rx_reg;
 678         void __iomem            *chstat_reg;
 679         int                     word_len;
 680
 681         mcspi = spi_master_get_devdata(spi->master);
 682         count = xfer->len;
 683         c = count;
 684         word_len = cs->word_len;
 685
 686         l = mcspi_cached_chconf0(spi);
 687
 688         /* We store the pre-calculated register addresses on stack to speed
 689          * up the transfer loop. */
 690         tx_reg          = base + OMAP2_MCSPI_TX0;
 691         rx_reg          = base + OMAP2_MCSPI_RX0;
 692         chstat_reg      = base + OMAP2_MCSPI_CHSTAT0;
 693
 694         if (c < (word_len>>3))
 695                 return 0;
 696
 697         if (word_len <= 8) {
 698                 u8              *rx;
 699                 const u8        *tx;
 700
 701                 rx = xfer->rx_buf;
 702                 tx = xfer->tx_buf;
 703
 704                 do {
 705                         c -= 1;
 706                         if (tx != NULL) {
 707                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 708                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 709                                         dev_err(&spi->dev, "TXS timed out\n");
 710                                         goto out;
 711                                 }
 712                                 dev_vdbg(&spi->dev, "write-%d %02x\n",
 713                                                 word_len, *tx);
 714                                 writel_relaxed(*tx++, tx_reg);
 715                         }
 716                         if (rx != NULL) {
 717                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 718                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 719                                         dev_err(&spi->dev, "RXS timed out\n");
 720                                         goto out;
 721                                 }
 722
 723                                 if (c == 1 && tx == NULL &&
 724                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 725                                         omap2_mcspi_set_enable(spi, 0);
 726                                         *rx++ = readl_relaxed(rx_reg);
 727                                         dev_vdbg(&spi->dev, "read-%d %02x\n",
 728                                                     word_len, *(rx - 1));
 729                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 730                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 731                                                 dev_err(&spi->dev,
 732                                                         "RXS timed out\n");
 733                                                 goto out;
 734                                         }
 735                                         c = 0;
 736                                 } else if (c == 0 && tx == NULL) {
 737                                         omap2_mcspi_set_enable(spi, 0);
 738                                 }
 739
 740                                 *rx++ = readl_relaxed(rx_reg);
 741                                 dev_vdbg(&spi->dev, "read-%d %02x\n",
 742                                                 word_len, *(rx - 1));
 743                         }
 744                 } while (c);
 745         } else if (word_len <= 16) {
 746                 u16             *rx;
 747                 const u16       *tx;
 748
 749                 rx = xfer->rx_buf;
 750                 tx = xfer->tx_buf;
 751                 do {
 752                         c -= 2;
 753                         if (tx != NULL) {
 754                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 755                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 756                                         dev_err(&spi->dev, "TXS timed out\n");
 757                                         goto out;
 758                                 }
 759                                 dev_vdbg(&spi->dev, "write-%d %04x\n",
 760                                                 word_len, *tx);
 761                                 writel_relaxed(*tx++, tx_reg);
 762                         }
 763                         if (rx != NULL) {
 764                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 765                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 766                                         dev_err(&spi->dev, "RXS timed out\n");
 767                                         goto out;
 768                                 }
 769
 770                                 if (c == 2 && tx == NULL &&
 771                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 772                                         omap2_mcspi_set_enable(spi, 0);
 773                                         *rx++ = readl_relaxed(rx_reg);
 774                                         dev_vdbg(&spi->dev, "read-%d %04x\n",
 775                                                     word_len, *(rx - 1));
 776                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 777                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 778                                                 dev_err(&spi->dev,
 779                                                         "RXS timed out\n");
 780                                                 goto out;
 781                                         }
 782                                         c = 0;
 783                                 } else if (c == 0 && tx == NULL) {
 784                                         omap2_mcspi_set_enable(spi, 0);
 785                                 }
 786
 787                                 *rx++ = readl_relaxed(rx_reg);
 788                                 dev_vdbg(&spi->dev, "read-%d %04x\n",
 789                                                 word_len, *(rx - 1));
 790                         }
 791                 } while (c >= 2);
 792         } else if (word_len <= 32) {
 793                 u32             *rx;
 794                 const u32       *tx;
 795
 796                 rx = xfer->rx_buf;
 797                 tx = xfer->tx_buf;
 798                 do {
 799                         c -= 4;
 800                         if (tx != NULL) {
 801                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 802                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 803                                         dev_err(&spi->dev, "TXS timed out\n");
 804                                         goto out;
 805                                 }
 806                                 dev_vdbg(&spi->dev, "write-%d %08x\n",
 807                                                 word_len, *tx);
 808                                 writel_relaxed(*tx++, tx_reg);
 809                         }
 810                         if (rx != NULL) {
 811                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 812                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 813                                         dev_err(&spi->dev, "RXS timed out\n");
 814                                         goto out;
 815                                 }
 816
 817                                 if (c == 4 && tx == NULL &&
 818                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 819                                         omap2_mcspi_set_enable(spi, 0);
 820                                         *rx++ = readl_relaxed(rx_reg);
 821                                         dev_vdbg(&spi->dev, "read-%d %08x\n",
 822                                                     word_len, *(rx - 1));
 823                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 824                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 825                                                 dev_err(&spi->dev,
 826                                                         "RXS timed out\n");
 827                                                 goto out;
 828                                         }
 829                                         c = 0;
 830                                 } else if (c == 0 && tx == NULL) {
 831                                         omap2_mcspi_set_enable(spi, 0);
 832                                 }
 833
 834                                 *rx++ = readl_relaxed(rx_reg);
 835                                 dev_vdbg(&spi->dev, "read-%d %08x\n",
 836                                                 word_len, *(rx - 1));
 837                         }
 838                 } while (c >= 4);
 839         }
 840
 841         /* for TX_ONLY mode, be sure all words have shifted out */
 842         if (xfer->rx_buf == NULL) {
 843                 if (mcspi_wait_for_reg_bit(chstat_reg,
 844                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 845                         dev_err(&spi->dev, "TXS timed out\n");
 846                 } else if (mcspi_wait_for_reg_bit(chstat_reg,
 847                                 OMAP2_MCSPI_CHSTAT_EOT) < 0)
 848                         dev_err(&spi->dev, "EOT timed out\n");
 849
 850                 /* disable chan to purge rx datas received in TX_ONLY transfer,
 851                  * otherwise these rx datas will affect the direct following
 852                  * RX_ONLY transfer.
 853                  */
 854                 omap2_mcspi_set_enable(spi, 0);
 855         }
 856 out:
 857         omap2_mcspi_set_enable(spi, 1);
 858         return count - c;
 859 }
 860
 861 static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
 862 {
 863         u32 div;
 864
 865         for (div = 0; div < 15; div++)
 866                 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
 867                         return div;
 868
 869         return 15;
 870 }
 871
 872 /* called only when no transfer is active to this device */
 873 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
 874                 struct spi_transfer *t)
 875 {
 876         struct omap2_mcspi_cs *cs = spi->controller_state;
 877         struct omap2_mcspi *mcspi;
 878         struct spi_master *spi_cntrl;
 879         u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0;
 880         u8 word_len = spi->bits_per_word;
 881         u32 speed_hz = spi->max_speed_hz;
 882
 883         mcspi = spi_master_get_devdata(spi->master);
 884         spi_cntrl = mcspi->master;
 885
 886         if (t != NULL && t->bits_per_word)
 887                 word_len = t->bits_per_word;
 888
 889         cs->word_len = word_len;
 890
 891         if (t && t->speed_hz)
 892                 speed_hz = t->speed_hz;
 893
 894         speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
 895         if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) {
 896                 clkd = omap2_mcspi_calc_divisor(speed_hz);
 897                 speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd;
 898                 clkg = 0;
 899         } else {
 900                 div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz;
 901                 speed_hz = OMAP2_MCSPI_MAX_FREQ / div;
 902                 clkd = (div - 1) & 0xf;
 903                 extclk = (div - 1) >> 4;
 904                 clkg = OMAP2_MCSPI_CHCONF_CLKG;
 905         }
 906
 907         l = mcspi_cached_chconf0(spi);
 908
 909         /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
 910          * REVISIT: this controller could support SPI_3WIRE mode.
 911          */
 912         if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
 913                 l &= ~OMAP2_MCSPI_CHCONF_IS;
 914                 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
 915                 l |= OMAP2_MCSPI_CHCONF_DPE0;
 916         } else {
 917                 l |= OMAP2_MCSPI_CHCONF_IS;
 918                 l |= OMAP2_MCSPI_CHCONF_DPE1;
 919                 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
 920         }
 921
 922         /* wordlength */
 923         l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
 924         l |= (word_len - 1) << 7;
 925
 926         /* set chipselect polarity; manage with FORCE */
 927         if (!(spi->mode & SPI_CS_HIGH))
 928                 l |= OMAP2_MCSPI_CHCONF_EPOL;   /* active-low; normal */
 929         else
 930                 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
 931
 932         /* set clock divisor */
 933         l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
 934         l |= clkd << 2;
 935
 936         /* set clock granularity */
 937         l &= ~OMAP2_MCSPI_CHCONF_CLKG;
 938         l |= clkg;
 939         if (clkg) {
 940                 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK;
 941                 cs->chctrl0 |= extclk << 8;
 942                 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
 943         }
 944
 945         /* set SPI mode 0..3 */
 946         if (spi->mode & SPI_CPOL)
 947                 l |= OMAP2_MCSPI_CHCONF_POL;
 948         else
 949                 l &= ~OMAP2_MCSPI_CHCONF_POL;
 950         if (spi->mode & SPI_CPHA)
 951                 l |= OMAP2_MCSPI_CHCONF_PHA;
 952         else
 953                 l &= ~OMAP2_MCSPI_CHCONF_PHA;
 954
 955         mcspi_write_chconf0(spi, l);
 956
 957         cs->mode = spi->mode;
 958
 959         dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
 960                         speed_hz,
 961                         (spi->mode & SPI_CPHA) ? "trailing" : "leading",
 962                         (spi->mode & SPI_CPOL) ? "inverted" : "normal");
 963
 964         return 0;
 965 }
 966
 967 /*
 968  * Note that we currently allow DMA only if we get a channel
 969  * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
 970  */
 971 static int omap2_mcspi_request_dma(struct spi_device *spi)
 972 {
 973         struct spi_master       *master = spi->master;
 974         struct omap2_mcspi      *mcspi;
 975         struct omap2_mcspi_dma  *mcspi_dma;
 976         int ret = 0;
 977
 978         mcspi = spi_master_get_devdata(master);
 979         mcspi_dma = mcspi->dma_channels + spi->chip_select;
 980
 981         init_completion(&mcspi_dma->dma_rx_completion);
 982         init_completion(&mcspi_dma->dma_tx_completion);
 983
 984         mcspi_dma->dma_rx = dma_request_chan(&master->dev,
 985                                              mcspi_dma->dma_rx_ch_name);
 986         if (IS_ERR(mcspi_dma->dma_rx)) {
 987                 ret = PTR_ERR(mcspi_dma->dma_rx);
 988                 mcspi_dma->dma_rx = NULL;
 989                 goto no_dma;
 990         }
 991
 992         mcspi_dma->dma_tx = dma_request_chan(&master->dev,
 993                                              mcspi_dma->dma_tx_ch_name);
 994         if (IS_ERR(mcspi_dma->dma_tx)) {
 995                 ret = PTR_ERR(mcspi_dma->dma_tx);
 996                 mcspi_dma->dma_tx = NULL;
 997                 dma_release_channel(mcspi_dma->dma_rx);
 998                 mcspi_dma->dma_rx = NULL;
 999         }
1000
1001 no_dma:
1002         return ret;
1003 }
1004
1005 static int omap2_mcspi_setup(struct spi_device *spi)
1006 {
1007         int                     ret;
1008         struct omap2_mcspi      *mcspi = spi_master_get_devdata(spi->master);
1009         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1010         struct omap2_mcspi_dma  *mcspi_dma;
1011         struct omap2_mcspi_cs   *cs = spi->controller_state;
1012
1013         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1014
1015         if (!cs) {
1016                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
1017                 if (!cs)
1018                         return -ENOMEM;
1019                 cs->base = mcspi->base + spi->chip_select * 0x14;
1020                 cs->phys = mcspi->phys + spi->chip_select * 0x14;
1021                 cs->mode = 0;
1022                 cs->chconf0 = 0;
1023                 cs->chctrl0 = 0;
1024                 spi->controller_state = cs;
1025                 /* Link this to context save list */
1026                 list_add_tail(&cs->node, &ctx->cs);
1027
1028                 if (gpio_is_valid(spi->cs_gpio)) {
1029                         ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev));
1030                         if (ret) {
1031                                 dev_err(&spi->dev, "failed to request gpio\n");
1032                                 return ret;
1033                         }
1034                         gpio_direction_output(spi->cs_gpio,
1035                                          !(spi->mode & SPI_CS_HIGH));
1036                 }
1037         }
1038
1039         if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
1040                 ret = omap2_mcspi_request_dma(spi);
1041                 if (ret)
1042                         dev_warn(&spi->dev, "not using DMA for McSPI (%d)\n",
1043                                  ret);
1044         }
1045
1046         ret = pm_runtime_get_sync(mcspi->dev);
1047         if (ret < 0)
1048                 return ret;
1049
1050         ret = omap2_mcspi_setup_transfer(spi, NULL);
1051         pm_runtime_mark_last_busy(mcspi->dev);
1052         pm_runtime_put_autosuspend(mcspi->dev);
1053
1054         return ret;
1055 }
1056
1057 static void omap2_mcspi_cleanup(struct spi_device *spi)
1058 {
1059         struct omap2_mcspi      *mcspi;
1060         struct omap2_mcspi_dma  *mcspi_dma;
1061         struct omap2_mcspi_cs   *cs;
1062
1063         mcspi = spi_master_get_devdata(spi->master);
1064
1065         if (spi->controller_state) {
1066                 /* Unlink controller state from context save list */
1067                 cs = spi->controller_state;
1068                 list_del(&cs->node);
1069
1070                 kfree(cs);
1071         }
1072
1073         if (spi->chip_select < spi->master->num_chipselect) {
1074                 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1075
1076                 if (mcspi_dma->dma_rx) {
1077                         dma_release_channel(mcspi_dma->dma_rx);
1078                         mcspi_dma->dma_rx = NULL;
1079                 }
1080                 if (mcspi_dma->dma_tx) {
1081                         dma_release_channel(mcspi_dma->dma_tx);
1082                         mcspi_dma->dma_tx = NULL;
1083                 }
1084         }
1085
1086         if (gpio_is_valid(spi->cs_gpio))
1087                 gpio_free(spi->cs_gpio);
1088 }
1089
1090 static int omap2_mcspi_work_one(struct omap2_mcspi *mcspi,
1091                 struct spi_device *spi, struct spi_transfer *t)
1092 {
1093
1094         /* We only enable one channel at a time -- the one whose message is
1095          * -- although this controller would gladly
1096          * arbitrate among multiple channels.  This corresponds to "single
1097          * channel" master mode.  As a side effect, we need to manage the
1098          * chipselect with the FORCE bit ... CS != channel enable.
1099          */
1100
1101         struct spi_master               *master;
1102         struct omap2_mcspi_dma          *mcspi_dma;
1103         struct omap2_mcspi_cs           *cs;
1104         struct omap2_mcspi_device_config *cd;
1105         int                             par_override = 0;
1106         int                             status = 0;
1107         u32                             chconf;
1108
1109         master = spi->master;
1110         mcspi_dma = mcspi->dma_channels + spi->chip_select;
1111         cs = spi->controller_state;
1112         cd = spi->controller_data;
1113
1114         /*
1115          * The slave driver could have changed spi->mode in which case
1116          * it will be different from cs->mode (the current hardware setup).
1117          * If so, set par_override (even though its not a parity issue) so
1118          * omap2_mcspi_setup_transfer will be called to configure the hardware
1119          * with the correct mode on the first iteration of the loop below.
1120          */
1121         if (spi->mode != cs->mode)
1122                 par_override = 1;
1123
1124         omap2_mcspi_set_enable(spi, 0);
1125
1126         if (gpio_is_valid(spi->cs_gpio))
1127                 omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH);
1128
1129         if (par_override ||
1130             (t->speed_hz != spi->max_speed_hz) ||
1131             (t->bits_per_word != spi->bits_per_word)) {
1132                 par_override = 1;
1133                 status = omap2_mcspi_setup_transfer(spi, t);
1134                 if (status < 0)
1135                         goto out;
1136                 if (t->speed_hz == spi->max_speed_hz &&
1137                     t->bits_per_word == spi->bits_per_word)
1138                         par_override = 0;
1139         }
1140         if (cd && cd->cs_per_word) {
1141                 chconf = mcspi->ctx.modulctrl;
1142                 chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
1143                 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1144                 mcspi->ctx.modulctrl =
1145                         mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1146         }
1147
1148         chconf = mcspi_cached_chconf0(spi);
1149         chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
1150         chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
1151
1152         if (t->tx_buf == NULL)
1153                 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
1154         else if (t->rx_buf == NULL)
1155                 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
1156
1157         if (cd && cd->turbo_mode && t->tx_buf == NULL) {
1158                 /* Turbo mode is for more than one word */
1159                 if (t->len > ((cs->word_len + 7) >> 3))
1160                         chconf |= OMAP2_MCSPI_CHCONF_TURBO;
1161         }
1162
1163         mcspi_write_chconf0(spi, chconf);
1164
1165         if (t->len) {
1166                 unsigned        count;
1167
1168                 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1169                     (t->len >= DMA_MIN_BYTES))
1170                         omap2_mcspi_set_fifo(spi, t, 1);
1171
1172                 omap2_mcspi_set_enable(spi, 1);
1173
1174                 /* RX_ONLY mode needs dummy data in TX reg */
1175                 if (t->tx_buf == NULL)
1176                         writel_relaxed(0, cs->base
1177                                         + OMAP2_MCSPI_TX0);
1178
1179                 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1180                     (t->len >= DMA_MIN_BYTES))
1181                         count = omap2_mcspi_txrx_dma(spi, t);
1182                 else
1183                         count = omap2_mcspi_txrx_pio(spi, t);
1184
1185                 if (count != t->len) {
1186                         status = -EIO;
1187                         goto out;
1188                 }
1189         }
1190
1191         omap2_mcspi_set_enable(spi, 0);
1192
1193         if (mcspi->fifo_depth > 0)
1194                 omap2_mcspi_set_fifo(spi, t, 0);
1195
1196 out:
1197         /* Restore defaults if they were overriden */
1198         if (par_override) {
1199                 par_override = 0;
1200                 status = omap2_mcspi_setup_transfer(spi, NULL);
1201         }
1202
1203         if (cd && cd->cs_per_word) {
1204                 chconf = mcspi->ctx.modulctrl;
1205                 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1206                 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1207                 mcspi->ctx.modulctrl =
1208                         mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1209         }
1210
1211         omap2_mcspi_set_enable(spi, 0);
1212
1213         if (gpio_is_valid(spi->cs_gpio))
1214                 omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH));
1215
1216         if (mcspi->fifo_depth > 0 && t)
1217                 omap2_mcspi_set_fifo(spi, t, 0);
1218
1219         return status;
1220 }
1221
1222 static int omap2_mcspi_prepare_message(struct spi_master *master,
1223                                        struct spi_message *msg)
1224 {
1225         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
1226         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1227         struct omap2_mcspi_cs   *cs;
1228
1229         /* Only a single channel can have the FORCE bit enabled
1230          * in its chconf0 register.
1231          * Scan all channels and disable them except the current one.
1232          * A FORCE can remain from a last transfer having cs_change enabled
1233          */
1234         list_for_each_entry(cs, &ctx->cs, node) {
1235                 if (msg->spi->controller_state == cs)
1236                         continue;
1237
1238                 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) {
1239                         cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1240                         writel_relaxed(cs->chconf0,
1241                                         cs->base + OMAP2_MCSPI_CHCONF0);
1242                         readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0);
1243                 }
1244         }
1245
1246         return 0;
1247 }
1248
1249 static int omap2_mcspi_transfer_one(struct spi_master *master,
1250                 struct spi_device *spi, struct spi_transfer *t)
1251 {
1252         struct omap2_mcspi      *mcspi;
1253         struct omap2_mcspi_dma  *mcspi_dma;
1254         const void      *tx_buf = t->tx_buf;
1255         void            *rx_buf = t->rx_buf;
1256         unsigned        len = t->len;
1257
1258         mcspi = spi_master_get_devdata(master);
1259         mcspi_dma = mcspi->dma_channels + spi->chip_select;
1260
1261         if ((len && !(rx_buf || tx_buf))) {
1262                 dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
1263                                 t->speed_hz,
1264                                 len,
1265                                 tx_buf ? "tx" : "",
1266                                 rx_buf ? "rx" : "",
1267                                 t->bits_per_word);
1268                 return -EINVAL;
1269         }
1270
1271         if (len < DMA_MIN_BYTES)
1272                 goto skip_dma_map;
1273
1274         if (mcspi_dma->dma_tx && tx_buf != NULL) {
1275                 t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
1276                                 len, DMA_TO_DEVICE);
1277                 if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
1278                         dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1279                                         'T', len);
1280                         return -EINVAL;
1281                 }
1282         }
1283         if (mcspi_dma->dma_rx && rx_buf != NULL) {
1284                 t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
1285                                 DMA_FROM_DEVICE);
1286                 if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
1287                         dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1288                                         'R', len);
1289                         if (tx_buf != NULL)
1290                                 dma_unmap_single(mcspi->dev, t->tx_dma,
1291                                                 len, DMA_TO_DEVICE);
1292                         return -EINVAL;
1293                 }
1294         }
1295
1296 skip_dma_map:
1297         return omap2_mcspi_work_one(mcspi, spi, t);
1298 }
1299
1300 static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1301 {
1302         struct spi_master       *master = mcspi->master;
1303         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1304         int                     ret = 0;
1305
1306         ret = pm_runtime_get_sync(mcspi->dev);
1307         if (ret < 0)
1308                 return ret;
1309
1310         mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1311                         OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1312         ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1313
1314         omap2_mcspi_set_master_mode(master);
1315         pm_runtime_mark_last_busy(mcspi->dev);
1316         pm_runtime_put_autosuspend(mcspi->dev);
1317         return 0;
1318 }
1319
1320 static int omap_mcspi_runtime_resume(struct device *dev)
1321 {
1322         struct omap2_mcspi      *mcspi;
1323         struct spi_master       *master;
1324
1325         master = dev_get_drvdata(dev);
1326         mcspi = spi_master_get_devdata(master);
1327         omap2_mcspi_restore_ctx(mcspi);
1328
1329         return 0;
1330 }
1331
1332 static struct omap2_mcspi_platform_config omap2_pdata = {
1333         .regs_offset = 0,
1334 };
1335
1336 static struct omap2_mcspi_platform_config omap4_pdata = {
1337         .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1338 };
1339
1340 static const struct of_device_id omap_mcspi_of_match[] = {
1341         {
1342                 .compatible = "ti,omap2-mcspi",
1343                 .data = &omap2_pdata,
1344         },
1345         {
1346                 .compatible = "ti,omap4-mcspi",
1347                 .data = &omap4_pdata,
1348         },
1349         { },
1350 };
1351 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1352
1353 static int omap2_mcspi_probe(struct platform_device *pdev)
1354 {
1355         struct spi_master       *master;
1356         const struct omap2_mcspi_platform_config *pdata;
1357         struct omap2_mcspi      *mcspi;
1358         struct resource         *r;
1359         int                     status = 0, i;
1360         u32                     regs_offset = 0;
1361         static int              bus_num = 1;
1362         struct device_node      *node = pdev->dev.of_node;
1363         const struct of_device_id *match;
1364
1365         master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1366         if (master == NULL) {
1367                 dev_dbg(&pdev->dev, "master allocation failed\n");
1368                 return -ENOMEM;
1369         }
1370
1371         /* the spi->mode bits understood by this driver: */
1372         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1373         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1374         master->setup = omap2_mcspi_setup;
1375         master->auto_runtime_pm = true;
1376         master->prepare_message = omap2_mcspi_prepare_message;
1377         master->transfer_one = omap2_mcspi_transfer_one;
1378         master->set_cs = omap2_mcspi_set_cs;
1379         master->cleanup = omap2_mcspi_cleanup;
1380         master->dev.of_node = node;
1381         master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;
1382         master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15;
1383
1384         platform_set_drvdata(pdev, master);
1385
1386         mcspi = spi_master_get_devdata(master);
1387         mcspi->master = master;
1388
1389         match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1390         if (match) {
1391                 u32 num_cs = 1; /* default number of chipselect */
1392                 pdata = match->data;
1393
1394                 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1395                 master->num_chipselect = num_cs;
1396                 master->bus_num = bus_num++;
1397                 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1398                         mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1399         } else {
1400                 pdata = dev_get_platdata(&pdev->dev);
1401                 master->num_chipselect = pdata->num_cs;
1402                 if (pdev->id != -1)
1403                         master->bus_num = pdev->id;
1404                 mcspi->pin_dir = pdata->pin_dir;
1405         }
1406         regs_offset = pdata->regs_offset;
1407
1408         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1409         if (r == NULL) {
1410                 status = -ENODEV;
1411                 goto free_master;
1412         }
1413
1414         r->start += regs_offset;
1415         r->end += regs_offset;
1416         mcspi->phys = r->start;
1417
1418         mcspi->base = devm_ioremap_resource(&pdev->dev, r);
1419         if (IS_ERR(mcspi->base)) {
1420                 status = PTR_ERR(mcspi->base);
1421                 goto free_master;
1422         }
1423
1424         mcspi->dev = &pdev->dev;
1425
1426         INIT_LIST_HEAD(&mcspi->ctx.cs);
1427
1428         mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect,
1429                                            sizeof(struct omap2_mcspi_dma),
1430                                            GFP_KERNEL);
1431         if (mcspi->dma_channels == NULL) {
1432                 status = -ENOMEM;
1433                 goto free_master;
1434         }
1435
1436         for (i = 0; i < master->num_chipselect; i++) {
1437                 sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i);
1438                 sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i);
1439         }
1440
1441         if (status < 0)
1442                 goto free_master;
1443
1444         pm_runtime_use_autosuspend(&pdev->dev);
1445         pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1446         pm_runtime_enable(&pdev->dev);
1447
1448         status = omap2_mcspi_master_setup(mcspi);
1449         if (status < 0)
1450                 goto disable_pm;
1451
1452         status = devm_spi_register_master(&pdev->dev, master);
1453         if (status < 0)
1454                 goto disable_pm;
1455
1456         return status;
1457
1458 disable_pm:
1459         pm_runtime_dont_use_autosuspend(&pdev->dev);
1460         pm_runtime_put_sync(&pdev->dev);
1461         pm_runtime_disable(&pdev->dev);
1462 free_master:
1463         spi_master_put(master);
1464         return status;
1465 }
1466
1467 static int omap2_mcspi_remove(struct platform_device *pdev)
1468 {
1469         struct spi_master *master = platform_get_drvdata(pdev);
1470         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1471
1472         pm_runtime_dont_use_autosuspend(mcspi->dev);
1473         pm_runtime_put_sync(mcspi->dev);
1474         pm_runtime_disable(&pdev->dev);
1475
1476         return 0;
1477 }
1478
1479 /* work with hotplug and coldplug */
1480 MODULE_ALIAS("platform:omap2_mcspi");
1481
1482 #ifdef  CONFIG_SUSPEND
1483 /*
1484  * When SPI wake up from off-mode, CS is in activate state. If it was in
1485  * unactive state when driver was suspend, then force it to unactive state at
1486  * wake up.
1487  */
1488 static int omap2_mcspi_resume(struct device *dev)
1489 {
1490         struct spi_master       *master = dev_get_drvdata(dev);
1491         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
1492         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1493         struct omap2_mcspi_cs   *cs;
1494
1495         pm_runtime_get_sync(mcspi->dev);
1496         list_for_each_entry(cs, &ctx->cs, node) {
1497                 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1498                         /*
1499                          * We need to toggle CS state for OMAP take this
1500                          * change in account.
1501                          */
1502                         cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1503                         writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1504                         cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1505                         writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1506                 }
1507         }
1508         pm_runtime_mark_last_busy(mcspi->dev);
1509         pm_runtime_put_autosuspend(mcspi->dev);
1510
1511         return pinctrl_pm_select_default_state(dev);
1512 }
1513
1514 static int omap2_mcspi_suspend(struct device *dev)
1515 {
1516         return pinctrl_pm_select_sleep_state(dev);
1517 }
1518
1519 #else
1520 #define omap2_mcspi_suspend     NULL
1521 #define omap2_mcspi_resume      NULL
1522 #endif
1523
1524 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1525         .resume = omap2_mcspi_resume,
1526         .suspend = omap2_mcspi_suspend,
1527         .runtime_resume = omap_mcspi_runtime_resume,
1528 };
1529
1530 static struct platform_driver omap2_mcspi_driver = {
1531         .driver = {
1532                 .name =         "omap2_mcspi",
1533                 .pm =           &omap2_mcspi_pm_ops,
1534                 .of_match_table = omap_mcspi_of_match,
1535         },
1536         .probe =        omap2_mcspi_probe,
1537         .remove =       omap2_mcspi_remove,
1538 };
1539
1540 module_platform_driver(omap2_mcspi_driver);
1541 MODULE_LICENSE("GPL");