2 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
4 * Copyright (C) 2008-2012 ST-Ericsson AB
5 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
7 * Author: Linus Walleij <linus.walleij@stericsson.com>
9 * Initial version inspired by:
10 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
11 * Initial adoption to PL022 by:
12 * Sachin Verma <sachin.verma@st.com>
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/device.h>
28 #include <linux/ioport.h>
29 #include <linux/errno.h>
30 #include <linux/interrupt.h>
31 #include <linux/spi/spi.h>
32 #include <linux/delay.h>
33 #include <linux/clk.h>
34 #include <linux/err.h>
35 #include <linux/amba/bus.h>
36 #include <linux/amba/pl022.h>
38 #include <linux/slab.h>
39 #include <linux/dmaengine.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/scatterlist.h>
42 #include <linux/pm_runtime.h>
43 #include <linux/gpio.h>
44 #include <linux/of_gpio.h>
45 #include <linux/pinctrl/consumer.h>
48 * This macro is used to define some register default values.
49 * reg is masked with mask, the OR:ed with an (again masked)
50 * val shifted sb steps to the left.
52 #define SSP_WRITE_BITS(reg, val, mask, sb) \
53 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask))))
56 * This macro is also used to define some default values.
57 * It will just shift val by sb steps to the left and mask
58 * the result with mask.
60 #define GEN_MASK_BITS(val, mask, sb) \
61 (((val)<<(sb)) & (mask))
64 #define DO_NOT_DRIVE_TX 1
66 #define DO_NOT_QUEUE_DMA 0
73 * Macros to access SSP Registers with their offsets
75 #define SSP_CR0(r) (r + 0x000)
76 #define SSP_CR1(r) (r + 0x004)
77 #define SSP_DR(r) (r + 0x008)
78 #define SSP_SR(r) (r + 0x00C)
79 #define SSP_CPSR(r) (r + 0x010)
80 #define SSP_IMSC(r) (r + 0x014)
81 #define SSP_RIS(r) (r + 0x018)
82 #define SSP_MIS(r) (r + 0x01C)
83 #define SSP_ICR(r) (r + 0x020)
84 #define SSP_DMACR(r) (r + 0x024)
85 #define SSP_CSR(r) (r + 0x030) /* vendor extension */
86 #define SSP_ITCR(r) (r + 0x080)
87 #define SSP_ITIP(r) (r + 0x084)
88 #define SSP_ITOP(r) (r + 0x088)
89 #define SSP_TDR(r) (r + 0x08C)
91 #define SSP_PID0(r) (r + 0xFE0)
92 #define SSP_PID1(r) (r + 0xFE4)
93 #define SSP_PID2(r) (r + 0xFE8)
94 #define SSP_PID3(r) (r + 0xFEC)
96 #define SSP_CID0(r) (r + 0xFF0)
97 #define SSP_CID1(r) (r + 0xFF4)
98 #define SSP_CID2(r) (r + 0xFF8)
99 #define SSP_CID3(r) (r + 0xFFC)
102 * SSP Control Register 0 - SSP_CR0
104 #define SSP_CR0_MASK_DSS (0x0FUL << 0)
105 #define SSP_CR0_MASK_FRF (0x3UL << 4)
106 #define SSP_CR0_MASK_SPO (0x1UL << 6)
107 #define SSP_CR0_MASK_SPH (0x1UL << 7)
108 #define SSP_CR0_MASK_SCR (0xFFUL << 8)
111 * The ST version of this block moves som bits
112 * in SSP_CR0 and extends it to 32 bits
114 #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0)
115 #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5)
116 #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16)
117 #define SSP_CR0_MASK_FRF_ST (0x3UL << 21)
120 * SSP Control Register 0 - SSP_CR1
122 #define SSP_CR1_MASK_LBM (0x1UL << 0)
123 #define SSP_CR1_MASK_SSE (0x1UL << 1)
124 #define SSP_CR1_MASK_MS (0x1UL << 2)
125 #define SSP_CR1_MASK_SOD (0x1UL << 3)
128 * The ST version of this block adds some bits
131 #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4)
132 #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5)
133 #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6)
134 #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7)
135 #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10)
136 /* This one is only in the PL023 variant */
137 #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)
140 * SSP Status Register - SSP_SR
142 #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */
143 #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */
144 #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */
145 #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */
146 #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */
149 * SSP Clock Prescale Register - SSP_CPSR
151 #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0)
154 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC
156 #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */
157 #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */
158 #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */
159 #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */
162 * SSP Raw Interrupt Status Register - SSP_RIS
164 /* Receive Overrun Raw Interrupt status */
165 #define SSP_RIS_MASK_RORRIS (0x1UL << 0)
166 /* Receive Timeout Raw Interrupt status */
167 #define SSP_RIS_MASK_RTRIS (0x1UL << 1)
168 /* Receive FIFO Raw Interrupt status */
169 #define SSP_RIS_MASK_RXRIS (0x1UL << 2)
170 /* Transmit FIFO Raw Interrupt status */
171 #define SSP_RIS_MASK_TXRIS (0x1UL << 3)
174 * SSP Masked Interrupt Status Register - SSP_MIS
176 /* Receive Overrun Masked Interrupt status */
177 #define SSP_MIS_MASK_RORMIS (0x1UL << 0)
178 /* Receive Timeout Masked Interrupt status */
179 #define SSP_MIS_MASK_RTMIS (0x1UL << 1)
180 /* Receive FIFO Masked Interrupt status */
181 #define SSP_MIS_MASK_RXMIS (0x1UL << 2)
182 /* Transmit FIFO Masked Interrupt status */
183 #define SSP_MIS_MASK_TXMIS (0x1UL << 3)
186 * SSP Interrupt Clear Register - SSP_ICR
188 /* Receive Overrun Raw Clear Interrupt bit */
189 #define SSP_ICR_MASK_RORIC (0x1UL << 0)
190 /* Receive Timeout Clear Interrupt bit */
191 #define SSP_ICR_MASK_RTIC (0x1UL << 1)
194 * SSP DMA Control Register - SSP_DMACR
196 /* Receive DMA Enable bit */
197 #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0)
198 /* Transmit DMA Enable bit */
199 #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1)
202 * SSP Chip Select Control Register - SSP_CSR
205 #define SSP_CSR_CSVALUE_MASK (0x1FUL << 0)
208 * SSP Integration Test control Register - SSP_ITCR
210 #define SSP_ITCR_MASK_ITEN (0x1UL << 0)
211 #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1)
214 * SSP Integration Test Input Register - SSP_ITIP
216 #define ITIP_MASK_SSPRXD (0x1UL << 0)
217 #define ITIP_MASK_SSPFSSIN (0x1UL << 1)
218 #define ITIP_MASK_SSPCLKIN (0x1UL << 2)
219 #define ITIP_MASK_RXDMAC (0x1UL << 3)
220 #define ITIP_MASK_TXDMAC (0x1UL << 4)
221 #define ITIP_MASK_SSPTXDIN (0x1UL << 5)
224 * SSP Integration Test output Register - SSP_ITOP
226 #define ITOP_MASK_SSPTXD (0x1UL << 0)
227 #define ITOP_MASK_SSPFSSOUT (0x1UL << 1)
228 #define ITOP_MASK_SSPCLKOUT (0x1UL << 2)
229 #define ITOP_MASK_SSPOEn (0x1UL << 3)
230 #define ITOP_MASK_SSPCTLOEn (0x1UL << 4)
231 #define ITOP_MASK_RORINTR (0x1UL << 5)
232 #define ITOP_MASK_RTINTR (0x1UL << 6)
233 #define ITOP_MASK_RXINTR (0x1UL << 7)
234 #define ITOP_MASK_TXINTR (0x1UL << 8)
235 #define ITOP_MASK_INTR (0x1UL << 9)
236 #define ITOP_MASK_RXDMABREQ (0x1UL << 10)
237 #define ITOP_MASK_RXDMASREQ (0x1UL << 11)
238 #define ITOP_MASK_TXDMABREQ (0x1UL << 12)
239 #define ITOP_MASK_TXDMASREQ (0x1UL << 13)
242 * SSP Test Data Register - SSP_TDR
244 #define TDR_MASK_TESTDATA (0xFFFFFFFF)
248 * we use the spi_message.state (void *) pointer to
249 * hold a single state value, that's why all this
250 * (void *) casting is done here.
252 #define STATE_START ((void *) 0)
253 #define STATE_RUNNING ((void *) 1)
254 #define STATE_DONE ((void *) 2)
255 #define STATE_ERROR ((void *) -1)
256 #define STATE_TIMEOUT ((void *) -2)
259 * SSP State - Whether Enabled or Disabled
261 #define SSP_DISABLED (0)
262 #define SSP_ENABLED (1)
265 * SSP DMA State - Whether DMA Enabled or Disabled
267 #define SSP_DMA_DISABLED (0)
268 #define SSP_DMA_ENABLED (1)
273 #define SSP_DEFAULT_CLKRATE 0x2
274 #define SSP_DEFAULT_PRESCALE 0x40
277 * SSP Clock Parameter ranges
279 #define CPSDVR_MIN 0x02
280 #define CPSDVR_MAX 0xFE
285 * SSP Interrupt related Macros
287 #define DEFAULT_SSP_REG_IMSC 0x0UL
288 #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC
289 #define ENABLE_ALL_INTERRUPTS ( \
290 SSP_IMSC_MASK_RORIM | \
291 SSP_IMSC_MASK_RTIM | \
292 SSP_IMSC_MASK_RXIM | \
296 #define CLEAR_ALL_INTERRUPTS 0x3
298 #define SPI_POLLING_TIMEOUT 1000
301 * The type of reading going on on this chip
311 * The type of writing going on on this chip
321 * struct vendor_data - vendor-specific config parameters
322 * for PL022 derivates
323 * @fifodepth: depth of FIFOs (both)
324 * @max_bpw: maximum number of bits per word
325 * @unidir: supports unidirection transfers
326 * @extended_cr: 32 bit wide control register 0 with extra
327 * features and extra features in CR1 as found in the ST variants
328 * @pl023: supports a subset of the ST extensions called "PL023"
329 * @internal_cs_ctrl: supports chip select control register
338 bool internal_cs_ctrl;
342 * struct pl022 - This is the private SSP driver data structure
343 * @adev: AMBA device model hookup
344 * @vendor: vendor data for the IP block
345 * @phybase: the physical memory where the SSP device resides
346 * @virtbase: the virtual memory where the SSP is mapped
347 * @clk: outgoing clock "SPICLK" for the SPI bus
348 * @master: SPI framework hookup
349 * @master_info: controller-specific data from machine setup
350 * @pump_transfers: Tasklet used in Interrupt Transfer mode
351 * @cur_msg: Pointer to current spi_message being processed
352 * @cur_transfer: Pointer to current spi_transfer
353 * @cur_chip: pointer to current clients chip(assigned from controller_state)
354 * @next_msg_cs_active: the next message in the queue has been examined
355 * and it was found that it uses the same chip select as the previous
356 * message, so we left it active after the previous transfer, and it's
358 * @tx: current position in TX buffer to be read
359 * @tx_end: end position in TX buffer to be read
360 * @rx: current position in RX buffer to be written
361 * @rx_end: end position in RX buffer to be written
362 * @read: the type of read currently going on
363 * @write: the type of write currently going on
364 * @exp_fifo_level: expected FIFO level
365 * @dma_rx_channel: optional channel for RX DMA
366 * @dma_tx_channel: optional channel for TX DMA
367 * @sgt_rx: scattertable for the RX transfer
368 * @sgt_tx: scattertable for the TX transfer
369 * @dummypage: a dummy page used for driving data on the bus with DMA
370 * @cur_cs: current chip select (gpio)
371 * @chipselects: list of chipselects (gpios)
374 struct amba_device *adev;
375 struct vendor_data *vendor;
376 resource_size_t phybase;
377 void __iomem *virtbase;
379 struct spi_master *master;
380 struct pl022_ssp_controller *master_info;
381 /* Message per-transfer pump */
382 struct tasklet_struct pump_transfers;
383 struct spi_message *cur_msg;
384 struct spi_transfer *cur_transfer;
385 struct chip_data *cur_chip;
386 bool next_msg_cs_active;
391 enum ssp_reading read;
392 enum ssp_writing write;
394 enum ssp_rx_level_trig rx_lev_trig;
395 enum ssp_tx_level_trig tx_lev_trig;
397 #ifdef CONFIG_DMA_ENGINE
398 struct dma_chan *dma_rx_channel;
399 struct dma_chan *dma_tx_channel;
400 struct sg_table sgt_rx;
401 struct sg_table sgt_tx;
410 * struct chip_data - To maintain runtime state of SSP for each client chip
411 * @cr0: Value of control register CR0 of SSP - on later ST variants this
412 * register is 32 bits wide rather than just 16
413 * @cr1: Value of control register CR1 of SSP
414 * @dmacr: Value of DMA control Register of SSP
415 * @cpsr: Value of Clock prescale register
416 * @n_bytes: how many bytes(power of 2) reqd for a given data width of client
417 * @enable_dma: Whether to enable DMA or not
418 * @read: function ptr to be used to read when doing xfer for this chip
419 * @write: function ptr to be used to write when doing xfer for this chip
420 * @cs_control: chip select callback provided by chip
421 * @xfer_type: polling/interrupt/DMA
423 * Runtime state of the SSP controller, maintained per chip,
424 * This would be set according to the current message that would be served
433 enum ssp_reading read;
434 enum ssp_writing write;
435 void (*cs_control) (u32 command);
440 * null_cs_control - Dummy chip select function
441 * @command: select/delect the chip
443 * If no chip select function is provided by client this is used as dummy
446 static void null_cs_control(u32 command)
448 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command);
452 * internal_cs_control - Control chip select signals via SSP_CSR.
453 * @pl022: SSP driver private data structure
454 * @command: select/delect the chip
456 * Used on controller with internal chip select control via SSP_CSR register
457 * (vendor extension). Each of the 5 LSB in the register controls one chip
460 static void internal_cs_control(struct pl022 *pl022, u32 command)
464 tmp = readw(SSP_CSR(pl022->virtbase));
465 if (command == SSP_CHIP_SELECT)
466 tmp &= ~BIT(pl022->cur_cs);
468 tmp |= BIT(pl022->cur_cs);
469 writew(tmp, SSP_CSR(pl022->virtbase));
472 static void pl022_cs_control(struct pl022 *pl022, u32 command)
474 if (pl022->vendor->internal_cs_ctrl)
475 internal_cs_control(pl022, command);
476 else if (gpio_is_valid(pl022->cur_cs))
477 gpio_set_value(pl022->cur_cs, command);
479 pl022->cur_chip->cs_control(command);
483 * giveback - current spi_message is over, schedule next message and call
484 * callback of this message. Assumes that caller already
485 * set message->status; dma and pio irqs are blocked
486 * @pl022: SSP driver private data structure
488 static void giveback(struct pl022 *pl022)
490 struct spi_transfer *last_transfer;
491 pl022->next_msg_cs_active = false;
493 last_transfer = list_last_entry(&pl022->cur_msg->transfers,
494 struct spi_transfer, transfer_list);
496 /* Delay if requested before any change in chip select */
497 if (last_transfer->delay_usecs)
499 * FIXME: This runs in interrupt context.
500 * Is this really smart?
502 udelay(last_transfer->delay_usecs);
504 if (!last_transfer->cs_change) {
505 struct spi_message *next_msg;
508 * cs_change was not set. We can keep the chip select
509 * enabled if there is message in the queue and it is
510 * for the same spi device.
512 * We cannot postpone this until pump_messages, because
513 * after calling msg->complete (below) the driver that
514 * sent the current message could be unloaded, which
515 * could invalidate the cs_control() callback...
517 /* get a pointer to the next message, if any */
518 next_msg = spi_get_next_queued_message(pl022->master);
521 * see if the next and current messages point
522 * to the same spi device.
524 if (next_msg && next_msg->spi != pl022->cur_msg->spi)
526 if (!next_msg || pl022->cur_msg->state == STATE_ERROR)
527 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
529 pl022->next_msg_cs_active = true;
533 pl022->cur_msg = NULL;
534 pl022->cur_transfer = NULL;
535 pl022->cur_chip = NULL;
537 /* disable the SPI/SSP operation */
538 writew((readw(SSP_CR1(pl022->virtbase)) &
539 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
541 spi_finalize_current_message(pl022->master);
545 * flush - flush the FIFO to reach a clean state
546 * @pl022: SSP driver private data structure
548 static int flush(struct pl022 *pl022)
550 unsigned long limit = loops_per_jiffy << 1;
552 dev_dbg(&pl022->adev->dev, "flush\n");
554 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
555 readw(SSP_DR(pl022->virtbase));
556 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
558 pl022->exp_fifo_level = 0;
564 * restore_state - Load configuration of current chip
565 * @pl022: SSP driver private data structure
567 static void restore_state(struct pl022 *pl022)
569 struct chip_data *chip = pl022->cur_chip;
571 if (pl022->vendor->extended_cr)
572 writel(chip->cr0, SSP_CR0(pl022->virtbase));
574 writew(chip->cr0, SSP_CR0(pl022->virtbase));
575 writew(chip->cr1, SSP_CR1(pl022->virtbase));
576 writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
577 writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
578 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
579 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
583 * Default SSP Register Values
585 #define DEFAULT_SSP_REG_CR0 ( \
586 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \
587 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \
588 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
589 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
590 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
593 /* ST versions have slightly different bit layout */
594 #define DEFAULT_SSP_REG_CR0_ST ( \
595 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
596 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \
597 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
598 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
599 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \
600 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \
601 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \
604 /* The PL023 version is slightly different again */
605 #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \
606 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
607 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
608 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
609 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
612 #define DEFAULT_SSP_REG_CR1 ( \
613 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \
614 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
615 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
616 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \
619 /* ST versions extend this register to use all 16 bits */
620 #define DEFAULT_SSP_REG_CR1_ST ( \
621 DEFAULT_SSP_REG_CR1 | \
622 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
623 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
624 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\
625 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
626 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \
630 * The PL023 variant has further differences: no loopback mode, no microwire
631 * support, and a new clock feedback delay setting.
633 #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \
634 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
635 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
636 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \
637 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
638 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
639 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
640 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \
641 GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \
644 #define DEFAULT_SSP_REG_CPSR ( \
645 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
648 #define DEFAULT_SSP_REG_DMACR (\
649 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \
650 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \
654 * load_ssp_default_config - Load default configuration for SSP
655 * @pl022: SSP driver private data structure
657 static void load_ssp_default_config(struct pl022 *pl022)
659 if (pl022->vendor->pl023) {
660 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
661 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
662 } else if (pl022->vendor->extended_cr) {
663 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
664 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
666 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
667 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
669 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
670 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
671 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
672 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
676 * This will write to TX and read from RX according to the parameters
679 static void readwriter(struct pl022 *pl022)
683 * The FIFO depth is different between primecell variants.
684 * I believe filling in too much in the FIFO might cause
685 * errons in 8bit wide transfers on ARM variants (just 8 words
686 * FIFO, means only 8x8 = 64 bits in FIFO) at least.
688 * To prevent this issue, the TX FIFO is only filled to the
689 * unused RX FIFO fill length, regardless of what the TX
690 * FIFO status flag indicates.
692 dev_dbg(&pl022->adev->dev,
693 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n",
694 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end);
696 /* Read as much as you can */
697 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
698 && (pl022->rx < pl022->rx_end)) {
699 switch (pl022->read) {
701 readw(SSP_DR(pl022->virtbase));
704 *(u8 *) (pl022->rx) =
705 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
708 *(u16 *) (pl022->rx) =
709 (u16) readw(SSP_DR(pl022->virtbase));
712 *(u32 *) (pl022->rx) =
713 readl(SSP_DR(pl022->virtbase));
716 pl022->rx += (pl022->cur_chip->n_bytes);
717 pl022->exp_fifo_level--;
720 * Write as much as possible up to the RX FIFO size
722 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth)
723 && (pl022->tx < pl022->tx_end)) {
724 switch (pl022->write) {
726 writew(0x0, SSP_DR(pl022->virtbase));
729 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
732 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
735 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
738 pl022->tx += (pl022->cur_chip->n_bytes);
739 pl022->exp_fifo_level++;
741 * This inner reader takes care of things appearing in the RX
742 * FIFO as we're transmitting. This will happen a lot since the
743 * clock starts running when you put things into the TX FIFO,
744 * and then things are continuously clocked into the RX FIFO.
746 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
747 && (pl022->rx < pl022->rx_end)) {
748 switch (pl022->read) {
750 readw(SSP_DR(pl022->virtbase));
753 *(u8 *) (pl022->rx) =
754 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
757 *(u16 *) (pl022->rx) =
758 (u16) readw(SSP_DR(pl022->virtbase));
761 *(u32 *) (pl022->rx) =
762 readl(SSP_DR(pl022->virtbase));
765 pl022->rx += (pl022->cur_chip->n_bytes);
766 pl022->exp_fifo_level--;
770 * When we exit here the TX FIFO should be full and the RX FIFO
776 * next_transfer - Move to the Next transfer in the current spi message
777 * @pl022: SSP driver private data structure
779 * This function moves though the linked list of spi transfers in the
780 * current spi message and returns with the state of current spi
781 * message i.e whether its last transfer is done(STATE_DONE) or
782 * Next transfer is ready(STATE_RUNNING)
784 static void *next_transfer(struct pl022 *pl022)
786 struct spi_message *msg = pl022->cur_msg;
787 struct spi_transfer *trans = pl022->cur_transfer;
789 /* Move to next transfer */
790 if (trans->transfer_list.next != &msg->transfers) {
791 pl022->cur_transfer =
792 list_entry(trans->transfer_list.next,
793 struct spi_transfer, transfer_list);
794 return STATE_RUNNING;
800 * This DMA functionality is only compiled in if we have
801 * access to the generic DMA devices/DMA engine.
803 #ifdef CONFIG_DMA_ENGINE
804 static void unmap_free_dma_scatter(struct pl022 *pl022)
806 /* Unmap and free the SG tables */
807 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl,
808 pl022->sgt_tx.nents, DMA_TO_DEVICE);
809 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl,
810 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
811 sg_free_table(&pl022->sgt_rx);
812 sg_free_table(&pl022->sgt_tx);
815 static void dma_callback(void *data)
817 struct pl022 *pl022 = data;
818 struct spi_message *msg = pl022->cur_msg;
820 BUG_ON(!pl022->sgt_rx.sgl);
824 * Optionally dump out buffers to inspect contents, this is
825 * good if you want to convince yourself that the loopback
826 * read/write contents are the same, when adopting to a new
830 struct scatterlist *sg;
833 dma_sync_sg_for_cpu(&pl022->adev->dev,
838 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) {
839 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i);
840 print_hex_dump(KERN_ERR, "SPI RX: ",
848 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) {
849 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i);
850 print_hex_dump(KERN_ERR, "SPI TX: ",
861 unmap_free_dma_scatter(pl022);
863 /* Update total bytes transferred */
864 msg->actual_length += pl022->cur_transfer->len;
865 /* Move to next transfer */
866 msg->state = next_transfer(pl022);
867 if (msg->state != STATE_DONE && pl022->cur_transfer->cs_change)
868 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
869 tasklet_schedule(&pl022->pump_transfers);
872 static void setup_dma_scatter(struct pl022 *pl022,
875 struct sg_table *sgtab)
877 struct scatterlist *sg;
878 int bytesleft = length;
884 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
886 * If there are less bytes left than what fits
887 * in the current page (plus page alignment offset)
888 * we just feed in this, else we stuff in as much
891 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp)))
892 mapbytes = bytesleft;
894 mapbytes = PAGE_SIZE - offset_in_page(bufp);
895 sg_set_page(sg, virt_to_page(bufp),
896 mapbytes, offset_in_page(bufp));
898 bytesleft -= mapbytes;
899 dev_dbg(&pl022->adev->dev,
900 "set RX/TX target page @ %p, %d bytes, %d left\n",
901 bufp, mapbytes, bytesleft);
904 /* Map the dummy buffer on every page */
905 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
906 if (bytesleft < PAGE_SIZE)
907 mapbytes = bytesleft;
909 mapbytes = PAGE_SIZE;
910 sg_set_page(sg, virt_to_page(pl022->dummypage),
912 bytesleft -= mapbytes;
913 dev_dbg(&pl022->adev->dev,
914 "set RX/TX to dummy page %d bytes, %d left\n",
915 mapbytes, bytesleft);
923 * configure_dma - configures the channels for the next transfer
924 * @pl022: SSP driver's private data structure
926 static int configure_dma(struct pl022 *pl022)
928 struct dma_slave_config rx_conf = {
929 .src_addr = SSP_DR(pl022->phybase),
930 .direction = DMA_DEV_TO_MEM,
933 struct dma_slave_config tx_conf = {
934 .dst_addr = SSP_DR(pl022->phybase),
935 .direction = DMA_MEM_TO_DEV,
940 int rx_sglen, tx_sglen;
941 struct dma_chan *rxchan = pl022->dma_rx_channel;
942 struct dma_chan *txchan = pl022->dma_tx_channel;
943 struct dma_async_tx_descriptor *rxdesc;
944 struct dma_async_tx_descriptor *txdesc;
946 /* Check that the channels are available */
947 if (!rxchan || !txchan)
951 * If supplied, the DMA burstsize should equal the FIFO trigger level.
952 * Notice that the DMA engine uses one-to-one mapping. Since we can
953 * not trigger on 2 elements this needs explicit mapping rather than
956 switch (pl022->rx_lev_trig) {
957 case SSP_RX_1_OR_MORE_ELEM:
958 rx_conf.src_maxburst = 1;
960 case SSP_RX_4_OR_MORE_ELEM:
961 rx_conf.src_maxburst = 4;
963 case SSP_RX_8_OR_MORE_ELEM:
964 rx_conf.src_maxburst = 8;
966 case SSP_RX_16_OR_MORE_ELEM:
967 rx_conf.src_maxburst = 16;
969 case SSP_RX_32_OR_MORE_ELEM:
970 rx_conf.src_maxburst = 32;
973 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1;
977 switch (pl022->tx_lev_trig) {
978 case SSP_TX_1_OR_MORE_EMPTY_LOC:
979 tx_conf.dst_maxburst = 1;
981 case SSP_TX_4_OR_MORE_EMPTY_LOC:
982 tx_conf.dst_maxburst = 4;
984 case SSP_TX_8_OR_MORE_EMPTY_LOC:
985 tx_conf.dst_maxburst = 8;
987 case SSP_TX_16_OR_MORE_EMPTY_LOC:
988 tx_conf.dst_maxburst = 16;
990 case SSP_TX_32_OR_MORE_EMPTY_LOC:
991 tx_conf.dst_maxburst = 32;
994 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1;
998 switch (pl022->read) {
1000 /* Use the same as for writing */
1001 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
1004 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1007 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1010 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1014 switch (pl022->write) {
1016 /* Use the same as for reading */
1017 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
1020 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1023 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1026 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1030 /* SPI pecularity: we need to read and write the same width */
1031 if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
1032 rx_conf.src_addr_width = tx_conf.dst_addr_width;
1033 if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
1034 tx_conf.dst_addr_width = rx_conf.src_addr_width;
1035 BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width);
1037 dmaengine_slave_config(rxchan, &rx_conf);
1038 dmaengine_slave_config(txchan, &tx_conf);
1040 /* Create sglists for the transfers */
1041 pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE);
1042 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages);
1044 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC);
1046 goto err_alloc_rx_sg;
1048 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC);
1050 goto err_alloc_tx_sg;
1052 /* Fill in the scatterlists for the RX+TX buffers */
1053 setup_dma_scatter(pl022, pl022->rx,
1054 pl022->cur_transfer->len, &pl022->sgt_rx);
1055 setup_dma_scatter(pl022, pl022->tx,
1056 pl022->cur_transfer->len, &pl022->sgt_tx);
1058 /* Map DMA buffers */
1059 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
1060 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
1064 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl,
1065 pl022->sgt_tx.nents, DMA_TO_DEVICE);
1069 /* Send both scatterlists */
1070 rxdesc = dmaengine_prep_slave_sg(rxchan,
1074 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1078 txdesc = dmaengine_prep_slave_sg(txchan,
1082 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1086 /* Put the callback on the RX transfer only, that should finish last */
1087 rxdesc->callback = dma_callback;
1088 rxdesc->callback_param = pl022;
1090 /* Submit and fire RX and TX with TX last so we're ready to read! */
1091 dmaengine_submit(rxdesc);
1092 dmaengine_submit(txdesc);
1093 dma_async_issue_pending(rxchan);
1094 dma_async_issue_pending(txchan);
1095 pl022->dma_running = true;
1100 dmaengine_terminate_all(txchan);
1102 dmaengine_terminate_all(rxchan);
1103 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl,
1104 pl022->sgt_tx.nents, DMA_TO_DEVICE);
1106 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
1107 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
1109 sg_free_table(&pl022->sgt_tx);
1111 sg_free_table(&pl022->sgt_rx);
1116 static int pl022_dma_probe(struct pl022 *pl022)
1118 dma_cap_mask_t mask;
1120 /* Try to acquire a generic DMA engine slave channel */
1122 dma_cap_set(DMA_SLAVE, mask);
1124 * We need both RX and TX channels to do DMA, else do none
1127 pl022->dma_rx_channel = dma_request_channel(mask,
1128 pl022->master_info->dma_filter,
1129 pl022->master_info->dma_rx_param);
1130 if (!pl022->dma_rx_channel) {
1131 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n");
1135 pl022->dma_tx_channel = dma_request_channel(mask,
1136 pl022->master_info->dma_filter,
1137 pl022->master_info->dma_tx_param);
1138 if (!pl022->dma_tx_channel) {
1139 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n");
1143 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1144 if (!pl022->dummypage)
1145 goto err_no_dummypage;
1147 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n",
1148 dma_chan_name(pl022->dma_rx_channel),
1149 dma_chan_name(pl022->dma_tx_channel));
1154 dma_release_channel(pl022->dma_tx_channel);
1156 dma_release_channel(pl022->dma_rx_channel);
1157 pl022->dma_rx_channel = NULL;
1159 dev_err(&pl022->adev->dev,
1160 "Failed to work in dma mode, work without dma!\n");
1164 static int pl022_dma_autoprobe(struct pl022 *pl022)
1166 struct device *dev = &pl022->adev->dev;
1167 struct dma_chan *chan;
1170 /* automatically configure DMA channels from platform, normally using DT */
1171 chan = dma_request_slave_channel_reason(dev, "rx");
1173 err = PTR_ERR(chan);
1177 pl022->dma_rx_channel = chan;
1179 chan = dma_request_slave_channel_reason(dev, "tx");
1181 err = PTR_ERR(chan);
1185 pl022->dma_tx_channel = chan;
1187 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1188 if (!pl022->dummypage) {
1190 goto err_no_dummypage;
1196 dma_release_channel(pl022->dma_tx_channel);
1197 pl022->dma_tx_channel = NULL;
1199 dma_release_channel(pl022->dma_rx_channel);
1200 pl022->dma_rx_channel = NULL;
1205 static void terminate_dma(struct pl022 *pl022)
1207 struct dma_chan *rxchan = pl022->dma_rx_channel;
1208 struct dma_chan *txchan = pl022->dma_tx_channel;
1210 dmaengine_terminate_all(rxchan);
1211 dmaengine_terminate_all(txchan);
1212 unmap_free_dma_scatter(pl022);
1213 pl022->dma_running = false;
1216 static void pl022_dma_remove(struct pl022 *pl022)
1218 if (pl022->dma_running)
1219 terminate_dma(pl022);
1220 if (pl022->dma_tx_channel)
1221 dma_release_channel(pl022->dma_tx_channel);
1222 if (pl022->dma_rx_channel)
1223 dma_release_channel(pl022->dma_rx_channel);
1224 kfree(pl022->dummypage);
1228 static inline int configure_dma(struct pl022 *pl022)
1233 static inline int pl022_dma_autoprobe(struct pl022 *pl022)
1238 static inline int pl022_dma_probe(struct pl022 *pl022)
1243 static inline void pl022_dma_remove(struct pl022 *pl022)
1249 * pl022_interrupt_handler - Interrupt handler for SSP controller
1251 * This function handles interrupts generated for an interrupt based transfer.
1252 * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the
1253 * current message's state as STATE_ERROR and schedule the tasklet
1254 * pump_transfers which will do the postprocessing of the current message by
1255 * calling giveback(). Otherwise it reads data from RX FIFO till there is no
1256 * more data, and writes data in TX FIFO till it is not full. If we complete
1257 * the transfer we move to the next transfer and schedule the tasklet.
1259 static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
1261 struct pl022 *pl022 = dev_id;
1262 struct spi_message *msg = pl022->cur_msg;
1265 if (unlikely(!msg)) {
1266 dev_err(&pl022->adev->dev,
1267 "bad message state in interrupt handler");
1272 /* Read the Interrupt Status Register */
1273 irq_status = readw(SSP_MIS(pl022->virtbase));
1275 if (unlikely(!irq_status))
1279 * This handles the FIFO interrupts, the timeout
1280 * interrupts are flatly ignored, they cannot be
1283 if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) {
1285 * Overrun interrupt - bail out since our Data has been
1288 dev_err(&pl022->adev->dev, "FIFO overrun\n");
1289 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
1290 dev_err(&pl022->adev->dev,
1291 "RXFIFO is full\n");
1294 * Disable and clear interrupts, disable SSP,
1295 * mark message with bad status so it can be
1298 writew(DISABLE_ALL_INTERRUPTS,
1299 SSP_IMSC(pl022->virtbase));
1300 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1301 writew((readw(SSP_CR1(pl022->virtbase)) &
1302 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1303 msg->state = STATE_ERROR;
1305 /* Schedule message queue handler */
1306 tasklet_schedule(&pl022->pump_transfers);
1312 if (pl022->tx == pl022->tx_end) {
1313 /* Disable Transmit interrupt, enable receive interrupt */
1314 writew((readw(SSP_IMSC(pl022->virtbase)) &
1315 ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM,
1316 SSP_IMSC(pl022->virtbase));
1320 * Since all transactions must write as much as shall be read,
1321 * we can conclude the entire transaction once RX is complete.
1322 * At this point, all TX will always be finished.
1324 if (pl022->rx >= pl022->rx_end) {
1325 writew(DISABLE_ALL_INTERRUPTS,
1326 SSP_IMSC(pl022->virtbase));
1327 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1328 if (unlikely(pl022->rx > pl022->rx_end)) {
1329 dev_warn(&pl022->adev->dev, "read %u surplus "
1330 "bytes (did you request an odd "
1331 "number of bytes on a 16bit bus?)\n",
1332 (u32) (pl022->rx - pl022->rx_end));
1334 /* Update total bytes transferred */
1335 msg->actual_length += pl022->cur_transfer->len;
1336 /* Move to next transfer */
1337 msg->state = next_transfer(pl022);
1338 if (msg->state != STATE_DONE && pl022->cur_transfer->cs_change)
1339 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
1340 tasklet_schedule(&pl022->pump_transfers);
1348 * This sets up the pointers to memory for the next message to
1349 * send out on the SPI bus.
1351 static int set_up_next_transfer(struct pl022 *pl022,
1352 struct spi_transfer *transfer)
1356 /* Sanity check the message for this bus width */
1357 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes;
1358 if (unlikely(residue != 0)) {
1359 dev_err(&pl022->adev->dev,
1360 "message of %u bytes to transmit but the current "
1361 "chip bus has a data width of %u bytes!\n",
1362 pl022->cur_transfer->len,
1363 pl022->cur_chip->n_bytes);
1364 dev_err(&pl022->adev->dev, "skipping this message\n");
1367 pl022->tx = (void *)transfer->tx_buf;
1368 pl022->tx_end = pl022->tx + pl022->cur_transfer->len;
1369 pl022->rx = (void *)transfer->rx_buf;
1370 pl022->rx_end = pl022->rx + pl022->cur_transfer->len;
1372 pl022->tx ? pl022->cur_chip->write : WRITING_NULL;
1373 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL;
1378 * pump_transfers - Tasklet function which schedules next transfer
1379 * when running in interrupt or DMA transfer mode.
1380 * @data: SSP driver private data structure
1383 static void pump_transfers(unsigned long data)
1385 struct pl022 *pl022 = (struct pl022 *) data;
1386 struct spi_message *message = NULL;
1387 struct spi_transfer *transfer = NULL;
1388 struct spi_transfer *previous = NULL;
1390 /* Get current state information */
1391 message = pl022->cur_msg;
1392 transfer = pl022->cur_transfer;
1394 /* Handle for abort */
1395 if (message->state == STATE_ERROR) {
1396 message->status = -EIO;
1401 /* Handle end of message */
1402 if (message->state == STATE_DONE) {
1403 message->status = 0;
1408 /* Delay if requested at end of transfer before CS change */
1409 if (message->state == STATE_RUNNING) {
1410 previous = list_entry(transfer->transfer_list.prev,
1411 struct spi_transfer,
1413 if (previous->delay_usecs)
1415 * FIXME: This runs in interrupt context.
1416 * Is this really smart?
1418 udelay(previous->delay_usecs);
1420 /* Reselect chip select only if cs_change was requested */
1421 if (previous->cs_change)
1422 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1425 message->state = STATE_RUNNING;
1428 if (set_up_next_transfer(pl022, transfer)) {
1429 message->state = STATE_ERROR;
1430 message->status = -EIO;
1434 /* Flush the FIFOs and let's go! */
1437 if (pl022->cur_chip->enable_dma) {
1438 if (configure_dma(pl022)) {
1439 dev_dbg(&pl022->adev->dev,
1440 "configuration of DMA failed, fall back to interrupt mode\n");
1441 goto err_config_dma;
1447 /* enable all interrupts except RX */
1448 writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase));
1451 static void do_interrupt_dma_transfer(struct pl022 *pl022)
1454 * Default is to enable all interrupts except RX -
1455 * this will be enabled once TX is complete
1457 u32 irqflags = (u32)(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM);
1459 /* Enable target chip, if not already active */
1460 if (!pl022->next_msg_cs_active)
1461 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1463 if (set_up_next_transfer(pl022, pl022->cur_transfer)) {
1465 pl022->cur_msg->state = STATE_ERROR;
1466 pl022->cur_msg->status = -EIO;
1470 /* If we're using DMA, set up DMA here */
1471 if (pl022->cur_chip->enable_dma) {
1472 /* Configure DMA transfer */
1473 if (configure_dma(pl022)) {
1474 dev_dbg(&pl022->adev->dev,
1475 "configuration of DMA failed, fall back to interrupt mode\n");
1476 goto err_config_dma;
1478 /* Disable interrupts in DMA mode, IRQ from DMA controller */
1479 irqflags = DISABLE_ALL_INTERRUPTS;
1482 /* Enable SSP, turn on interrupts */
1483 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1484 SSP_CR1(pl022->virtbase));
1485 writew(irqflags, SSP_IMSC(pl022->virtbase));
1488 static void print_current_status(struct pl022 *pl022)
1491 u16 read_cr1, read_dmacr, read_sr;
1493 if (pl022->vendor->extended_cr)
1494 read_cr0 = readl(SSP_CR0(pl022->virtbase));
1496 read_cr0 = readw(SSP_CR0(pl022->virtbase));
1497 read_cr1 = readw(SSP_CR1(pl022->virtbase));
1498 read_dmacr = readw(SSP_DMACR(pl022->virtbase));
1499 read_sr = readw(SSP_SR(pl022->virtbase));
1501 dev_warn(&pl022->adev->dev, "spi-pl022 CR0: %x\n", read_cr0);
1502 dev_warn(&pl022->adev->dev, "spi-pl022 CR1: %x\n", read_cr1);
1503 dev_warn(&pl022->adev->dev, "spi-pl022 DMACR: %x\n", read_dmacr);
1504 dev_warn(&pl022->adev->dev, "spi-pl022 SR: %x\n", read_sr);
1505 dev_warn(&pl022->adev->dev,
1506 "spi-pl022 exp_fifo_level/fifodepth: %u/%d\n",
1507 pl022->exp_fifo_level,
1508 pl022->vendor->fifodepth);
1512 static void do_polling_transfer(struct pl022 *pl022)
1514 struct spi_message *message = NULL;
1515 struct spi_transfer *transfer = NULL;
1516 struct spi_transfer *previous = NULL;
1517 unsigned long time, timeout;
1519 message = pl022->cur_msg;
1521 while (message->state != STATE_DONE) {
1522 /* Handle for abort */
1523 if (message->state == STATE_ERROR)
1525 transfer = pl022->cur_transfer;
1527 /* Delay if requested at end of transfer */
1528 if (message->state == STATE_RUNNING) {
1530 list_entry(transfer->transfer_list.prev,
1531 struct spi_transfer, transfer_list);
1532 if (previous->delay_usecs)
1533 udelay(previous->delay_usecs);
1534 if (previous->cs_change)
1535 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1538 message->state = STATE_RUNNING;
1539 if (!pl022->next_msg_cs_active)
1540 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1543 /* Configuration Changing Per Transfer */
1544 if (set_up_next_transfer(pl022, transfer)) {
1546 message->state = STATE_ERROR;
1549 /* Flush FIFOs and enable SSP */
1551 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1552 SSP_CR1(pl022->virtbase));
1554 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n");
1556 timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT);
1557 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) {
1560 if (time_after(time, timeout)) {
1561 dev_warn(&pl022->adev->dev,
1562 "%s: timeout!\n", __func__);
1563 message->state = STATE_TIMEOUT;
1564 print_current_status(pl022);
1570 /* Update total byte transferred */
1571 message->actual_length += pl022->cur_transfer->len;
1572 /* Move to next transfer */
1573 message->state = next_transfer(pl022);
1574 if (message->state != STATE_DONE
1575 && pl022->cur_transfer->cs_change)
1576 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
1579 /* Handle end of message */
1580 if (message->state == STATE_DONE)
1581 message->status = 0;
1582 else if (message->state == STATE_TIMEOUT)
1583 message->status = -EAGAIN;
1585 message->status = -EIO;
1591 static int pl022_transfer_one_message(struct spi_master *master,
1592 struct spi_message *msg)
1594 struct pl022 *pl022 = spi_master_get_devdata(master);
1596 /* Initial message state */
1597 pl022->cur_msg = msg;
1598 msg->state = STATE_START;
1600 pl022->cur_transfer = list_entry(msg->transfers.next,
1601 struct spi_transfer, transfer_list);
1603 /* Setup the SPI using the per chip configuration */
1604 pl022->cur_chip = spi_get_ctldata(msg->spi);
1605 pl022->cur_cs = pl022->chipselects[msg->spi->chip_select];
1607 restore_state(pl022);
1610 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER)
1611 do_polling_transfer(pl022);
1613 do_interrupt_dma_transfer(pl022);
1618 static int pl022_unprepare_transfer_hardware(struct spi_master *master)
1620 struct pl022 *pl022 = spi_master_get_devdata(master);
1622 /* nothing more to do - disable spi/ssp and power off */
1623 writew((readw(SSP_CR1(pl022->virtbase)) &
1624 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1629 static int verify_controller_parameters(struct pl022 *pl022,
1630 struct pl022_config_chip const *chip_info)
1632 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI)
1633 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) {
1634 dev_err(&pl022->adev->dev,
1635 "interface is configured incorrectly\n");
1638 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) &&
1639 (!pl022->vendor->unidir)) {
1640 dev_err(&pl022->adev->dev,
1641 "unidirectional mode not supported in this "
1642 "hardware version\n");
1645 if ((chip_info->hierarchy != SSP_MASTER)
1646 && (chip_info->hierarchy != SSP_SLAVE)) {
1647 dev_err(&pl022->adev->dev,
1648 "hierarchy is configured incorrectly\n");
1651 if ((chip_info->com_mode != INTERRUPT_TRANSFER)
1652 && (chip_info->com_mode != DMA_TRANSFER)
1653 && (chip_info->com_mode != POLLING_TRANSFER)) {
1654 dev_err(&pl022->adev->dev,
1655 "Communication mode is configured incorrectly\n");
1658 switch (chip_info->rx_lev_trig) {
1659 case SSP_RX_1_OR_MORE_ELEM:
1660 case SSP_RX_4_OR_MORE_ELEM:
1661 case SSP_RX_8_OR_MORE_ELEM:
1662 /* These are always OK, all variants can handle this */
1664 case SSP_RX_16_OR_MORE_ELEM:
1665 if (pl022->vendor->fifodepth < 16) {
1666 dev_err(&pl022->adev->dev,
1667 "RX FIFO Trigger Level is configured incorrectly\n");
1671 case SSP_RX_32_OR_MORE_ELEM:
1672 if (pl022->vendor->fifodepth < 32) {
1673 dev_err(&pl022->adev->dev,
1674 "RX FIFO Trigger Level is configured incorrectly\n");
1679 dev_err(&pl022->adev->dev,
1680 "RX FIFO Trigger Level is configured incorrectly\n");
1683 switch (chip_info->tx_lev_trig) {
1684 case SSP_TX_1_OR_MORE_EMPTY_LOC:
1685 case SSP_TX_4_OR_MORE_EMPTY_LOC:
1686 case SSP_TX_8_OR_MORE_EMPTY_LOC:
1687 /* These are always OK, all variants can handle this */
1689 case SSP_TX_16_OR_MORE_EMPTY_LOC:
1690 if (pl022->vendor->fifodepth < 16) {
1691 dev_err(&pl022->adev->dev,
1692 "TX FIFO Trigger Level is configured incorrectly\n");
1696 case SSP_TX_32_OR_MORE_EMPTY_LOC:
1697 if (pl022->vendor->fifodepth < 32) {
1698 dev_err(&pl022->adev->dev,
1699 "TX FIFO Trigger Level is configured incorrectly\n");
1704 dev_err(&pl022->adev->dev,
1705 "TX FIFO Trigger Level is configured incorrectly\n");
1708 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) {
1709 if ((chip_info->ctrl_len < SSP_BITS_4)
1710 || (chip_info->ctrl_len > SSP_BITS_32)) {
1711 dev_err(&pl022->adev->dev,
1712 "CTRL LEN is configured incorrectly\n");
1715 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO)
1716 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) {
1717 dev_err(&pl022->adev->dev,
1718 "Wait State is configured incorrectly\n");
1721 /* Half duplex is only available in the ST Micro version */
1722 if (pl022->vendor->extended_cr) {
1723 if ((chip_info->duplex !=
1724 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1725 && (chip_info->duplex !=
1726 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) {
1727 dev_err(&pl022->adev->dev,
1728 "Microwire duplex mode is configured incorrectly\n");
1732 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1733 dev_err(&pl022->adev->dev,
1734 "Microwire half duplex mode requested,"
1735 " but this is only available in the"
1736 " ST version of PL022\n");
1743 static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr)
1745 return rate / (cpsdvsr * (1 + scr));
1748 static int calculate_effective_freq(struct pl022 *pl022, int freq, struct
1749 ssp_clock_params * clk_freq)
1751 /* Lets calculate the frequency parameters */
1752 u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN;
1753 u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0,
1754 best_scr = 0, tmp, found = 0;
1756 rate = clk_get_rate(pl022->clk);
1757 /* cpsdvscr = 2 & scr 0 */
1758 max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN);
1759 /* cpsdvsr = 254 & scr = 255 */
1760 min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX);
1762 if (freq > max_tclk)
1763 dev_warn(&pl022->adev->dev,
1764 "Max speed that can be programmed is %d Hz, you requested %d\n",
1767 if (freq < min_tclk) {
1768 dev_err(&pl022->adev->dev,
1769 "Requested frequency: %d Hz is less than minimum possible %d Hz\n",
1775 * best_freq will give closest possible available rate (<= requested
1776 * freq) for all values of scr & cpsdvsr.
1778 while ((cpsdvsr <= CPSDVR_MAX) && !found) {
1779 while (scr <= SCR_MAX) {
1780 tmp = spi_rate(rate, cpsdvsr, scr);
1783 /* we need lower freq */
1789 * If found exact value, mark found and break.
1790 * If found more closer value, update and break.
1792 if (tmp > best_freq) {
1794 best_cpsdvsr = cpsdvsr;
1801 * increased scr will give lower rates, which are not
1810 WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n",
1813 clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF);
1814 clk_freq->scr = (u8) (best_scr & 0xFF);
1815 dev_dbg(&pl022->adev->dev,
1816 "SSP Target Frequency is: %u, Effective Frequency is %u\n",
1818 dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n",
1819 clk_freq->cpsdvsr, clk_freq->scr);
1825 * A piece of default chip info unless the platform
1828 static const struct pl022_config_chip pl022_default_chip_info = {
1829 .com_mode = POLLING_TRANSFER,
1830 .iface = SSP_INTERFACE_MOTOROLA_SPI,
1831 .hierarchy = SSP_SLAVE,
1832 .slave_tx_disable = DO_NOT_DRIVE_TX,
1833 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
1834 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
1835 .ctrl_len = SSP_BITS_8,
1836 .wait_state = SSP_MWIRE_WAIT_ZERO,
1837 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
1838 .cs_control = null_cs_control,
1842 * pl022_setup - setup function registered to SPI master framework
1843 * @spi: spi device which is requesting setup
1845 * This function is registered to the SPI framework for this SPI master
1846 * controller. If it is the first time when setup is called by this device,
1847 * this function will initialize the runtime state for this chip and save
1848 * the same in the device structure. Else it will update the runtime info
1849 * with the updated chip info. Nothing is really being written to the
1850 * controller hardware here, that is not done until the actual transfer
1853 static int pl022_setup(struct spi_device *spi)
1855 struct pl022_config_chip const *chip_info;
1856 struct pl022_config_chip chip_info_dt;
1857 struct chip_data *chip;
1858 struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0};
1860 struct pl022 *pl022 = spi_master_get_devdata(spi->master);
1861 unsigned int bits = spi->bits_per_word;
1863 struct device_node *np = spi->dev.of_node;
1865 if (!spi->max_speed_hz)
1868 /* Get controller_state if one is supplied */
1869 chip = spi_get_ctldata(spi);
1872 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1876 "allocated memory for controller's runtime state\n");
1879 /* Get controller data if one is supplied */
1880 chip_info = spi->controller_data;
1882 if (chip_info == NULL) {
1884 chip_info_dt = pl022_default_chip_info;
1886 chip_info_dt.hierarchy = SSP_MASTER;
1887 of_property_read_u32(np, "pl022,interface",
1888 &chip_info_dt.iface);
1889 of_property_read_u32(np, "pl022,com-mode",
1890 &chip_info_dt.com_mode);
1891 of_property_read_u32(np, "pl022,rx-level-trig",
1892 &chip_info_dt.rx_lev_trig);
1893 of_property_read_u32(np, "pl022,tx-level-trig",
1894 &chip_info_dt.tx_lev_trig);
1895 of_property_read_u32(np, "pl022,ctrl-len",
1896 &chip_info_dt.ctrl_len);
1897 of_property_read_u32(np, "pl022,wait-state",
1898 &chip_info_dt.wait_state);
1899 of_property_read_u32(np, "pl022,duplex",
1900 &chip_info_dt.duplex);
1902 chip_info = &chip_info_dt;
1904 chip_info = &pl022_default_chip_info;
1905 /* spi_board_info.controller_data not is supplied */
1907 "using default controller_data settings\n");
1911 "using user supplied controller_data settings\n");
1914 * We can override with custom divisors, else we use the board
1917 if ((0 == chip_info->clk_freq.cpsdvsr)
1918 && (0 == chip_info->clk_freq.scr)) {
1919 status = calculate_effective_freq(pl022,
1923 goto err_config_params;
1925 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq));
1926 if ((clk_freq.cpsdvsr % 2) != 0)
1928 clk_freq.cpsdvsr - 1;
1930 if ((clk_freq.cpsdvsr < CPSDVR_MIN)
1931 || (clk_freq.cpsdvsr > CPSDVR_MAX)) {
1934 "cpsdvsr is configured incorrectly\n");
1935 goto err_config_params;
1938 status = verify_controller_parameters(pl022, chip_info);
1940 dev_err(&spi->dev, "controller data is incorrect");
1941 goto err_config_params;
1944 pl022->rx_lev_trig = chip_info->rx_lev_trig;
1945 pl022->tx_lev_trig = chip_info->tx_lev_trig;
1947 /* Now set controller state based on controller data */
1948 chip->xfer_type = chip_info->com_mode;
1949 if (!chip_info->cs_control) {
1950 chip->cs_control = null_cs_control;
1951 if (!gpio_is_valid(pl022->chipselects[spi->chip_select]))
1953 "invalid chip select\n");
1955 chip->cs_control = chip_info->cs_control;
1957 /* Check bits per word with vendor specific range */
1958 if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) {
1960 dev_err(&spi->dev, "illegal data size for this controller!\n");
1961 dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n",
1962 pl022->vendor->max_bpw);
1963 goto err_config_params;
1964 } else if (bits <= 8) {
1965 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n");
1967 chip->read = READING_U8;
1968 chip->write = WRITING_U8;
1969 } else if (bits <= 16) {
1970 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n");
1972 chip->read = READING_U16;
1973 chip->write = WRITING_U16;
1975 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n");
1977 chip->read = READING_U32;
1978 chip->write = WRITING_U32;
1981 /* Now Initialize all register settings required for this chip */
1986 if ((chip_info->com_mode == DMA_TRANSFER)
1987 && ((pl022->master_info)->enable_dma)) {
1988 chip->enable_dma = true;
1989 dev_dbg(&spi->dev, "DMA mode set in controller state\n");
1990 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1991 SSP_DMACR_MASK_RXDMAE, 0);
1992 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1993 SSP_DMACR_MASK_TXDMAE, 1);
1995 chip->enable_dma = false;
1996 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n");
1997 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1998 SSP_DMACR_MASK_RXDMAE, 0);
1999 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
2000 SSP_DMACR_MASK_TXDMAE, 1);
2003 chip->cpsr = clk_freq.cpsdvsr;
2005 /* Special setup for the ST micro extended control registers */
2006 if (pl022->vendor->extended_cr) {
2009 if (pl022->vendor->pl023) {
2010 /* These bits are only in the PL023 */
2011 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,
2012 SSP_CR1_MASK_FBCLKDEL_ST, 13);
2014 /* These bits are in the PL022 but not PL023 */
2015 SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
2016 SSP_CR0_MASK_HALFDUP_ST, 5);
2017 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
2018 SSP_CR0_MASK_CSS_ST, 16);
2019 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
2020 SSP_CR0_MASK_FRF_ST, 21);
2021 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,
2022 SSP_CR1_MASK_MWAIT_ST, 6);
2024 SSP_WRITE_BITS(chip->cr0, bits - 1,
2025 SSP_CR0_MASK_DSS_ST, 0);
2027 if (spi->mode & SPI_LSB_FIRST) {
2034 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4);
2035 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5);
2036 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,
2037 SSP_CR1_MASK_RXIFLSEL_ST, 7);
2038 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
2039 SSP_CR1_MASK_TXIFLSEL_ST, 10);
2041 SSP_WRITE_BITS(chip->cr0, bits - 1,
2042 SSP_CR0_MASK_DSS, 0);
2043 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
2044 SSP_CR0_MASK_FRF, 4);
2047 /* Stuff that is common for all versions */
2048 if (spi->mode & SPI_CPOL)
2049 tmp = SSP_CLK_POL_IDLE_HIGH;
2051 tmp = SSP_CLK_POL_IDLE_LOW;
2052 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6);
2054 if (spi->mode & SPI_CPHA)
2055 tmp = SSP_CLK_SECOND_EDGE;
2057 tmp = SSP_CLK_FIRST_EDGE;
2058 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7);
2060 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8);
2061 /* Loopback is available on all versions except PL023 */
2062 if (pl022->vendor->loopback) {
2063 if (spi->mode & SPI_LOOP)
2064 tmp = LOOPBACK_ENABLED;
2066 tmp = LOOPBACK_DISABLED;
2067 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0);
2069 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);
2070 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
2071 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD,
2074 /* Save controller_state */
2075 spi_set_ctldata(spi, chip);
2078 spi_set_ctldata(spi, NULL);
2084 * pl022_cleanup - cleanup function registered to SPI master framework
2085 * @spi: spi device which is requesting cleanup
2087 * This function is registered to the SPI framework for this SPI master
2088 * controller. It will free the runtime state of chip.
2090 static void pl022_cleanup(struct spi_device *spi)
2092 struct chip_data *chip = spi_get_ctldata(spi);
2094 spi_set_ctldata(spi, NULL);
2098 static struct pl022_ssp_controller *
2099 pl022_platform_data_dt_get(struct device *dev)
2101 struct device_node *np = dev->of_node;
2102 struct pl022_ssp_controller *pd;
2106 dev_err(dev, "no dt node defined\n");
2110 pd = devm_kzalloc(dev, sizeof(struct pl022_ssp_controller), GFP_KERNEL);
2116 of_property_read_u32(np, "num-cs", &tmp);
2117 pd->num_chipselect = tmp;
2118 of_property_read_u32(np, "pl022,autosuspend-delay",
2119 &pd->autosuspend_delay);
2120 pd->rt = of_property_read_bool(np, "pl022,rt");
2125 static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
2127 struct device *dev = &adev->dev;
2128 struct pl022_ssp_controller *platform_info =
2129 dev_get_platdata(&adev->dev);
2130 struct spi_master *master;
2131 struct pl022 *pl022 = NULL; /*Data for this driver */
2132 struct device_node *np = adev->dev.of_node;
2133 int status = 0, i, num_cs;
2135 dev_info(&adev->dev,
2136 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid);
2137 if (!platform_info && IS_ENABLED(CONFIG_OF))
2138 platform_info = pl022_platform_data_dt_get(dev);
2140 if (!platform_info) {
2141 dev_err(dev, "probe: no platform data defined\n");
2145 if (platform_info->num_chipselect) {
2146 num_cs = platform_info->num_chipselect;
2148 dev_err(dev, "probe: no chip select defined\n");
2152 /* Allocate master with space for data */
2153 master = spi_alloc_master(dev, sizeof(struct pl022));
2154 if (master == NULL) {
2155 dev_err(&adev->dev, "probe - cannot alloc SPI master\n");
2159 pl022 = spi_master_get_devdata(master);
2160 pl022->master = master;
2161 pl022->master_info = platform_info;
2163 pl022->vendor = id->data;
2164 pl022->chipselects = devm_kcalloc(dev, num_cs, sizeof(int),
2166 if (!pl022->chipselects) {
2172 * Bus Number Which has been Assigned to this SSP controller
2175 master->bus_num = platform_info->bus_id;
2176 master->num_chipselect = num_cs;
2177 master->cleanup = pl022_cleanup;
2178 master->setup = pl022_setup;
2179 master->auto_runtime_pm = true;
2180 master->transfer_one_message = pl022_transfer_one_message;
2181 master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware;
2182 master->rt = platform_info->rt;
2183 master->dev.of_node = dev->of_node;
2185 if (platform_info->num_chipselect && platform_info->chipselects) {
2186 for (i = 0; i < num_cs; i++)
2187 pl022->chipselects[i] = platform_info->chipselects[i];
2188 } else if (pl022->vendor->internal_cs_ctrl) {
2189 for (i = 0; i < num_cs; i++)
2190 pl022->chipselects[i] = i;
2191 } else if (IS_ENABLED(CONFIG_OF)) {
2192 for (i = 0; i < num_cs; i++) {
2193 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
2195 if (cs_gpio == -EPROBE_DEFER) {
2196 status = -EPROBE_DEFER;
2200 pl022->chipselects[i] = cs_gpio;
2202 if (gpio_is_valid(cs_gpio)) {
2203 if (devm_gpio_request(dev, cs_gpio, "ssp-pl022"))
2205 "could not request %d gpio\n",
2207 else if (gpio_direction_output(cs_gpio, 1))
2209 "could not set gpio %d as output\n",
2216 * Supports mode 0-3, loopback, and active low CS. Transfers are
2217 * always MS bit first on the original pl022.
2219 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
2220 if (pl022->vendor->extended_cr)
2221 master->mode_bits |= SPI_LSB_FIRST;
2223 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num);
2225 status = amba_request_regions(adev, NULL);
2227 goto err_no_ioregion;
2229 pl022->phybase = adev->res.start;
2230 pl022->virtbase = devm_ioremap(dev, adev->res.start,
2231 resource_size(&adev->res));
2232 if (pl022->virtbase == NULL) {
2234 goto err_no_ioremap;
2236 dev_info(&adev->dev, "mapped registers from %pa to %p\n",
2237 &adev->res.start, pl022->virtbase);
2239 pl022->clk = devm_clk_get(&adev->dev, NULL);
2240 if (IS_ERR(pl022->clk)) {
2241 status = PTR_ERR(pl022->clk);
2242 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n");
2246 status = clk_prepare_enable(pl022->clk);
2248 dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n");
2252 /* Initialize transfer pump */
2253 tasklet_init(&pl022->pump_transfers, pump_transfers,
2254 (unsigned long)pl022);
2257 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
2258 SSP_CR1(pl022->virtbase));
2259 load_ssp_default_config(pl022);
2261 status = devm_request_irq(dev, adev->irq[0], pl022_interrupt_handler,
2264 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status);
2268 /* Get DMA channels, try autoconfiguration first */
2269 status = pl022_dma_autoprobe(pl022);
2270 if (status == -EPROBE_DEFER) {
2271 dev_dbg(dev, "deferring probe to get DMA channel\n");
2275 /* If that failed, use channels from platform_info */
2277 platform_info->enable_dma = 1;
2278 else if (platform_info->enable_dma) {
2279 status = pl022_dma_probe(pl022);
2281 platform_info->enable_dma = 0;
2284 /* Register with the SPI framework */
2285 amba_set_drvdata(adev, pl022);
2286 status = devm_spi_register_master(&adev->dev, master);
2289 "probe - problem registering spi master\n");
2290 goto err_spi_register;
2292 dev_dbg(dev, "probe succeeded\n");
2294 /* let runtime pm put suspend */
2295 if (platform_info->autosuspend_delay > 0) {
2296 dev_info(&adev->dev,
2297 "will use autosuspend for runtime pm, delay %dms\n",
2298 platform_info->autosuspend_delay);
2299 pm_runtime_set_autosuspend_delay(dev,
2300 platform_info->autosuspend_delay);
2301 pm_runtime_use_autosuspend(dev);
2303 pm_runtime_put(dev);
2308 if (platform_info->enable_dma)
2309 pl022_dma_remove(pl022);
2311 clk_disable_unprepare(pl022->clk);
2315 amba_release_regions(adev);
2319 spi_master_put(master);
2324 pl022_remove(struct amba_device *adev)
2326 struct pl022 *pl022 = amba_get_drvdata(adev);
2332 * undo pm_runtime_put() in probe. I assume that we're not
2333 * accessing the primecell here.
2335 pm_runtime_get_noresume(&adev->dev);
2337 load_ssp_default_config(pl022);
2338 if (pl022->master_info->enable_dma)
2339 pl022_dma_remove(pl022);
2341 clk_disable_unprepare(pl022->clk);
2342 amba_release_regions(adev);
2343 tasklet_disable(&pl022->pump_transfers);
2347 #ifdef CONFIG_PM_SLEEP
2348 static int pl022_suspend(struct device *dev)
2350 struct pl022 *pl022 = dev_get_drvdata(dev);
2353 ret = spi_master_suspend(pl022->master);
2357 ret = pm_runtime_force_suspend(dev);
2359 spi_master_resume(pl022->master);
2363 pinctrl_pm_select_sleep_state(dev);
2365 dev_dbg(dev, "suspended\n");
2369 static int pl022_resume(struct device *dev)
2371 struct pl022 *pl022 = dev_get_drvdata(dev);
2374 ret = pm_runtime_force_resume(dev);
2376 dev_err(dev, "problem resuming\n");
2378 /* Start the queue running */
2379 ret = spi_master_resume(pl022->master);
2381 dev_dbg(dev, "resumed\n");
2388 static int pl022_runtime_suspend(struct device *dev)
2390 struct pl022 *pl022 = dev_get_drvdata(dev);
2392 clk_disable_unprepare(pl022->clk);
2393 pinctrl_pm_select_idle_state(dev);
2398 static int pl022_runtime_resume(struct device *dev)
2400 struct pl022 *pl022 = dev_get_drvdata(dev);
2402 pinctrl_pm_select_default_state(dev);
2403 clk_prepare_enable(pl022->clk);
2409 static const struct dev_pm_ops pl022_dev_pm_ops = {
2410 SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume)
2411 SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL)
2414 static struct vendor_data vendor_arm = {
2418 .extended_cr = false,
2421 .internal_cs_ctrl = false,
2424 static struct vendor_data vendor_st = {
2428 .extended_cr = true,
2431 .internal_cs_ctrl = false,
2434 static struct vendor_data vendor_st_pl023 = {
2438 .extended_cr = true,
2441 .internal_cs_ctrl = false,
2444 static struct vendor_data vendor_lsi = {
2448 .extended_cr = false,
2451 .internal_cs_ctrl = true,
2454 static const struct amba_id pl022_ids[] = {
2457 * ARM PL022 variant, this has a 16bit wide
2458 * and 8 locations deep TX/RX FIFO
2462 .data = &vendor_arm,
2466 * ST Micro derivative, this has 32bit wide
2467 * and 32 locations deep TX/RX FIFO
2475 * ST-Ericsson derivative "PL023" (this is not
2476 * an official ARM number), this is a PL022 SSP block
2477 * stripped to SPI mode only, it has 32bit wide
2478 * and 32 locations deep TX/RX FIFO but no extended
2483 .data = &vendor_st_pl023,
2487 * PL022 variant that has a chip select control register whih
2488 * allows control of 5 output signals nCS[0:4].
2492 .data = &vendor_lsi,
2497 MODULE_DEVICE_TABLE(amba, pl022_ids);
2499 static struct amba_driver pl022_driver = {
2501 .name = "ssp-pl022",
2502 .pm = &pl022_dev_pm_ops,
2504 .id_table = pl022_ids,
2505 .probe = pl022_probe,
2506 .remove = pl022_remove,
2509 static int __init pl022_init(void)
2511 return amba_driver_register(&pl022_driver);
2513 subsys_initcall(pl022_init);
2515 static void __exit pl022_exit(void)
2517 amba_driver_unregister(&pl022_driver);
2519 module_exit(pl022_exit);
2521 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
2522 MODULE_DESCRIPTION("PL022 SSP Controller Driver");
2523 MODULE_LICENSE("GPL");