drivers/spi/spi-pxa2xx-dma.c

   1 /*
   2  * PXA2xx SPI DMA engine support.
   3  *
   4  * Copyright (C) 2013, Intel Corporation
   5  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/device.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/dmaengine.h>
  15 #include <linux/pxa2xx_ssp.h>
  16 #include <linux/scatterlist.h>
  17 #include <linux/sizes.h>
  18 #include <linux/spi/spi.h>
  19 #include <linux/spi/pxa2xx_spi.h>
  20
  21 #include "spi-pxa2xx.h"
  22
  23 static int pxa2xx_spi_map_dma_buffer(struct driver_data *drv_data,
  24                                      enum dma_data_direction dir)
  25 {
  26         int i, nents, len = drv_data->len;
  27         struct scatterlist *sg;
  28         struct device *dmadev;
  29         struct sg_table *sgt;
  30         void *buf, *pbuf;
  31
  32         if (dir == DMA_TO_DEVICE) {
  33                 dmadev = drv_data->tx_chan->device->dev;
  34                 sgt = &drv_data->tx_sgt;
  35                 buf = drv_data->tx;
  36         } else {
  37                 dmadev = drv_data->rx_chan->device->dev;
  38                 sgt = &drv_data->rx_sgt;
  39                 buf = drv_data->rx;
  40         }
  41
  42         nents = DIV_ROUND_UP(len, SZ_2K);
  43         if (nents != sgt->nents) {
  44                 int ret;
  45
  46                 sg_free_table(sgt);
  47                 ret = sg_alloc_table(sgt, nents, GFP_ATOMIC);
  48                 if (ret)
  49                         return ret;
  50         }
  51
  52         pbuf = buf;
  53         for_each_sg(sgt->sgl, sg, sgt->nents, i) {
  54                 size_t bytes = min_t(size_t, len, SZ_2K);
  55
  56                 if (buf)
  57                         sg_set_buf(sg, pbuf, bytes);
  58                 else
  59                         sg_set_buf(sg, drv_data->dummy, bytes);
  60
  61                 pbuf += bytes;
  62                 len -= bytes;
  63         }
  64
  65         nents = dma_map_sg(dmadev, sgt->sgl, sgt->nents, dir);
  66         if (!nents)
  67                 return -ENOMEM;
  68
  69         return nents;
  70 }
  71
  72 static void pxa2xx_spi_unmap_dma_buffer(struct driver_data *drv_data,
  73                                         enum dma_data_direction dir)
  74 {
  75         struct device *dmadev;
  76         struct sg_table *sgt;
  77
  78         if (dir == DMA_TO_DEVICE) {
  79                 dmadev = drv_data->tx_chan->device->dev;
  80                 sgt = &drv_data->tx_sgt;
  81         } else {
  82                 dmadev = drv_data->rx_chan->device->dev;
  83                 sgt = &drv_data->rx_sgt;
  84         }
  85
  86         dma_unmap_sg(dmadev, sgt->sgl, sgt->nents, dir);
  87 }
  88
  89 static void pxa2xx_spi_unmap_dma_buffers(struct driver_data *drv_data)
  90 {
  91         if (!drv_data->dma_mapped)
  92                 return;
  93
  94         pxa2xx_spi_unmap_dma_buffer(drv_data, DMA_FROM_DEVICE);
  95         pxa2xx_spi_unmap_dma_buffer(drv_data, DMA_TO_DEVICE);
  96
  97         drv_data->dma_mapped = 0;
  98 }
  99
 100 static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data,
 101                                              bool error)
 102 {
 103         struct spi_message *msg = drv_data->cur_msg;
 104
 105         /*
 106          * It is possible that one CPU is handling ROR interrupt and other
 107          * just gets DMA completion. Calling pump_transfers() twice for the
 108          * same transfer leads to problems thus we prevent concurrent calls
 109          * by using ->dma_running.
 110          */
 111         if (atomic_dec_and_test(&drv_data->dma_running)) {
 112                 /*
 113                  * If the other CPU is still handling the ROR interrupt we
 114                  * might not know about the error yet. So we re-check the
 115                  * ROR bit here before we clear the status register.
 116                  */
 117                 if (!error) {
 118                         u32 status = pxa2xx_spi_read(drv_data, SSSR)
 119                                      & drv_data->mask_sr;
 120                         error = status & SSSR_ROR;
 121                 }
 122
 123                 /* Clear status & disable interrupts */
 124                 pxa2xx_spi_write(drv_data, SSCR1,
 125                                  pxa2xx_spi_read(drv_data, SSCR1)
 126                                  & ~drv_data->dma_cr1);
 127                 write_SSSR_CS(drv_data, drv_data->clear_sr);
 128                 if (!pxa25x_ssp_comp(drv_data))
 129                         pxa2xx_spi_write(drv_data, SSTO, 0);
 130
 131                 if (!error) {
 132                         pxa2xx_spi_unmap_dma_buffers(drv_data);
 133
 134                         msg->actual_length += drv_data->len;
 135                         msg->state = pxa2xx_spi_next_transfer(drv_data);
 136                 } else {
 137                         /* In case we got an error we disable the SSP now */
 138                         pxa2xx_spi_write(drv_data, SSCR0,
 139                                          pxa2xx_spi_read(drv_data, SSCR0)
 140                                          & ~SSCR0_SSE);
 141
 142                         msg->state = ERROR_STATE;
 143                 }
 144
 145                 tasklet_schedule(&drv_data->pump_transfers);
 146         }
 147 }
 148
 149 static void pxa2xx_spi_dma_callback(void *data)
 150 {
 151         pxa2xx_spi_dma_transfer_complete(data, false);
 152 }
 153
 154 static struct dma_async_tx_descriptor *
 155 pxa2xx_spi_dma_prepare_one(struct driver_data *drv_data,
 156                            enum dma_transfer_direction dir)
 157 {
 158         struct chip_data *chip = drv_data->cur_chip;
 159         enum dma_slave_buswidth width;
 160         struct dma_slave_config cfg;
 161         struct dma_chan *chan;
 162         struct sg_table *sgt;
 163         int nents, ret;
 164
 165         switch (drv_data->n_bytes) {
 166         case 1:
 167                 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 168                 break;
 169         case 2:
 170                 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 171                 break;
 172         default:
 173                 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 174                 break;
 175         }
 176
 177         memset(&cfg, 0, sizeof(cfg));
 178         cfg.direction = dir;
 179
 180         if (dir == DMA_MEM_TO_DEV) {
 181                 cfg.dst_addr = drv_data->ssdr_physical;
 182                 cfg.dst_addr_width = width;
 183                 cfg.dst_maxburst = chip->dma_burst_size;
 184
 185                 sgt = &drv_data->tx_sgt;
 186                 nents = drv_data->tx_nents;
 187                 chan = drv_data->tx_chan;
 188         } else {
 189                 cfg.src_addr = drv_data->ssdr_physical;
 190                 cfg.src_addr_width = width;
 191                 cfg.src_maxburst = chip->dma_burst_size;
 192
 193                 sgt = &drv_data->rx_sgt;
 194                 nents = drv_data->rx_nents;
 195                 chan = drv_data->rx_chan;
 196         }
 197
 198         ret = dmaengine_slave_config(chan, &cfg);
 199         if (ret) {
 200                 dev_warn(&drv_data->pdev->dev, "DMA slave config failed\n");
 201                 return NULL;
 202         }
 203
 204         return dmaengine_prep_slave_sg(chan, sgt->sgl, nents, dir,
 205                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 206 }
 207
 208 bool pxa2xx_spi_dma_is_possible(size_t len)
 209 {
 210         return len <= MAX_DMA_LEN;
 211 }
 212
 213 int pxa2xx_spi_map_dma_buffers(struct driver_data *drv_data)
 214 {
 215         const struct chip_data *chip = drv_data->cur_chip;
 216         int ret;
 217
 218         if (!chip->enable_dma)
 219                 return 0;
 220
 221         /* Don't bother with DMA if we can't do even a single burst */
 222         if (drv_data->len < chip->dma_burst_size)
 223                 return 0;
 224
 225         ret = pxa2xx_spi_map_dma_buffer(drv_data, DMA_TO_DEVICE);
 226         if (ret <= 0) {
 227                 dev_warn(&drv_data->pdev->dev, "failed to DMA map TX\n");
 228                 return 0;
 229         }
 230
 231         drv_data->tx_nents = ret;
 232
 233         ret = pxa2xx_spi_map_dma_buffer(drv_data, DMA_FROM_DEVICE);
 234         if (ret <= 0) {
 235                 pxa2xx_spi_unmap_dma_buffer(drv_data, DMA_TO_DEVICE);
 236                 dev_warn(&drv_data->pdev->dev, "failed to DMA map RX\n");
 237                 return 0;
 238         }
 239
 240         drv_data->rx_nents = ret;
 241         return 1;
 242 }
 243
 244 irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data)
 245 {
 246         u32 status;
 247
 248         status = pxa2xx_spi_read(drv_data, SSSR) & drv_data->mask_sr;
 249         if (status & SSSR_ROR) {
 250                 dev_err(&drv_data->pdev->dev, "FIFO overrun\n");
 251
 252                 dmaengine_terminate_async(drv_data->rx_chan);
 253                 dmaengine_terminate_async(drv_data->tx_chan);
 254
 255                 pxa2xx_spi_dma_transfer_complete(drv_data, true);
 256                 return IRQ_HANDLED;
 257         }
 258
 259         return IRQ_NONE;
 260 }
 261
 262 int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst)
 263 {
 264         struct dma_async_tx_descriptor *tx_desc, *rx_desc;
 265         int err = 0;
 266
 267         tx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_MEM_TO_DEV);
 268         if (!tx_desc) {
 269                 dev_err(&drv_data->pdev->dev,
 270                         "failed to get DMA TX descriptor\n");
 271                 err = -EBUSY;
 272                 goto err_tx;
 273         }
 274
 275         rx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_DEV_TO_MEM);
 276         if (!rx_desc) {
 277                 dev_err(&drv_data->pdev->dev,
 278                         "failed to get DMA RX descriptor\n");
 279                 err = -EBUSY;
 280                 goto err_rx;
 281         }
 282
 283         /* We are ready when RX completes */
 284         rx_desc->callback = pxa2xx_spi_dma_callback;
 285         rx_desc->callback_param = drv_data;
 286
 287         dmaengine_submit(rx_desc);
 288         dmaengine_submit(tx_desc);
 289         return 0;
 290
 291 err_rx:
 292         dmaengine_terminate_async(drv_data->tx_chan);
 293 err_tx:
 294         pxa2xx_spi_unmap_dma_buffers(drv_data);
 295         return err;
 296 }
 297
 298 void pxa2xx_spi_dma_start(struct driver_data *drv_data)
 299 {
 300         dma_async_issue_pending(drv_data->rx_chan);
 301         dma_async_issue_pending(drv_data->tx_chan);
 302
 303         atomic_set(&drv_data->dma_running, 1);
 304 }
 305
 306 int pxa2xx_spi_dma_setup(struct driver_data *drv_data)
 307 {
 308         struct pxa2xx_spi_master *pdata = drv_data->master_info;
 309         struct device *dev = &drv_data->pdev->dev;
 310         dma_cap_mask_t mask;
 311
 312         dma_cap_zero(mask);
 313         dma_cap_set(DMA_SLAVE, mask);
 314
 315         drv_data->dummy = devm_kzalloc(dev, SZ_2K, GFP_KERNEL);
 316         if (!drv_data->dummy)
 317                 return -ENOMEM;
 318
 319         drv_data->tx_chan = dma_request_slave_channel_compat(mask,
 320                                 pdata->dma_filter, pdata->tx_param, dev, "tx");
 321         if (!drv_data->tx_chan)
 322                 return -ENODEV;
 323
 324         drv_data->rx_chan = dma_request_slave_channel_compat(mask,
 325                                 pdata->dma_filter, pdata->rx_param, dev, "rx");
 326         if (!drv_data->rx_chan) {
 327                 dma_release_channel(drv_data->tx_chan);
 328                 drv_data->tx_chan = NULL;
 329                 return -ENODEV;
 330         }
 331
 332         return 0;
 333 }
 334
 335 void pxa2xx_spi_dma_release(struct driver_data *drv_data)
 336 {
 337         if (drv_data->rx_chan) {
 338                 dmaengine_terminate_sync(drv_data->rx_chan);
 339                 dma_release_channel(drv_data->rx_chan);
 340                 sg_free_table(&drv_data->rx_sgt);
 341                 drv_data->rx_chan = NULL;
 342         }
 343         if (drv_data->tx_chan) {
 344                 dmaengine_terminate_sync(drv_data->tx_chan);
 345                 dma_release_channel(drv_data->tx_chan);
 346                 sg_free_table(&drv_data->tx_sgt);
 347                 drv_data->tx_chan = NULL;
 348         }
 349 }
 350
 351 int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
 352                                            struct spi_device *spi,
 353                                            u8 bits_per_word, u32 *burst_code,
 354                                            u32 *threshold)
 355 {
 356         struct pxa2xx_spi_chip *chip_info = spi->controller_data;
 357
 358         /*
 359          * If the DMA burst size is given in chip_info we use that,
 360          * otherwise we use the default. Also we use the default FIFO
 361          * thresholds for now.
 362          */
 363         *burst_code = chip_info ? chip_info->dma_burst_size : 1;
 364         *threshold = SSCR1_RxTresh(RX_THRESH_DFLT)
 365                    | SSCR1_TxTresh(TX_THRESH_DFLT);
 366
 367         return 0;
 368 }