drivers/spi/spi-pxa2xx.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
   4  * Copyright (C) 2013, Intel Corporation
   5  */
   6
   7 #include <linux/acpi.h>
   8 #include <linux/bitops.h>
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/device.h>
  12 #include <linux/err.h>
  13 #include <linux/errno.h>
  14 #include <linux/gpio/consumer.h>
  15 #include <linux/gpio.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/ioport.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/mod_devicetable.h>
  22 #include <linux/of.h>
  23 #include <linux/pci.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/property.h>
  27 #include <linux/slab.h>
  28 #include <linux/spi/pxa2xx_spi.h>
  29 #include <linux/spi/spi.h>
  30
  31 #include "spi-pxa2xx.h"
  32
  33 MODULE_AUTHOR("Stephen Street");
  34 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
  35 MODULE_LICENSE("GPL");
  36 MODULE_ALIAS("platform:pxa2xx-spi");
  37
  38 #define TIMOUT_DFLT             1000
  39
  40 /*
  41  * for testing SSCR1 changes that require SSP restart, basically
  42  * everything except the service and interrupt enables, the pxa270 developer
  43  * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
  44  * list, but the PXA255 dev man says all bits without really meaning the
  45  * service and interrupt enables
  46  */
  47 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
  48                                 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
  49                                 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
  50                                 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
  51                                 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
  52                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  53
  54 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF   \
  55                                 | QUARK_X1000_SSCR1_EFWR        \
  56                                 | QUARK_X1000_SSCR1_RFT         \
  57                                 | QUARK_X1000_SSCR1_TFT         \
  58                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  59
  60 #define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
  61                                 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
  62                                 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
  63                                 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
  64                                 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
  65                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  66
  67 #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE   BIT(24)
  68 #define LPSS_CS_CONTROL_SW_MODE                 BIT(0)
  69 #define LPSS_CS_CONTROL_CS_HIGH                 BIT(1)
  70 #define LPSS_CAPS_CS_EN_SHIFT                   9
  71 #define LPSS_CAPS_CS_EN_MASK                    (0xf << LPSS_CAPS_CS_EN_SHIFT)
  72
  73 #define LPSS_PRIV_CLOCK_GATE 0x38
  74 #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3
  75 #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3
  76
  77 struct lpss_config {
  78         /* LPSS offset from drv_data->ioaddr */
  79         unsigned offset;
  80         /* Register offsets from drv_data->lpss_base or -1 */
  81         int reg_general;
  82         int reg_ssp;
  83         int reg_cs_ctrl;
  84         int reg_capabilities;
  85         /* FIFO thresholds */
  86         u32 rx_threshold;
  87         u32 tx_threshold_lo;
  88         u32 tx_threshold_hi;
  89         /* Chip select control */
  90         unsigned cs_sel_shift;
  91         unsigned cs_sel_mask;
  92         unsigned cs_num;
  93         /* Quirks */
  94         unsigned cs_clk_stays_gated : 1;
  95 };
  96
  97 /* Keep these sorted with enum pxa_ssp_type */
  98 static const struct lpss_config lpss_platforms[] = {
  99         {       /* LPSS_LPT_SSP */
 100                 .offset = 0x800,
 101                 .reg_general = 0x08,
 102                 .reg_ssp = 0x0c,
 103                 .reg_cs_ctrl = 0x18,
 104                 .reg_capabilities = -1,
 105                 .rx_threshold = 64,
 106                 .tx_threshold_lo = 160,
 107                 .tx_threshold_hi = 224,
 108         },
 109         {       /* LPSS_BYT_SSP */
 110                 .offset = 0x400,
 111                 .reg_general = 0x08,
 112                 .reg_ssp = 0x0c,
 113                 .reg_cs_ctrl = 0x18,
 114                 .reg_capabilities = -1,
 115                 .rx_threshold = 64,
 116                 .tx_threshold_lo = 160,
 117                 .tx_threshold_hi = 224,
 118         },
 119         {       /* LPSS_BSW_SSP */
 120                 .offset = 0x400,
 121                 .reg_general = 0x08,
 122                 .reg_ssp = 0x0c,
 123                 .reg_cs_ctrl = 0x18,
 124                 .reg_capabilities = -1,
 125                 .rx_threshold = 64,
 126                 .tx_threshold_lo = 160,
 127                 .tx_threshold_hi = 224,
 128                 .cs_sel_shift = 2,
 129                 .cs_sel_mask = 1 << 2,
 130                 .cs_num = 2,
 131         },
 132         {       /* LPSS_SPT_SSP */
 133                 .offset = 0x200,
 134                 .reg_general = -1,
 135                 .reg_ssp = 0x20,
 136                 .reg_cs_ctrl = 0x24,
 137                 .reg_capabilities = -1,
 138                 .rx_threshold = 1,
 139                 .tx_threshold_lo = 32,
 140                 .tx_threshold_hi = 56,
 141         },
 142         {       /* LPSS_BXT_SSP */
 143                 .offset = 0x200,
 144                 .reg_general = -1,
 145                 .reg_ssp = 0x20,
 146                 .reg_cs_ctrl = 0x24,
 147                 .reg_capabilities = 0xfc,
 148                 .rx_threshold = 1,
 149                 .tx_threshold_lo = 16,
 150                 .tx_threshold_hi = 48,
 151                 .cs_sel_shift = 8,
 152                 .cs_sel_mask = 3 << 8,
 153         },
 154         {       /* LPSS_CNL_SSP */
 155                 .offset = 0x200,
 156                 .reg_general = -1,
 157                 .reg_ssp = 0x20,
 158                 .reg_cs_ctrl = 0x24,
 159                 .reg_capabilities = 0xfc,
 160                 .rx_threshold = 1,
 161                 .tx_threshold_lo = 32,
 162                 .tx_threshold_hi = 56,
 163                 .cs_sel_shift = 8,
 164                 .cs_sel_mask = 3 << 8,
 165                 .cs_clk_stays_gated = true,
 166         },
 167 };
 168
 169 static inline const struct lpss_config
 170 *lpss_get_config(const struct driver_data *drv_data)
 171 {
 172         return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
 173 }
 174
 175 static bool is_lpss_ssp(const struct driver_data *drv_data)
 176 {
 177         switch (drv_data->ssp_type) {
 178         case LPSS_LPT_SSP:
 179         case LPSS_BYT_SSP:
 180         case LPSS_BSW_SSP:
 181         case LPSS_SPT_SSP:
 182         case LPSS_BXT_SSP:
 183         case LPSS_CNL_SSP:
 184                 return true;
 185         default:
 186                 return false;
 187         }
 188 }
 189
 190 static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
 191 {
 192         return drv_data->ssp_type == QUARK_X1000_SSP;
 193 }
 194
 195 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
 196 {
 197         switch (drv_data->ssp_type) {
 198         case QUARK_X1000_SSP:
 199                 return QUARK_X1000_SSCR1_CHANGE_MASK;
 200         case CE4100_SSP:
 201                 return CE4100_SSCR1_CHANGE_MASK;
 202         default:
 203                 return SSCR1_CHANGE_MASK;
 204         }
 205 }
 206
 207 static u32
 208 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
 209 {
 210         switch (drv_data->ssp_type) {
 211         case QUARK_X1000_SSP:
 212                 return RX_THRESH_QUARK_X1000_DFLT;
 213         case CE4100_SSP:
 214                 return RX_THRESH_CE4100_DFLT;
 215         default:
 216                 return RX_THRESH_DFLT;
 217         }
 218 }
 219
 220 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
 221 {
 222         u32 mask;
 223
 224         switch (drv_data->ssp_type) {
 225         case QUARK_X1000_SSP:
 226                 mask = QUARK_X1000_SSSR_TFL_MASK;
 227                 break;
 228         case CE4100_SSP:
 229                 mask = CE4100_SSSR_TFL_MASK;
 230                 break;
 231         default:
 232                 mask = SSSR_TFL_MASK;
 233                 break;
 234         }
 235
 236         return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
 237 }
 238
 239 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
 240                                      u32 *sccr1_reg)
 241 {
 242         u32 mask;
 243
 244         switch (drv_data->ssp_type) {
 245         case QUARK_X1000_SSP:
 246                 mask = QUARK_X1000_SSCR1_RFT;
 247                 break;
 248         case CE4100_SSP:
 249                 mask = CE4100_SSCR1_RFT;
 250                 break;
 251         default:
 252                 mask = SSCR1_RFT;
 253                 break;
 254         }
 255         *sccr1_reg &= ~mask;
 256 }
 257
 258 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
 259                                    u32 *sccr1_reg, u32 threshold)
 260 {
 261         switch (drv_data->ssp_type) {
 262         case QUARK_X1000_SSP:
 263                 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
 264                 break;
 265         case CE4100_SSP:
 266                 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);
 267                 break;
 268         default:
 269                 *sccr1_reg |= SSCR1_RxTresh(threshold);
 270                 break;
 271         }
 272 }
 273
 274 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
 275                                   u32 clk_div, u8 bits)
 276 {
 277         switch (drv_data->ssp_type) {
 278         case QUARK_X1000_SSP:
 279                 return clk_div
 280                         | QUARK_X1000_SSCR0_Motorola
 281                         | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
 282                         | SSCR0_SSE;
 283         default:
 284                 return clk_div
 285                         | SSCR0_Motorola
 286                         | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
 287                         | SSCR0_SSE
 288                         | (bits > 16 ? SSCR0_EDSS : 0);
 289         }
 290 }
 291
 292 /*
 293  * Read and write LPSS SSP private registers. Caller must first check that
 294  * is_lpss_ssp() returns true before these can be called.
 295  */
 296 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
 297 {
 298         WARN_ON(!drv_data->lpss_base);
 299         return readl(drv_data->lpss_base + offset);
 300 }
 301
 302 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
 303                                   unsigned offset, u32 value)
 304 {
 305         WARN_ON(!drv_data->lpss_base);
 306         writel(value, drv_data->lpss_base + offset);
 307 }
 308
 309 /*
 310  * lpss_ssp_setup - perform LPSS SSP specific setup
 311  * @drv_data: pointer to the driver private data
 312  *
 313  * Perform LPSS SSP specific setup. This function must be called first if
 314  * one is going to use LPSS SSP private registers.
 315  */
 316 static void lpss_ssp_setup(struct driver_data *drv_data)
 317 {
 318         const struct lpss_config *config;
 319         u32 value;
 320
 321         config = lpss_get_config(drv_data);
 322         drv_data->lpss_base = drv_data->ioaddr + config->offset;
 323
 324         /* Enable software chip select control */
 325         value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
 326         value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
 327         value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
 328         __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
 329
 330         /* Enable multiblock DMA transfers */
 331         if (drv_data->controller_info->enable_dma) {
 332                 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
 333
 334                 if (config->reg_general >= 0) {
 335                         value = __lpss_ssp_read_priv(drv_data,
 336                                                      config->reg_general);
 337                         value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
 338                         __lpss_ssp_write_priv(drv_data,
 339                                               config->reg_general, value);
 340                 }
 341         }
 342 }
 343
 344 static void lpss_ssp_select_cs(struct spi_device *spi,
 345                                const struct lpss_config *config)
 346 {
 347         struct driver_data *drv_data =
 348                 spi_controller_get_devdata(spi->controller);
 349         u32 value, cs;
 350
 351         if (!config->cs_sel_mask)
 352                 return;
 353
 354         value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
 355
 356         cs = spi->chip_select;
 357         cs <<= config->cs_sel_shift;
 358         if (cs != (value & config->cs_sel_mask)) {
 359                 /*
 360                  * When switching another chip select output active the
 361                  * output must be selected first and wait 2 ssp_clk cycles
 362                  * before changing state to active. Otherwise a short
 363                  * glitch will occur on the previous chip select since
 364                  * output select is latched but state control is not.
 365                  */
 366                 value &= ~config->cs_sel_mask;
 367                 value |= cs;
 368                 __lpss_ssp_write_priv(drv_data,
 369                                       config->reg_cs_ctrl, value);
 370                 ndelay(1000000000 /
 371                        (drv_data->controller->max_speed_hz / 2));
 372         }
 373 }
 374
 375 static void lpss_ssp_cs_control(struct spi_device *spi, bool enable)
 376 {
 377         struct driver_data *drv_data =
 378                 spi_controller_get_devdata(spi->controller);
 379         const struct lpss_config *config;
 380         u32 value;
 381
 382         config = lpss_get_config(drv_data);
 383
 384         if (enable)
 385                 lpss_ssp_select_cs(spi, config);
 386
 387         value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
 388         if (enable)
 389                 value &= ~LPSS_CS_CONTROL_CS_HIGH;
 390         else
 391                 value |= LPSS_CS_CONTROL_CS_HIGH;
 392         __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
 393         if (config->cs_clk_stays_gated) {
 394                 u32 clkgate;
 395
 396                 /*
 397                  * Changing CS alone when dynamic clock gating is on won't
 398                  * actually flip CS at that time. This ruins SPI transfers
 399                  * that specify delays, or have no data. Toggle the clock mode
 400                  * to force on briefly to poke the CS pin to move.
 401                  */
 402                 clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE);
 403                 value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) |
 404                         LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON;
 405
 406                 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value);
 407                 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate);
 408         }
 409 }
 410
 411 static void cs_assert(struct spi_device *spi)
 412 {
 413         struct chip_data *chip = spi_get_ctldata(spi);
 414         struct driver_data *drv_data =
 415                 spi_controller_get_devdata(spi->controller);
 416
 417         if (drv_data->ssp_type == CE4100_SSP) {
 418                 pxa2xx_spi_write(drv_data, SSSR, chip->frm);
 419                 return;
 420         }
 421
 422         if (chip->cs_control) {
 423                 chip->cs_control(PXA2XX_CS_ASSERT);
 424                 return;
 425         }
 426
 427         if (chip->gpiod_cs) {
 428                 gpiod_set_value(chip->gpiod_cs, chip->gpio_cs_inverted);
 429                 return;
 430         }
 431
 432         if (is_lpss_ssp(drv_data))
 433                 lpss_ssp_cs_control(spi, true);
 434 }
 435
 436 static void cs_deassert(struct spi_device *spi)
 437 {
 438         struct chip_data *chip = spi_get_ctldata(spi);
 439         struct driver_data *drv_data =
 440                 spi_controller_get_devdata(spi->controller);
 441         unsigned long timeout;
 442
 443         if (drv_data->ssp_type == CE4100_SSP)
 444                 return;
 445
 446         /* Wait until SSP becomes idle before deasserting the CS */
 447         timeout = jiffies + msecs_to_jiffies(10);
 448         while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
 449                !time_after(jiffies, timeout))
 450                 cpu_relax();
 451
 452         if (chip->cs_control) {
 453                 chip->cs_control(PXA2XX_CS_DEASSERT);
 454                 return;
 455         }
 456
 457         if (chip->gpiod_cs) {
 458                 gpiod_set_value(chip->gpiod_cs, !chip->gpio_cs_inverted);
 459                 return;
 460         }
 461
 462         if (is_lpss_ssp(drv_data))
 463                 lpss_ssp_cs_control(spi, false);
 464 }
 465
 466 static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level)
 467 {
 468         if (level)
 469                 cs_deassert(spi);
 470         else
 471                 cs_assert(spi);
 472 }
 473
 474 int pxa2xx_spi_flush(struct driver_data *drv_data)
 475 {
 476         unsigned long limit = loops_per_jiffy << 1;
 477
 478         do {
 479                 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 480                         pxa2xx_spi_read(drv_data, SSDR);
 481         } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
 482         write_SSSR_CS(drv_data, SSSR_ROR);
 483
 484         return limit;
 485 }
 486
 487 static void pxa2xx_spi_off(struct driver_data *drv_data)
 488 {
 489         /* On MMP, disabling SSE seems to corrupt the rx fifo */
 490         if (drv_data->ssp_type == MMP2_SSP)
 491                 return;
 492
 493         pxa2xx_spi_write(drv_data, SSCR0,
 494                          pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
 495 }
 496
 497 static int null_writer(struct driver_data *drv_data)
 498 {
 499         u8 n_bytes = drv_data->n_bytes;
 500
 501         if (pxa2xx_spi_txfifo_full(drv_data)
 502                 || (drv_data->tx == drv_data->tx_end))
 503                 return 0;
 504
 505         pxa2xx_spi_write(drv_data, SSDR, 0);
 506         drv_data->tx += n_bytes;
 507
 508         return 1;
 509 }
 510
 511 static int null_reader(struct driver_data *drv_data)
 512 {
 513         u8 n_bytes = drv_data->n_bytes;
 514
 515         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 516                && (drv_data->rx < drv_data->rx_end)) {
 517                 pxa2xx_spi_read(drv_data, SSDR);
 518                 drv_data->rx += n_bytes;
 519         }
 520
 521         return drv_data->rx == drv_data->rx_end;
 522 }
 523
 524 static int u8_writer(struct driver_data *drv_data)
 525 {
 526         if (pxa2xx_spi_txfifo_full(drv_data)
 527                 || (drv_data->tx == drv_data->tx_end))
 528                 return 0;
 529
 530         pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
 531         ++drv_data->tx;
 532
 533         return 1;
 534 }
 535
 536 static int u8_reader(struct driver_data *drv_data)
 537 {
 538         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 539                && (drv_data->rx < drv_data->rx_end)) {
 540                 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
 541                 ++drv_data->rx;
 542         }
 543
 544         return drv_data->rx == drv_data->rx_end;
 545 }
 546
 547 static int u16_writer(struct driver_data *drv_data)
 548 {
 549         if (pxa2xx_spi_txfifo_full(drv_data)
 550                 || (drv_data->tx == drv_data->tx_end))
 551                 return 0;
 552
 553         pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
 554         drv_data->tx += 2;
 555
 556         return 1;
 557 }
 558
 559 static int u16_reader(struct driver_data *drv_data)
 560 {
 561         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 562                && (drv_data->rx < drv_data->rx_end)) {
 563                 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
 564                 drv_data->rx += 2;
 565         }
 566
 567         return drv_data->rx == drv_data->rx_end;
 568 }
 569
 570 static int u32_writer(struct driver_data *drv_data)
 571 {
 572         if (pxa2xx_spi_txfifo_full(drv_data)
 573                 || (drv_data->tx == drv_data->tx_end))
 574                 return 0;
 575
 576         pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
 577         drv_data->tx += 4;
 578
 579         return 1;
 580 }
 581
 582 static int u32_reader(struct driver_data *drv_data)
 583 {
 584         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 585                && (drv_data->rx < drv_data->rx_end)) {
 586                 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
 587                 drv_data->rx += 4;
 588         }
 589
 590         return drv_data->rx == drv_data->rx_end;
 591 }
 592
 593 static void reset_sccr1(struct driver_data *drv_data)
 594 {
 595         struct chip_data *chip =
 596                 spi_get_ctldata(drv_data->controller->cur_msg->spi);
 597         u32 sccr1_reg;
 598
 599         sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
 600         switch (drv_data->ssp_type) {
 601         case QUARK_X1000_SSP:
 602                 sccr1_reg &= ~QUARK_X1000_SSCR1_RFT;
 603                 break;
 604         case CE4100_SSP:
 605                 sccr1_reg &= ~CE4100_SSCR1_RFT;
 606                 break;
 607         default:
 608                 sccr1_reg &= ~SSCR1_RFT;
 609                 break;
 610         }
 611         sccr1_reg |= chip->threshold;
 612         pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
 613 }
 614
 615 static void int_error_stop(struct driver_data *drv_data, const char* msg)
 616 {
 617         /* Stop and reset SSP */
 618         write_SSSR_CS(drv_data, drv_data->clear_sr);
 619         reset_sccr1(drv_data);
 620         if (!pxa25x_ssp_comp(drv_data))
 621                 pxa2xx_spi_write(drv_data, SSTO, 0);
 622         pxa2xx_spi_flush(drv_data);
 623         pxa2xx_spi_off(drv_data);
 624
 625         dev_err(&drv_data->pdev->dev, "%s\n", msg);
 626
 627         drv_data->controller->cur_msg->status = -EIO;
 628         spi_finalize_current_transfer(drv_data->controller);
 629 }
 630
 631 static void int_transfer_complete(struct driver_data *drv_data)
 632 {
 633         /* Clear and disable interrupts */
 634         write_SSSR_CS(drv_data, drv_data->clear_sr);
 635         reset_sccr1(drv_data);
 636         if (!pxa25x_ssp_comp(drv_data))
 637                 pxa2xx_spi_write(drv_data, SSTO, 0);
 638
 639         spi_finalize_current_transfer(drv_data->controller);
 640 }
 641
 642 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
 643 {
 644         u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
 645                        drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
 646
 647         u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
 648
 649         if (irq_status & SSSR_ROR) {
 650                 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
 651                 return IRQ_HANDLED;
 652         }
 653
 654         if (irq_status & SSSR_TUR) {
 655                 int_error_stop(drv_data, "interrupt_transfer: fifo underrun");
 656                 return IRQ_HANDLED;
 657         }
 658
 659         if (irq_status & SSSR_TINT) {
 660                 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
 661                 if (drv_data->read(drv_data)) {
 662                         int_transfer_complete(drv_data);
 663                         return IRQ_HANDLED;
 664                 }
 665         }
 666
 667         /* Drain rx fifo, Fill tx fifo and prevent overruns */
 668         do {
 669                 if (drv_data->read(drv_data)) {
 670                         int_transfer_complete(drv_data);
 671                         return IRQ_HANDLED;
 672                 }
 673         } while (drv_data->write(drv_data));
 674
 675         if (drv_data->read(drv_data)) {
 676                 int_transfer_complete(drv_data);
 677                 return IRQ_HANDLED;
 678         }
 679
 680         if (drv_data->tx == drv_data->tx_end) {
 681                 u32 bytes_left;
 682                 u32 sccr1_reg;
 683
 684                 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
 685                 sccr1_reg &= ~SSCR1_TIE;
 686
 687                 /*
 688                  * PXA25x_SSP has no timeout, set up rx threshould for the
 689                  * remaining RX bytes.
 690                  */
 691                 if (pxa25x_ssp_comp(drv_data)) {
 692                         u32 rx_thre;
 693
 694                         pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
 695
 696                         bytes_left = drv_data->rx_end - drv_data->rx;
 697                         switch (drv_data->n_bytes) {
 698                         case 4:
 699                                 bytes_left >>= 2;
 700                                 break;
 701                         case 2:
 702                                 bytes_left >>= 1;
 703                                 break;
 704                         }
 705
 706                         rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
 707                         if (rx_thre > bytes_left)
 708                                 rx_thre = bytes_left;
 709
 710                         pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
 711                 }
 712                 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
 713         }
 714
 715         /* We did something */
 716         return IRQ_HANDLED;
 717 }
 718
 719 static void handle_bad_msg(struct driver_data *drv_data)
 720 {
 721         pxa2xx_spi_off(drv_data);
 722         pxa2xx_spi_write(drv_data, SSCR1,
 723                          pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1);
 724         if (!pxa25x_ssp_comp(drv_data))
 725                 pxa2xx_spi_write(drv_data, SSTO, 0);
 726         write_SSSR_CS(drv_data, drv_data->clear_sr);
 727
 728         dev_err(&drv_data->pdev->dev,
 729                 "bad message state in interrupt handler\n");
 730 }
 731
 732 static irqreturn_t ssp_int(int irq, void *dev_id)
 733 {
 734         struct driver_data *drv_data = dev_id;
 735         u32 sccr1_reg;
 736         u32 mask = drv_data->mask_sr;
 737         u32 status;
 738
 739         /*
 740          * The IRQ might be shared with other peripherals so we must first
 741          * check that are we RPM suspended or not. If we are we assume that
 742          * the IRQ was not for us (we shouldn't be RPM suspended when the
 743          * interrupt is enabled).
 744          */
 745         if (pm_runtime_suspended(&drv_data->pdev->dev))
 746                 return IRQ_NONE;
 747
 748         /*
 749          * If the device is not yet in RPM suspended state and we get an
 750          * interrupt that is meant for another device, check if status bits
 751          * are all set to one. That means that the device is already
 752          * powered off.
 753          */
 754         status = pxa2xx_spi_read(drv_data, SSSR);
 755         if (status == ~0)
 756                 return IRQ_NONE;
 757
 758         sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
 759
 760         /* Ignore possible writes if we don't need to write */
 761         if (!(sccr1_reg & SSCR1_TIE))
 762                 mask &= ~SSSR_TFS;
 763
 764         /* Ignore RX timeout interrupt if it is disabled */
 765         if (!(sccr1_reg & SSCR1_TINTE))
 766                 mask &= ~SSSR_TINT;
 767
 768         if (!(status & mask))
 769                 return IRQ_NONE;
 770
 771         pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
 772         pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
 773
 774         if (!drv_data->controller->cur_msg) {
 775                 handle_bad_msg(drv_data);
 776                 /* Never fail */
 777                 return IRQ_HANDLED;
 778         }
 779
 780         return drv_data->transfer_handler(drv_data);
 781 }
 782
 783 /*
 784  * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
 785  * input frequency by fractions of 2^24. It also has a divider by 5.
 786  *
 787  * There are formulas to get baud rate value for given input frequency and
 788  * divider parameters, such as DDS_CLK_RATE and SCR:
 789  *
 790  * Fsys = 200MHz
 791  *
 792  * Fssp = Fsys * DDS_CLK_RATE / 2^24                    (1)
 793  * Baud rate = Fsclk = Fssp / (2 * (SCR + 1))           (2)
 794  *
 795  * DDS_CLK_RATE either 2^n or 2^n / 5.
 796  * SCR is in range 0 .. 255
 797  *
 798  * Divisor = 5^i * 2^j * 2 * k
 799  *       i = [0, 1]      i = 1 iff j = 0 or j > 3
 800  *       j = [0, 23]     j = 0 iff i = 1
 801  *       k = [1, 256]
 802  * Special case: j = 0, i = 1: Divisor = 2 / 5
 803  *
 804  * Accordingly to the specification the recommended values for DDS_CLK_RATE
 805  * are:
 806  *      Case 1:         2^n, n = [0, 23]
 807  *      Case 2:         2^24 * 2 / 5 (0x666666)
 808  *      Case 3:         less than or equal to 2^24 / 5 / 16 (0x33333)
 809  *
 810  * In all cases the lowest possible value is better.
 811  *
 812  * The function calculates parameters for all cases and chooses the one closest
 813  * to the asked baud rate.
 814  */
 815 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
 816 {
 817         unsigned long xtal = 200000000;
 818         unsigned long fref = xtal / 2;          /* mandatory division by 2,
 819                                                    see (2) */
 820                                                 /* case 3 */
 821         unsigned long fref1 = fref / 2;         /* case 1 */
 822         unsigned long fref2 = fref * 2 / 5;     /* case 2 */
 823         unsigned long scale;
 824         unsigned long q, q1, q2;
 825         long r, r1, r2;
 826         u32 mul;
 827
 828         /* Case 1 */
 829
 830         /* Set initial value for DDS_CLK_RATE */
 831         mul = (1 << 24) >> 1;
 832
 833         /* Calculate initial quot */
 834         q1 = DIV_ROUND_UP(fref1, rate);
 835
 836         /* Scale q1 if it's too big */
 837         if (q1 > 256) {
 838                 /* Scale q1 to range [1, 512] */
 839                 scale = fls_long(q1 - 1);
 840                 if (scale > 9) {
 841                         q1 >>= scale - 9;
 842                         mul >>= scale - 9;
 843                 }
 844
 845                 /* Round the result if we have a remainder */
 846                 q1 += q1 & 1;
 847         }
 848
 849         /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
 850         scale = __ffs(q1);
 851         q1 >>= scale;
 852         mul >>= scale;
 853
 854         /* Get the remainder */
 855         r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
 856
 857         /* Case 2 */
 858
 859         q2 = DIV_ROUND_UP(fref2, rate);
 860         r2 = abs(fref2 / q2 - rate);
 861
 862         /*
 863          * Choose the best between two: less remainder we have the better. We
 864          * can't go case 2 if q2 is greater than 256 since SCR register can
 865          * hold only values 0 .. 255.
 866          */
 867         if (r2 >= r1 || q2 > 256) {
 868                 /* case 1 is better */
 869                 r = r1;
 870                 q = q1;
 871         } else {
 872                 /* case 2 is better */
 873                 r = r2;
 874                 q = q2;
 875                 mul = (1 << 24) * 2 / 5;
 876         }
 877
 878         /* Check case 3 only if the divisor is big enough */
 879         if (fref / rate >= 80) {
 880                 u64 fssp;
 881                 u32 m;
 882
 883                 /* Calculate initial quot */
 884                 q1 = DIV_ROUND_UP(fref, rate);
 885                 m = (1 << 24) / q1;
 886
 887                 /* Get the remainder */
 888                 fssp = (u64)fref * m;
 889                 do_div(fssp, 1 << 24);
 890                 r1 = abs(fssp - rate);
 891
 892                 /* Choose this one if it suits better */
 893                 if (r1 < r) {
 894                         /* case 3 is better */
 895                         q = 1;
 896                         mul = m;
 897                 }
 898         }
 899
 900         *dds = mul;
 901         return q - 1;
 902 }
 903
 904 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
 905 {
 906         unsigned long ssp_clk = drv_data->controller->max_speed_hz;
 907         const struct ssp_device *ssp = drv_data->ssp;
 908
 909         rate = min_t(int, ssp_clk, rate);
 910
 911         /*
 912          * Calculate the divisor for the SCR (Serial Clock Rate), avoiding
 913          * that the SSP transmission rate can be greater than the device rate
 914          */
 915         if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
 916                 return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff;
 917         else
 918                 return (DIV_ROUND_UP(ssp_clk, rate) - 1)  & 0xfff;
 919 }
 920
 921 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
 922                                            int rate)
 923 {
 924         struct chip_data *chip =
 925                 spi_get_ctldata(drv_data->controller->cur_msg->spi);
 926         unsigned int clk_div;
 927
 928         switch (drv_data->ssp_type) {
 929         case QUARK_X1000_SSP:
 930                 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
 931                 break;
 932         default:
 933                 clk_div = ssp_get_clk_div(drv_data, rate);
 934                 break;
 935         }
 936         return clk_div << 8;
 937 }
 938
 939 static bool pxa2xx_spi_can_dma(struct spi_controller *controller,
 940                                struct spi_device *spi,
 941                                struct spi_transfer *xfer)
 942 {
 943         struct chip_data *chip = spi_get_ctldata(spi);
 944
 945         return chip->enable_dma &&
 946                xfer->len <= MAX_DMA_LEN &&
 947                xfer->len >= chip->dma_burst_size;
 948 }
 949
 950 static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
 951                                    struct spi_device *spi,
 952                                    struct spi_transfer *transfer)
 953 {
 954         struct driver_data *drv_data = spi_controller_get_devdata(controller);
 955         struct spi_message *message = controller->cur_msg;
 956         struct chip_data *chip = spi_get_ctldata(spi);
 957         u32 dma_thresh = chip->dma_threshold;
 958         u32 dma_burst = chip->dma_burst_size;
 959         u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
 960         u32 clk_div;
 961         u8 bits;
 962         u32 speed;
 963         u32 cr0;
 964         u32 cr1;
 965         int err;
 966         int dma_mapped;
 967
 968         /* Check if we can DMA this transfer */
 969         if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
 970
 971                 /* reject already-mapped transfers; PIO won't always work */
 972                 if (message->is_dma_mapped
 973                                 || transfer->rx_dma || transfer->tx_dma) {
 974                         dev_err(&spi->dev,
 975                                 "Mapped transfer length of %u is greater than %d\n",
 976                                 transfer->len, MAX_DMA_LEN);
 977                         return -EINVAL;
 978                 }
 979
 980                 /* warn ... we force this to PIO mode */
 981                 dev_warn_ratelimited(&spi->dev,
 982                                      "DMA disabled for transfer length %ld greater than %d\n",
 983                                      (long)transfer->len, MAX_DMA_LEN);
 984         }
 985
 986         /* Setup the transfer state based on the type of transfer */
 987         if (pxa2xx_spi_flush(drv_data) == 0) {
 988                 dev_err(&spi->dev, "Flush failed\n");
 989                 return -EIO;
 990         }
 991         drv_data->n_bytes = chip->n_bytes;
 992         drv_data->tx = (void *)transfer->tx_buf;
 993         drv_data->tx_end = drv_data->tx + transfer->len;
 994         drv_data->rx = transfer->rx_buf;
 995         drv_data->rx_end = drv_data->rx + transfer->len;
 996         drv_data->write = drv_data->tx ? chip->write : null_writer;
 997         drv_data->read = drv_data->rx ? chip->read : null_reader;
 998
 999         /* Change speed and bit per word on a per transfer */
1000         bits = transfer->bits_per_word;
1001         speed = transfer->speed_hz;
1002
1003         clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
1004
1005         if (bits <= 8) {
1006                 drv_data->n_bytes = 1;
1007                 drv_data->read = drv_data->read != null_reader ?
1008                                         u8_reader : null_reader;
1009                 drv_data->write = drv_data->write != null_writer ?
1010                                         u8_writer : null_writer;
1011         } else if (bits <= 16) {
1012                 drv_data->n_bytes = 2;
1013                 drv_data->read = drv_data->read != null_reader ?
1014                                         u16_reader : null_reader;
1015                 drv_data->write = drv_data->write != null_writer ?
1016                                         u16_writer : null_writer;
1017         } else if (bits <= 32) {
1018                 drv_data->n_bytes = 4;
1019                 drv_data->read = drv_data->read != null_reader ?
1020                                         u32_reader : null_reader;
1021                 drv_data->write = drv_data->write != null_writer ?
1022                                         u32_writer : null_writer;
1023         }
1024         /*
1025          * if bits/word is changed in dma mode, then must check the
1026          * thresholds and burst also
1027          */
1028         if (chip->enable_dma) {
1029                 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
1030                                                 spi,
1031                                                 bits, &dma_burst,
1032                                                 &dma_thresh))
1033                         dev_warn_ratelimited(&spi->dev,
1034                                              "DMA burst size reduced to match bits_per_word\n");
1035         }
1036
1037         dma_mapped = controller->can_dma &&
1038                      controller->can_dma(controller, spi, transfer) &&
1039                      controller->cur_msg_mapped;
1040         if (dma_mapped) {
1041
1042                 /* Ensure we have the correct interrupt handler */
1043                 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1044
1045                 err = pxa2xx_spi_dma_prepare(drv_data, transfer);
1046                 if (err)
1047                         return err;
1048
1049                 /* Clear status and start DMA engine */
1050                 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1051                 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1052
1053                 pxa2xx_spi_dma_start(drv_data);
1054         } else {
1055                 /* Ensure we have the correct interrupt handler */
1056                 drv_data->transfer_handler = interrupt_transfer;
1057
1058                 /* Clear status  */
1059                 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1060                 write_SSSR_CS(drv_data, drv_data->clear_sr);
1061         }
1062
1063         /* NOTE:  PXA25x_SSP _could_ use external clocking ... */
1064         cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1065         if (!pxa25x_ssp_comp(drv_data))
1066                 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1067                         controller->max_speed_hz
1068                                 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1069                         dma_mapped ? "DMA" : "PIO");
1070         else
1071                 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1072                         controller->max_speed_hz / 2
1073                                 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1074                         dma_mapped ? "DMA" : "PIO");
1075
1076         if (is_lpss_ssp(drv_data)) {
1077                 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1078                     != chip->lpss_rx_threshold)
1079                         pxa2xx_spi_write(drv_data, SSIRF,
1080                                          chip->lpss_rx_threshold);
1081                 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1082                     != chip->lpss_tx_threshold)
1083                         pxa2xx_spi_write(drv_data, SSITF,
1084                                          chip->lpss_tx_threshold);
1085         }
1086
1087         if (is_quark_x1000_ssp(drv_data) &&
1088             (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1089                 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1090
1091         /* see if we need to reload the config registers */
1092         if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1093             || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1094             != (cr1 & change_mask)) {
1095                 /* stop the SSP, and update the other bits */
1096                 if (drv_data->ssp_type != MMP2_SSP)
1097                         pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1098                 if (!pxa25x_ssp_comp(drv_data))
1099                         pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1100                 /* first set CR1 without interrupt and service enables */
1101                 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1102                 /* restart the SSP */
1103                 pxa2xx_spi_write(drv_data, SSCR0, cr0);
1104
1105         } else {
1106                 if (!pxa25x_ssp_comp(drv_data))
1107                         pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1108         }
1109
1110         if (drv_data->ssp_type == MMP2_SSP) {
1111                 u8 tx_level = (pxa2xx_spi_read(drv_data, SSSR)
1112                                         & SSSR_TFL_MASK) >> 8;
1113
1114                 if (tx_level) {
1115                         /* On MMP2, flipping SSE doesn't to empty TXFIFO. */
1116                         dev_warn(&spi->dev, "%d bytes of garbage in TXFIFO!\n",
1117                                                                 tx_level);
1118                         if (tx_level > transfer->len)
1119                                 tx_level = transfer->len;
1120                         drv_data->tx += tx_level;
1121                 }
1122         }
1123
1124         if (spi_controller_is_slave(controller)) {
1125                 while (drv_data->write(drv_data))
1126                         ;
1127                 if (drv_data->gpiod_ready) {
1128                         gpiod_set_value(drv_data->gpiod_ready, 1);
1129                         udelay(1);
1130                         gpiod_set_value(drv_data->gpiod_ready, 0);
1131                 }
1132         }
1133
1134         /*
1135          * Release the data by enabling service requests and interrupts,
1136          * without changing any mode bits
1137          */
1138         pxa2xx_spi_write(drv_data, SSCR1, cr1);
1139
1140         return 1;
1141 }
1142
1143 static int pxa2xx_spi_slave_abort(struct spi_controller *controller)
1144 {
1145         struct driver_data *drv_data = spi_controller_get_devdata(controller);
1146
1147         /* Stop and reset SSP */
1148         write_SSSR_CS(drv_data, drv_data->clear_sr);
1149         reset_sccr1(drv_data);
1150         if (!pxa25x_ssp_comp(drv_data))
1151                 pxa2xx_spi_write(drv_data, SSTO, 0);
1152         pxa2xx_spi_flush(drv_data);
1153         pxa2xx_spi_off(drv_data);
1154
1155         dev_dbg(&drv_data->pdev->dev, "transfer aborted\n");
1156
1157         drv_data->controller->cur_msg->status = -EINTR;
1158         spi_finalize_current_transfer(drv_data->controller);
1159
1160         return 0;
1161 }
1162
1163 static void pxa2xx_spi_handle_err(struct spi_controller *controller,
1164                                  struct spi_message *msg)
1165 {
1166         struct driver_data *drv_data = spi_controller_get_devdata(controller);
1167
1168         /* Disable the SSP */
1169         pxa2xx_spi_off(drv_data);
1170         /* Clear and disable interrupts and service requests */
1171         write_SSSR_CS(drv_data, drv_data->clear_sr);
1172         pxa2xx_spi_write(drv_data, SSCR1,
1173                          pxa2xx_spi_read(drv_data, SSCR1)
1174                          & ~(drv_data->int_cr1 | drv_data->dma_cr1));
1175         if (!pxa25x_ssp_comp(drv_data))
1176                 pxa2xx_spi_write(drv_data, SSTO, 0);
1177
1178         /*
1179          * Stop the DMA if running. Note DMA callback handler may have unset
1180          * the dma_running already, which is fine as stopping is not needed
1181          * then but we shouldn't rely this flag for anything else than
1182          * stopping. For instance to differentiate between PIO and DMA
1183          * transfers.
1184          */
1185         if (atomic_read(&drv_data->dma_running))
1186                 pxa2xx_spi_dma_stop(drv_data);
1187 }
1188
1189 static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller)
1190 {
1191         struct driver_data *drv_data = spi_controller_get_devdata(controller);
1192
1193         /* Disable the SSP now */
1194         pxa2xx_spi_off(drv_data);
1195
1196         return 0;
1197 }
1198
1199 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1200                     struct pxa2xx_spi_chip *chip_info)
1201 {
1202         struct driver_data *drv_data =
1203                 spi_controller_get_devdata(spi->controller);
1204         struct gpio_desc *gpiod;
1205         int err = 0;
1206
1207         if (chip == NULL)
1208                 return 0;
1209
1210         if (drv_data->cs_gpiods) {
1211                 gpiod = drv_data->cs_gpiods[spi->chip_select];
1212                 if (gpiod) {
1213                         chip->gpiod_cs = gpiod;
1214                         chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1215                         gpiod_set_value(gpiod, chip->gpio_cs_inverted);
1216                 }
1217
1218                 return 0;
1219         }
1220
1221         if (chip_info == NULL)
1222                 return 0;
1223
1224         /* NOTE: setup() can be called multiple times, possibly with
1225          * different chip_info, release previously requested GPIO
1226          */
1227         if (chip->gpiod_cs) {
1228                 gpiod_put(chip->gpiod_cs);
1229                 chip->gpiod_cs = NULL;
1230         }
1231
1232         /* If (*cs_control) is provided, ignore GPIO chip select */
1233         if (chip_info->cs_control) {
1234                 chip->cs_control = chip_info->cs_control;
1235                 return 0;
1236         }
1237
1238         if (gpio_is_valid(chip_info->gpio_cs)) {
1239                 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1240                 if (err) {
1241                         dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1242                                 chip_info->gpio_cs);
1243                         return err;
1244                 }
1245
1246                 gpiod = gpio_to_desc(chip_info->gpio_cs);
1247                 chip->gpiod_cs = gpiod;
1248                 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1249
1250                 err = gpiod_direction_output(gpiod, !chip->gpio_cs_inverted);
1251         }
1252
1253         return err;
1254 }
1255
1256 static int setup(struct spi_device *spi)
1257 {
1258         struct pxa2xx_spi_chip *chip_info;
1259         struct chip_data *chip;
1260         const struct lpss_config *config;
1261         struct driver_data *drv_data =
1262                 spi_controller_get_devdata(spi->controller);
1263         uint tx_thres, tx_hi_thres, rx_thres;
1264
1265         switch (drv_data->ssp_type) {
1266         case QUARK_X1000_SSP:
1267                 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1268                 tx_hi_thres = 0;
1269                 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1270                 break;
1271         case CE4100_SSP:
1272                 tx_thres = TX_THRESH_CE4100_DFLT;
1273                 tx_hi_thres = 0;
1274                 rx_thres = RX_THRESH_CE4100_DFLT;
1275                 break;
1276         case LPSS_LPT_SSP:
1277         case LPSS_BYT_SSP:
1278         case LPSS_BSW_SSP:
1279         case LPSS_SPT_SSP:
1280         case LPSS_BXT_SSP:
1281         case LPSS_CNL_SSP:
1282                 config = lpss_get_config(drv_data);
1283                 tx_thres = config->tx_threshold_lo;
1284                 tx_hi_thres = config->tx_threshold_hi;
1285                 rx_thres = config->rx_threshold;
1286                 break;
1287         default:
1288                 tx_hi_thres = 0;
1289                 if (spi_controller_is_slave(drv_data->controller)) {
1290                         tx_thres = 1;
1291                         rx_thres = 2;
1292                 } else {
1293                         tx_thres = TX_THRESH_DFLT;
1294                         rx_thres = RX_THRESH_DFLT;
1295                 }
1296                 break;
1297         }
1298
1299         /* Only alloc on first setup */
1300         chip = spi_get_ctldata(spi);
1301         if (!chip) {
1302                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1303                 if (!chip)
1304                         return -ENOMEM;
1305
1306                 if (drv_data->ssp_type == CE4100_SSP) {
1307                         if (spi->chip_select > 4) {
1308                                 dev_err(&spi->dev,
1309                                         "failed setup: cs number must not be > 4.\n");
1310                                 kfree(chip);
1311                                 return -EINVAL;
1312                         }
1313
1314                         chip->frm = spi->chip_select;
1315                 }
1316                 chip->enable_dma = drv_data->controller_info->enable_dma;
1317                 chip->timeout = TIMOUT_DFLT;
1318         }
1319
1320         /* protocol drivers may change the chip settings, so...
1321          * if chip_info exists, use it */
1322         chip_info = spi->controller_data;
1323
1324         /* chip_info isn't always needed */
1325         chip->cr1 = 0;
1326         if (chip_info) {
1327                 if (chip_info->timeout)
1328                         chip->timeout = chip_info->timeout;
1329                 if (chip_info->tx_threshold)
1330                         tx_thres = chip_info->tx_threshold;
1331                 if (chip_info->tx_hi_threshold)
1332                         tx_hi_thres = chip_info->tx_hi_threshold;
1333                 if (chip_info->rx_threshold)
1334                         rx_thres = chip_info->rx_threshold;
1335                 chip->dma_threshold = 0;
1336                 if (chip_info->enable_loopback)
1337                         chip->cr1 = SSCR1_LBM;
1338         }
1339         if (spi_controller_is_slave(drv_data->controller)) {
1340                 chip->cr1 |= SSCR1_SCFR;
1341                 chip->cr1 |= SSCR1_SCLKDIR;
1342                 chip->cr1 |= SSCR1_SFRMDIR;
1343                 chip->cr1 |= SSCR1_SPH;
1344         }
1345
1346         chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1347         chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1348                                 | SSITF_TxHiThresh(tx_hi_thres);
1349
1350         /* set dma burst and threshold outside of chip_info path so that if
1351          * chip_info goes away after setting chip->enable_dma, the
1352          * burst and threshold can still respond to changes in bits_per_word */
1353         if (chip->enable_dma) {
1354                 /* set up legal burst and threshold for dma */
1355                 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1356                                                 spi->bits_per_word,
1357                                                 &chip->dma_burst_size,
1358                                                 &chip->dma_threshold)) {
1359                         dev_warn(&spi->dev,
1360                                  "in setup: DMA burst size reduced to match bits_per_word\n");
1361                 }
1362                 dev_dbg(&spi->dev,
1363                         "in setup: DMA burst size set to %u\n",
1364                         chip->dma_burst_size);
1365         }
1366
1367         switch (drv_data->ssp_type) {
1368         case QUARK_X1000_SSP:
1369                 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1370                                    & QUARK_X1000_SSCR1_RFT)
1371                                    | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1372                                    & QUARK_X1000_SSCR1_TFT);
1373                 break;
1374         case CE4100_SSP:
1375                 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) |
1376                         (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT);
1377                 break;
1378         default:
1379                 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1380                         (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1381                 break;
1382         }
1383
1384         chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1385         chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1386                         | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1387
1388         if (spi->mode & SPI_LOOP)
1389                 chip->cr1 |= SSCR1_LBM;
1390
1391         if (spi->bits_per_word <= 8) {
1392                 chip->n_bytes = 1;
1393                 chip->read = u8_reader;
1394                 chip->write = u8_writer;
1395         } else if (spi->bits_per_word <= 16) {
1396                 chip->n_bytes = 2;
1397                 chip->read = u16_reader;
1398                 chip->write = u16_writer;
1399         } else if (spi->bits_per_word <= 32) {
1400                 chip->n_bytes = 4;
1401                 chip->read = u32_reader;
1402                 chip->write = u32_writer;
1403         }
1404
1405         spi_set_ctldata(spi, chip);
1406
1407         if (drv_data->ssp_type == CE4100_SSP)
1408                 return 0;
1409
1410         return setup_cs(spi, chip, chip_info);
1411 }
1412
1413 static void cleanup(struct spi_device *spi)
1414 {
1415         struct chip_data *chip = spi_get_ctldata(spi);
1416         struct driver_data *drv_data =
1417                 spi_controller_get_devdata(spi->controller);
1418
1419         if (!chip)
1420                 return;
1421
1422         if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods &&
1423             chip->gpiod_cs)
1424                 gpiod_put(chip->gpiod_cs);
1425
1426         kfree(chip);
1427 }
1428
1429 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1430         { "INT33C0", LPSS_LPT_SSP },
1431         { "INT33C1", LPSS_LPT_SSP },
1432         { "INT3430", LPSS_LPT_SSP },
1433         { "INT3431", LPSS_LPT_SSP },
1434         { "80860F0E", LPSS_BYT_SSP },
1435         { "8086228E", LPSS_BSW_SSP },
1436         { },
1437 };
1438 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1439
1440 /*
1441  * PCI IDs of compound devices that integrate both host controller and private
1442  * integrated DMA engine. Please note these are not used in module
1443  * autoloading and probing in this module but matching the LPSS SSP type.
1444  */
1445 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1446         /* SPT-LP */
1447         { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1448         { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1449         /* SPT-H */
1450         { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1451         { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1452         /* KBL-H */
1453         { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP },
1454         { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP },
1455         /* CML-V */
1456         { PCI_VDEVICE(INTEL, 0xa3a9), LPSS_SPT_SSP },
1457         { PCI_VDEVICE(INTEL, 0xa3aa), LPSS_SPT_SSP },
1458         /* BXT A-Step */
1459         { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
1460         { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
1461         { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
1462         /* BXT B-Step */
1463         { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP },
1464         { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP },
1465         { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP },
1466         /* GLK */
1467         { PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP },
1468         { PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP },
1469         { PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP },
1470         /* ICL-LP */
1471         { PCI_VDEVICE(INTEL, 0x34aa), LPSS_CNL_SSP },
1472         { PCI_VDEVICE(INTEL, 0x34ab), LPSS_CNL_SSP },
1473         { PCI_VDEVICE(INTEL, 0x34fb), LPSS_CNL_SSP },
1474         /* EHL */
1475         { PCI_VDEVICE(INTEL, 0x4b2a), LPSS_BXT_SSP },
1476         { PCI_VDEVICE(INTEL, 0x4b2b), LPSS_BXT_SSP },
1477         { PCI_VDEVICE(INTEL, 0x4b37), LPSS_BXT_SSP },
1478         /* JSL */
1479         { PCI_VDEVICE(INTEL, 0x4daa), LPSS_CNL_SSP },
1480         { PCI_VDEVICE(INTEL, 0x4dab), LPSS_CNL_SSP },
1481         { PCI_VDEVICE(INTEL, 0x4dfb), LPSS_CNL_SSP },
1482         /* APL */
1483         { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1484         { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
1485         { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
1486         /* CNL-LP */
1487         { PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP },
1488         { PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP },
1489         { PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP },
1490         /* CNL-H */
1491         { PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP },
1492         { PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP },
1493         { PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP },
1494         /* CML-LP */
1495         { PCI_VDEVICE(INTEL, 0x02aa), LPSS_CNL_SSP },
1496         { PCI_VDEVICE(INTEL, 0x02ab), LPSS_CNL_SSP },
1497         { PCI_VDEVICE(INTEL, 0x02fb), LPSS_CNL_SSP },
1498         /* CML-H */
1499         { PCI_VDEVICE(INTEL, 0x06aa), LPSS_CNL_SSP },
1500         { PCI_VDEVICE(INTEL, 0x06ab), LPSS_CNL_SSP },
1501         { PCI_VDEVICE(INTEL, 0x06fb), LPSS_CNL_SSP },
1502         /* TGL-LP */
1503         { PCI_VDEVICE(INTEL, 0xa0aa), LPSS_CNL_SSP },
1504         { PCI_VDEVICE(INTEL, 0xa0ab), LPSS_CNL_SSP },
1505         { PCI_VDEVICE(INTEL, 0xa0de), LPSS_CNL_SSP },
1506         { PCI_VDEVICE(INTEL, 0xa0df), LPSS_CNL_SSP },
1507         { PCI_VDEVICE(INTEL, 0xa0fb), LPSS_CNL_SSP },
1508         { PCI_VDEVICE(INTEL, 0xa0fd), LPSS_CNL_SSP },
1509         { PCI_VDEVICE(INTEL, 0xa0fe), LPSS_CNL_SSP },
1510         { },
1511 };
1512
1513 static const struct of_device_id pxa2xx_spi_of_match[] = {
1514         { .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP },
1515         {},
1516 };
1517 MODULE_DEVICE_TABLE(of, pxa2xx_spi_of_match);
1518
1519 #ifdef CONFIG_ACPI
1520
1521 static int pxa2xx_spi_get_port_id(struct device *dev)
1522 {
1523         struct acpi_device *adev;
1524         unsigned int devid;
1525         int port_id = -1;
1526
1527         adev = ACPI_COMPANION(dev);
1528         if (adev && adev->pnp.unique_id &&
1529             !kstrtouint(adev->pnp.unique_id, 0, &devid))
1530                 port_id = devid;
1531         return port_id;
1532 }
1533
1534 #else /* !CONFIG_ACPI */
1535
1536 static int pxa2xx_spi_get_port_id(struct device *dev)
1537 {
1538         return -1;
1539 }
1540
1541 #endif /* CONFIG_ACPI */
1542
1543
1544 #ifdef CONFIG_PCI
1545
1546 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1547 {
1548         return param == chan->device->dev;
1549 }
1550
1551 #endif /* CONFIG_PCI */
1552
1553 static struct pxa2xx_spi_controller *
1554 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1555 {
1556         struct pxa2xx_spi_controller *pdata;
1557         struct ssp_device *ssp;
1558         struct resource *res;
1559         struct device *parent = pdev->dev.parent;
1560         struct pci_dev *pcidev = dev_is_pci(parent) ? to_pci_dev(parent) : NULL;
1561         const struct pci_device_id *pcidev_id = NULL;
1562         enum pxa_ssp_type type;
1563         const void *match;
1564
1565         if (pcidev)
1566                 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match, pcidev);
1567
1568         match = device_get_match_data(&pdev->dev);
1569         if (match)
1570                 type = (enum pxa_ssp_type)match;
1571         else if (pcidev_id)
1572                 type = (enum pxa_ssp_type)pcidev_id->driver_data;
1573         else
1574                 return NULL;
1575
1576         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1577         if (!pdata)
1578                 return NULL;
1579
1580         ssp = &pdata->ssp;
1581
1582         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1583         ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1584         if (IS_ERR(ssp->mmio_base))
1585                 return NULL;
1586
1587         ssp->phys_base = res->start;
1588
1589 #ifdef CONFIG_PCI
1590         if (pcidev_id) {
1591                 pdata->tx_param = parent;
1592                 pdata->rx_param = parent;
1593                 pdata->dma_filter = pxa2xx_spi_idma_filter;
1594         }
1595 #endif
1596
1597         ssp->clk = devm_clk_get(&pdev->dev, NULL);
1598         if (IS_ERR(ssp->clk))
1599                 return NULL;
1600
1601         ssp->irq = platform_get_irq(pdev, 0);
1602         if (ssp->irq < 0)
1603                 return NULL;
1604
1605         ssp->type = type;
1606         ssp->dev = &pdev->dev;
1607         ssp->port_id = pxa2xx_spi_get_port_id(&pdev->dev);
1608
1609         pdata->is_slave = device_property_read_bool(&pdev->dev, "spi-slave");
1610         pdata->num_chipselect = 1;
1611         pdata->enable_dma = true;
1612         pdata->dma_burst_size = 1;
1613
1614         return pdata;
1615 }
1616
1617 static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller,
1618                                       unsigned int cs)
1619 {
1620         struct driver_data *drv_data = spi_controller_get_devdata(controller);
1621
1622         if (has_acpi_companion(&drv_data->pdev->dev)) {
1623                 switch (drv_data->ssp_type) {
1624                 /*
1625                  * For Atoms the ACPI DeviceSelection used by the Windows
1626                  * driver starts from 1 instead of 0 so translate it here
1627                  * to match what Linux expects.
1628                  */
1629                 case LPSS_BYT_SSP:
1630                 case LPSS_BSW_SSP:
1631                         return cs - 1;
1632
1633                 default:
1634                         break;
1635                 }
1636         }
1637
1638         return cs;
1639 }
1640
1641 static size_t pxa2xx_spi_max_dma_transfer_size(struct spi_device *spi)
1642 {
1643         return MAX_DMA_LEN;
1644 }
1645
1646 static int pxa2xx_spi_probe(struct platform_device *pdev)
1647 {
1648         struct device *dev = &pdev->dev;
1649         struct pxa2xx_spi_controller *platform_info;
1650         struct spi_controller *controller;
1651         struct driver_data *drv_data;
1652         struct ssp_device *ssp;
1653         const struct lpss_config *config;
1654         int status, count;
1655         u32 tmp;
1656
1657         platform_info = dev_get_platdata(dev);
1658         if (!platform_info) {
1659                 platform_info = pxa2xx_spi_init_pdata(pdev);
1660                 if (!platform_info) {
1661                         dev_err(&pdev->dev, "missing platform data\n");
1662                         return -ENODEV;
1663                 }
1664         }
1665
1666         ssp = pxa_ssp_request(pdev->id, pdev->name);
1667         if (!ssp)
1668                 ssp = &platform_info->ssp;
1669
1670         if (!ssp->mmio_base) {
1671                 dev_err(&pdev->dev, "failed to get ssp\n");
1672                 return -ENODEV;
1673         }
1674
1675         if (platform_info->is_slave)
1676                 controller = spi_alloc_slave(dev, sizeof(struct driver_data));
1677         else
1678                 controller = spi_alloc_master(dev, sizeof(struct driver_data));
1679
1680         if (!controller) {
1681                 dev_err(&pdev->dev, "cannot alloc spi_controller\n");
1682                 pxa_ssp_free(ssp);
1683                 return -ENOMEM;
1684         }
1685         drv_data = spi_controller_get_devdata(controller);
1686         drv_data->controller = controller;
1687         drv_data->controller_info = platform_info;
1688         drv_data->pdev = pdev;
1689         drv_data->ssp = ssp;
1690
1691         controller->dev.of_node = pdev->dev.of_node;
1692         /* the spi->mode bits understood by this driver: */
1693         controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1694
1695         controller->bus_num = ssp->port_id;
1696         controller->dma_alignment = DMA_ALIGNMENT;
1697         controller->cleanup = cleanup;
1698         controller->setup = setup;
1699         controller->set_cs = pxa2xx_spi_set_cs;
1700         controller->transfer_one = pxa2xx_spi_transfer_one;
1701         controller->slave_abort = pxa2xx_spi_slave_abort;
1702         controller->handle_err = pxa2xx_spi_handle_err;
1703         controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1704         controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
1705         controller->auto_runtime_pm = true;
1706         controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
1707
1708         drv_data->ssp_type = ssp->type;
1709
1710         drv_data->ioaddr = ssp->mmio_base;
1711         drv_data->ssdr_physical = ssp->phys_base + SSDR;
1712         if (pxa25x_ssp_comp(drv_data)) {
1713                 switch (drv_data->ssp_type) {
1714                 case QUARK_X1000_SSP:
1715                         controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1716                         break;
1717                 default:
1718                         controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1719                         break;
1720                 }
1721
1722                 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1723                 drv_data->dma_cr1 = 0;
1724                 drv_data->clear_sr = SSSR_ROR;
1725                 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1726         } else {
1727                 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1728                 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1729                 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1730                 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1731                 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS
1732                                                 | SSSR_ROR | SSSR_TUR;
1733         }
1734
1735         status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1736                         drv_data);
1737         if (status < 0) {
1738                 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1739                 goto out_error_controller_alloc;
1740         }
1741
1742         /* Setup DMA if requested */
1743         if (platform_info->enable_dma) {
1744                 status = pxa2xx_spi_dma_setup(drv_data);
1745                 if (status) {
1746                         dev_warn(dev, "no DMA channels available, using PIO\n");
1747                         platform_info->enable_dma = false;
1748                 } else {
1749                         controller->can_dma = pxa2xx_spi_can_dma;
1750                         controller->max_dma_len = MAX_DMA_LEN;
1751                         controller->max_transfer_size =
1752                                 pxa2xx_spi_max_dma_transfer_size;
1753                 }
1754         }
1755
1756         /* Enable SOC clock */
1757         status = clk_prepare_enable(ssp->clk);
1758         if (status)
1759                 goto out_error_dma_irq_alloc;
1760
1761         controller->max_speed_hz = clk_get_rate(ssp->clk);
1762         /*
1763          * Set minimum speed for all other platforms than Intel Quark which is
1764          * able do under 1 Hz transfers.
1765          */
1766         if (!pxa25x_ssp_comp(drv_data))
1767                 controller->min_speed_hz =
1768                         DIV_ROUND_UP(controller->max_speed_hz, 4096);
1769         else if (!is_quark_x1000_ssp(drv_data))
1770                 controller->min_speed_hz =
1771                         DIV_ROUND_UP(controller->max_speed_hz, 512);
1772
1773         /* Load default SSP configuration */
1774         pxa2xx_spi_write(drv_data, SSCR0, 0);
1775         switch (drv_data->ssp_type) {
1776         case QUARK_X1000_SSP:
1777                 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1778                       QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1779                 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1780
1781                 /* using the Motorola SPI protocol and use 8 bit frame */
1782                 tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8);
1783                 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1784                 break;
1785         case CE4100_SSP:
1786                 tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) |
1787                       CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT);
1788                 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1789                 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1790                 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1791                 break;
1792         default:
1793
1794                 if (spi_controller_is_slave(controller)) {
1795                         tmp = SSCR1_SCFR |
1796                               SSCR1_SCLKDIR |
1797                               SSCR1_SFRMDIR |
1798                               SSCR1_RxTresh(2) |
1799                               SSCR1_TxTresh(1) |
1800                               SSCR1_SPH;
1801                 } else {
1802                         tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1803                               SSCR1_TxTresh(TX_THRESH_DFLT);
1804                 }
1805                 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1806                 tmp = SSCR0_Motorola | SSCR0_DataSize(8);
1807                 if (!spi_controller_is_slave(controller))
1808                         tmp |= SSCR0_SCR(2);
1809                 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1810                 break;
1811         }
1812
1813         if (!pxa25x_ssp_comp(drv_data))
1814                 pxa2xx_spi_write(drv_data, SSTO, 0);
1815
1816         if (!is_quark_x1000_ssp(drv_data))
1817                 pxa2xx_spi_write(drv_data, SSPSP, 0);
1818
1819         if (is_lpss_ssp(drv_data)) {
1820                 lpss_ssp_setup(drv_data);
1821                 config = lpss_get_config(drv_data);
1822                 if (config->reg_capabilities >= 0) {
1823                         tmp = __lpss_ssp_read_priv(drv_data,
1824                                                    config->reg_capabilities);
1825                         tmp &= LPSS_CAPS_CS_EN_MASK;
1826                         tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1827                         platform_info->num_chipselect = ffz(tmp);
1828                 } else if (config->cs_num) {
1829                         platform_info->num_chipselect = config->cs_num;
1830                 }
1831         }
1832         controller->num_chipselect = platform_info->num_chipselect;
1833
1834         count = gpiod_count(&pdev->dev, "cs");
1835         if (count > 0) {
1836                 int i;
1837
1838                 controller->num_chipselect = max_t(int, count,
1839                         controller->num_chipselect);
1840
1841                 drv_data->cs_gpiods = devm_kcalloc(&pdev->dev,
1842                         controller->num_chipselect, sizeof(struct gpio_desc *),
1843                         GFP_KERNEL);
1844                 if (!drv_data->cs_gpiods) {
1845                         status = -ENOMEM;
1846                         goto out_error_clock_enabled;
1847                 }
1848
1849                 for (i = 0; i < controller->num_chipselect; i++) {
1850                         struct gpio_desc *gpiod;
1851
1852                         gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
1853                         if (IS_ERR(gpiod)) {
1854                                 /* Means use native chip select */
1855                                 if (PTR_ERR(gpiod) == -ENOENT)
1856                                         continue;
1857
1858                                 status = PTR_ERR(gpiod);
1859                                 goto out_error_clock_enabled;
1860                         } else {
1861                                 drv_data->cs_gpiods[i] = gpiod;
1862                         }
1863                 }
1864         }
1865
1866         if (platform_info->is_slave) {
1867                 drv_data->gpiod_ready = devm_gpiod_get_optional(dev,
1868                                                 "ready", GPIOD_OUT_LOW);
1869                 if (IS_ERR(drv_data->gpiod_ready)) {
1870                         status = PTR_ERR(drv_data->gpiod_ready);
1871                         goto out_error_clock_enabled;
1872                 }
1873         }
1874
1875         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1876         pm_runtime_use_autosuspend(&pdev->dev);
1877         pm_runtime_set_active(&pdev->dev);
1878         pm_runtime_enable(&pdev->dev);
1879
1880         /* Register with the SPI framework */
1881         platform_set_drvdata(pdev, drv_data);
1882         status = devm_spi_register_controller(&pdev->dev, controller);
1883         if (status != 0) {
1884                 dev_err(&pdev->dev, "problem registering spi controller\n");
1885                 goto out_error_pm_runtime_enabled;
1886         }
1887
1888         return status;
1889
1890 out_error_pm_runtime_enabled:
1891         pm_runtime_put_noidle(&pdev->dev);
1892         pm_runtime_disable(&pdev->dev);
1893
1894 out_error_clock_enabled:
1895         clk_disable_unprepare(ssp->clk);
1896
1897 out_error_dma_irq_alloc:
1898         pxa2xx_spi_dma_release(drv_data);
1899         free_irq(ssp->irq, drv_data);
1900
1901 out_error_controller_alloc:
1902         spi_controller_put(controller);
1903         pxa_ssp_free(ssp);
1904         return status;
1905 }
1906
1907 static int pxa2xx_spi_remove(struct platform_device *pdev)
1908 {
1909         struct driver_data *drv_data = platform_get_drvdata(pdev);
1910         struct ssp_device *ssp;
1911
1912         if (!drv_data)
1913                 return 0;
1914         ssp = drv_data->ssp;
1915
1916         pm_runtime_get_sync(&pdev->dev);
1917
1918         /* Disable the SSP at the peripheral and SOC level */
1919         pxa2xx_spi_write(drv_data, SSCR0, 0);
1920         clk_disable_unprepare(ssp->clk);
1921
1922         /* Release DMA */
1923         if (drv_data->controller_info->enable_dma)
1924                 pxa2xx_spi_dma_release(drv_data);
1925
1926         pm_runtime_put_noidle(&pdev->dev);
1927         pm_runtime_disable(&pdev->dev);
1928
1929         /* Release IRQ */
1930         free_irq(ssp->irq, drv_data);
1931
1932         /* Release SSP */
1933         pxa_ssp_free(ssp);
1934
1935         return 0;
1936 }
1937
1938 #ifdef CONFIG_PM_SLEEP
1939 static int pxa2xx_spi_suspend(struct device *dev)
1940 {
1941         struct driver_data *drv_data = dev_get_drvdata(dev);
1942         struct ssp_device *ssp = drv_data->ssp;
1943         int status;
1944
1945         status = spi_controller_suspend(drv_data->controller);
1946         if (status != 0)
1947                 return status;
1948         pxa2xx_spi_write(drv_data, SSCR0, 0);
1949
1950         if (!pm_runtime_suspended(dev))
1951                 clk_disable_unprepare(ssp->clk);
1952
1953         return 0;
1954 }
1955
1956 static int pxa2xx_spi_resume(struct device *dev)
1957 {
1958         struct driver_data *drv_data = dev_get_drvdata(dev);
1959         struct ssp_device *ssp = drv_data->ssp;
1960         int status;
1961
1962         /* Enable the SSP clock */
1963         if (!pm_runtime_suspended(dev)) {
1964                 status = clk_prepare_enable(ssp->clk);
1965                 if (status)
1966                         return status;
1967         }
1968
1969         /* Start the queue running */
1970         return spi_controller_resume(drv_data->controller);
1971 }
1972 #endif
1973
1974 #ifdef CONFIG_PM
1975 static int pxa2xx_spi_runtime_suspend(struct device *dev)
1976 {
1977         struct driver_data *drv_data = dev_get_drvdata(dev);
1978
1979         clk_disable_unprepare(drv_data->ssp->clk);
1980         return 0;
1981 }
1982
1983 static int pxa2xx_spi_runtime_resume(struct device *dev)
1984 {
1985         struct driver_data *drv_data = dev_get_drvdata(dev);
1986         int status;
1987
1988         status = clk_prepare_enable(drv_data->ssp->clk);
1989         return status;
1990 }
1991 #endif
1992
1993 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1994         SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1995         SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1996                            pxa2xx_spi_runtime_resume, NULL)
1997 };
1998
1999 static struct platform_driver driver = {
2000         .driver = {
2001                 .name   = "pxa2xx-spi",
2002                 .pm     = &pxa2xx_spi_pm_ops,
2003                 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
2004                 .of_match_table = of_match_ptr(pxa2xx_spi_of_match),
2005         },
2006         .probe = pxa2xx_spi_probe,
2007         .remove = pxa2xx_spi_remove,
2008 };
2009
2010 static int __init pxa2xx_spi_init(void)
2011 {
2012         return platform_driver_register(&driver);
2013 }
2014 subsys_initcall(pxa2xx_spi_init);
2015
2016 static void __exit pxa2xx_spi_exit(void)
2017 {
2018         platform_driver_unregister(&driver);
2019 }
2020 module_exit(pxa2xx_spi_exit);
2021
2022 MODULE_SOFTDEP("pre: dw_dmac");