2 * Copyright (C) 2009 Samsung Electronics Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/interrupt.h>
19 #include <linux/delay.h>
20 #include <linux/clk.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/dmaengine.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/spi/spi.h>
26 #include <linux/gpio.h>
28 #include <linux/of_gpio.h>
30 #include <linux/platform_data/spi-s3c64xx.h>
32 #define MAX_SPI_PORTS 6
33 #define S3C64XX_SPI_QUIRK_POLL (1 << 0)
34 #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1)
35 #define AUTOSUSPEND_TIMEOUT 2000
37 /* Registers and bit-fields */
39 #define S3C64XX_SPI_CH_CFG 0x00
40 #define S3C64XX_SPI_CLK_CFG 0x04
41 #define S3C64XX_SPI_MODE_CFG 0x08
42 #define S3C64XX_SPI_SLAVE_SEL 0x0C
43 #define S3C64XX_SPI_INT_EN 0x10
44 #define S3C64XX_SPI_STATUS 0x14
45 #define S3C64XX_SPI_TX_DATA 0x18
46 #define S3C64XX_SPI_RX_DATA 0x1C
47 #define S3C64XX_SPI_PACKET_CNT 0x20
48 #define S3C64XX_SPI_PENDING_CLR 0x24
49 #define S3C64XX_SPI_SWAP_CFG 0x28
50 #define S3C64XX_SPI_FB_CLK 0x2C
52 #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */
53 #define S3C64XX_SPI_CH_SW_RST (1<<5)
54 #define S3C64XX_SPI_CH_SLAVE (1<<4)
55 #define S3C64XX_SPI_CPOL_L (1<<3)
56 #define S3C64XX_SPI_CPHA_B (1<<2)
57 #define S3C64XX_SPI_CH_RXCH_ON (1<<1)
58 #define S3C64XX_SPI_CH_TXCH_ON (1<<0)
60 #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
61 #define S3C64XX_SPI_CLKSEL_SRCSHFT 9
62 #define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
63 #define S3C64XX_SPI_PSR_MASK 0xff
65 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
66 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
67 #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
68 #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
69 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
70 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
71 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
72 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
73 #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
74 #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
75 #define S3C64XX_SPI_MODE_4BURST (1<<0)
77 #define S3C64XX_SPI_SLAVE_AUTO (1<<1)
78 #define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0)
79 #define S3C64XX_SPI_SLAVE_NSC_CNT_2 (2<<4)
81 #define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
82 #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
83 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
84 #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
85 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
86 #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
87 #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
89 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
90 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
91 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
92 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
93 #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
94 #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
96 #define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
98 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
99 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
100 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
101 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
102 #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
104 #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
105 #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
106 #define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
107 #define S3C64XX_SPI_SWAP_RX_EN (1<<4)
108 #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
109 #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
110 #define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
111 #define S3C64XX_SPI_SWAP_TX_EN (1<<0)
113 #define S3C64XX_SPI_FBCLK_MSK (3<<0)
115 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
116 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
117 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
118 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
119 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
122 #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
123 #define S3C64XX_SPI_TRAILCNT_OFF 19
125 #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
127 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
128 #define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
130 #define RXBUSY (1<<2)
131 #define TXBUSY (1<<3)
133 struct s3c64xx_spi_dma_data {
135 enum dma_transfer_direction direction;
139 * struct s3c64xx_spi_info - SPI Controller hardware info
140 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
141 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
142 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
143 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
144 * @clk_from_cmu: True, if the controller does not include a clock mux and
147 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
148 * differ in some aspects such as the size of the fifo and spi bus clock
149 * setup. Such differences are specified to the driver using this structure
150 * which is provided as driver data to the driver.
152 struct s3c64xx_spi_port_config {
153 int fifo_lvl_mask[MAX_SPI_PORTS];
163 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
164 * @clk: Pointer to the spi clock.
165 * @src_clk: Pointer to the clock used to generate SPI signals.
166 * @ioclk: Pointer to the i/o clock between master and slave
167 * @master: Pointer to the SPI Protocol master.
168 * @cntrlr_info: Platform specific data for the controller this driver manages.
169 * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
170 * @lock: Controller specific lock.
171 * @state: Set of FLAGS to indicate status.
172 * @rx_dmach: Controller's DMA channel for Rx.
173 * @tx_dmach: Controller's DMA channel for Tx.
174 * @sfr_start: BUS address of SPI controller regs.
175 * @regs: Pointer to ioremap'ed controller registers.
177 * @xfer_completion: To indicate completion of xfer task.
178 * @cur_mode: Stores the active configuration of the controller.
179 * @cur_bpw: Stores the active bits per word settings.
180 * @cur_speed: Stores the active xfer clock speed.
182 struct s3c64xx_spi_driver_data {
187 struct platform_device *pdev;
188 struct spi_master *master;
189 struct s3c64xx_spi_info *cntrlr_info;
190 struct spi_device *tgl_spi;
192 unsigned long sfr_start;
193 struct completion xfer_completion;
195 unsigned cur_mode, cur_bpw;
197 struct s3c64xx_spi_dma_data rx_dma;
198 struct s3c64xx_spi_dma_data tx_dma;
199 struct s3c64xx_spi_port_config *port_conf;
200 unsigned int port_id;
203 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
205 void __iomem *regs = sdd->regs;
209 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
211 val = readl(regs + S3C64XX_SPI_CH_CFG);
212 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
213 writel(val, regs + S3C64XX_SPI_CH_CFG);
215 val = readl(regs + S3C64XX_SPI_CH_CFG);
216 val |= S3C64XX_SPI_CH_SW_RST;
217 val &= ~S3C64XX_SPI_CH_HS_EN;
218 writel(val, regs + S3C64XX_SPI_CH_CFG);
221 loops = msecs_to_loops(1);
223 val = readl(regs + S3C64XX_SPI_STATUS);
224 } while (TX_FIFO_LVL(val, sdd) && loops--);
227 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
230 loops = msecs_to_loops(1);
232 val = readl(regs + S3C64XX_SPI_STATUS);
233 if (RX_FIFO_LVL(val, sdd))
234 readl(regs + S3C64XX_SPI_RX_DATA);
240 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
242 val = readl(regs + S3C64XX_SPI_CH_CFG);
243 val &= ~S3C64XX_SPI_CH_SW_RST;
244 writel(val, regs + S3C64XX_SPI_CH_CFG);
246 val = readl(regs + S3C64XX_SPI_MODE_CFG);
247 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
248 writel(val, regs + S3C64XX_SPI_MODE_CFG);
251 static void s3c64xx_spi_dmacb(void *data)
253 struct s3c64xx_spi_driver_data *sdd;
254 struct s3c64xx_spi_dma_data *dma = data;
257 if (dma->direction == DMA_DEV_TO_MEM)
258 sdd = container_of(data,
259 struct s3c64xx_spi_driver_data, rx_dma);
261 sdd = container_of(data,
262 struct s3c64xx_spi_driver_data, tx_dma);
264 spin_lock_irqsave(&sdd->lock, flags);
266 if (dma->direction == DMA_DEV_TO_MEM) {
267 sdd->state &= ~RXBUSY;
268 if (!(sdd->state & TXBUSY))
269 complete(&sdd->xfer_completion);
271 sdd->state &= ~TXBUSY;
272 if (!(sdd->state & RXBUSY))
273 complete(&sdd->xfer_completion);
276 spin_unlock_irqrestore(&sdd->lock, flags);
279 static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
280 struct sg_table *sgt)
282 struct s3c64xx_spi_driver_data *sdd;
283 struct dma_slave_config config;
284 struct dma_async_tx_descriptor *desc;
286 memset(&config, 0, sizeof(config));
288 if (dma->direction == DMA_DEV_TO_MEM) {
289 sdd = container_of((void *)dma,
290 struct s3c64xx_spi_driver_data, rx_dma);
291 config.direction = dma->direction;
292 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
293 config.src_addr_width = sdd->cur_bpw / 8;
294 config.src_maxburst = 1;
295 dmaengine_slave_config(dma->ch, &config);
297 sdd = container_of((void *)dma,
298 struct s3c64xx_spi_driver_data, tx_dma);
299 config.direction = dma->direction;
300 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
301 config.dst_addr_width = sdd->cur_bpw / 8;
302 config.dst_maxburst = 1;
303 dmaengine_slave_config(dma->ch, &config);
306 desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
307 dma->direction, DMA_PREP_INTERRUPT);
309 desc->callback = s3c64xx_spi_dmacb;
310 desc->callback_param = dma;
312 dmaengine_submit(desc);
313 dma_async_issue_pending(dma->ch);
316 static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable)
318 struct s3c64xx_spi_driver_data *sdd =
319 spi_master_get_devdata(spi->master);
321 if (sdd->cntrlr_info->no_cs)
325 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) {
326 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
328 u32 ssel = readl(sdd->regs + S3C64XX_SPI_SLAVE_SEL);
330 ssel |= (S3C64XX_SPI_SLAVE_AUTO |
331 S3C64XX_SPI_SLAVE_NSC_CNT_2);
332 writel(ssel, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
335 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
336 writel(S3C64XX_SPI_SLAVE_SIG_INACT,
337 sdd->regs + S3C64XX_SPI_SLAVE_SEL);
341 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
343 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
344 struct device *dev = &sdd->pdev->dev;
349 /* Acquire DMA channels */
350 sdd->rx_dma.ch = dma_request_slave_channel(dev, "rx");
351 if (!sdd->rx_dma.ch) {
352 dev_err(dev, "Failed to get RX DMA channel\n");
355 spi->dma_rx = sdd->rx_dma.ch;
357 sdd->tx_dma.ch = dma_request_slave_channel(dev, "tx");
358 if (!sdd->tx_dma.ch) {
359 dev_err(dev, "Failed to get TX DMA channel\n");
360 dma_release_channel(sdd->rx_dma.ch);
363 spi->dma_tx = sdd->tx_dma.ch;
368 static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
370 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
372 /* Free DMA channels */
373 if (!is_polling(sdd)) {
374 dma_release_channel(sdd->rx_dma.ch);
375 dma_release_channel(sdd->tx_dma.ch);
381 static bool s3c64xx_spi_can_dma(struct spi_master *master,
382 struct spi_device *spi,
383 struct spi_transfer *xfer)
385 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
387 return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1;
390 static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
391 struct spi_device *spi,
392 struct spi_transfer *xfer, int dma_mode)
394 void __iomem *regs = sdd->regs;
397 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
398 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
400 chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
401 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
404 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
406 /* Always shift in data in FIFO, even if xfer is Tx only,
407 * this helps setting PCKT_CNT value for generating clocks
410 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
411 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
412 | S3C64XX_SPI_PACKET_CNT_EN,
413 regs + S3C64XX_SPI_PACKET_CNT);
416 if (xfer->tx_buf != NULL) {
417 sdd->state |= TXBUSY;
418 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
420 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
421 prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
423 switch (sdd->cur_bpw) {
425 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
426 xfer->tx_buf, xfer->len / 4);
429 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
430 xfer->tx_buf, xfer->len / 2);
433 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
434 xfer->tx_buf, xfer->len);
440 if (xfer->rx_buf != NULL) {
441 sdd->state |= RXBUSY;
443 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
444 && !(sdd->cur_mode & SPI_CPHA))
445 chcfg |= S3C64XX_SPI_CH_HS_EN;
448 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
449 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
450 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
451 | S3C64XX_SPI_PACKET_CNT_EN,
452 regs + S3C64XX_SPI_PACKET_CNT);
453 prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
457 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
458 writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
461 static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
464 void __iomem *regs = sdd->regs;
465 unsigned long val = 1;
468 /* max fifo depth available */
469 u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
472 val = msecs_to_loops(timeout_ms);
475 status = readl(regs + S3C64XX_SPI_STATUS);
476 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
478 /* return the actual received data length */
479 return RX_FIFO_LVL(status, sdd);
482 static int wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
483 struct spi_transfer *xfer)
485 void __iomem *regs = sdd->regs;
490 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
491 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
492 ms += 10; /* some tolerance */
494 val = msecs_to_jiffies(ms) + 10;
495 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
498 * If the previous xfer was completed within timeout, then
499 * proceed further else return -EIO.
500 * DmaTx returns after simply writing data in the FIFO,
501 * w/o waiting for real transmission on the bus to finish.
502 * DmaRx returns only after Dma read data from FIFO which
503 * needs bus transmission to finish, so we don't worry if
504 * Xfer involved Rx(with or without Tx).
506 if (val && !xfer->rx_buf) {
507 val = msecs_to_loops(10);
508 status = readl(regs + S3C64XX_SPI_STATUS);
509 while ((TX_FIFO_LVL(status, sdd)
510 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
513 status = readl(regs + S3C64XX_SPI_STATUS);
518 /* If timed out while checking rx/tx status return error */
525 static int wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
526 struct spi_transfer *xfer)
528 void __iomem *regs = sdd->regs;
536 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
537 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
538 ms += 10; /* some tolerance */
540 val = msecs_to_loops(ms);
542 status = readl(regs + S3C64XX_SPI_STATUS);
543 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
546 /* If it was only Tx */
548 sdd->state &= ~TXBUSY;
553 * If the receive length is bigger than the controller fifo
554 * size, calculate the loops and read the fifo as many times.
555 * loops = length / max fifo size (calculated by using the
557 * For any size less than the fifo size the below code is
558 * executed atleast once.
560 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
563 /* wait for data to be received in the fifo */
564 cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
567 switch (sdd->cur_bpw) {
569 ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
573 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
577 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
584 sdd->state &= ~RXBUSY;
589 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
591 void __iomem *regs = sdd->regs;
595 if (!sdd->port_conf->clk_from_cmu) {
596 val = readl(regs + S3C64XX_SPI_CLK_CFG);
597 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
598 writel(val, regs + S3C64XX_SPI_CLK_CFG);
601 /* Set Polarity and Phase */
602 val = readl(regs + S3C64XX_SPI_CH_CFG);
603 val &= ~(S3C64XX_SPI_CH_SLAVE |
607 if (sdd->cur_mode & SPI_CPOL)
608 val |= S3C64XX_SPI_CPOL_L;
610 if (sdd->cur_mode & SPI_CPHA)
611 val |= S3C64XX_SPI_CPHA_B;
613 writel(val, regs + S3C64XX_SPI_CH_CFG);
615 /* Set Channel & DMA Mode */
616 val = readl(regs + S3C64XX_SPI_MODE_CFG);
617 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
618 | S3C64XX_SPI_MODE_CH_TSZ_MASK);
620 switch (sdd->cur_bpw) {
622 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
623 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
626 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
627 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
630 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
631 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
635 writel(val, regs + S3C64XX_SPI_MODE_CFG);
637 if (sdd->port_conf->clk_from_cmu) {
638 /* The src_clk clock is divided internally by 2 */
639 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
641 /* Configure Clock */
642 val = readl(regs + S3C64XX_SPI_CLK_CFG);
643 val &= ~S3C64XX_SPI_PSR_MASK;
644 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
645 & S3C64XX_SPI_PSR_MASK);
646 writel(val, regs + S3C64XX_SPI_CLK_CFG);
649 val = readl(regs + S3C64XX_SPI_CLK_CFG);
650 val |= S3C64XX_SPI_ENCLK_ENABLE;
651 writel(val, regs + S3C64XX_SPI_CLK_CFG);
655 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
657 static int s3c64xx_spi_prepare_message(struct spi_master *master,
658 struct spi_message *msg)
660 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
661 struct spi_device *spi = msg->spi;
662 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
664 /* Configure feedback delay */
665 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
670 static int s3c64xx_spi_transfer_one(struct spi_master *master,
671 struct spi_device *spi,
672 struct spi_transfer *xfer)
674 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
681 reinit_completion(&sdd->xfer_completion);
683 /* Only BPW and Speed may change across transfers */
684 bpw = xfer->bits_per_word;
685 speed = xfer->speed_hz;
687 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
689 sdd->cur_speed = speed;
690 sdd->cur_mode = spi->mode;
691 s3c64xx_spi_config(sdd);
694 /* Polling method for xfers not bigger than FIFO capacity */
696 if (!is_polling(sdd) &&
697 (sdd->rx_dma.ch && sdd->tx_dma.ch &&
698 (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1))))
701 spin_lock_irqsave(&sdd->lock, flags);
703 /* Pending only which is to be done */
704 sdd->state &= ~RXBUSY;
705 sdd->state &= ~TXBUSY;
707 enable_datapath(sdd, spi, xfer, use_dma);
709 /* Start the signals */
710 s3c64xx_spi_set_cs(spi, true);
712 spin_unlock_irqrestore(&sdd->lock, flags);
715 status = wait_for_dma(sdd, xfer);
717 status = wait_for_pio(sdd, xfer);
720 dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
721 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
722 (sdd->state & RXBUSY) ? 'f' : 'p',
723 (sdd->state & TXBUSY) ? 'f' : 'p',
727 if (xfer->tx_buf != NULL
728 && (sdd->state & TXBUSY))
729 dmaengine_terminate_all(sdd->tx_dma.ch);
730 if (xfer->rx_buf != NULL
731 && (sdd->state & RXBUSY))
732 dmaengine_terminate_all(sdd->rx_dma.ch);
741 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
742 struct spi_device *spi)
744 struct s3c64xx_spi_csinfo *cs;
745 struct device_node *slave_np, *data_np = NULL;
748 slave_np = spi->dev.of_node;
750 dev_err(&spi->dev, "device node not found\n");
751 return ERR_PTR(-EINVAL);
754 data_np = of_get_child_by_name(slave_np, "controller-data");
756 dev_err(&spi->dev, "child node 'controller-data' not found\n");
757 return ERR_PTR(-EINVAL);
760 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
762 of_node_put(data_np);
763 return ERR_PTR(-ENOMEM);
766 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
767 cs->fb_delay = fb_delay;
768 of_node_put(data_np);
773 * Here we only check the validity of requested configuration
774 * and save the configuration in a local data-structure.
775 * The controller is actually configured only just before we
776 * get a message to transfer.
778 static int s3c64xx_spi_setup(struct spi_device *spi)
780 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
781 struct s3c64xx_spi_driver_data *sdd;
782 struct s3c64xx_spi_info *sci;
785 sdd = spi_master_get_devdata(spi->master);
786 if (spi->dev.of_node) {
787 cs = s3c64xx_get_slave_ctrldata(spi);
788 spi->controller_data = cs;
790 /* On non-DT platforms the SPI core will set spi->cs_gpio
791 * to -ENOENT. The GPIO pin used to drive the chip select
792 * is defined by using platform data so spi->cs_gpio value
793 * has to be override to have the proper GPIO pin number.
795 spi->cs_gpio = cs->line;
798 if (IS_ERR_OR_NULL(cs)) {
799 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
803 if (!spi_get_ctldata(spi)) {
804 if (gpio_is_valid(spi->cs_gpio)) {
805 err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH,
806 dev_name(&spi->dev));
809 "Failed to get /CS gpio [%d]: %d\n",
815 spi_set_ctldata(spi, cs);
818 sci = sdd->cntrlr_info;
820 pm_runtime_get_sync(&sdd->pdev->dev);
822 /* Check if we can provide the requested rate */
823 if (!sdd->port_conf->clk_from_cmu) {
827 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
829 if (spi->max_speed_hz > speed)
830 spi->max_speed_hz = speed;
832 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
833 psr &= S3C64XX_SPI_PSR_MASK;
834 if (psr == S3C64XX_SPI_PSR_MASK)
837 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
838 if (spi->max_speed_hz < speed) {
839 if (psr+1 < S3C64XX_SPI_PSR_MASK) {
847 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
848 if (spi->max_speed_hz >= speed) {
849 spi->max_speed_hz = speed;
851 dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
858 pm_runtime_mark_last_busy(&sdd->pdev->dev);
859 pm_runtime_put_autosuspend(&sdd->pdev->dev);
860 s3c64xx_spi_set_cs(spi, false);
865 pm_runtime_mark_last_busy(&sdd->pdev->dev);
866 pm_runtime_put_autosuspend(&sdd->pdev->dev);
867 /* setup() returns with device de-selected */
868 s3c64xx_spi_set_cs(spi, false);
870 if (gpio_is_valid(spi->cs_gpio))
871 gpio_free(spi->cs_gpio);
872 spi_set_ctldata(spi, NULL);
875 if (spi->dev.of_node)
881 static void s3c64xx_spi_cleanup(struct spi_device *spi)
883 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
885 if (gpio_is_valid(spi->cs_gpio)) {
886 gpio_free(spi->cs_gpio);
887 if (spi->dev.of_node)
890 /* On non-DT platforms, the SPI core sets
891 * spi->cs_gpio to -ENOENT and .setup()
892 * overrides it with the GPIO pin value
893 * passed using platform data.
895 spi->cs_gpio = -ENOENT;
899 spi_set_ctldata(spi, NULL);
902 static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
904 struct s3c64xx_spi_driver_data *sdd = data;
905 struct spi_master *spi = sdd->master;
906 unsigned int val, clr = 0;
908 val = readl(sdd->regs + S3C64XX_SPI_STATUS);
910 if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
911 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
912 dev_err(&spi->dev, "RX overrun\n");
914 if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
915 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
916 dev_err(&spi->dev, "RX underrun\n");
918 if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
919 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
920 dev_err(&spi->dev, "TX overrun\n");
922 if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
923 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
924 dev_err(&spi->dev, "TX underrun\n");
927 /* Clear the pending irq by setting and then clearing it */
928 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
929 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
934 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
936 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
937 void __iomem *regs = sdd->regs;
943 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
944 else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
945 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
947 /* Disable Interrupts - we use Polling if not DMA mode */
948 writel(0, regs + S3C64XX_SPI_INT_EN);
950 if (!sdd->port_conf->clk_from_cmu)
951 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
952 regs + S3C64XX_SPI_CLK_CFG);
953 writel(0, regs + S3C64XX_SPI_MODE_CFG);
954 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
956 /* Clear any irq pending bits, should set and clear the bits */
957 val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
958 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
959 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
960 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
961 writel(val, regs + S3C64XX_SPI_PENDING_CLR);
962 writel(0, regs + S3C64XX_SPI_PENDING_CLR);
964 writel(0, regs + S3C64XX_SPI_SWAP_CFG);
966 val = readl(regs + S3C64XX_SPI_MODE_CFG);
967 val &= ~S3C64XX_SPI_MODE_4BURST;
968 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
969 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
970 writel(val, regs + S3C64XX_SPI_MODE_CFG);
976 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
978 struct s3c64xx_spi_info *sci;
981 sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
983 return ERR_PTR(-ENOMEM);
985 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
986 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
989 sci->src_clk_nr = temp;
992 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
993 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
999 sci->no_cs = of_property_read_bool(dev->of_node, "broken-cs");
1004 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1006 return dev_get_platdata(dev);
1010 static const struct of_device_id s3c64xx_spi_dt_match[];
1012 static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1013 struct platform_device *pdev)
1016 if (pdev->dev.of_node) {
1017 const struct of_device_id *match;
1018 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1019 return (struct s3c64xx_spi_port_config *)match->data;
1022 return (struct s3c64xx_spi_port_config *)
1023 platform_get_device_id(pdev)->driver_data;
1026 static int s3c64xx_spi_probe(struct platform_device *pdev)
1028 struct resource *mem_res;
1029 struct s3c64xx_spi_driver_data *sdd;
1030 struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
1031 struct spi_master *master;
1035 if (!sci && pdev->dev.of_node) {
1036 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1038 return PTR_ERR(sci);
1042 dev_err(&pdev->dev, "platform_data missing!\n");
1046 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1047 if (mem_res == NULL) {
1048 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1052 irq = platform_get_irq(pdev, 0);
1054 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1058 master = spi_alloc_master(&pdev->dev,
1059 sizeof(struct s3c64xx_spi_driver_data));
1060 if (master == NULL) {
1061 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1065 platform_set_drvdata(pdev, master);
1067 sdd = spi_master_get_devdata(master);
1068 sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1069 sdd->master = master;
1070 sdd->cntrlr_info = sci;
1072 sdd->sfr_start = mem_res->start;
1073 if (pdev->dev.of_node) {
1074 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1076 dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1078 goto err_deref_master;
1082 sdd->port_id = pdev->id;
1087 sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1088 sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1090 master->dev.of_node = pdev->dev.of_node;
1091 master->bus_num = sdd->port_id;
1092 master->setup = s3c64xx_spi_setup;
1093 master->cleanup = s3c64xx_spi_cleanup;
1094 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1095 master->prepare_message = s3c64xx_spi_prepare_message;
1096 master->transfer_one = s3c64xx_spi_transfer_one;
1097 master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
1098 master->num_chipselect = sci->num_cs;
1099 master->dma_alignment = 8;
1100 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1102 /* the spi->mode bits understood by this driver: */
1103 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1104 master->auto_runtime_pm = true;
1105 if (!is_polling(sdd))
1106 master->can_dma = s3c64xx_spi_can_dma;
1108 sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1109 if (IS_ERR(sdd->regs)) {
1110 ret = PTR_ERR(sdd->regs);
1111 goto err_deref_master;
1114 if (sci->cfg_gpio && sci->cfg_gpio()) {
1115 dev_err(&pdev->dev, "Unable to config gpio\n");
1117 goto err_deref_master;
1121 sdd->clk = devm_clk_get(&pdev->dev, "spi");
1122 if (IS_ERR(sdd->clk)) {
1123 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1124 ret = PTR_ERR(sdd->clk);
1125 goto err_deref_master;
1128 ret = clk_prepare_enable(sdd->clk);
1130 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1131 goto err_deref_master;
1134 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1135 sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
1136 if (IS_ERR(sdd->src_clk)) {
1138 "Unable to acquire clock '%s'\n", clk_name);
1139 ret = PTR_ERR(sdd->src_clk);
1140 goto err_disable_clk;
1143 ret = clk_prepare_enable(sdd->src_clk);
1145 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1146 goto err_disable_clk;
1149 if (sdd->port_conf->clk_ioclk) {
1150 sdd->ioclk = devm_clk_get(&pdev->dev, "spi_ioclk");
1151 if (IS_ERR(sdd->ioclk)) {
1152 dev_err(&pdev->dev, "Unable to acquire 'ioclk'\n");
1153 ret = PTR_ERR(sdd->ioclk);
1154 goto err_disable_src_clk;
1157 ret = clk_prepare_enable(sdd->ioclk);
1159 dev_err(&pdev->dev, "Couldn't enable clock 'ioclk'\n");
1160 goto err_disable_src_clk;
1164 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1165 pm_runtime_use_autosuspend(&pdev->dev);
1166 pm_runtime_set_active(&pdev->dev);
1167 pm_runtime_enable(&pdev->dev);
1168 pm_runtime_get_sync(&pdev->dev);
1170 /* Setup Deufult Mode */
1171 s3c64xx_spi_hwinit(sdd, sdd->port_id);
1173 spin_lock_init(&sdd->lock);
1174 init_completion(&sdd->xfer_completion);
1176 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1177 "spi-s3c64xx", sdd);
1179 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1184 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1185 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1186 sdd->regs + S3C64XX_SPI_INT_EN);
1188 ret = devm_spi_register_master(&pdev->dev, master);
1190 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret);
1194 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1195 sdd->port_id, master->num_chipselect);
1196 dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n",
1197 mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1);
1199 pm_runtime_mark_last_busy(&pdev->dev);
1200 pm_runtime_put_autosuspend(&pdev->dev);
1205 pm_runtime_put_noidle(&pdev->dev);
1206 pm_runtime_disable(&pdev->dev);
1207 pm_runtime_set_suspended(&pdev->dev);
1209 clk_disable_unprepare(sdd->ioclk);
1210 err_disable_src_clk:
1211 clk_disable_unprepare(sdd->src_clk);
1213 clk_disable_unprepare(sdd->clk);
1215 spi_master_put(master);
1220 static int s3c64xx_spi_remove(struct platform_device *pdev)
1222 struct spi_master *master = platform_get_drvdata(pdev);
1223 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1225 pm_runtime_get_sync(&pdev->dev);
1227 writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1229 clk_disable_unprepare(sdd->ioclk);
1231 clk_disable_unprepare(sdd->src_clk);
1233 clk_disable_unprepare(sdd->clk);
1235 pm_runtime_put_noidle(&pdev->dev);
1236 pm_runtime_disable(&pdev->dev);
1237 pm_runtime_set_suspended(&pdev->dev);
1242 #ifdef CONFIG_PM_SLEEP
1243 static int s3c64xx_spi_suspend(struct device *dev)
1245 struct spi_master *master = dev_get_drvdata(dev);
1246 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1248 int ret = spi_master_suspend(master);
1252 ret = pm_runtime_force_suspend(dev);
1256 sdd->cur_speed = 0; /* Output Clock is stopped */
1261 static int s3c64xx_spi_resume(struct device *dev)
1263 struct spi_master *master = dev_get_drvdata(dev);
1264 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1265 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1271 ret = pm_runtime_force_resume(dev);
1275 s3c64xx_spi_hwinit(sdd, sdd->port_id);
1277 return spi_master_resume(master);
1279 #endif /* CONFIG_PM_SLEEP */
1282 static int s3c64xx_spi_runtime_suspend(struct device *dev)
1284 struct spi_master *master = dev_get_drvdata(dev);
1285 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1287 clk_disable_unprepare(sdd->clk);
1288 clk_disable_unprepare(sdd->src_clk);
1289 clk_disable_unprepare(sdd->ioclk);
1294 static int s3c64xx_spi_runtime_resume(struct device *dev)
1296 struct spi_master *master = dev_get_drvdata(dev);
1297 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1300 if (sdd->port_conf->clk_ioclk) {
1301 ret = clk_prepare_enable(sdd->ioclk);
1306 ret = clk_prepare_enable(sdd->src_clk);
1308 goto err_disable_ioclk;
1310 ret = clk_prepare_enable(sdd->clk);
1312 goto err_disable_src_clk;
1316 err_disable_src_clk:
1317 clk_disable_unprepare(sdd->src_clk);
1319 clk_disable_unprepare(sdd->ioclk);
1323 #endif /* CONFIG_PM */
1325 static const struct dev_pm_ops s3c64xx_spi_pm = {
1326 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1327 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1328 s3c64xx_spi_runtime_resume, NULL)
1331 static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1332 .fifo_lvl_mask = { 0x7f },
1333 .rx_lvl_offset = 13,
1338 static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1339 .fifo_lvl_mask = { 0x7f, 0x7F },
1340 .rx_lvl_offset = 13,
1344 static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1345 .fifo_lvl_mask = { 0x1ff, 0x7F },
1346 .rx_lvl_offset = 15,
1351 static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1352 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F },
1353 .rx_lvl_offset = 15,
1356 .clk_from_cmu = true,
1359 static struct s3c64xx_spi_port_config exynos5440_spi_port_config = {
1360 .fifo_lvl_mask = { 0x1ff },
1361 .rx_lvl_offset = 15,
1364 .clk_from_cmu = true,
1365 .quirks = S3C64XX_SPI_QUIRK_POLL,
1368 static struct s3c64xx_spi_port_config exynos7_spi_port_config = {
1369 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
1370 .rx_lvl_offset = 15,
1373 .clk_from_cmu = true,
1374 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1377 static struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
1378 .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff},
1379 .rx_lvl_offset = 15,
1382 .clk_from_cmu = true,
1384 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1387 static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
1389 .name = "s3c2443-spi",
1390 .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config,
1392 .name = "s3c6410-spi",
1393 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config,
1398 static const struct of_device_id s3c64xx_spi_dt_match[] = {
1399 { .compatible = "samsung,s3c2443-spi",
1400 .data = (void *)&s3c2443_spi_port_config,
1402 { .compatible = "samsung,s3c6410-spi",
1403 .data = (void *)&s3c6410_spi_port_config,
1405 { .compatible = "samsung,s5pv210-spi",
1406 .data = (void *)&s5pv210_spi_port_config,
1408 { .compatible = "samsung,exynos4210-spi",
1409 .data = (void *)&exynos4_spi_port_config,
1411 { .compatible = "samsung,exynos5440-spi",
1412 .data = (void *)&exynos5440_spi_port_config,
1414 { .compatible = "samsung,exynos7-spi",
1415 .data = (void *)&exynos7_spi_port_config,
1417 { .compatible = "samsung,exynos5433-spi",
1418 .data = (void *)&exynos5433_spi_port_config,
1422 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1424 static struct platform_driver s3c64xx_spi_driver = {
1426 .name = "s3c64xx-spi",
1427 .pm = &s3c64xx_spi_pm,
1428 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1430 .probe = s3c64xx_spi_probe,
1431 .remove = s3c64xx_spi_remove,
1432 .id_table = s3c64xx_spi_driver_ids,
1434 MODULE_ALIAS("platform:s3c64xx-spi");
1436 module_platform_driver(s3c64xx_spi_driver);
1438 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1439 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1440 MODULE_LICENSE("GPL");