1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH MSIOF SPI Controller Interface
5 * Copyright (c) 2009 Magnus Damm
6 * Copyright (C) 2014 Renesas Electronics Corporation
7 * Copyright (C) 2014-2017 Glider bvba
10 #include <linux/bitmap.h>
11 #include <linux/clk.h>
12 #include <linux/completion.h>
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/dmaengine.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
24 #include <linux/of_device.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/sh_dma.h>
29 #include <linux/spi/sh_msiof.h>
30 #include <linux/spi/spi.h>
32 #include <asm/unaligned.h>
34 struct sh_msiof_chipdata {
35 u32 bits_per_word_mask;
42 struct sh_msiof_spi_priv {
43 struct spi_controller *ctlr;
44 void __iomem *mapbase;
46 struct platform_device *pdev;
47 struct sh_msiof_spi_info *info;
48 struct completion done;
49 struct completion done_txdma;
50 unsigned int tx_fifo_size;
51 unsigned int rx_fifo_size;
52 unsigned int min_div_pow;
55 dma_addr_t tx_dma_addr;
56 dma_addr_t rx_dma_addr;
57 unsigned short unused_ss;
58 bool native_cs_inited;
63 #define MAX_SS 3 /* Maximum number of native chip selects */
65 #define TMDR1 0x00 /* Transmit Mode Register 1 */
66 #define TMDR2 0x04 /* Transmit Mode Register 2 */
67 #define TMDR3 0x08 /* Transmit Mode Register 3 */
68 #define RMDR1 0x10 /* Receive Mode Register 1 */
69 #define RMDR2 0x14 /* Receive Mode Register 2 */
70 #define RMDR3 0x18 /* Receive Mode Register 3 */
71 #define TSCR 0x20 /* Transmit Clock Select Register */
72 #define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
73 #define CTR 0x28 /* Control Register */
74 #define FCTR 0x30 /* FIFO Control Register */
75 #define STR 0x40 /* Status Register */
76 #define IER 0x44 /* Interrupt Enable Register */
77 #define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
78 #define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
79 #define TFDR 0x50 /* Transmit FIFO Data Register */
80 #define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
81 #define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
82 #define RFDR 0x60 /* Receive FIFO Data Register */
85 #define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */
86 #define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */
87 #define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */
88 #define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */
89 #define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
90 #define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
91 #define MDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */
92 #define MDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */
93 #define MDR1_FLD_MASK 0x0000000c /* Frame Sync Signal Interval (0-3) */
94 #define MDR1_FLD_SHIFT 2
95 #define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */
97 #define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */
98 #define TMDR1_SYNCCH_MASK 0xc000000 /* Synchronization Signal Channel Select */
99 #define TMDR1_SYNCCH_SHIFT 26 /* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */
101 /* TMDR2 and RMDR2 */
102 #define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */
103 #define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
104 #define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */
107 #define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */
108 #define SCR_BRPS(i) (((i) - 1) << 8)
109 #define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */
110 #define SCR_BRDV_DIV_2 0x0000
111 #define SCR_BRDV_DIV_4 0x0001
112 #define SCR_BRDV_DIV_8 0x0002
113 #define SCR_BRDV_DIV_16 0x0003
114 #define SCR_BRDV_DIV_32 0x0004
115 #define SCR_BRDV_DIV_1 0x0007
118 #define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */
119 #define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */
120 #define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */
121 #define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */
122 #define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */
123 #define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */
124 #define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */
125 #define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */
126 #define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */
127 #define CTR_TXDIZ_LOW 0x00000000 /* 0 */
128 #define CTR_TXDIZ_HIGH 0x00400000 /* 1 */
129 #define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */
130 #define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */
131 #define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */
132 #define CTR_TXE 0x00000200 /* Transmit Enable */
133 #define CTR_RXE 0x00000100 /* Receive Enable */
136 #define FCTR_TFWM_MASK 0xe0000000 /* Transmit FIFO Watermark */
137 #define FCTR_TFWM_64 0x00000000 /* Transfer Request when 64 empty stages */
138 #define FCTR_TFWM_32 0x20000000 /* Transfer Request when 32 empty stages */
139 #define FCTR_TFWM_24 0x40000000 /* Transfer Request when 24 empty stages */
140 #define FCTR_TFWM_16 0x60000000 /* Transfer Request when 16 empty stages */
141 #define FCTR_TFWM_12 0x80000000 /* Transfer Request when 12 empty stages */
142 #define FCTR_TFWM_8 0xa0000000 /* Transfer Request when 8 empty stages */
143 #define FCTR_TFWM_4 0xc0000000 /* Transfer Request when 4 empty stages */
144 #define FCTR_TFWM_1 0xe0000000 /* Transfer Request when 1 empty stage */
145 #define FCTR_TFUA_MASK 0x07f00000 /* Transmit FIFO Usable Area */
146 #define FCTR_TFUA_SHIFT 20
147 #define FCTR_TFUA(i) ((i) << FCTR_TFUA_SHIFT)
148 #define FCTR_RFWM_MASK 0x0000e000 /* Receive FIFO Watermark */
149 #define FCTR_RFWM_1 0x00000000 /* Transfer Request when 1 valid stages */
150 #define FCTR_RFWM_4 0x00002000 /* Transfer Request when 4 valid stages */
151 #define FCTR_RFWM_8 0x00004000 /* Transfer Request when 8 valid stages */
152 #define FCTR_RFWM_16 0x00006000 /* Transfer Request when 16 valid stages */
153 #define FCTR_RFWM_32 0x00008000 /* Transfer Request when 32 valid stages */
154 #define FCTR_RFWM_64 0x0000a000 /* Transfer Request when 64 valid stages */
155 #define FCTR_RFWM_128 0x0000c000 /* Transfer Request when 128 valid stages */
156 #define FCTR_RFWM_256 0x0000e000 /* Transfer Request when 256 valid stages */
157 #define FCTR_RFUA_MASK 0x00001ff0 /* Receive FIFO Usable Area (0x40 = full) */
158 #define FCTR_RFUA_SHIFT 4
159 #define FCTR_RFUA(i) ((i) << FCTR_RFUA_SHIFT)
162 #define STR_TFEMP 0x20000000 /* Transmit FIFO Empty */
163 #define STR_TDREQ 0x10000000 /* Transmit Data Transfer Request */
164 #define STR_TEOF 0x00800000 /* Frame Transmission End */
165 #define STR_TFSERR 0x00200000 /* Transmit Frame Synchronization Error */
166 #define STR_TFOVF 0x00100000 /* Transmit FIFO Overflow */
167 #define STR_TFUDF 0x00080000 /* Transmit FIFO Underflow */
168 #define STR_RFFUL 0x00002000 /* Receive FIFO Full */
169 #define STR_RDREQ 0x00001000 /* Receive Data Transfer Request */
170 #define STR_REOF 0x00000080 /* Frame Reception End */
171 #define STR_RFSERR 0x00000020 /* Receive Frame Synchronization Error */
172 #define STR_RFUDF 0x00000010 /* Receive FIFO Underflow */
173 #define STR_RFOVF 0x00000008 /* Receive FIFO Overflow */
176 #define IER_TDMAE 0x80000000 /* Transmit Data DMA Transfer Req. Enable */
177 #define IER_TFEMPE 0x20000000 /* Transmit FIFO Empty Enable */
178 #define IER_TDREQE 0x10000000 /* Transmit Data Transfer Request Enable */
179 #define IER_TEOFE 0x00800000 /* Frame Transmission End Enable */
180 #define IER_TFSERRE 0x00200000 /* Transmit Frame Sync Error Enable */
181 #define IER_TFOVFE 0x00100000 /* Transmit FIFO Overflow Enable */
182 #define IER_TFUDFE 0x00080000 /* Transmit FIFO Underflow Enable */
183 #define IER_RDMAE 0x00008000 /* Receive Data DMA Transfer Req. Enable */
184 #define IER_RFFULE 0x00002000 /* Receive FIFO Full Enable */
185 #define IER_RDREQE 0x00001000 /* Receive Data Transfer Request Enable */
186 #define IER_REOFE 0x00000080 /* Frame Reception End Enable */
187 #define IER_RFSERRE 0x00000020 /* Receive Frame Sync Error Enable */
188 #define IER_RFUDFE 0x00000010 /* Receive FIFO Underflow Enable */
189 #define IER_RFOVFE 0x00000008 /* Receive FIFO Overflow Enable */
192 static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
197 return ioread16(p->mapbase + reg_offs);
199 return ioread32(p->mapbase + reg_offs);
203 static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
209 iowrite16(value, p->mapbase + reg_offs);
212 iowrite32(value, p->mapbase + reg_offs);
217 static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
220 u32 mask = clr | set;
224 data = sh_msiof_read(p, CTR);
227 sh_msiof_write(p, CTR, data);
229 for (k = 100; k > 0; k--) {
230 if ((sh_msiof_read(p, CTR) & mask) == set)
236 return k > 0 ? 0 : -ETIMEDOUT;
239 static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
241 struct sh_msiof_spi_priv *p = data;
243 /* just disable the interrupt and wake up */
244 sh_msiof_write(p, IER, 0);
250 static const u32 sh_msiof_spi_div_array[] = {
251 SCR_BRDV_DIV_1, SCR_BRDV_DIV_2, SCR_BRDV_DIV_4,
252 SCR_BRDV_DIV_8, SCR_BRDV_DIV_16, SCR_BRDV_DIV_32,
255 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
256 unsigned long parent_rate, u32 spi_hz)
260 unsigned int div_pow = p->min_div_pow;
262 if (!spi_hz || !parent_rate) {
263 WARN(1, "Invalid clock rate parameters %lu and %u\n",
264 parent_rate, spi_hz);
268 div = DIV_ROUND_UP(parent_rate, spi_hz);
270 /* SCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */
271 if (!div_pow && div <= 32 && div > 2)
275 brps = (div + 1) >> div_pow;
279 for (; brps > 32; div_pow++)
280 brps = (brps + 1) >> 1;
282 /* Set transfer rate composite divisor to 2^5 * 32 = 1024 */
283 dev_err(&p->pdev->dev,
284 "Requested SPI transfer rate %d is too low\n", spi_hz);
289 scr = sh_msiof_spi_div_array[div_pow] | SCR_BRPS(brps);
290 sh_msiof_write(p, TSCR, scr);
291 if (!(p->ctlr->flags & SPI_CONTROLLER_MUST_TX))
292 sh_msiof_write(p, RSCR, scr);
295 static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl)
298 * DTDL/SYNCDL bit : p->info->dtdl or p->info->syncdl
302 * b'011 (SYNCDL only) : 300
306 if (dtdl_or_syncdl % 100)
307 return dtdl_or_syncdl / 100 + 5;
309 return dtdl_or_syncdl / 100;
312 static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p)
319 /* check if DTDL and SYNCDL is allowed value */
320 if (p->info->dtdl > 200 || p->info->syncdl > 300) {
321 dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n");
325 /* check if the sum of DTDL and SYNCDL becomes an integer value */
326 if ((p->info->dtdl + p->info->syncdl) % 100) {
327 dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n");
331 val = sh_msiof_get_delay_bit(p->info->dtdl) << MDR1_DTDL_SHIFT;
332 val |= sh_msiof_get_delay_bit(p->info->syncdl) << MDR1_SYNCDL_SHIFT;
337 static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, u32 ss,
339 u32 tx_hi_z, u32 lsb_first, u32 cs_high)
345 * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG
351 tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP;
352 tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
353 tmp |= lsb_first << MDR1_BITLSB_SHIFT;
354 tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p);
355 if (spi_controller_is_slave(p->ctlr)) {
356 sh_msiof_write(p, TMDR1, tmp | TMDR1_PCON);
358 sh_msiof_write(p, TMDR1,
359 tmp | MDR1_TRMD | TMDR1_PCON |
360 (ss < MAX_SS ? ss : 0) << TMDR1_SYNCCH_SHIFT);
362 if (p->ctlr->flags & SPI_CONTROLLER_MUST_TX) {
363 /* These bits are reserved if RX needs TX */
366 sh_msiof_write(p, RMDR1, tmp);
369 tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT;
370 tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT;
374 tmp |= edge << CTR_TEDG_SHIFT;
375 tmp |= edge << CTR_REDG_SHIFT;
376 tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW;
377 sh_msiof_write(p, CTR, tmp);
380 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
381 const void *tx_buf, void *rx_buf,
384 u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words);
386 if (tx_buf || (p->ctlr->flags & SPI_CONTROLLER_MUST_TX))
387 sh_msiof_write(p, TMDR2, dr2);
389 sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1);
392 sh_msiof_write(p, RMDR2, dr2);
395 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
397 sh_msiof_write(p, STR,
398 sh_msiof_read(p, STR) & ~(STR_TDREQ | STR_RDREQ));
401 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
402 const void *tx_buf, int words, int fs)
404 const u8 *buf_8 = tx_buf;
407 for (k = 0; k < words; k++)
408 sh_msiof_write(p, TFDR, buf_8[k] << fs);
411 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
412 const void *tx_buf, int words, int fs)
414 const u16 *buf_16 = tx_buf;
417 for (k = 0; k < words; k++)
418 sh_msiof_write(p, TFDR, buf_16[k] << fs);
421 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
422 const void *tx_buf, int words, int fs)
424 const u16 *buf_16 = tx_buf;
427 for (k = 0; k < words; k++)
428 sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs);
431 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
432 const void *tx_buf, int words, int fs)
434 const u32 *buf_32 = tx_buf;
437 for (k = 0; k < words; k++)
438 sh_msiof_write(p, TFDR, buf_32[k] << fs);
441 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
442 const void *tx_buf, int words, int fs)
444 const u32 *buf_32 = tx_buf;
447 for (k = 0; k < words; k++)
448 sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs);
451 static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
452 const void *tx_buf, int words, int fs)
454 const u32 *buf_32 = tx_buf;
457 for (k = 0; k < words; k++)
458 sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs));
461 static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
462 const void *tx_buf, int words, int fs)
464 const u32 *buf_32 = tx_buf;
467 for (k = 0; k < words; k++)
468 sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs));
471 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
472 void *rx_buf, int words, int fs)
477 for (k = 0; k < words; k++)
478 buf_8[k] = sh_msiof_read(p, RFDR) >> fs;
481 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
482 void *rx_buf, int words, int fs)
484 u16 *buf_16 = rx_buf;
487 for (k = 0; k < words; k++)
488 buf_16[k] = sh_msiof_read(p, RFDR) >> fs;
491 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
492 void *rx_buf, int words, int fs)
494 u16 *buf_16 = rx_buf;
497 for (k = 0; k < words; k++)
498 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]);
501 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
502 void *rx_buf, int words, int fs)
504 u32 *buf_32 = rx_buf;
507 for (k = 0; k < words; k++)
508 buf_32[k] = sh_msiof_read(p, RFDR) >> fs;
511 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
512 void *rx_buf, int words, int fs)
514 u32 *buf_32 = rx_buf;
517 for (k = 0; k < words; k++)
518 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]);
521 static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
522 void *rx_buf, int words, int fs)
524 u32 *buf_32 = rx_buf;
527 for (k = 0; k < words; k++)
528 buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs);
531 static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
532 void *rx_buf, int words, int fs)
534 u32 *buf_32 = rx_buf;
537 for (k = 0; k < words; k++)
538 put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]);
541 static int sh_msiof_spi_setup(struct spi_device *spi)
543 struct device_node *np = spi->controller->dev.of_node;
544 struct sh_msiof_spi_priv *p =
545 spi_controller_get_devdata(spi->controller);
550 * Use spi->controller_data for CS (same strategy as spi_gpio),
551 * if any. otherwise let HW control CS
553 spi->cs_gpio = (uintptr_t)spi->controller_data;
556 if (gpio_is_valid(spi->cs_gpio)) {
557 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
561 if (spi_controller_is_slave(p->ctlr))
564 if (p->native_cs_inited &&
565 (p->native_cs_high == !!(spi->mode & SPI_CS_HIGH)))
568 /* Configure native chip select mode/polarity early */
569 clr = MDR1_SYNCMD_MASK;
570 set = MDR1_SYNCMD_SPI;
571 if (spi->mode & SPI_CS_HIGH)
572 clr |= BIT(MDR1_SYNCAC_SHIFT);
574 set |= BIT(MDR1_SYNCAC_SHIFT);
575 pm_runtime_get_sync(&p->pdev->dev);
576 tmp = sh_msiof_read(p, TMDR1) & ~clr;
577 sh_msiof_write(p, TMDR1, tmp | set | MDR1_TRMD | TMDR1_PCON);
578 tmp = sh_msiof_read(p, RMDR1) & ~clr;
579 sh_msiof_write(p, RMDR1, tmp | set);
580 pm_runtime_put(&p->pdev->dev);
581 p->native_cs_high = spi->mode & SPI_CS_HIGH;
582 p->native_cs_inited = true;
586 static int sh_msiof_prepare_message(struct spi_controller *ctlr,
587 struct spi_message *msg)
589 struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
590 const struct spi_device *spi = msg->spi;
593 /* Configure pins before asserting CS */
594 if (gpio_is_valid(spi->cs_gpio)) {
596 cs_high = p->native_cs_high;
598 ss = spi->chip_select;
599 cs_high = !!(spi->mode & SPI_CS_HIGH);
601 sh_msiof_spi_set_pin_regs(p, ss, !!(spi->mode & SPI_CPOL),
602 !!(spi->mode & SPI_CPHA),
603 !!(spi->mode & SPI_3WIRE),
604 !!(spi->mode & SPI_LSB_FIRST), cs_high);
608 static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf)
610 bool slave = spi_controller_is_slave(p->ctlr);
613 /* setup clock and rx/tx signals */
615 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE);
617 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_RXE);
619 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TXE);
621 /* start by setting frame bit */
623 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE);
628 static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf)
630 bool slave = spi_controller_is_slave(p->ctlr);
633 /* shut down frame, rx/tx and clock signals */
635 ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
637 ret = sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
639 ret = sh_msiof_modify_ctr_wait(p, CTR_RXE, 0);
641 ret = sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0);
646 static int sh_msiof_slave_abort(struct spi_controller *ctlr)
648 struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
650 p->slave_aborted = true;
652 complete(&p->done_txdma);
656 static int sh_msiof_wait_for_completion(struct sh_msiof_spi_priv *p,
657 struct completion *x)
659 if (spi_controller_is_slave(p->ctlr)) {
660 if (wait_for_completion_interruptible(x) ||
662 dev_dbg(&p->pdev->dev, "interrupted\n");
666 if (!wait_for_completion_timeout(x, HZ)) {
667 dev_err(&p->pdev->dev, "timeout\n");
675 static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
676 void (*tx_fifo)(struct sh_msiof_spi_priv *,
677 const void *, int, int),
678 void (*rx_fifo)(struct sh_msiof_spi_priv *,
680 const void *tx_buf, void *rx_buf,
686 /* limit maximum word transfer to rx/tx fifo size */
688 words = min_t(int, words, p->tx_fifo_size);
690 words = min_t(int, words, p->rx_fifo_size);
692 /* the fifo contents need shifting */
693 fifo_shift = 32 - bits;
695 /* default FIFO watermarks for PIO */
696 sh_msiof_write(p, FCTR, 0);
698 /* setup msiof transfer mode registers */
699 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
700 sh_msiof_write(p, IER, IER_TEOFE | IER_REOFE);
704 tx_fifo(p, tx_buf, words, fifo_shift);
706 reinit_completion(&p->done);
707 p->slave_aborted = false;
709 ret = sh_msiof_spi_start(p, rx_buf);
711 dev_err(&p->pdev->dev, "failed to start hardware\n");
715 /* wait for tx fifo to be emptied / rx fifo to be filled */
716 ret = sh_msiof_wait_for_completion(p, &p->done);
722 rx_fifo(p, rx_buf, words, fifo_shift);
724 /* clear status bits */
725 sh_msiof_reset_str(p);
727 ret = sh_msiof_spi_stop(p, rx_buf);
729 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
736 sh_msiof_reset_str(p);
737 sh_msiof_spi_stop(p, rx_buf);
739 sh_msiof_write(p, IER, 0);
743 static void sh_msiof_dma_complete(void *arg)
748 static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
749 void *rx, unsigned int len)
752 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
756 /* First prepare and submit the DMA request(s), as this may fail */
758 ier_bits |= IER_RDREQE | IER_RDMAE;
759 desc_rx = dmaengine_prep_slave_single(p->ctlr->dma_rx,
760 p->rx_dma_addr, len, DMA_DEV_TO_MEM,
761 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
765 desc_rx->callback = sh_msiof_dma_complete;
766 desc_rx->callback_param = &p->done;
767 cookie = dmaengine_submit(desc_rx);
768 if (dma_submit_error(cookie))
773 ier_bits |= IER_TDREQE | IER_TDMAE;
774 dma_sync_single_for_device(p->ctlr->dma_tx->device->dev,
775 p->tx_dma_addr, len, DMA_TO_DEVICE);
776 desc_tx = dmaengine_prep_slave_single(p->ctlr->dma_tx,
777 p->tx_dma_addr, len, DMA_MEM_TO_DEV,
778 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
784 desc_tx->callback = sh_msiof_dma_complete;
785 desc_tx->callback_param = &p->done_txdma;
786 cookie = dmaengine_submit(desc_tx);
787 if (dma_submit_error(cookie)) {
793 /* 1 stage FIFO watermarks for DMA */
794 sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1);
796 /* setup msiof transfer mode registers (32-bit words) */
797 sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
799 sh_msiof_write(p, IER, ier_bits);
801 reinit_completion(&p->done);
803 reinit_completion(&p->done_txdma);
804 p->slave_aborted = false;
808 dma_async_issue_pending(p->ctlr->dma_rx);
810 dma_async_issue_pending(p->ctlr->dma_tx);
812 ret = sh_msiof_spi_start(p, rx);
814 dev_err(&p->pdev->dev, "failed to start hardware\n");
819 /* wait for tx DMA completion */
820 ret = sh_msiof_wait_for_completion(p, &p->done_txdma);
826 /* wait for rx DMA completion */
827 ret = sh_msiof_wait_for_completion(p, &p->done);
831 sh_msiof_write(p, IER, 0);
833 /* wait for tx fifo to be emptied */
834 sh_msiof_write(p, IER, IER_TEOFE);
835 ret = sh_msiof_wait_for_completion(p, &p->done);
840 /* clear status bits */
841 sh_msiof_reset_str(p);
843 ret = sh_msiof_spi_stop(p, rx);
845 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
850 dma_sync_single_for_cpu(p->ctlr->dma_rx->device->dev,
851 p->rx_dma_addr, len, DMA_FROM_DEVICE);
856 sh_msiof_reset_str(p);
857 sh_msiof_spi_stop(p, rx);
860 dmaengine_terminate_all(p->ctlr->dma_tx);
863 dmaengine_terminate_all(p->ctlr->dma_rx);
864 sh_msiof_write(p, IER, 0);
868 static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words)
870 /* src or dst can be unaligned, but not both */
871 if ((unsigned long)src & 3) {
873 *dst++ = swab32(get_unaligned(src));
876 } else if ((unsigned long)dst & 3) {
878 put_unaligned(swab32(*src++), dst);
883 *dst++ = swab32(*src++);
887 static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words)
889 /* src or dst can be unaligned, but not both */
890 if ((unsigned long)src & 3) {
892 *dst++ = swahw32(get_unaligned(src));
895 } else if ((unsigned long)dst & 3) {
897 put_unaligned(swahw32(*src++), dst);
902 *dst++ = swahw32(*src++);
906 static void copy_plain32(u32 *dst, const u32 *src, unsigned int words)
908 memcpy(dst, src, words * 4);
911 static int sh_msiof_transfer_one(struct spi_controller *ctlr,
912 struct spi_device *spi,
913 struct spi_transfer *t)
915 struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
916 void (*copy32)(u32 *, const u32 *, unsigned int);
917 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
918 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
919 const void *tx_buf = t->tx_buf;
920 void *rx_buf = t->rx_buf;
921 unsigned int len = t->len;
922 unsigned int bits = t->bits_per_word;
923 unsigned int bytes_per_word;
929 /* setup clocks (clock already enabled in chipselect()) */
930 if (!spi_controller_is_slave(p->ctlr))
931 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
933 while (ctlr->dma_tx && len > 15) {
935 * DMA supports 32-bit words only, hence pack 8-bit and 16-bit
936 * words, with byte resp. word swapping.
941 l = min(round_down(len, 4), p->tx_fifo_size * 4);
943 l = min(round_down(len, 4), p->rx_fifo_size * 4);
946 copy32 = copy_bswap32;
947 } else if (bits <= 16) {
948 copy32 = copy_wswap32;
950 copy32 = copy_plain32;
954 copy32(p->tx_dma_page, tx_buf, l / 4);
956 ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l);
957 if (ret == -EAGAIN) {
958 dev_warn_once(&p->pdev->dev,
959 "DMA not available, falling back to PIO\n");
966 copy32(rx_buf, p->rx_dma_page, l / 4);
977 if (bits <= 8 && len > 15) {
984 /* setup bytes per word and fifo read/write functions */
987 tx_fifo = sh_msiof_spi_write_fifo_8;
988 rx_fifo = sh_msiof_spi_read_fifo_8;
989 } else if (bits <= 16) {
991 if ((unsigned long)tx_buf & 0x01)
992 tx_fifo = sh_msiof_spi_write_fifo_16u;
994 tx_fifo = sh_msiof_spi_write_fifo_16;
996 if ((unsigned long)rx_buf & 0x01)
997 rx_fifo = sh_msiof_spi_read_fifo_16u;
999 rx_fifo = sh_msiof_spi_read_fifo_16;
1002 if ((unsigned long)tx_buf & 0x03)
1003 tx_fifo = sh_msiof_spi_write_fifo_s32u;
1005 tx_fifo = sh_msiof_spi_write_fifo_s32;
1007 if ((unsigned long)rx_buf & 0x03)
1008 rx_fifo = sh_msiof_spi_read_fifo_s32u;
1010 rx_fifo = sh_msiof_spi_read_fifo_s32;
1013 if ((unsigned long)tx_buf & 0x03)
1014 tx_fifo = sh_msiof_spi_write_fifo_32u;
1016 tx_fifo = sh_msiof_spi_write_fifo_32;
1018 if ((unsigned long)rx_buf & 0x03)
1019 rx_fifo = sh_msiof_spi_read_fifo_32u;
1021 rx_fifo = sh_msiof_spi_read_fifo_32;
1024 /* transfer in fifo sized chunks */
1025 words = len / bytes_per_word;
1028 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf,
1034 tx_buf += n * bytes_per_word;
1036 rx_buf += n * bytes_per_word;
1039 if (words == 0 && (len % bytes_per_word)) {
1040 words = len % bytes_per_word;
1041 bits = t->bits_per_word;
1043 tx_fifo = sh_msiof_spi_write_fifo_8;
1044 rx_fifo = sh_msiof_spi_read_fifo_8;
1051 static const struct sh_msiof_chipdata sh_data = {
1052 .bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32),
1059 static const struct sh_msiof_chipdata rcar_gen2_data = {
1060 .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
1061 SPI_BPW_MASK(24) | SPI_BPW_MASK(32),
1064 .ctlr_flags = SPI_CONTROLLER_MUST_TX,
1068 static const struct sh_msiof_chipdata rcar_gen3_data = {
1069 .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
1070 SPI_BPW_MASK(24) | SPI_BPW_MASK(32),
1073 .ctlr_flags = SPI_CONTROLLER_MUST_TX,
1077 static const struct of_device_id sh_msiof_match[] = {
1078 { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
1079 { .compatible = "renesas,msiof-r8a7743", .data = &rcar_gen2_data },
1080 { .compatible = "renesas,msiof-r8a7745", .data = &rcar_gen2_data },
1081 { .compatible = "renesas,msiof-r8a7790", .data = &rcar_gen2_data },
1082 { .compatible = "renesas,msiof-r8a7791", .data = &rcar_gen2_data },
1083 { .compatible = "renesas,msiof-r8a7792", .data = &rcar_gen2_data },
1084 { .compatible = "renesas,msiof-r8a7793", .data = &rcar_gen2_data },
1085 { .compatible = "renesas,msiof-r8a7794", .data = &rcar_gen2_data },
1086 { .compatible = "renesas,rcar-gen2-msiof", .data = &rcar_gen2_data },
1087 { .compatible = "renesas,msiof-r8a7796", .data = &rcar_gen3_data },
1088 { .compatible = "renesas,rcar-gen3-msiof", .data = &rcar_gen3_data },
1089 { .compatible = "renesas,sh-msiof", .data = &sh_data }, /* Deprecated */
1092 MODULE_DEVICE_TABLE(of, sh_msiof_match);
1095 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1097 struct sh_msiof_spi_info *info;
1098 struct device_node *np = dev->of_node;
1101 info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL);
1105 info->mode = of_property_read_bool(np, "spi-slave") ? MSIOF_SPI_SLAVE
1108 /* Parse the MSIOF properties */
1109 if (info->mode == MSIOF_SPI_MASTER)
1110 of_property_read_u32(np, "num-cs", &num_cs);
1111 of_property_read_u32(np, "renesas,tx-fifo-size",
1112 &info->tx_fifo_override);
1113 of_property_read_u32(np, "renesas,rx-fifo-size",
1114 &info->rx_fifo_override);
1115 of_property_read_u32(np, "renesas,dtdl", &info->dtdl);
1116 of_property_read_u32(np, "renesas,syncdl", &info->syncdl);
1118 info->num_chipselect = num_cs;
1123 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1129 static int sh_msiof_get_cs_gpios(struct sh_msiof_spi_priv *p)
1131 struct device *dev = &p->pdev->dev;
1132 unsigned int used_ss_mask = 0;
1133 unsigned int cs_gpios = 0;
1134 unsigned int num_cs, i;
1137 ret = gpiod_count(dev, "cs");
1141 num_cs = max_t(unsigned int, ret, p->ctlr->num_chipselect);
1142 for (i = 0; i < num_cs; i++) {
1143 struct gpio_desc *gpiod;
1145 gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
1146 if (!IS_ERR(gpiod)) {
1151 if (PTR_ERR(gpiod) != -ENOENT)
1152 return PTR_ERR(gpiod);
1155 dev_err(dev, "Invalid native chip select %d\n", i);
1158 used_ss_mask |= BIT(i);
1160 p->unused_ss = ffz(used_ss_mask);
1161 if (cs_gpios && p->unused_ss >= MAX_SS) {
1162 dev_err(dev, "No unused native chip select available\n");
1168 static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev,
1169 enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr)
1171 dma_cap_mask_t mask;
1172 struct dma_chan *chan;
1173 struct dma_slave_config cfg;
1177 dma_cap_set(DMA_SLAVE, mask);
1179 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1180 (void *)(unsigned long)id, dev,
1181 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1183 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
1187 memset(&cfg, 0, sizeof(cfg));
1188 cfg.direction = dir;
1189 if (dir == DMA_MEM_TO_DEV) {
1190 cfg.dst_addr = port_addr;
1191 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1193 cfg.src_addr = port_addr;
1194 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1197 ret = dmaengine_slave_config(chan, &cfg);
1199 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1200 dma_release_channel(chan);
1207 static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p)
1209 struct platform_device *pdev = p->pdev;
1210 struct device *dev = &pdev->dev;
1211 const struct sh_msiof_spi_info *info = p->info;
1212 unsigned int dma_tx_id, dma_rx_id;
1213 const struct resource *res;
1214 struct spi_controller *ctlr;
1215 struct device *tx_dev, *rx_dev;
1218 /* In the OF case we will get the slave IDs from the DT */
1221 } else if (info && info->dma_tx_id && info->dma_rx_id) {
1222 dma_tx_id = info->dma_tx_id;
1223 dma_rx_id = info->dma_rx_id;
1225 /* The driver assumes no error */
1229 /* The DMA engine uses the second register set, if present */
1230 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1232 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1235 ctlr->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV,
1236 dma_tx_id, res->start + TFDR);
1240 ctlr->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM,
1241 dma_rx_id, res->start + RFDR);
1245 p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1246 if (!p->tx_dma_page)
1249 p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1250 if (!p->rx_dma_page)
1253 tx_dev = ctlr->dma_tx->device->dev;
1254 p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE,
1256 if (dma_mapping_error(tx_dev, p->tx_dma_addr))
1259 rx_dev = ctlr->dma_rx->device->dev;
1260 p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE,
1262 if (dma_mapping_error(rx_dev, p->rx_dma_addr))
1265 dev_info(dev, "DMA available");
1269 dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE);
1271 free_page((unsigned long)p->rx_dma_page);
1273 free_page((unsigned long)p->tx_dma_page);
1275 dma_release_channel(ctlr->dma_rx);
1277 dma_release_channel(ctlr->dma_tx);
1278 ctlr->dma_tx = NULL;
1282 static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p)
1284 struct spi_controller *ctlr = p->ctlr;
1289 dma_unmap_single(ctlr->dma_rx->device->dev, p->rx_dma_addr, PAGE_SIZE,
1291 dma_unmap_single(ctlr->dma_tx->device->dev, p->tx_dma_addr, PAGE_SIZE,
1293 free_page((unsigned long)p->rx_dma_page);
1294 free_page((unsigned long)p->tx_dma_page);
1295 dma_release_channel(ctlr->dma_rx);
1296 dma_release_channel(ctlr->dma_tx);
1299 static int sh_msiof_spi_probe(struct platform_device *pdev)
1302 struct spi_controller *ctlr;
1303 const struct sh_msiof_chipdata *chipdata;
1304 struct sh_msiof_spi_info *info;
1305 struct sh_msiof_spi_priv *p;
1309 chipdata = of_device_get_match_data(&pdev->dev);
1311 info = sh_msiof_spi_parse_dt(&pdev->dev);
1313 chipdata = (const void *)pdev->id_entry->driver_data;
1314 info = dev_get_platdata(&pdev->dev);
1318 dev_err(&pdev->dev, "failed to obtain device info\n");
1322 if (info->mode == MSIOF_SPI_SLAVE)
1323 ctlr = spi_alloc_slave(&pdev->dev,
1324 sizeof(struct sh_msiof_spi_priv));
1326 ctlr = spi_alloc_master(&pdev->dev,
1327 sizeof(struct sh_msiof_spi_priv));
1331 p = spi_controller_get_devdata(ctlr);
1333 platform_set_drvdata(pdev, p);
1336 p->min_div_pow = chipdata->min_div_pow;
1338 init_completion(&p->done);
1339 init_completion(&p->done_txdma);
1341 p->clk = devm_clk_get(&pdev->dev, NULL);
1342 if (IS_ERR(p->clk)) {
1343 dev_err(&pdev->dev, "cannot get clock\n");
1344 ret = PTR_ERR(p->clk);
1348 i = platform_get_irq(pdev, 0);
1350 dev_err(&pdev->dev, "cannot get IRQ\n");
1355 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1356 p->mapbase = devm_ioremap_resource(&pdev->dev, r);
1357 if (IS_ERR(p->mapbase)) {
1358 ret = PTR_ERR(p->mapbase);
1362 ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0,
1363 dev_name(&pdev->dev), p);
1365 dev_err(&pdev->dev, "unable to request irq\n");
1370 pm_runtime_enable(&pdev->dev);
1372 /* Platform data may override FIFO sizes */
1373 p->tx_fifo_size = chipdata->tx_fifo_size;
1374 p->rx_fifo_size = chipdata->rx_fifo_size;
1375 if (p->info->tx_fifo_override)
1376 p->tx_fifo_size = p->info->tx_fifo_override;
1377 if (p->info->rx_fifo_override)
1378 p->rx_fifo_size = p->info->rx_fifo_override;
1380 /* Setup GPIO chip selects */
1381 ctlr->num_chipselect = p->info->num_chipselect;
1382 ret = sh_msiof_get_cs_gpios(p);
1386 /* init controller code */
1387 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1388 ctlr->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
1389 ctlr->flags = chipdata->ctlr_flags;
1390 ctlr->bus_num = pdev->id;
1391 ctlr->dev.of_node = pdev->dev.of_node;
1392 ctlr->setup = sh_msiof_spi_setup;
1393 ctlr->prepare_message = sh_msiof_prepare_message;
1394 ctlr->slave_abort = sh_msiof_slave_abort;
1395 ctlr->bits_per_word_mask = chipdata->bits_per_word_mask;
1396 ctlr->auto_runtime_pm = true;
1397 ctlr->transfer_one = sh_msiof_transfer_one;
1399 ret = sh_msiof_request_dma(p);
1401 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1403 ret = devm_spi_register_controller(&pdev->dev, ctlr);
1405 dev_err(&pdev->dev, "devm_spi_register_controller error.\n");
1412 sh_msiof_release_dma(p);
1413 pm_runtime_disable(&pdev->dev);
1415 spi_controller_put(ctlr);
1419 static int sh_msiof_spi_remove(struct platform_device *pdev)
1421 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1423 sh_msiof_release_dma(p);
1424 pm_runtime_disable(&pdev->dev);
1428 static const struct platform_device_id spi_driver_ids[] = {
1429 { "spi_sh_msiof", (kernel_ulong_t)&sh_data },
1432 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1434 #ifdef CONFIG_PM_SLEEP
1435 static int sh_msiof_spi_suspend(struct device *dev)
1437 struct sh_msiof_spi_priv *p = dev_get_drvdata(dev);
1439 return spi_controller_suspend(p->ctlr);
1442 static int sh_msiof_spi_resume(struct device *dev)
1444 struct sh_msiof_spi_priv *p = dev_get_drvdata(dev);
1446 return spi_controller_resume(p->ctlr);
1449 static SIMPLE_DEV_PM_OPS(sh_msiof_spi_pm_ops, sh_msiof_spi_suspend,
1450 sh_msiof_spi_resume);
1451 #define DEV_PM_OPS &sh_msiof_spi_pm_ops
1453 #define DEV_PM_OPS NULL
1454 #endif /* CONFIG_PM_SLEEP */
1456 static struct platform_driver sh_msiof_spi_drv = {
1457 .probe = sh_msiof_spi_probe,
1458 .remove = sh_msiof_spi_remove,
1459 .id_table = spi_driver_ids,
1461 .name = "spi_sh_msiof",
1463 .of_match_table = of_match_ptr(sh_msiof_match),
1466 module_platform_driver(sh_msiof_spi_drv);
1468 MODULE_DESCRIPTION("SuperH MSIOF SPI Controller Interface Driver");
1469 MODULE_AUTHOR("Magnus Damm");
1470 MODULE_LICENSE("GPL v2");
1471 MODULE_ALIAS("platform:spi_sh_msiof");