1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
6 * Author: Sourav Poddar <sourav.poddar@ti.com>
9 #include <linux/kernel.h>
10 #include <linux/init.h>
11 #include <linux/interrupt.h>
12 #include <linux/module.h>
13 #include <linux/device.h>
14 #include <linux/delay.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/dmaengine.h>
17 #include <linux/omap-dma.h>
18 #include <linux/platform_device.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
22 #include <linux/slab.h>
23 #include <linux/pm_runtime.h>
25 #include <linux/of_device.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/regmap.h>
29 #include <linux/sizes.h>
31 #include <linux/spi/spi.h>
32 #include <linux/spi/spi-mem.h>
39 struct completion transfer_complete;
41 /* list synchronization */
42 struct mutex list_lock;
44 struct spi_master *master;
46 void __iomem *mmap_base;
48 struct regmap *ctrl_base;
49 unsigned int ctrl_reg;
53 struct ti_qspi_regs ctx_reg;
55 dma_addr_t mmap_phys_base;
56 dma_addr_t rx_bb_dma_addr;
58 struct dma_chan *rx_chan;
60 u32 spi_max_frequency;
67 #define QSPI_PID (0x0)
68 #define QSPI_SYSCONFIG (0x10)
69 #define QSPI_SPI_CLOCK_CNTRL_REG (0x40)
70 #define QSPI_SPI_DC_REG (0x44)
71 #define QSPI_SPI_CMD_REG (0x48)
72 #define QSPI_SPI_STATUS_REG (0x4c)
73 #define QSPI_SPI_DATA_REG (0x50)
74 #define QSPI_SPI_SETUP_REG(n) ((0x54 + 4 * n))
75 #define QSPI_SPI_SWITCH_REG (0x64)
76 #define QSPI_SPI_DATA_REG_1 (0x68)
77 #define QSPI_SPI_DATA_REG_2 (0x6c)
78 #define QSPI_SPI_DATA_REG_3 (0x70)
80 #define QSPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
82 #define QSPI_FCLK 192000000
85 #define QSPI_CLK_EN (1 << 31)
86 #define QSPI_CLK_DIV_MAX 0xffff
89 #define QSPI_EN_CS(n) (n << 28)
90 #define QSPI_WLEN(n) ((n - 1) << 19)
91 #define QSPI_3_PIN (1 << 18)
92 #define QSPI_RD_SNGL (1 << 16)
93 #define QSPI_WR_SNGL (2 << 16)
94 #define QSPI_RD_DUAL (3 << 16)
95 #define QSPI_RD_QUAD (7 << 16)
96 #define QSPI_INVAL (4 << 16)
97 #define QSPI_FLEN(n) ((n - 1) << 0)
98 #define QSPI_WLEN_MAX_BITS 128
99 #define QSPI_WLEN_MAX_BYTES 16
100 #define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
102 /* STATUS REGISTER */
107 #define QSPI_DD(m, n) (m << (3 + n * 8))
108 #define QSPI_CKPHA(n) (1 << (2 + n * 8))
109 #define QSPI_CSPOL(n) (1 << (1 + n * 8))
110 #define QSPI_CKPOL(n) (1 << (n * 8))
112 #define QSPI_FRAME 4096
114 #define QSPI_AUTOSUSPEND_TIMEOUT 2000
116 #define MEM_CS_EN(n) ((n + 1) << 8)
117 #define MEM_CS_MASK (7 << 8)
119 #define MM_SWITCH 0x1
121 #define QSPI_SETUP_RD_NORMAL (0x0 << 12)
122 #define QSPI_SETUP_RD_DUAL (0x1 << 12)
123 #define QSPI_SETUP_RD_QUAD (0x3 << 12)
124 #define QSPI_SETUP_ADDR_SHIFT 8
125 #define QSPI_SETUP_DUMMY_SHIFT 10
127 #define QSPI_DMA_BUFFER_SIZE SZ_64K
129 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
132 return readl(qspi->base + reg);
135 static inline void ti_qspi_write(struct ti_qspi *qspi,
136 unsigned long val, unsigned long reg)
138 writel(val, qspi->base + reg);
141 static int ti_qspi_setup(struct spi_device *spi)
143 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
144 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
145 int clk_div = 0, ret;
146 u32 clk_ctrl_reg, clk_rate, clk_mask;
148 if (spi->master->busy) {
149 dev_dbg(qspi->dev, "master busy doing other transfers\n");
153 if (!qspi->spi_max_frequency) {
154 dev_err(qspi->dev, "spi max frequency not defined\n");
158 clk_rate = clk_get_rate(qspi->fclk);
160 clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
163 dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
167 if (clk_div > QSPI_CLK_DIV_MAX) {
168 dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
169 QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
173 dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
174 qspi->spi_max_frequency, clk_div);
176 ret = pm_runtime_get_sync(qspi->dev);
178 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
182 clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
184 clk_ctrl_reg &= ~QSPI_CLK_EN;
187 ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
190 clk_mask = QSPI_CLK_EN | clk_div;
191 ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
192 ctx_reg->clkctrl = clk_mask;
194 pm_runtime_mark_last_busy(qspi->dev);
195 ret = pm_runtime_put_autosuspend(qspi->dev);
197 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
204 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
206 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
208 ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
211 static inline u32 qspi_is_busy(struct ti_qspi *qspi)
214 unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
216 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
217 while ((stat & BUSY) && time_after(timeout, jiffies)) {
219 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
222 WARN(stat & BUSY, "qspi busy\n");
226 static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
229 unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
232 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
236 } while (time_after(timeout, jiffies));
238 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
244 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t,
253 cmd = qspi->cmd | QSPI_WR_SNGL;
254 wlen = t->bits_per_word >> 3; /* in bytes */
258 if (qspi_is_busy(qspi))
263 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
264 cmd, qspi->dc, *txbuf);
265 if (count >= QSPI_WLEN_MAX_BYTES) {
266 u32 *txp = (u32 *)txbuf;
268 data = cpu_to_be32(*txp++);
269 writel(data, qspi->base +
270 QSPI_SPI_DATA_REG_3);
271 data = cpu_to_be32(*txp++);
272 writel(data, qspi->base +
273 QSPI_SPI_DATA_REG_2);
274 data = cpu_to_be32(*txp++);
275 writel(data, qspi->base +
276 QSPI_SPI_DATA_REG_1);
277 data = cpu_to_be32(*txp++);
278 writel(data, qspi->base +
280 xfer_len = QSPI_WLEN_MAX_BYTES;
281 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
283 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
284 cmd = qspi->cmd | QSPI_WR_SNGL;
286 cmd |= QSPI_WLEN(wlen);
290 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
291 cmd, qspi->dc, *txbuf);
292 writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
295 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
296 cmd, qspi->dc, *txbuf);
297 writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
301 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
302 if (ti_qspi_poll_wc(qspi)) {
303 dev_err(qspi->dev, "write timed out\n");
313 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t,
322 switch (t->rx_nbits) {
333 wlen = t->bits_per_word >> 3; /* in bytes */
336 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
337 if (qspi_is_busy(qspi))
340 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
341 if (ti_qspi_poll_wc(qspi)) {
342 dev_err(qspi->dev, "read timed out\n");
347 *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
350 *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
353 *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
363 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t,
369 ret = qspi_write_msg(qspi, t, count);
371 dev_dbg(qspi->dev, "Error while writing\n");
377 ret = qspi_read_msg(qspi, t, count);
379 dev_dbg(qspi->dev, "Error while reading\n");
387 static void ti_qspi_dma_callback(void *param)
389 struct ti_qspi *qspi = param;
391 complete(&qspi->transfer_complete);
394 static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst,
395 dma_addr_t dma_src, size_t len)
397 struct dma_chan *chan = qspi->rx_chan;
399 enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
400 struct dma_async_tx_descriptor *tx;
403 tx = dmaengine_prep_dma_memcpy(chan, dma_dst, dma_src, len, flags);
405 dev_err(qspi->dev, "device_prep_dma_memcpy error\n");
409 tx->callback = ti_qspi_dma_callback;
410 tx->callback_param = qspi;
411 cookie = tx->tx_submit(tx);
412 reinit_completion(&qspi->transfer_complete);
414 ret = dma_submit_error(cookie);
416 dev_err(qspi->dev, "dma_submit_error %d\n", cookie);
420 dma_async_issue_pending(chan);
421 ret = wait_for_completion_timeout(&qspi->transfer_complete,
422 msecs_to_jiffies(len));
424 dmaengine_terminate_sync(chan);
425 dev_err(qspi->dev, "DMA wait_for_completion_timeout\n");
432 static int ti_qspi_dma_bounce_buffer(struct ti_qspi *qspi, loff_t offs,
433 void *to, size_t readsize)
435 dma_addr_t dma_src = qspi->mmap_phys_base + offs;
439 * Use bounce buffer as FS like jffs2, ubifs may pass
440 * buffers that does not belong to kernel lowmem region.
442 while (readsize != 0) {
443 size_t xfer_len = min_t(size_t, QSPI_DMA_BUFFER_SIZE,
446 ret = ti_qspi_dma_xfer(qspi, qspi->rx_bb_dma_addr,
450 memcpy(to, qspi->rx_bb_addr, xfer_len);
451 readsize -= xfer_len;
459 static int ti_qspi_dma_xfer_sg(struct ti_qspi *qspi, struct sg_table rx_sg,
462 struct scatterlist *sg;
463 dma_addr_t dma_src = qspi->mmap_phys_base + from;
467 for_each_sg(rx_sg.sgl, sg, rx_sg.nents, i) {
468 dma_dst = sg_dma_address(sg);
469 len = sg_dma_len(sg);
470 ret = ti_qspi_dma_xfer(qspi, dma_dst, dma_src, len);
479 static void ti_qspi_enable_memory_map(struct spi_device *spi)
481 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
483 ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
484 if (qspi->ctrl_base) {
485 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
487 MEM_CS_EN(spi->chip_select));
489 qspi->mmap_enabled = true;
492 static void ti_qspi_disable_memory_map(struct spi_device *spi)
494 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
496 ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
498 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
500 qspi->mmap_enabled = false;
503 static void ti_qspi_setup_mmap_read(struct spi_device *spi, u8 opcode,
504 u8 data_nbits, u8 addr_width,
507 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
510 switch (data_nbits) {
512 memval |= QSPI_SETUP_RD_QUAD;
515 memval |= QSPI_SETUP_RD_DUAL;
518 memval |= QSPI_SETUP_RD_NORMAL;
521 memval |= ((addr_width - 1) << QSPI_SETUP_ADDR_SHIFT |
522 dummy_bytes << QSPI_SETUP_DUMMY_SHIFT);
523 ti_qspi_write(qspi, memval,
524 QSPI_SPI_SETUP_REG(spi->chip_select));
527 static int ti_qspi_exec_mem_op(struct spi_mem *mem,
528 const struct spi_mem_op *op)
530 struct ti_qspi *qspi = spi_master_get_devdata(mem->spi->master);
534 /* Only optimize read path. */
535 if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
536 !op->addr.nbytes || op->addr.nbytes > 4)
539 /* Address exceeds MMIO window size, fall back to regular mode. */
541 if (from + op->data.nbytes > qspi->mmap_size)
544 mutex_lock(&qspi->list_lock);
546 if (!qspi->mmap_enabled)
547 ti_qspi_enable_memory_map(mem->spi);
548 ti_qspi_setup_mmap_read(mem->spi, op->cmd.opcode, op->data.buswidth,
549 op->addr.nbytes, op->dummy.nbytes);
554 if (virt_addr_valid(op->data.buf.in) &&
555 !spi_controller_dma_map_mem_op_data(mem->spi->master, op,
557 ret = ti_qspi_dma_xfer_sg(qspi, sgt, from);
558 spi_controller_dma_unmap_mem_op_data(mem->spi->master,
561 ret = ti_qspi_dma_bounce_buffer(qspi, from,
566 memcpy_fromio(op->data.buf.in, qspi->mmap_base + from,
570 mutex_unlock(&qspi->list_lock);
575 static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
576 .exec_op = ti_qspi_exec_mem_op,
579 static int ti_qspi_start_transfer_one(struct spi_master *master,
580 struct spi_message *m)
582 struct ti_qspi *qspi = spi_master_get_devdata(master);
583 struct spi_device *spi = m->spi;
584 struct spi_transfer *t;
586 unsigned int frame_len_words, transfer_len_words;
589 /* setup device control reg */
592 if (spi->mode & SPI_CPHA)
593 qspi->dc |= QSPI_CKPHA(spi->chip_select);
594 if (spi->mode & SPI_CPOL)
595 qspi->dc |= QSPI_CKPOL(spi->chip_select);
596 if (spi->mode & SPI_CS_HIGH)
597 qspi->dc |= QSPI_CSPOL(spi->chip_select);
600 list_for_each_entry(t, &m->transfers, transfer_list)
601 frame_len_words += t->len / (t->bits_per_word >> 3);
602 frame_len_words = min_t(unsigned int, frame_len_words, QSPI_FRAME);
604 /* setup command reg */
606 qspi->cmd |= QSPI_EN_CS(spi->chip_select);
607 qspi->cmd |= QSPI_FLEN(frame_len_words);
609 ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
611 mutex_lock(&qspi->list_lock);
613 if (qspi->mmap_enabled)
614 ti_qspi_disable_memory_map(spi);
616 list_for_each_entry(t, &m->transfers, transfer_list) {
617 qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) |
618 QSPI_WLEN(t->bits_per_word));
620 wlen = t->bits_per_word >> 3;
621 transfer_len_words = min(t->len / wlen, frame_len_words);
623 ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen);
625 dev_dbg(qspi->dev, "transfer message failed\n");
626 mutex_unlock(&qspi->list_lock);
630 m->actual_length += transfer_len_words * wlen;
631 frame_len_words -= transfer_len_words;
632 if (frame_len_words == 0)
636 mutex_unlock(&qspi->list_lock);
638 ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
640 spi_finalize_current_message(master);
645 static int ti_qspi_runtime_resume(struct device *dev)
647 struct ti_qspi *qspi;
649 qspi = dev_get_drvdata(dev);
650 ti_qspi_restore_ctx(qspi);
655 static const struct of_device_id ti_qspi_match[] = {
656 {.compatible = "ti,dra7xxx-qspi" },
657 {.compatible = "ti,am4372-qspi" },
660 MODULE_DEVICE_TABLE(of, ti_qspi_match);
662 static int ti_qspi_probe(struct platform_device *pdev)
664 struct ti_qspi *qspi;
665 struct spi_master *master;
666 struct resource *r, *res_mmap;
667 struct device_node *np = pdev->dev.of_node;
669 int ret = 0, num_cs, irq;
672 master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
676 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;
678 master->flags = SPI_MASTER_HALF_DUPLEX;
679 master->setup = ti_qspi_setup;
680 master->auto_runtime_pm = true;
681 master->transfer_one_message = ti_qspi_start_transfer_one;
682 master->dev.of_node = pdev->dev.of_node;
683 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
685 master->mem_ops = &ti_qspi_mem_ops;
687 if (!of_property_read_u32(np, "num-cs", &num_cs))
688 master->num_chipselect = num_cs;
690 qspi = spi_master_get_devdata(master);
691 qspi->master = master;
692 qspi->dev = &pdev->dev;
693 platform_set_drvdata(pdev, qspi);
695 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
697 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
699 dev_err(&pdev->dev, "missing platform data\n");
705 res_mmap = platform_get_resource_byname(pdev,
706 IORESOURCE_MEM, "qspi_mmap");
707 if (res_mmap == NULL) {
708 res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
709 if (res_mmap == NULL) {
711 "memory mapped resource not required\n");
716 qspi->mmap_size = resource_size(res_mmap);
718 irq = platform_get_irq(pdev, 0);
724 mutex_init(&qspi->list_lock);
726 qspi->base = devm_ioremap_resource(&pdev->dev, r);
727 if (IS_ERR(qspi->base)) {
728 ret = PTR_ERR(qspi->base);
733 if (of_property_read_bool(np, "syscon-chipselects")) {
735 syscon_regmap_lookup_by_phandle(np,
736 "syscon-chipselects");
737 if (IS_ERR(qspi->ctrl_base)) {
738 ret = PTR_ERR(qspi->ctrl_base);
741 ret = of_property_read_u32_index(np,
742 "syscon-chipselects",
746 "couldn't get ctrl_mod reg index\n");
751 qspi->fclk = devm_clk_get(&pdev->dev, "fck");
752 if (IS_ERR(qspi->fclk)) {
753 ret = PTR_ERR(qspi->fclk);
754 dev_err(&pdev->dev, "could not get clk: %d\n", ret);
757 pm_runtime_use_autosuspend(&pdev->dev);
758 pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
759 pm_runtime_enable(&pdev->dev);
761 if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
762 qspi->spi_max_frequency = max_freq;
765 dma_cap_set(DMA_MEMCPY, mask);
767 qspi->rx_chan = dma_request_chan_by_mask(&mask);
768 if (IS_ERR(qspi->rx_chan)) {
770 "No Rx DMA available, trying mmap mode\n");
771 qspi->rx_chan = NULL;
775 qspi->rx_bb_addr = dma_alloc_coherent(qspi->dev,
776 QSPI_DMA_BUFFER_SIZE,
777 &qspi->rx_bb_dma_addr,
778 GFP_KERNEL | GFP_DMA);
779 if (!qspi->rx_bb_addr) {
781 "dma_alloc_coherent failed, using PIO mode\n");
782 dma_release_channel(qspi->rx_chan);
785 master->dma_rx = qspi->rx_chan;
786 init_completion(&qspi->transfer_complete);
788 qspi->mmap_phys_base = (dma_addr_t)res_mmap->start;
791 if (!qspi->rx_chan && res_mmap) {
792 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
793 if (IS_ERR(qspi->mmap_base)) {
795 "mmap failed with error %ld using PIO mode\n",
796 PTR_ERR(qspi->mmap_base));
797 qspi->mmap_base = NULL;
798 master->mem_ops = NULL;
801 qspi->mmap_enabled = false;
803 ret = devm_spi_register_master(&pdev->dev, master);
807 pm_runtime_disable(&pdev->dev);
809 spi_master_put(master);
813 static int ti_qspi_remove(struct platform_device *pdev)
815 struct ti_qspi *qspi = platform_get_drvdata(pdev);
818 rc = spi_master_suspend(qspi->master);
822 pm_runtime_put_sync(&pdev->dev);
823 pm_runtime_disable(&pdev->dev);
825 if (qspi->rx_bb_addr)
826 dma_free_coherent(qspi->dev, QSPI_DMA_BUFFER_SIZE,
828 qspi->rx_bb_dma_addr);
830 dma_release_channel(qspi->rx_chan);
835 static const struct dev_pm_ops ti_qspi_pm_ops = {
836 .runtime_resume = ti_qspi_runtime_resume,
839 static struct platform_driver ti_qspi_driver = {
840 .probe = ti_qspi_probe,
841 .remove = ti_qspi_remove,
844 .pm = &ti_qspi_pm_ops,
845 .of_match_table = ti_qspi_match,
849 module_platform_driver(ti_qspi_driver);
851 MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
852 MODULE_LICENSE("GPL v2");
853 MODULE_DESCRIPTION("TI QSPI controller driver");
854 MODULE_ALIAS("platform:ti-qspi");