1 // SPDX-License-Identifier: GPL-2.0
2 // spi-uniphier.c - Socionext UniPhier SPI controller driver
3 // Copyright 2012 Panasonic Corporation
4 // Copyright 2016-2018 Socionext Inc.
6 #include <linux/kernel.h>
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
10 #include <linux/delay.h>
11 #include <linux/interrupt.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/spi/spi.h>
17 #include <asm/unaligned.h>
19 #define SSI_TIMEOUT_MS 2000
20 #define SSI_POLL_TIMEOUT_US 200
21 #define SSI_MAX_CLK_DIVIDER 254
22 #define SSI_MIN_CLK_DIVIDER 4
24 struct uniphier_spi_priv {
27 struct spi_master *master;
28 struct completion xfer_done;
31 unsigned int tx_bytes;
32 unsigned int rx_bytes;
43 #define SSI_CTL_EN BIT(0)
46 #define SSI_CKS_CKRAT_MASK GENMASK(7, 0)
47 #define SSI_CKS_CKPHS BIT(14)
48 #define SSI_CKS_CKINIT BIT(13)
49 #define SSI_CKS_CKDLY BIT(12)
51 #define SSI_TXWDS 0x08
52 #define SSI_TXWDS_WDLEN_MASK GENMASK(13, 8)
53 #define SSI_TXWDS_TDTF_MASK GENMASK(7, 6)
54 #define SSI_TXWDS_DTLEN_MASK GENMASK(5, 0)
56 #define SSI_RXWDS 0x0c
57 #define SSI_RXWDS_DTLEN_MASK GENMASK(5, 0)
60 #define SSI_FPS_FSPOL BIT(15)
61 #define SSI_FPS_FSTRT BIT(14)
64 #define SSI_SR_RNE BIT(0)
67 #define SSI_IE_RCIE BIT(3)
68 #define SSI_IE_RORIE BIT(0)
71 #define SSI_IS_RXRS BIT(9)
72 #define SSI_IS_RCID BIT(3)
73 #define SSI_IS_RORID BIT(0)
76 #define SSI_IC_TCIC BIT(4)
77 #define SSI_IC_RCIC BIT(3)
78 #define SSI_IC_RORIC BIT(0)
81 #define SSI_FC_TXFFL BIT(12)
82 #define SSI_FC_TXFTH_MASK GENMASK(11, 8)
83 #define SSI_FC_RXFFL BIT(4)
84 #define SSI_FC_RXFTH_MASK GENMASK(3, 0)
89 #define SSI_FIFO_DEPTH 8U
91 static inline unsigned int bytes_per_word(unsigned int bits)
93 return bits <= 8 ? 1 : (bits <= 16 ? 2 : 4);
96 static inline void uniphier_spi_irq_enable(struct spi_device *spi, u32 mask)
98 struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
101 val = readl(priv->base + SSI_IE);
103 writel(val, priv->base + SSI_IE);
106 static inline void uniphier_spi_irq_disable(struct spi_device *spi, u32 mask)
108 struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
111 val = readl(priv->base + SSI_IE);
113 writel(val, priv->base + SSI_IE);
116 static void uniphier_spi_set_mode(struct spi_device *spi)
118 struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
123 * CKPHS capture timing. 0:rising edge, 1:falling edge
124 * CKINIT clock initial level. 0:low, 1:high
125 * CKDLY clock delay. 0:no delay, 1:delay depending on FSTRT
126 * (FSTRT=0: 1 clock, FSTRT=1: 0.5 clock)
129 * FSPOL frame signal porarity. 0: low, 1: high
130 * FSTRT start frame timing
131 * 0: rising edge of clock, 1: falling edge of clock
133 switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
135 /* CKPHS=1, CKINIT=0, CKDLY=1, FSTRT=0 */
136 val1 = SSI_CKS_CKPHS | SSI_CKS_CKDLY;
140 /* CKPHS=0, CKINIT=0, CKDLY=0, FSTRT=1 */
142 val2 = SSI_FPS_FSTRT;
145 /* CKPHS=0, CKINIT=1, CKDLY=1, FSTRT=1 */
146 val1 = SSI_CKS_CKINIT | SSI_CKS_CKDLY;
147 val2 = SSI_FPS_FSTRT;
150 /* CKPHS=1, CKINIT=1, CKDLY=0, FSTRT=0 */
151 val1 = SSI_CKS_CKPHS | SSI_CKS_CKINIT;
156 if (!(spi->mode & SPI_CS_HIGH))
157 val2 |= SSI_FPS_FSPOL;
159 writel(val1, priv->base + SSI_CKS);
160 writel(val2, priv->base + SSI_FPS);
163 if (spi->mode & SPI_LSB_FIRST)
164 val1 |= FIELD_PREP(SSI_TXWDS_TDTF_MASK, 1);
165 writel(val1, priv->base + SSI_TXWDS);
166 writel(val1, priv->base + SSI_RXWDS);
169 static void uniphier_spi_set_transfer_size(struct spi_device *spi, int size)
171 struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
174 val = readl(priv->base + SSI_TXWDS);
175 val &= ~(SSI_TXWDS_WDLEN_MASK | SSI_TXWDS_DTLEN_MASK);
176 val |= FIELD_PREP(SSI_TXWDS_WDLEN_MASK, size);
177 val |= FIELD_PREP(SSI_TXWDS_DTLEN_MASK, size);
178 writel(val, priv->base + SSI_TXWDS);
180 val = readl(priv->base + SSI_RXWDS);
181 val &= ~SSI_RXWDS_DTLEN_MASK;
182 val |= FIELD_PREP(SSI_RXWDS_DTLEN_MASK, size);
183 writel(val, priv->base + SSI_RXWDS);
186 static void uniphier_spi_set_baudrate(struct spi_device *spi,
189 struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
193 * the supported rates are even numbers from 4 to 254. (4,6,8...254)
194 * round up as we look for equal or less speed
196 ckdiv = DIV_ROUND_UP(clk_get_rate(priv->clk), speed);
197 ckdiv = round_up(ckdiv, 2);
199 val = readl(priv->base + SSI_CKS);
200 val &= ~SSI_CKS_CKRAT_MASK;
201 val |= ckdiv & SSI_CKS_CKRAT_MASK;
202 writel(val, priv->base + SSI_CKS);
205 static void uniphier_spi_setup_transfer(struct spi_device *spi,
206 struct spi_transfer *t)
208 struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
212 priv->tx_buf = t->tx_buf;
213 priv->rx_buf = t->rx_buf;
214 priv->tx_bytes = priv->rx_bytes = t->len;
216 if (!priv->is_save_param || priv->mode != spi->mode) {
217 uniphier_spi_set_mode(spi);
218 priv->mode = spi->mode;
221 if (!priv->is_save_param || priv->bits_per_word != t->bits_per_word) {
222 uniphier_spi_set_transfer_size(spi, t->bits_per_word);
223 priv->bits_per_word = t->bits_per_word;
226 if (!priv->is_save_param || priv->speed_hz != t->speed_hz) {
227 uniphier_spi_set_baudrate(spi, t->speed_hz);
228 priv->speed_hz = t->speed_hz;
231 priv->is_save_param = true;
234 val = SSI_FC_TXFFL | SSI_FC_RXFFL;
235 writel(val, priv->base + SSI_FC);
238 static void uniphier_spi_send(struct uniphier_spi_priv *priv)
243 wsize = min(bytes_per_word(priv->bits_per_word), priv->tx_bytes);
244 priv->tx_bytes -= wsize;
252 val = get_unaligned_le16(priv->tx_buf);
255 val = get_unaligned_le32(priv->tx_buf);
259 priv->tx_buf += wsize;
262 writel(val, priv->base + SSI_TXDR);
265 static void uniphier_spi_recv(struct uniphier_spi_priv *priv)
270 rsize = min(bytes_per_word(priv->bits_per_word), priv->rx_bytes);
271 priv->rx_bytes -= rsize;
273 val = readl(priv->base + SSI_RXDR);
281 put_unaligned_le16(val, priv->rx_buf);
284 put_unaligned_le32(val, priv->rx_buf);
288 priv->rx_buf += rsize;
292 static void uniphier_spi_fill_tx_fifo(struct uniphier_spi_priv *priv)
294 unsigned int fifo_threshold, fill_bytes;
297 fifo_threshold = DIV_ROUND_UP(priv->rx_bytes,
298 bytes_per_word(priv->bits_per_word));
299 fifo_threshold = min(fifo_threshold, SSI_FIFO_DEPTH);
301 fill_bytes = fifo_threshold - (priv->rx_bytes - priv->tx_bytes);
303 /* set fifo threshold */
304 val = readl(priv->base + SSI_FC);
305 val &= ~(SSI_FC_TXFTH_MASK | SSI_FC_RXFTH_MASK);
306 val |= FIELD_PREP(SSI_FC_TXFTH_MASK, fifo_threshold);
307 val |= FIELD_PREP(SSI_FC_RXFTH_MASK, fifo_threshold);
308 writel(val, priv->base + SSI_FC);
311 uniphier_spi_send(priv);
314 static void uniphier_spi_set_cs(struct spi_device *spi, bool enable)
316 struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
319 val = readl(priv->base + SSI_FPS);
322 val |= SSI_FPS_FSPOL;
324 val &= ~SSI_FPS_FSPOL;
326 writel(val, priv->base + SSI_FPS);
329 static int uniphier_spi_transfer_one_irq(struct spi_master *master,
330 struct spi_device *spi,
331 struct spi_transfer *t)
333 struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
334 struct device *dev = master->dev.parent;
335 unsigned long time_left;
337 reinit_completion(&priv->xfer_done);
339 uniphier_spi_fill_tx_fifo(priv);
341 uniphier_spi_irq_enable(spi, SSI_IE_RCIE | SSI_IE_RORIE);
343 time_left = wait_for_completion_timeout(&priv->xfer_done,
344 msecs_to_jiffies(SSI_TIMEOUT_MS));
346 uniphier_spi_irq_disable(spi, SSI_IE_RCIE | SSI_IE_RORIE);
349 dev_err(dev, "transfer timeout.\n");
356 static int uniphier_spi_transfer_one_poll(struct spi_master *master,
357 struct spi_device *spi,
358 struct spi_transfer *t)
360 struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
361 int loop = SSI_POLL_TIMEOUT_US * 10;
363 while (priv->tx_bytes) {
364 uniphier_spi_fill_tx_fifo(priv);
366 while ((priv->rx_bytes - priv->tx_bytes) > 0) {
367 while (!(readl(priv->base + SSI_SR) & SSI_SR_RNE)
374 uniphier_spi_recv(priv);
381 return uniphier_spi_transfer_one_irq(master, spi, t);
384 static int uniphier_spi_transfer_one(struct spi_master *master,
385 struct spi_device *spi,
386 struct spi_transfer *t)
388 struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
389 unsigned long threshold;
391 /* Terminate and return success for 0 byte length transfer */
395 uniphier_spi_setup_transfer(spi, t);
398 * If the transfer operation will take longer than
399 * SSI_POLL_TIMEOUT_US, it should use irq.
401 threshold = DIV_ROUND_UP(SSI_POLL_TIMEOUT_US * priv->speed_hz,
402 USEC_PER_SEC * BITS_PER_BYTE);
403 if (t->len > threshold)
404 return uniphier_spi_transfer_one_irq(master, spi, t);
406 return uniphier_spi_transfer_one_poll(master, spi, t);
409 static int uniphier_spi_prepare_transfer_hardware(struct spi_master *master)
411 struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
413 writel(SSI_CTL_EN, priv->base + SSI_CTL);
418 static int uniphier_spi_unprepare_transfer_hardware(struct spi_master *master)
420 struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
422 writel(0, priv->base + SSI_CTL);
427 static irqreturn_t uniphier_spi_handler(int irq, void *dev_id)
429 struct uniphier_spi_priv *priv = dev_id;
432 stat = readl(priv->base + SSI_IS);
433 val = SSI_IC_TCIC | SSI_IC_RCIC | SSI_IC_RORIC;
434 writel(val, priv->base + SSI_IC);
436 /* rx fifo overrun */
437 if (stat & SSI_IS_RORID) {
443 if ((stat & SSI_IS_RCID) && (stat & SSI_IS_RXRS)) {
444 while ((readl(priv->base + SSI_SR) & SSI_SR_RNE) &&
445 (priv->rx_bytes - priv->tx_bytes) > 0)
446 uniphier_spi_recv(priv);
448 if ((readl(priv->base + SSI_SR) & SSI_SR_RNE) ||
449 (priv->rx_bytes != priv->tx_bytes)) {
452 } else if (priv->rx_bytes == 0)
455 /* next tx transfer */
456 uniphier_spi_fill_tx_fifo(priv);
464 complete(&priv->xfer_done);
468 static int uniphier_spi_probe(struct platform_device *pdev)
470 struct uniphier_spi_priv *priv;
471 struct spi_master *master;
472 unsigned long clk_rate;
476 master = spi_alloc_master(&pdev->dev, sizeof(*priv));
480 platform_set_drvdata(pdev, master);
482 priv = spi_master_get_devdata(master);
483 priv->master = master;
484 priv->is_save_param = false;
486 priv->base = devm_platform_ioremap_resource(pdev, 0);
487 if (IS_ERR(priv->base)) {
488 ret = PTR_ERR(priv->base);
492 priv->clk = devm_clk_get(&pdev->dev, NULL);
493 if (IS_ERR(priv->clk)) {
494 dev_err(&pdev->dev, "failed to get clock\n");
495 ret = PTR_ERR(priv->clk);
499 ret = clk_prepare_enable(priv->clk);
503 irq = platform_get_irq(pdev, 0);
506 goto out_disable_clk;
509 ret = devm_request_irq(&pdev->dev, irq, uniphier_spi_handler,
510 0, "uniphier-spi", priv);
512 dev_err(&pdev->dev, "failed to request IRQ\n");
513 goto out_disable_clk;
516 init_completion(&priv->xfer_done);
518 clk_rate = clk_get_rate(priv->clk);
520 master->max_speed_hz = DIV_ROUND_UP(clk_rate, SSI_MIN_CLK_DIVIDER);
521 master->min_speed_hz = DIV_ROUND_UP(clk_rate, SSI_MAX_CLK_DIVIDER);
522 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
523 master->dev.of_node = pdev->dev.of_node;
524 master->bus_num = pdev->id;
525 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
527 master->set_cs = uniphier_spi_set_cs;
528 master->transfer_one = uniphier_spi_transfer_one;
529 master->prepare_transfer_hardware
530 = uniphier_spi_prepare_transfer_hardware;
531 master->unprepare_transfer_hardware
532 = uniphier_spi_unprepare_transfer_hardware;
533 master->num_chipselect = 1;
535 ret = devm_spi_register_master(&pdev->dev, master);
537 goto out_disable_clk;
542 clk_disable_unprepare(priv->clk);
545 spi_master_put(master);
549 static int uniphier_spi_remove(struct platform_device *pdev)
551 struct uniphier_spi_priv *priv = platform_get_drvdata(pdev);
553 clk_disable_unprepare(priv->clk);
558 static const struct of_device_id uniphier_spi_match[] = {
559 { .compatible = "socionext,uniphier-scssi" },
562 MODULE_DEVICE_TABLE(of, uniphier_spi_match);
564 static struct platform_driver uniphier_spi_driver = {
565 .probe = uniphier_spi_probe,
566 .remove = uniphier_spi_remove,
568 .name = "uniphier-spi",
569 .of_match_table = uniphier_spi_match,
572 module_platform_driver(uniphier_spi_driver);
574 MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
575 MODULE_AUTHOR("Keiji Hayashibara <hayashibara.keiji@socionext.com>");
576 MODULE_DESCRIPTION("Socionext UniPhier SPI controller driver");
577 MODULE_LICENSE("GPL v2");