1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019 Xilinx, Inc.
5 * Author: Naga Sureshkumar Relli <nagasure@xilinx.com>
9 #include <linux/delay.h>
10 #include <linux/interrupt.h>
12 #include <linux/module.h>
13 #include <linux/of_irq.h>
14 #include <linux/of_address.h>
15 #include <linux/platform_device.h>
16 #include <linux/spi/spi.h>
17 #include <linux/workqueue.h>
18 #include <linux/spi/spi-mem.h>
20 /* Register offset definitions */
21 #define ZYNQ_QSPI_CONFIG_OFFSET 0x00 /* Configuration Register, RW */
22 #define ZYNQ_QSPI_STATUS_OFFSET 0x04 /* Interrupt Status Register, RO */
23 #define ZYNQ_QSPI_IEN_OFFSET 0x08 /* Interrupt Enable Register, WO */
24 #define ZYNQ_QSPI_IDIS_OFFSET 0x0C /* Interrupt Disable Reg, WO */
25 #define ZYNQ_QSPI_IMASK_OFFSET 0x10 /* Interrupt Enabled Mask Reg,RO */
26 #define ZYNQ_QSPI_ENABLE_OFFSET 0x14 /* Enable/Disable Register, RW */
27 #define ZYNQ_QSPI_DELAY_OFFSET 0x18 /* Delay Register, RW */
28 #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst, WO */
29 #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst, WO */
30 #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst, WO */
31 #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst, WO */
32 #define ZYNQ_QSPI_RXD_OFFSET 0x20 /* Data Receive Register, RO */
33 #define ZYNQ_QSPI_SIC_OFFSET 0x24 /* Slave Idle Count Register, RW */
34 #define ZYNQ_QSPI_TX_THRESH_OFFSET 0x28 /* TX FIFO Watermark Reg, RW */
35 #define ZYNQ_QSPI_RX_THRESH_OFFSET 0x2C /* RX FIFO Watermark Reg, RW */
36 #define ZYNQ_QSPI_GPIO_OFFSET 0x30 /* GPIO Register, RW */
37 #define ZYNQ_QSPI_LINEAR_CFG_OFFSET 0xA0 /* Linear Adapter Config Ref, RW */
38 #define ZYNQ_QSPI_MOD_ID_OFFSET 0xFC /* Module ID Register, RO */
41 * QSPI Configuration Register bit Masks
43 * This register contains various control bits that effect the operation
44 * of the QSPI controller
46 #define ZYNQ_QSPI_CONFIG_IFMODE_MASK BIT(31) /* Flash Memory Interface */
47 #define ZYNQ_QSPI_CONFIG_MANSRT_MASK BIT(16) /* Manual TX Start */
48 #define ZYNQ_QSPI_CONFIG_MANSRTEN_MASK BIT(15) /* Enable Manual TX Mode */
49 #define ZYNQ_QSPI_CONFIG_SSFORCE_MASK BIT(14) /* Manual Chip Select */
50 #define ZYNQ_QSPI_CONFIG_BDRATE_MASK GENMASK(5, 3) /* Baud Rate Mask */
51 #define ZYNQ_QSPI_CONFIG_CPHA_MASK BIT(2) /* Clock Phase Control */
52 #define ZYNQ_QSPI_CONFIG_CPOL_MASK BIT(1) /* Clock Polarity Control */
53 #define ZYNQ_QSPI_CONFIG_SSCTRL_MASK BIT(10) /* Slave Select Mask */
54 #define ZYNQ_QSPI_CONFIG_FWIDTH_MASK GENMASK(7, 6) /* FIFO width */
55 #define ZYNQ_QSPI_CONFIG_MSTREN_MASK BIT(0) /* Master Mode */
58 * QSPI Configuration Register - Baud rate and slave select
60 * These are the values used in the calculation of baud rate divisor and
61 * setting the slave select.
63 #define ZYNQ_QSPI_BAUD_DIV_MAX GENMASK(2, 0) /* Baud rate maximum */
64 #define ZYNQ_QSPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */
65 #define ZYNQ_QSPI_SS_SHIFT 10 /* Slave Select field shift in CR */
68 * QSPI Interrupt Registers bit Masks
70 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
73 #define ZYNQ_QSPI_IXR_RX_OVERFLOW_MASK BIT(0) /* QSPI RX FIFO Overflow */
74 #define ZYNQ_QSPI_IXR_TXNFULL_MASK BIT(2) /* QSPI TX FIFO Overflow */
75 #define ZYNQ_QSPI_IXR_TXFULL_MASK BIT(3) /* QSPI TX FIFO is full */
76 #define ZYNQ_QSPI_IXR_RXNEMTY_MASK BIT(4) /* QSPI RX FIFO Not Empty */
77 #define ZYNQ_QSPI_IXR_RXF_FULL_MASK BIT(5) /* QSPI RX FIFO is full */
78 #define ZYNQ_QSPI_IXR_TXF_UNDRFLOW_MASK BIT(6) /* QSPI TX FIFO Underflow */
79 #define ZYNQ_QSPI_IXR_ALL_MASK (ZYNQ_QSPI_IXR_RX_OVERFLOW_MASK | \
80 ZYNQ_QSPI_IXR_TXNFULL_MASK | \
81 ZYNQ_QSPI_IXR_TXFULL_MASK | \
82 ZYNQ_QSPI_IXR_RXNEMTY_MASK | \
83 ZYNQ_QSPI_IXR_RXF_FULL_MASK | \
84 ZYNQ_QSPI_IXR_TXF_UNDRFLOW_MASK)
85 #define ZYNQ_QSPI_IXR_RXTX_MASK (ZYNQ_QSPI_IXR_TXNFULL_MASK | \
86 ZYNQ_QSPI_IXR_RXNEMTY_MASK)
89 * QSPI Enable Register bit Masks
91 * This register is used to enable or disable the QSPI controller
93 #define ZYNQ_QSPI_ENABLE_ENABLE_MASK BIT(0) /* QSPI Enable Bit Mask */
96 * QSPI Linear Configuration Register
98 * It is named Linear Configuration but it controls other modes when not in
101 #define ZYNQ_QSPI_LCFG_TWO_MEM_MASK BIT(30) /* LQSPI Two memories Mask */
102 #define ZYNQ_QSPI_LCFG_SEP_BUS_MASK BIT(29) /* LQSPI Separate bus Mask */
103 #define ZYNQ_QSPI_LCFG_U_PAGE_MASK BIT(28) /* LQSPI Upper Page Mask */
105 #define ZYNQ_QSPI_LCFG_DUMMY_SHIFT 8
107 #define ZYNQ_QSPI_FAST_READ_QOUT_CODE 0x6B /* read instruction code */
108 #define ZYNQ_QSPI_FIFO_DEPTH 63 /* FIFO depth in words */
109 #define ZYNQ_QSPI_RX_THRESHOLD 32 /* Rx FIFO threshold level */
110 #define ZYNQ_QSPI_TX_THRESHOLD 1 /* Tx FIFO threshold level */
113 * The modebits configurable by the driver to make the SPI support different
116 #define ZYNQ_QSPI_MODEBITS (SPI_CPOL | SPI_CPHA)
118 /* Default number of chip selects */
119 #define ZYNQ_QSPI_DEFAULT_NUM_CS 1
122 * struct zynq_qspi - Defines qspi driver instance
123 * @regs: Virtual address of the QSPI controller registers
124 * @refclk: Pointer to the peripheral clock
125 * @pclk: Pointer to the APB clock
127 * @txbuf: Pointer to the TX buffer
128 * @rxbuf: Pointer to the RX buffer
129 * @tx_bytes: Number of bytes left to transfer
130 * @rx_bytes: Number of bytes left to receive
131 * @data_completion: completion structure
143 struct completion data_completion;
147 * Inline functions for the QSPI controller read/write
149 static inline u32 zynq_qspi_read(struct zynq_qspi *xqspi, u32 offset)
151 return readl_relaxed(xqspi->regs + offset);
154 static inline void zynq_qspi_write(struct zynq_qspi *xqspi, u32 offset,
157 writel_relaxed(val, xqspi->regs + offset);
161 * zynq_qspi_init_hw - Initialize the hardware
162 * @xqspi: Pointer to the zynq_qspi structure
164 * The default settings of the QSPI controller's configurable parameters on
167 * - Baud rate divisor is set to 2
168 * - Tx threshold set to 1l Rx threshold set to 32
169 * - Flash memory interface mode enabled
170 * - Size of the word to be transferred as 8 bit
171 * This function performs the following actions
172 * - Disable and clear all the interrupts
173 * - Enable manual slave select
174 * - Enable manual start
175 * - Deselect all the chip select lines
176 * - Set the size of the word to be transferred as 32 bit
177 * - Set the little endian mode of TX FIFO and
178 * - Enable the QSPI controller
180 static void zynq_qspi_init_hw(struct zynq_qspi *xqspi)
184 zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET, 0);
185 zynq_qspi_write(xqspi, ZYNQ_QSPI_IDIS_OFFSET, ZYNQ_QSPI_IXR_ALL_MASK);
187 /* Disable linear mode as the boot loader may have used it */
188 zynq_qspi_write(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET, 0);
190 /* Clear the RX FIFO */
191 while (zynq_qspi_read(xqspi, ZYNQ_QSPI_STATUS_OFFSET) &
192 ZYNQ_QSPI_IXR_RXNEMTY_MASK)
193 zynq_qspi_read(xqspi, ZYNQ_QSPI_RXD_OFFSET);
195 zynq_qspi_write(xqspi, ZYNQ_QSPI_STATUS_OFFSET, ZYNQ_QSPI_IXR_ALL_MASK);
196 config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET);
197 config_reg &= ~(ZYNQ_QSPI_CONFIG_MSTREN_MASK |
198 ZYNQ_QSPI_CONFIG_CPOL_MASK |
199 ZYNQ_QSPI_CONFIG_CPHA_MASK |
200 ZYNQ_QSPI_CONFIG_BDRATE_MASK |
201 ZYNQ_QSPI_CONFIG_SSFORCE_MASK |
202 ZYNQ_QSPI_CONFIG_MANSRTEN_MASK |
203 ZYNQ_QSPI_CONFIG_MANSRT_MASK);
204 config_reg |= (ZYNQ_QSPI_CONFIG_MSTREN_MASK |
205 ZYNQ_QSPI_CONFIG_SSFORCE_MASK |
206 ZYNQ_QSPI_CONFIG_FWIDTH_MASK |
207 ZYNQ_QSPI_CONFIG_IFMODE_MASK);
208 zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);
210 zynq_qspi_write(xqspi, ZYNQ_QSPI_RX_THRESH_OFFSET,
211 ZYNQ_QSPI_RX_THRESHOLD);
212 zynq_qspi_write(xqspi, ZYNQ_QSPI_TX_THRESH_OFFSET,
213 ZYNQ_QSPI_TX_THRESHOLD);
215 zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET,
216 ZYNQ_QSPI_ENABLE_ENABLE_MASK);
219 static bool zynq_qspi_supports_op(struct spi_mem *mem,
220 const struct spi_mem_op *op)
222 if (!spi_mem_default_supports_op(mem, op))
226 * The number of address bytes should be equal to or less than 3 bytes.
228 if (op->addr.nbytes > 3)
235 * zynq_qspi_rxfifo_op - Read 1..4 bytes from RxFIFO to RX buffer
236 * @xqspi: Pointer to the zynq_qspi structure
237 * @size: Number of bytes to be read (1..4)
239 static void zynq_qspi_rxfifo_op(struct zynq_qspi *xqspi, unsigned int size)
243 data = zynq_qspi_read(xqspi, ZYNQ_QSPI_RXD_OFFSET);
246 memcpy(xqspi->rxbuf, ((u8 *)&data) + 4 - size, size);
247 xqspi->rxbuf += size;
250 xqspi->rx_bytes -= size;
251 if (xqspi->rx_bytes < 0)
256 * zynq_qspi_txfifo_op - Write 1..4 bytes from TX buffer to TxFIFO
257 * @xqspi: Pointer to the zynq_qspi structure
258 * @size: Number of bytes to be written (1..4)
260 static void zynq_qspi_txfifo_op(struct zynq_qspi *xqspi, unsigned int size)
262 static const unsigned int offset[4] = {
263 ZYNQ_QSPI_TXD_00_01_OFFSET, ZYNQ_QSPI_TXD_00_10_OFFSET,
264 ZYNQ_QSPI_TXD_00_11_OFFSET, ZYNQ_QSPI_TXD_00_00_OFFSET };
269 memcpy(&data, xqspi->txbuf, size);
270 xqspi->txbuf += size;
275 xqspi->tx_bytes -= size;
276 zynq_qspi_write(xqspi, offset[size - 1], data);
280 * zynq_qspi_chipselect - Select or deselect the chip select line
281 * @spi: Pointer to the spi_device structure
282 * @assert: 1 for select or 0 for deselect the chip select line
284 static void zynq_qspi_chipselect(struct spi_device *spi, bool assert)
286 struct spi_controller *ctlr = spi->master;
287 struct zynq_qspi *xqspi = spi_controller_get_devdata(ctlr);
290 config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET);
292 /* Select the slave */
293 config_reg &= ~ZYNQ_QSPI_CONFIG_SSCTRL_MASK;
294 config_reg |= (((~(BIT(spi->chip_select))) <<
295 ZYNQ_QSPI_SS_SHIFT) &
296 ZYNQ_QSPI_CONFIG_SSCTRL_MASK);
298 config_reg |= ZYNQ_QSPI_CONFIG_SSCTRL_MASK;
301 zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);
305 * zynq_qspi_config_op - Configure QSPI controller for specified transfer
306 * @xqspi: Pointer to the zynq_qspi structure
307 * @qspi: Pointer to the spi_device structure
309 * Sets the operational mode of QSPI controller for the next QSPI transfer and
310 * sets the requested clock frequency.
312 * Return: 0 on success and -EINVAL on invalid input parameter
314 * Note: If the requested frequency is not an exact match with what can be
315 * obtained using the prescalar value, the driver sets the clock frequency which
316 * is lower than the requested frequency (maximum lower) for the transfer. If
317 * the requested frequency is higher or lower than that is supported by the QSPI
318 * controller the driver will set the highest or lowest frequency supported by
321 static int zynq_qspi_config_op(struct zynq_qspi *xqspi, struct spi_device *spi)
323 u32 config_reg, baud_rate_val = 0;
326 * Set the clock frequency
327 * The baud rate divisor is not a direct mapping to the value written
328 * into the configuration register (config_reg[5:3])
329 * i.e. 000 - divide by 2
332 * 111 - divide by 256
334 while ((baud_rate_val < ZYNQ_QSPI_BAUD_DIV_MAX) &&
335 (clk_get_rate(xqspi->refclk) / (2 << baud_rate_val)) >
339 config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET);
341 /* Set the QSPI clock phase and clock polarity */
342 config_reg &= (~ZYNQ_QSPI_CONFIG_CPHA_MASK) &
343 (~ZYNQ_QSPI_CONFIG_CPOL_MASK);
344 if (spi->mode & SPI_CPHA)
345 config_reg |= ZYNQ_QSPI_CONFIG_CPHA_MASK;
346 if (spi->mode & SPI_CPOL)
347 config_reg |= ZYNQ_QSPI_CONFIG_CPOL_MASK;
349 config_reg &= ~ZYNQ_QSPI_CONFIG_BDRATE_MASK;
350 config_reg |= (baud_rate_val << ZYNQ_QSPI_BAUD_DIV_SHIFT);
351 zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);
357 * zynq_qspi_setup - Configure the QSPI controller
358 * @spi: Pointer to the spi_device structure
360 * Sets the operational mode of QSPI controller for the next QSPI transfer, baud
361 * rate and divisor value to setup the requested qspi clock.
363 * Return: 0 on success and error value on failure
365 static int zynq_qspi_setup_op(struct spi_device *spi)
367 struct spi_controller *ctlr = spi->master;
368 struct zynq_qspi *qspi = spi_controller_get_devdata(ctlr);
373 clk_enable(qspi->refclk);
374 clk_enable(qspi->pclk);
375 zynq_qspi_write(qspi, ZYNQ_QSPI_ENABLE_OFFSET,
376 ZYNQ_QSPI_ENABLE_ENABLE_MASK);
382 * zynq_qspi_write_op - Fills the TX FIFO with as many bytes as possible
383 * @xqspi: Pointer to the zynq_qspi structure
384 * @txcount: Maximum number of words to write
385 * @txempty: Indicates that TxFIFO is empty
387 static void zynq_qspi_write_op(struct zynq_qspi *xqspi, int txcount,
392 len = xqspi->tx_bytes;
393 if (len && len < 4) {
395 * We must empty the TxFIFO between accesses to TXD0,
399 zynq_qspi_txfifo_op(xqspi, len);
409 iowrite32_rep(xqspi->regs + ZYNQ_QSPI_TXD_00_00_OFFSET,
410 xqspi->txbuf, count);
411 xqspi->txbuf += count * 4;
413 for (k = 0; k < count; k++)
414 writel_relaxed(0, xqspi->regs +
415 ZYNQ_QSPI_TXD_00_00_OFFSET);
418 xqspi->tx_bytes -= count * 4;
422 * zynq_qspi_read_op - Drains the RX FIFO by as many bytes as possible
423 * @xqspi: Pointer to the zynq_qspi structure
424 * @rxcount: Maximum number of words to read
426 static void zynq_qspi_read_op(struct zynq_qspi *xqspi, int rxcount)
430 len = xqspi->rx_bytes - xqspi->tx_bytes;
435 ioread32_rep(xqspi->regs + ZYNQ_QSPI_RXD_OFFSET,
436 xqspi->rxbuf, count);
437 xqspi->rxbuf += count * 4;
439 for (k = 0; k < count; k++)
440 readl_relaxed(xqspi->regs + ZYNQ_QSPI_RXD_OFFSET);
442 xqspi->rx_bytes -= count * 4;
445 if (len && len < 4 && count < rxcount)
446 zynq_qspi_rxfifo_op(xqspi, len);
450 * zynq_qspi_irq - Interrupt service routine of the QSPI controller
452 * @dev_id: Pointer to the xqspi structure
454 * This function handles TX empty only.
455 * On TX empty interrupt this function reads the received data from RX FIFO and
456 * fills the TX FIFO if there is any data remaining to be transferred.
458 * Return: IRQ_HANDLED when interrupt is handled; IRQ_NONE otherwise.
460 static irqreturn_t zynq_qspi_irq(int irq, void *dev_id)
464 struct zynq_qspi *xqspi = (struct zynq_qspi *)dev_id;
466 intr_status = zynq_qspi_read(xqspi, ZYNQ_QSPI_STATUS_OFFSET);
467 zynq_qspi_write(xqspi, ZYNQ_QSPI_STATUS_OFFSET, intr_status);
469 if ((intr_status & ZYNQ_QSPI_IXR_TXNFULL_MASK) ||
470 (intr_status & ZYNQ_QSPI_IXR_RXNEMTY_MASK)) {
472 * This bit is set when Tx FIFO has < THRESHOLD entries.
473 * We have the THRESHOLD value set to 1,
474 * so this bit indicates Tx FIFO is empty.
476 txempty = !!(intr_status & ZYNQ_QSPI_IXR_TXNFULL_MASK);
477 /* Read out the data from the RX FIFO */
478 zynq_qspi_read_op(xqspi, ZYNQ_QSPI_RX_THRESHOLD);
479 if (xqspi->tx_bytes) {
480 /* There is more data to send */
481 zynq_qspi_write_op(xqspi, ZYNQ_QSPI_RX_THRESHOLD,
485 * If transfer and receive is completed then only send
488 if (!xqspi->rx_bytes) {
489 zynq_qspi_write(xqspi,
490 ZYNQ_QSPI_IDIS_OFFSET,
491 ZYNQ_QSPI_IXR_RXTX_MASK);
492 complete(&xqspi->data_completion);
502 * zynq_qspi_exec_mem_op() - Initiates the QSPI transfer
503 * @mem: the SPI memory
504 * @op: the memory operation to execute
506 * Executes a memory operation.
508 * This function first selects the chip and starts the memory operation.
510 * Return: 0 in case of success, a negative error code otherwise.
512 static int zynq_qspi_exec_mem_op(struct spi_mem *mem,
513 const struct spi_mem_op *op)
515 struct zynq_qspi *xqspi = spi_controller_get_devdata(mem->spi->master);
519 dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n",
520 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
521 op->dummy.buswidth, op->data.buswidth);
523 zynq_qspi_chipselect(mem->spi, true);
524 zynq_qspi_config_op(xqspi, mem->spi);
526 if (op->cmd.opcode) {
527 reinit_completion(&xqspi->data_completion);
528 xqspi->txbuf = (u8 *)&op->cmd.opcode;
530 xqspi->tx_bytes = sizeof(op->cmd.opcode);
531 xqspi->rx_bytes = sizeof(op->cmd.opcode);
532 zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true);
533 zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,
534 ZYNQ_QSPI_IXR_RXTX_MASK);
535 if (!wait_for_completion_interruptible_timeout(&xqspi->data_completion,
536 msecs_to_jiffies(1000)))
540 if (op->addr.nbytes) {
541 for (i = 0; i < op->addr.nbytes; i++) {
542 xqspi->txbuf[i] = op->addr.val >>
543 (8 * (op->addr.nbytes - i - 1));
546 reinit_completion(&xqspi->data_completion);
548 xqspi->tx_bytes = op->addr.nbytes;
549 xqspi->rx_bytes = op->addr.nbytes;
550 zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true);
551 zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,
552 ZYNQ_QSPI_IXR_RXTX_MASK);
553 if (!wait_for_completion_interruptible_timeout(&xqspi->data_completion,
554 msecs_to_jiffies(1000)))
558 if (op->dummy.nbytes) {
559 tmpbuf = kzalloc(op->dummy.nbytes, GFP_KERNEL);
560 memset(tmpbuf, 0xff, op->dummy.nbytes);
561 reinit_completion(&xqspi->data_completion);
562 xqspi->txbuf = tmpbuf;
564 xqspi->tx_bytes = op->dummy.nbytes;
565 xqspi->rx_bytes = op->dummy.nbytes;
566 zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true);
567 zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,
568 ZYNQ_QSPI_IXR_RXTX_MASK);
569 if (!wait_for_completion_interruptible_timeout(&xqspi->data_completion,
570 msecs_to_jiffies(1000)))
576 if (op->data.nbytes) {
577 reinit_completion(&xqspi->data_completion);
578 if (op->data.dir == SPI_MEM_DATA_OUT) {
579 xqspi->txbuf = (u8 *)op->data.buf.out;
580 xqspi->tx_bytes = op->data.nbytes;
582 xqspi->rx_bytes = op->data.nbytes;
585 xqspi->rxbuf = (u8 *)op->data.buf.in;
586 xqspi->rx_bytes = op->data.nbytes;
587 xqspi->tx_bytes = op->data.nbytes;
590 zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true);
591 zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,
592 ZYNQ_QSPI_IXR_RXTX_MASK);
593 if (!wait_for_completion_interruptible_timeout(&xqspi->data_completion,
594 msecs_to_jiffies(1000)))
597 zynq_qspi_chipselect(mem->spi, false);
602 static const struct spi_controller_mem_ops zynq_qspi_mem_ops = {
603 .supports_op = zynq_qspi_supports_op,
604 .exec_op = zynq_qspi_exec_mem_op,
608 * zynq_qspi_probe - Probe method for the QSPI driver
609 * @pdev: Pointer to the platform_device structure
611 * This function initializes the driver data structures and the hardware.
613 * Return: 0 on success and error value on failure
615 static int zynq_qspi_probe(struct platform_device *pdev)
618 struct spi_controller *ctlr;
619 struct device *dev = &pdev->dev;
620 struct device_node *np = dev->of_node;
621 struct zynq_qspi *xqspi;
624 ctlr = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
628 xqspi = spi_controller_get_devdata(ctlr);
630 platform_set_drvdata(pdev, xqspi);
631 xqspi->regs = devm_platform_ioremap_resource(pdev, 0);
632 if (IS_ERR(xqspi->regs)) {
633 ret = PTR_ERR(xqspi->regs);
637 xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
638 if (IS_ERR(xqspi->pclk)) {
639 dev_err(&pdev->dev, "pclk clock not found.\n");
640 ret = PTR_ERR(xqspi->pclk);
644 init_completion(&xqspi->data_completion);
646 xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
647 if (IS_ERR(xqspi->refclk)) {
648 dev_err(&pdev->dev, "ref_clk clock not found.\n");
649 ret = PTR_ERR(xqspi->refclk);
653 ret = clk_prepare_enable(xqspi->pclk);
655 dev_err(&pdev->dev, "Unable to enable APB clock.\n");
659 ret = clk_prepare_enable(xqspi->refclk);
661 dev_err(&pdev->dev, "Unable to enable device clock.\n");
665 /* QSPI controller initializations */
666 zynq_qspi_init_hw(xqspi);
668 xqspi->irq = platform_get_irq(pdev, 0);
669 if (xqspi->irq <= 0) {
673 ret = devm_request_irq(&pdev->dev, xqspi->irq, zynq_qspi_irq,
674 0, pdev->name, xqspi);
677 dev_err(&pdev->dev, "request_irq failed\n");
681 ret = of_property_read_u32(np, "num-cs",
684 ctlr->num_chipselect = ZYNQ_QSPI_DEFAULT_NUM_CS;
685 } else if (num_cs > ZYNQ_QSPI_DEFAULT_NUM_CS) {
686 dev_err(&pdev->dev, "anything but CS0 is not yet supported\n");
689 ctlr->num_chipselect = num_cs;
692 ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
693 SPI_TX_DUAL | SPI_TX_QUAD;
694 ctlr->mem_ops = &zynq_qspi_mem_ops;
695 ctlr->setup = zynq_qspi_setup_op;
696 ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
697 ctlr->dev.of_node = np;
698 ret = devm_spi_register_controller(&pdev->dev, ctlr);
700 dev_err(&pdev->dev, "spi_register_master failed\n");
707 clk_disable_unprepare(xqspi->refclk);
709 clk_disable_unprepare(xqspi->pclk);
711 spi_controller_put(ctlr);
717 * zynq_qspi_remove - Remove method for the QSPI driver
718 * @pdev: Pointer to the platform_device structure
720 * This function is called if a device is physically removed from the system or
721 * if the driver module is being unloaded. It frees all resources allocated to
724 * Return: 0 on success and error value on failure
726 static int zynq_qspi_remove(struct platform_device *pdev)
728 struct zynq_qspi *xqspi = platform_get_drvdata(pdev);
730 zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET, 0);
732 clk_disable_unprepare(xqspi->refclk);
733 clk_disable_unprepare(xqspi->pclk);
738 static const struct of_device_id zynq_qspi_of_match[] = {
739 { .compatible = "xlnx,zynq-qspi-1.0", },
740 { /* end of table */ }
743 MODULE_DEVICE_TABLE(of, zynq_qspi_of_match);
746 * zynq_qspi_driver - This structure defines the QSPI platform driver
748 static struct platform_driver zynq_qspi_driver = {
749 .probe = zynq_qspi_probe,
750 .remove = zynq_qspi_remove,
753 .of_match_table = zynq_qspi_of_match,
757 module_platform_driver(zynq_qspi_driver);
759 MODULE_AUTHOR("Xilinx, Inc.");
760 MODULE_DESCRIPTION("Xilinx Zynq QSPI driver");
761 MODULE_LICENSE("GPL");