1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019 Xilinx, Inc.
5 * Author: Naga Sureshkumar Relli <nagasure@xilinx.com>
9 #include <linux/delay.h>
10 #include <linux/interrupt.h>
12 #include <linux/module.h>
13 #include <linux/of_irq.h>
14 #include <linux/of_address.h>
15 #include <linux/platform_device.h>
16 #include <linux/spi/spi.h>
17 #include <linux/workqueue.h>
18 #include <linux/spi/spi-mem.h>
20 /* Register offset definitions */
21 #define ZYNQ_QSPI_CONFIG_OFFSET 0x00 /* Configuration Register, RW */
22 #define ZYNQ_QSPI_STATUS_OFFSET 0x04 /* Interrupt Status Register, RO */
23 #define ZYNQ_QSPI_IEN_OFFSET 0x08 /* Interrupt Enable Register, WO */
24 #define ZYNQ_QSPI_IDIS_OFFSET 0x0C /* Interrupt Disable Reg, WO */
25 #define ZYNQ_QSPI_IMASK_OFFSET 0x10 /* Interrupt Enabled Mask Reg,RO */
26 #define ZYNQ_QSPI_ENABLE_OFFSET 0x14 /* Enable/Disable Register, RW */
27 #define ZYNQ_QSPI_DELAY_OFFSET 0x18 /* Delay Register, RW */
28 #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst, WO */
29 #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst, WO */
30 #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst, WO */
31 #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst, WO */
32 #define ZYNQ_QSPI_RXD_OFFSET 0x20 /* Data Receive Register, RO */
33 #define ZYNQ_QSPI_SIC_OFFSET 0x24 /* Slave Idle Count Register, RW */
34 #define ZYNQ_QSPI_TX_THRESH_OFFSET 0x28 /* TX FIFO Watermark Reg, RW */
35 #define ZYNQ_QSPI_RX_THRESH_OFFSET 0x2C /* RX FIFO Watermark Reg, RW */
36 #define ZYNQ_QSPI_GPIO_OFFSET 0x30 /* GPIO Register, RW */
37 #define ZYNQ_QSPI_LINEAR_CFG_OFFSET 0xA0 /* Linear Adapter Config Ref, RW */
38 #define ZYNQ_QSPI_MOD_ID_OFFSET 0xFC /* Module ID Register, RO */
41 * QSPI Configuration Register bit Masks
43 * This register contains various control bits that effect the operation
44 * of the QSPI controller
46 #define ZYNQ_QSPI_CONFIG_IFMODE_MASK BIT(31) /* Flash Memory Interface */
47 #define ZYNQ_QSPI_CONFIG_MANSRT_MASK BIT(16) /* Manual TX Start */
48 #define ZYNQ_QSPI_CONFIG_MANSRTEN_MASK BIT(15) /* Enable Manual TX Mode */
49 #define ZYNQ_QSPI_CONFIG_SSFORCE_MASK BIT(14) /* Manual Chip Select */
50 #define ZYNQ_QSPI_CONFIG_BDRATE_MASK GENMASK(5, 3) /* Baud Rate Mask */
51 #define ZYNQ_QSPI_CONFIG_CPHA_MASK BIT(2) /* Clock Phase Control */
52 #define ZYNQ_QSPI_CONFIG_CPOL_MASK BIT(1) /* Clock Polarity Control */
53 #define ZYNQ_QSPI_CONFIG_FWIDTH_MASK GENMASK(7, 6) /* FIFO width */
54 #define ZYNQ_QSPI_CONFIG_MSTREN_MASK BIT(0) /* Master Mode */
57 * QSPI Configuration Register - Baud rate and slave select
59 * These are the values used in the calculation of baud rate divisor and
60 * setting the slave select.
62 #define ZYNQ_QSPI_CONFIG_BAUD_DIV_MAX GENMASK(2, 0) /* Baud rate maximum */
63 #define ZYNQ_QSPI_CONFIG_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift */
64 #define ZYNQ_QSPI_CONFIG_PCS BIT(10) /* Peripheral Chip Select */
67 * QSPI Interrupt Registers bit Masks
69 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
72 #define ZYNQ_QSPI_IXR_RX_OVERFLOW_MASK BIT(0) /* QSPI RX FIFO Overflow */
73 #define ZYNQ_QSPI_IXR_TXNFULL_MASK BIT(2) /* QSPI TX FIFO Overflow */
74 #define ZYNQ_QSPI_IXR_TXFULL_MASK BIT(3) /* QSPI TX FIFO is full */
75 #define ZYNQ_QSPI_IXR_RXNEMTY_MASK BIT(4) /* QSPI RX FIFO Not Empty */
76 #define ZYNQ_QSPI_IXR_RXF_FULL_MASK BIT(5) /* QSPI RX FIFO is full */
77 #define ZYNQ_QSPI_IXR_TXF_UNDRFLOW_MASK BIT(6) /* QSPI TX FIFO Underflow */
78 #define ZYNQ_QSPI_IXR_ALL_MASK (ZYNQ_QSPI_IXR_RX_OVERFLOW_MASK | \
79 ZYNQ_QSPI_IXR_TXNFULL_MASK | \
80 ZYNQ_QSPI_IXR_TXFULL_MASK | \
81 ZYNQ_QSPI_IXR_RXNEMTY_MASK | \
82 ZYNQ_QSPI_IXR_RXF_FULL_MASK | \
83 ZYNQ_QSPI_IXR_TXF_UNDRFLOW_MASK)
84 #define ZYNQ_QSPI_IXR_RXTX_MASK (ZYNQ_QSPI_IXR_TXNFULL_MASK | \
85 ZYNQ_QSPI_IXR_RXNEMTY_MASK)
88 * QSPI Enable Register bit Masks
90 * This register is used to enable or disable the QSPI controller
92 #define ZYNQ_QSPI_ENABLE_ENABLE_MASK BIT(0) /* QSPI Enable Bit Mask */
95 * QSPI Linear Configuration Register
97 * It is named Linear Configuration but it controls other modes when not in
100 #define ZYNQ_QSPI_LCFG_TWO_MEM BIT(30) /* LQSPI Two memories */
101 #define ZYNQ_QSPI_LCFG_SEP_BUS BIT(29) /* LQSPI Separate bus */
102 #define ZYNQ_QSPI_LCFG_U_PAGE BIT(28) /* LQSPI Upper Page */
104 #define ZYNQ_QSPI_LCFG_DUMMY_SHIFT 8
106 #define ZYNQ_QSPI_FAST_READ_QOUT_CODE 0x6B /* read instruction code */
107 #define ZYNQ_QSPI_FIFO_DEPTH 63 /* FIFO depth in words */
108 #define ZYNQ_QSPI_RX_THRESHOLD 32 /* Rx FIFO threshold level */
109 #define ZYNQ_QSPI_TX_THRESHOLD 1 /* Tx FIFO threshold level */
112 * The modebits configurable by the driver to make the SPI support different
115 #define ZYNQ_QSPI_MODEBITS (SPI_CPOL | SPI_CPHA)
117 /* Default number of chip selects */
118 #define ZYNQ_QSPI_DEFAULT_NUM_CS 1
121 * struct zynq_qspi - Defines qspi driver instance
122 * @regs: Virtual address of the QSPI controller registers
123 * @refclk: Pointer to the peripheral clock
124 * @pclk: Pointer to the APB clock
126 * @txbuf: Pointer to the TX buffer
127 * @rxbuf: Pointer to the RX buffer
128 * @tx_bytes: Number of bytes left to transfer
129 * @rx_bytes: Number of bytes left to receive
130 * @data_completion: completion structure
142 struct completion data_completion;
146 * Inline functions for the QSPI controller read/write
148 static inline u32 zynq_qspi_read(struct zynq_qspi *xqspi, u32 offset)
150 return readl_relaxed(xqspi->regs + offset);
153 static inline void zynq_qspi_write(struct zynq_qspi *xqspi, u32 offset,
156 writel_relaxed(val, xqspi->regs + offset);
160 * zynq_qspi_init_hw - Initialize the hardware
161 * @xqspi: Pointer to the zynq_qspi structure
163 * The default settings of the QSPI controller's configurable parameters on
166 * - Baud rate divisor is set to 2
167 * - Tx threshold set to 1l Rx threshold set to 32
168 * - Flash memory interface mode enabled
169 * - Size of the word to be transferred as 8 bit
170 * This function performs the following actions
171 * - Disable and clear all the interrupts
172 * - Enable manual slave select
173 * - Enable manual start
174 * - Deselect all the chip select lines
175 * - Set the size of the word to be transferred as 32 bit
176 * - Set the little endian mode of TX FIFO and
177 * - Enable the QSPI controller
179 static void zynq_qspi_init_hw(struct zynq_qspi *xqspi)
183 zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET, 0);
184 zynq_qspi_write(xqspi, ZYNQ_QSPI_IDIS_OFFSET, ZYNQ_QSPI_IXR_ALL_MASK);
186 /* Disable linear mode as the boot loader may have used it */
187 zynq_qspi_write(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET, 0);
189 /* Clear the RX FIFO */
190 while (zynq_qspi_read(xqspi, ZYNQ_QSPI_STATUS_OFFSET) &
191 ZYNQ_QSPI_IXR_RXNEMTY_MASK)
192 zynq_qspi_read(xqspi, ZYNQ_QSPI_RXD_OFFSET);
194 zynq_qspi_write(xqspi, ZYNQ_QSPI_STATUS_OFFSET, ZYNQ_QSPI_IXR_ALL_MASK);
195 config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET);
196 config_reg &= ~(ZYNQ_QSPI_CONFIG_MSTREN_MASK |
197 ZYNQ_QSPI_CONFIG_CPOL_MASK |
198 ZYNQ_QSPI_CONFIG_CPHA_MASK |
199 ZYNQ_QSPI_CONFIG_BDRATE_MASK |
200 ZYNQ_QSPI_CONFIG_SSFORCE_MASK |
201 ZYNQ_QSPI_CONFIG_MANSRTEN_MASK |
202 ZYNQ_QSPI_CONFIG_MANSRT_MASK);
203 config_reg |= (ZYNQ_QSPI_CONFIG_MSTREN_MASK |
204 ZYNQ_QSPI_CONFIG_SSFORCE_MASK |
205 ZYNQ_QSPI_CONFIG_FWIDTH_MASK |
206 ZYNQ_QSPI_CONFIG_IFMODE_MASK);
207 zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);
209 zynq_qspi_write(xqspi, ZYNQ_QSPI_RX_THRESH_OFFSET,
210 ZYNQ_QSPI_RX_THRESHOLD);
211 zynq_qspi_write(xqspi, ZYNQ_QSPI_TX_THRESH_OFFSET,
212 ZYNQ_QSPI_TX_THRESHOLD);
214 zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET,
215 ZYNQ_QSPI_ENABLE_ENABLE_MASK);
218 static bool zynq_qspi_supports_op(struct spi_mem *mem,
219 const struct spi_mem_op *op)
221 if (!spi_mem_default_supports_op(mem, op))
225 * The number of address bytes should be equal to or less than 3 bytes.
227 if (op->addr.nbytes > 3)
234 * zynq_qspi_rxfifo_op - Read 1..4 bytes from RxFIFO to RX buffer
235 * @xqspi: Pointer to the zynq_qspi structure
236 * @size: Number of bytes to be read (1..4)
238 static void zynq_qspi_rxfifo_op(struct zynq_qspi *xqspi, unsigned int size)
242 data = zynq_qspi_read(xqspi, ZYNQ_QSPI_RXD_OFFSET);
245 memcpy(xqspi->rxbuf, ((u8 *)&data) + 4 - size, size);
246 xqspi->rxbuf += size;
249 xqspi->rx_bytes -= size;
250 if (xqspi->rx_bytes < 0)
255 * zynq_qspi_txfifo_op - Write 1..4 bytes from TX buffer to TxFIFO
256 * @xqspi: Pointer to the zynq_qspi structure
257 * @size: Number of bytes to be written (1..4)
259 static void zynq_qspi_txfifo_op(struct zynq_qspi *xqspi, unsigned int size)
261 static const unsigned int offset[4] = {
262 ZYNQ_QSPI_TXD_00_01_OFFSET, ZYNQ_QSPI_TXD_00_10_OFFSET,
263 ZYNQ_QSPI_TXD_00_11_OFFSET, ZYNQ_QSPI_TXD_00_00_OFFSET };
268 memcpy(&data, xqspi->txbuf, size);
269 xqspi->txbuf += size;
274 xqspi->tx_bytes -= size;
275 zynq_qspi_write(xqspi, offset[size - 1], data);
279 * zynq_qspi_chipselect - Select or deselect the chip select line
280 * @spi: Pointer to the spi_device structure
281 * @assert: 1 for select or 0 for deselect the chip select line
283 static void zynq_qspi_chipselect(struct spi_device *spi, bool assert)
285 struct spi_controller *ctlr = spi->master;
286 struct zynq_qspi *xqspi = spi_controller_get_devdata(ctlr);
289 /* Ground the line to assert the CS */
290 config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET);
292 config_reg &= ~ZYNQ_QSPI_CONFIG_PCS;
294 config_reg |= ZYNQ_QSPI_CONFIG_PCS;
296 zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);
300 * zynq_qspi_config_op - Configure QSPI controller for specified transfer
301 * @xqspi: Pointer to the zynq_qspi structure
302 * @qspi: Pointer to the spi_device structure
304 * Sets the operational mode of QSPI controller for the next QSPI transfer and
305 * sets the requested clock frequency.
307 * Return: 0 on success and -EINVAL on invalid input parameter
309 * Note: If the requested frequency is not an exact match with what can be
310 * obtained using the prescalar value, the driver sets the clock frequency which
311 * is lower than the requested frequency (maximum lower) for the transfer. If
312 * the requested frequency is higher or lower than that is supported by the QSPI
313 * controller the driver will set the highest or lowest frequency supported by
316 static int zynq_qspi_config_op(struct zynq_qspi *xqspi, struct spi_device *spi)
318 u32 config_reg, baud_rate_val = 0;
321 * Set the clock frequency
322 * The baud rate divisor is not a direct mapping to the value written
323 * into the configuration register (config_reg[5:3])
324 * i.e. 000 - divide by 2
327 * 111 - divide by 256
329 while ((baud_rate_val < ZYNQ_QSPI_CONFIG_BAUD_DIV_MAX) &&
330 (clk_get_rate(xqspi->refclk) / (2 << baud_rate_val)) >
334 config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET);
336 /* Set the QSPI clock phase and clock polarity */
337 config_reg &= (~ZYNQ_QSPI_CONFIG_CPHA_MASK) &
338 (~ZYNQ_QSPI_CONFIG_CPOL_MASK);
339 if (spi->mode & SPI_CPHA)
340 config_reg |= ZYNQ_QSPI_CONFIG_CPHA_MASK;
341 if (spi->mode & SPI_CPOL)
342 config_reg |= ZYNQ_QSPI_CONFIG_CPOL_MASK;
344 config_reg &= ~ZYNQ_QSPI_CONFIG_BDRATE_MASK;
345 config_reg |= (baud_rate_val << ZYNQ_QSPI_CONFIG_BAUD_DIV_SHIFT);
346 zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);
352 * zynq_qspi_setup - Configure the QSPI controller
353 * @spi: Pointer to the spi_device structure
355 * Sets the operational mode of QSPI controller for the next QSPI transfer, baud
356 * rate and divisor value to setup the requested qspi clock.
358 * Return: 0 on success and error value on failure
360 static int zynq_qspi_setup_op(struct spi_device *spi)
362 struct spi_controller *ctlr = spi->master;
363 struct zynq_qspi *qspi = spi_controller_get_devdata(ctlr);
368 clk_enable(qspi->refclk);
369 clk_enable(qspi->pclk);
370 zynq_qspi_write(qspi, ZYNQ_QSPI_ENABLE_OFFSET,
371 ZYNQ_QSPI_ENABLE_ENABLE_MASK);
377 * zynq_qspi_write_op - Fills the TX FIFO with as many bytes as possible
378 * @xqspi: Pointer to the zynq_qspi structure
379 * @txcount: Maximum number of words to write
380 * @txempty: Indicates that TxFIFO is empty
382 static void zynq_qspi_write_op(struct zynq_qspi *xqspi, int txcount,
387 len = xqspi->tx_bytes;
388 if (len && len < 4) {
390 * We must empty the TxFIFO between accesses to TXD0,
394 zynq_qspi_txfifo_op(xqspi, len);
404 iowrite32_rep(xqspi->regs + ZYNQ_QSPI_TXD_00_00_OFFSET,
405 xqspi->txbuf, count);
406 xqspi->txbuf += count * 4;
408 for (k = 0; k < count; k++)
409 writel_relaxed(0, xqspi->regs +
410 ZYNQ_QSPI_TXD_00_00_OFFSET);
413 xqspi->tx_bytes -= count * 4;
417 * zynq_qspi_read_op - Drains the RX FIFO by as many bytes as possible
418 * @xqspi: Pointer to the zynq_qspi structure
419 * @rxcount: Maximum number of words to read
421 static void zynq_qspi_read_op(struct zynq_qspi *xqspi, int rxcount)
425 len = xqspi->rx_bytes - xqspi->tx_bytes;
430 ioread32_rep(xqspi->regs + ZYNQ_QSPI_RXD_OFFSET,
431 xqspi->rxbuf, count);
432 xqspi->rxbuf += count * 4;
434 for (k = 0; k < count; k++)
435 readl_relaxed(xqspi->regs + ZYNQ_QSPI_RXD_OFFSET);
437 xqspi->rx_bytes -= count * 4;
440 if (len && len < 4 && count < rxcount)
441 zynq_qspi_rxfifo_op(xqspi, len);
445 * zynq_qspi_irq - Interrupt service routine of the QSPI controller
447 * @dev_id: Pointer to the xqspi structure
449 * This function handles TX empty only.
450 * On TX empty interrupt this function reads the received data from RX FIFO and
451 * fills the TX FIFO if there is any data remaining to be transferred.
453 * Return: IRQ_HANDLED when interrupt is handled; IRQ_NONE otherwise.
455 static irqreturn_t zynq_qspi_irq(int irq, void *dev_id)
459 struct zynq_qspi *xqspi = (struct zynq_qspi *)dev_id;
461 intr_status = zynq_qspi_read(xqspi, ZYNQ_QSPI_STATUS_OFFSET);
462 zynq_qspi_write(xqspi, ZYNQ_QSPI_STATUS_OFFSET, intr_status);
464 if ((intr_status & ZYNQ_QSPI_IXR_TXNFULL_MASK) ||
465 (intr_status & ZYNQ_QSPI_IXR_RXNEMTY_MASK)) {
467 * This bit is set when Tx FIFO has < THRESHOLD entries.
468 * We have the THRESHOLD value set to 1,
469 * so this bit indicates Tx FIFO is empty.
471 txempty = !!(intr_status & ZYNQ_QSPI_IXR_TXNFULL_MASK);
472 /* Read out the data from the RX FIFO */
473 zynq_qspi_read_op(xqspi, ZYNQ_QSPI_RX_THRESHOLD);
474 if (xqspi->tx_bytes) {
475 /* There is more data to send */
476 zynq_qspi_write_op(xqspi, ZYNQ_QSPI_RX_THRESHOLD,
480 * If transfer and receive is completed then only send
483 if (!xqspi->rx_bytes) {
484 zynq_qspi_write(xqspi,
485 ZYNQ_QSPI_IDIS_OFFSET,
486 ZYNQ_QSPI_IXR_RXTX_MASK);
487 complete(&xqspi->data_completion);
497 * zynq_qspi_exec_mem_op() - Initiates the QSPI transfer
498 * @mem: the SPI memory
499 * @op: the memory operation to execute
501 * Executes a memory operation.
503 * This function first selects the chip and starts the memory operation.
505 * Return: 0 in case of success, a negative error code otherwise.
507 static int zynq_qspi_exec_mem_op(struct spi_mem *mem,
508 const struct spi_mem_op *op)
510 struct zynq_qspi *xqspi = spi_controller_get_devdata(mem->spi->master);
514 dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n",
515 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
516 op->dummy.buswidth, op->data.buswidth);
518 zynq_qspi_chipselect(mem->spi, true);
519 zynq_qspi_config_op(xqspi, mem->spi);
521 if (op->cmd.opcode) {
522 reinit_completion(&xqspi->data_completion);
523 xqspi->txbuf = (u8 *)&op->cmd.opcode;
525 xqspi->tx_bytes = sizeof(op->cmd.opcode);
526 xqspi->rx_bytes = sizeof(op->cmd.opcode);
527 zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true);
528 zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,
529 ZYNQ_QSPI_IXR_RXTX_MASK);
530 if (!wait_for_completion_interruptible_timeout(&xqspi->data_completion,
531 msecs_to_jiffies(1000)))
535 if (op->addr.nbytes) {
536 for (i = 0; i < op->addr.nbytes; i++) {
537 xqspi->txbuf[i] = op->addr.val >>
538 (8 * (op->addr.nbytes - i - 1));
541 reinit_completion(&xqspi->data_completion);
543 xqspi->tx_bytes = op->addr.nbytes;
544 xqspi->rx_bytes = op->addr.nbytes;
545 zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true);
546 zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,
547 ZYNQ_QSPI_IXR_RXTX_MASK);
548 if (!wait_for_completion_interruptible_timeout(&xqspi->data_completion,
549 msecs_to_jiffies(1000)))
553 if (op->dummy.nbytes) {
554 tmpbuf = kzalloc(op->dummy.nbytes, GFP_KERNEL);
555 memset(tmpbuf, 0xff, op->dummy.nbytes);
556 reinit_completion(&xqspi->data_completion);
557 xqspi->txbuf = tmpbuf;
559 xqspi->tx_bytes = op->dummy.nbytes;
560 xqspi->rx_bytes = op->dummy.nbytes;
561 zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true);
562 zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,
563 ZYNQ_QSPI_IXR_RXTX_MASK);
564 if (!wait_for_completion_interruptible_timeout(&xqspi->data_completion,
565 msecs_to_jiffies(1000)))
571 if (op->data.nbytes) {
572 reinit_completion(&xqspi->data_completion);
573 if (op->data.dir == SPI_MEM_DATA_OUT) {
574 xqspi->txbuf = (u8 *)op->data.buf.out;
575 xqspi->tx_bytes = op->data.nbytes;
577 xqspi->rx_bytes = op->data.nbytes;
580 xqspi->rxbuf = (u8 *)op->data.buf.in;
581 xqspi->rx_bytes = op->data.nbytes;
582 xqspi->tx_bytes = op->data.nbytes;
585 zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true);
586 zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,
587 ZYNQ_QSPI_IXR_RXTX_MASK);
588 if (!wait_for_completion_interruptible_timeout(&xqspi->data_completion,
589 msecs_to_jiffies(1000)))
592 zynq_qspi_chipselect(mem->spi, false);
597 static const struct spi_controller_mem_ops zynq_qspi_mem_ops = {
598 .supports_op = zynq_qspi_supports_op,
599 .exec_op = zynq_qspi_exec_mem_op,
603 * zynq_qspi_probe - Probe method for the QSPI driver
604 * @pdev: Pointer to the platform_device structure
606 * This function initializes the driver data structures and the hardware.
608 * Return: 0 on success and error value on failure
610 static int zynq_qspi_probe(struct platform_device *pdev)
613 struct spi_controller *ctlr;
614 struct device *dev = &pdev->dev;
615 struct device_node *np = dev->of_node;
616 struct zynq_qspi *xqspi;
619 ctlr = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
623 xqspi = spi_controller_get_devdata(ctlr);
625 platform_set_drvdata(pdev, xqspi);
626 xqspi->regs = devm_platform_ioremap_resource(pdev, 0);
627 if (IS_ERR(xqspi->regs)) {
628 ret = PTR_ERR(xqspi->regs);
632 xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
633 if (IS_ERR(xqspi->pclk)) {
634 dev_err(&pdev->dev, "pclk clock not found.\n");
635 ret = PTR_ERR(xqspi->pclk);
639 init_completion(&xqspi->data_completion);
641 xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
642 if (IS_ERR(xqspi->refclk)) {
643 dev_err(&pdev->dev, "ref_clk clock not found.\n");
644 ret = PTR_ERR(xqspi->refclk);
648 ret = clk_prepare_enable(xqspi->pclk);
650 dev_err(&pdev->dev, "Unable to enable APB clock.\n");
654 ret = clk_prepare_enable(xqspi->refclk);
656 dev_err(&pdev->dev, "Unable to enable device clock.\n");
660 xqspi->irq = platform_get_irq(pdev, 0);
661 if (xqspi->irq <= 0) {
665 ret = devm_request_irq(&pdev->dev, xqspi->irq, zynq_qspi_irq,
666 0, pdev->name, xqspi);
669 dev_err(&pdev->dev, "request_irq failed\n");
673 ret = of_property_read_u32(np, "num-cs",
676 ctlr->num_chipselect = ZYNQ_QSPI_DEFAULT_NUM_CS;
677 } else if (num_cs > ZYNQ_QSPI_DEFAULT_NUM_CS) {
678 dev_err(&pdev->dev, "anything but CS0 is not yet supported\n");
681 ctlr->num_chipselect = num_cs;
684 ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
685 SPI_TX_DUAL | SPI_TX_QUAD;
686 ctlr->mem_ops = &zynq_qspi_mem_ops;
687 ctlr->setup = zynq_qspi_setup_op;
688 ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
689 ctlr->dev.of_node = np;
691 /* QSPI controller initializations */
692 zynq_qspi_init_hw(xqspi);
694 ret = devm_spi_register_controller(&pdev->dev, ctlr);
696 dev_err(&pdev->dev, "spi_register_master failed\n");
703 clk_disable_unprepare(xqspi->refclk);
705 clk_disable_unprepare(xqspi->pclk);
707 spi_controller_put(ctlr);
713 * zynq_qspi_remove - Remove method for the QSPI driver
714 * @pdev: Pointer to the platform_device structure
716 * This function is called if a device is physically removed from the system or
717 * if the driver module is being unloaded. It frees all resources allocated to
720 * Return: 0 on success and error value on failure
722 static int zynq_qspi_remove(struct platform_device *pdev)
724 struct zynq_qspi *xqspi = platform_get_drvdata(pdev);
726 zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET, 0);
728 clk_disable_unprepare(xqspi->refclk);
729 clk_disable_unprepare(xqspi->pclk);
734 static const struct of_device_id zynq_qspi_of_match[] = {
735 { .compatible = "xlnx,zynq-qspi-1.0", },
736 { /* end of table */ }
739 MODULE_DEVICE_TABLE(of, zynq_qspi_of_match);
742 * zynq_qspi_driver - This structure defines the QSPI platform driver
744 static struct platform_driver zynq_qspi_driver = {
745 .probe = zynq_qspi_probe,
746 .remove = zynq_qspi_remove,
749 .of_match_table = zynq_qspi_of_match,
753 module_platform_driver(zynq_qspi_driver);
755 MODULE_AUTHOR("Xilinx, Inc.");
756 MODULE_DESCRIPTION("Xilinx Zynq QSPI driver");
757 MODULE_LICENSE("GPL");