drivers/staging/ccree/cc_hw_queue_defs.h

   1 /*
   2  * Copyright (C) 2012-2017 ARM Limited or its affiliates.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #ifndef __CC_HW_QUEUE_DEFS_H__
  18 #define __CC_HW_QUEUE_DEFS_H__
  19
  20 #include "cc_regs.h"
  21 #include "dx_crys_kernel.h"
  22
  23 #ifdef __KERNEL__
  24 #include <linux/types.h>
  25 #define UINT32_MAX 0xFFFFFFFFL
  26 #define INT32_MAX  0x7FFFFFFFL
  27 #define UINT16_MAX 0xFFFFL
  28 #else
  29 #include <stdint.h>
  30 #endif
  31
  32 /******************************************************************************
  33 *                               DEFINITIONS
  34 ******************************************************************************/
  35
  36
  37 /* Dma AXI Secure bit */
  38 #define AXI_SECURE      0
  39 #define AXI_NOT_SECURE  1
  40
  41 #define HW_DESC_SIZE_WORDS              6
  42 #define HW_QUEUE_SLOTS_MAX              15 /* Max. available slots in HW queue */
  43
  44 #define _HW_DESC_MONITOR_KICK 0x7FFFC00
  45
  46 /******************************************************************************
  47 *                               TYPE DEFINITIONS
  48 ******************************************************************************/
  49
  50 typedef struct HwDesc {
  51         uint32_t word[HW_DESC_SIZE_WORDS];
  52 } HwDesc_s;
  53
  54 typedef enum DescDirection {
  55         DESC_DIRECTION_ILLEGAL = -1,
  56         DESC_DIRECTION_ENCRYPT_ENCRYPT = 0,
  57         DESC_DIRECTION_DECRYPT_DECRYPT = 1,
  58         DESC_DIRECTION_DECRYPT_ENCRYPT = 3,
  59         DESC_DIRECTION_END = INT32_MAX,
  60 }DescDirection_t;
  61
  62 typedef enum DmaMode {
  63         DMA_MODE_NULL           = -1,
  64         NO_DMA                  = 0,
  65         DMA_SRAM                = 1,
  66         DMA_DLLI                = 2,
  67         DMA_MLLI                = 3,
  68         DmaMode_OPTIONTS,
  69         DmaMode_END             = INT32_MAX,
  70 }DmaMode_t;
  71
  72 typedef enum FlowMode {
  73         FLOW_MODE_NULL          = -1,
  74         /* data flows */
  75         BYPASS                  = 0,
  76         DIN_AES_DOUT            = 1,
  77         AES_to_HASH             = 2,
  78         AES_and_HASH            = 3,
  79         DIN_DES_DOUT            = 4,
  80         DES_to_HASH             = 5,
  81         DES_and_HASH            = 6,
  82         DIN_HASH                = 7,
  83         DIN_HASH_and_BYPASS     = 8,
  84         AESMAC_and_BYPASS       = 9,
  85         AES_to_HASH_and_DOUT    = 10,
  86         DIN_RC4_DOUT            = 11,
  87         DES_to_HASH_and_DOUT    = 12,
  88         AES_to_AES_to_HASH_and_DOUT     = 13,
  89         AES_to_AES_to_HASH      = 14,
  90         AES_to_HASH_and_AES     = 15,
  91         DIN_MULTI2_DOUT         = 16,
  92         DIN_AES_AESMAC          = 17,
  93         HASH_to_DOUT            = 18,
  94         /* setup flows */
  95         S_DIN_to_AES            = 32,
  96         S_DIN_to_AES2           = 33,
  97         S_DIN_to_DES            = 34,
  98         S_DIN_to_RC4            = 35,
  99         S_DIN_to_MULTI2         = 36,
 100         S_DIN_to_HASH           = 37,
 101         S_AES_to_DOUT           = 38,
 102         S_AES2_to_DOUT          = 39,
 103         S_RC4_to_DOUT           = 41,
 104         S_DES_to_DOUT           = 42,
 105         S_HASH_to_DOUT          = 43,
 106         SET_FLOW_ID             = 44,
 107         FlowMode_OPTIONTS,
 108         FlowMode_END = INT32_MAX,
 109 }FlowMode_t;
 110
 111 typedef enum TunnelOp {
 112         TUNNEL_OP_INVALID = -1,
 113         TUNNEL_OFF = 0,
 114         TUNNEL_ON = 1,
 115         TunnelOp_OPTIONS,
 116         TunnelOp_END = INT32_MAX,
 117 } TunnelOp_t;
 118
 119 typedef enum SetupOp {
 120         SETUP_LOAD_NOP          = 0,
 121         SETUP_LOAD_STATE0       = 1,
 122         SETUP_LOAD_STATE1       = 2,
 123         SETUP_LOAD_STATE2       = 3,
 124         SETUP_LOAD_KEY0         = 4,
 125         SETUP_LOAD_XEX_KEY      = 5,
 126         SETUP_WRITE_STATE0      = 8,
 127         SETUP_WRITE_STATE1      = 9,
 128         SETUP_WRITE_STATE2      = 10,
 129         SETUP_WRITE_STATE3      = 11,
 130         setupOp_OPTIONTS,
 131         setupOp_END = INT32_MAX,
 132 }SetupOp_t;
 133
 134 enum AesMacSelector {
 135         AES_SK = 1,
 136         AES_CMAC_INIT = 2,
 137         AES_CMAC_SIZE0 = 3,
 138         AesMacEnd = INT32_MAX,
 139 };
 140
 141 #define HW_KEY_MASK_CIPHER_DO     0x3
 142 #define HW_KEY_SHIFT_CIPHER_CFG2  2
 143
 144
 145 /* HwCryptoKey[1:0] is mapped to cipher_do[1:0] */
 146 /* HwCryptoKey[2:3] is mapped to cipher_config2[1:0] */
 147 typedef enum HwCryptoKey {
 148         USER_KEY = 0,                   /* 0x0000 */
 149         ROOT_KEY = 1,                   /* 0x0001 */
 150         PROVISIONING_KEY = 2,           /* 0x0010 */ /* ==KCP */
 151         SESSION_KEY = 3,                /* 0x0011 */
 152         RESERVED_KEY = 4,               /* NA */
 153         PLATFORM_KEY = 5,               /* 0x0101 */
 154         CUSTOMER_KEY = 6,               /* 0x0110 */
 155         KFDE0_KEY = 7,                  /* 0x0111 */
 156         KFDE1_KEY = 9,                  /* 0x1001 */
 157         KFDE2_KEY = 10,                 /* 0x1010 */
 158         KFDE3_KEY = 11,                 /* 0x1011 */
 159         END_OF_KEYS = INT32_MAX,
 160 }HwCryptoKey_t;
 161
 162 typedef enum HwAesKeySize {
 163         AES_128_KEY = 0,
 164         AES_192_KEY = 1,
 165         AES_256_KEY = 2,
 166         END_OF_AES_KEYS = INT32_MAX,
 167 }HwAesKeySize_t;
 168
 169 typedef enum HwDesKeySize {
 170         DES_ONE_KEY = 0,
 171         DES_TWO_KEYS = 1,
 172         DES_THREE_KEYS = 2,
 173         END_OF_DES_KEYS = INT32_MAX,
 174 }HwDesKeySize_t;
 175
 176 /*****************************/
 177 /* Descriptor packing macros */
 178 /*****************************/
 179
 180 #define GET_HW_Q_DESC_WORD_IDX(descWordIdx) (CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD ## descWordIdx) )
 181
 182 #define HW_DESC_INIT(pDesc)  do { \
 183         (pDesc)->word[0] = 0;     \
 184         (pDesc)->word[1] = 0;     \
 185         (pDesc)->word[2] = 0;     \
 186         (pDesc)->word[3] = 0;     \
 187         (pDesc)->word[4] = 0;     \
 188         (pDesc)->word[5] = 0;     \
 189 } while (0)
 190
 191 /*!
 192  * This macro indicates the end of current HW descriptors flow and release the HW engines.
 193  *
 194  * \param pDesc pointer HW descriptor struct
 195  */
 196 #define HW_DESC_SET_QUEUE_LAST_IND(pDesc)                                                               \
 197         do {                                                                                            \
 198                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, QUEUE_LAST_IND, (pDesc)->word[3], 1);   \
 199         } while (0)
 200
 201 /*!
 202  * This macro signs the end of HW descriptors flow by asking for completion ack, and release the HW engines
 203  *
 204  * \param pDesc pointer HW descriptor struct
 205  */
 206 #define HW_DESC_SET_ACK_LAST(pDesc)                                                                     \
 207         do {                                                                                            \
 208                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, QUEUE_LAST_IND, (pDesc)->word[3], 1);   \
 209                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, ACK_NEEDED, (pDesc)->word[4], 1);       \
 210         } while (0)
 211
 212
 213 #define MSB64(_addr) (sizeof(_addr) == 4 ? 0 : ((_addr) >> 32)&UINT16_MAX)
 214
 215 /*!
 216  * This macro sets the DIN field of a HW descriptors
 217  *
 218  * \param pDesc pointer HW descriptor struct
 219  * \param dmaMode The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT
 220  * \param dinAdr DIN address
 221  * \param dinSize Data size in bytes
 222  * \param axiNs AXI secure bit
 223  */
 224 #define HW_DESC_SET_DIN_TYPE(pDesc, dmaMode, dinAdr, dinSize, axiNs)                                                            \
 225         do {                                                                                                                    \
 226                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0, VALUE, (pDesc)->word[0], (dinAdr)&UINT32_MAX );                 \
 227                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD5, DIN_ADDR_HIGH, (pDesc)->word[5], MSB64(dinAdr) );               \
 228                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_DMA_MODE, (pDesc)->word[1], (dmaMode));                     \
 229                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_SIZE, (pDesc)->word[1], (dinSize));                         \
 230                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, NS_BIT, (pDesc)->word[1], (axiNs));                             \
 231         } while (0)
 232
 233
 234 /*!
 235  * This macro sets the DIN field of a HW descriptors to NO DMA mode. Used for NOP descriptor, register patches and
 236  * other special modes
 237  *
 238  * \param pDesc pointer HW descriptor struct
 239  * \param dinAdr DIN address
 240  * \param dinSize Data size in bytes
 241  */
 242 #define HW_DESC_SET_DIN_NO_DMA(pDesc, dinAdr, dinSize)                                                                  \
 243         do {                                                                                                            \
 244                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0, VALUE, (pDesc)->word[0], (uint32_t)(dinAdr));           \
 245                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_SIZE, (pDesc)->word[1], (dinSize));                 \
 246         } while (0)
 247
 248 /*!
 249  * This macro sets the DIN field of a HW descriptors to SRAM mode.
 250  * Note: No need to check SRAM alignment since host requests do not use SRAM and
 251  * adaptor will enforce alignment check.
 252  *
 253  * \param pDesc pointer HW descriptor struct
 254  * \param dinAdr DIN address
 255  * \param dinSize Data size in bytes
 256  */
 257 #define HW_DESC_SET_DIN_SRAM(pDesc, dinAdr, dinSize)                                                                    \
 258         do {                                                                                                            \
 259                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0, VALUE, (pDesc)->word[0], (uint32_t)(dinAdr));           \
 260                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_DMA_MODE, (pDesc)->word[1], DMA_SRAM);              \
 261                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_SIZE, (pDesc)->word[1], (dinSize));                 \
 262         } while (0)
 263
 264 /*! This macro sets the DIN field of a HW descriptors to CONST mode
 265  *
 266  * \param pDesc pointer HW descriptor struct
 267  * \param val DIN const value
 268  * \param dinSize Data size in bytes
 269  */
 270 #define HW_DESC_SET_DIN_CONST(pDesc, val, dinSize)                                                                      \
 271         do {                                                                                                            \
 272                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0, VALUE, (pDesc)->word[0], (uint32_t)(val));              \
 273                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_CONST_VALUE, (pDesc)->word[1], 1);                  \
 274                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_DMA_MODE, (pDesc)->word[1], DMA_SRAM);              \
 275                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_SIZE, (pDesc)->word[1], (dinSize));                 \
 276         } while (0)
 277
 278 /*!
 279  * This macro sets the DIN not last input data indicator
 280  *
 281  * \param pDesc pointer HW descriptor struct
 282  */
 283 #define HW_DESC_SET_DIN_NOT_LAST_INDICATION(pDesc)                                                                      \
 284         do {                                                                                                            \
 285                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, NOT_LAST, (pDesc)->word[1], 1);                         \
 286         } while (0)
 287
 288 /*!
 289  * This macro sets the DOUT field of a HW descriptors
 290  *
 291  * \param pDesc pointer HW descriptor struct
 292  * \param dmaMode The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT
 293  * \param doutAdr DOUT address
 294  * \param doutSize Data size in bytes
 295  * \param axiNs AXI secure bit
 296  */
 297 #define HW_DESC_SET_DOUT_TYPE(pDesc, dmaMode, doutAdr, doutSize, axiNs)                                                 \
 298         do {                                                                                                            \
 299                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (doutAdr)&UINT32_MAX );                \
 300                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD5, DOUT_ADDR_HIGH, (pDesc)->word[5], MSB64(doutAdr) );     \
 301                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_DMA_MODE, (pDesc)->word[3], (dmaMode));            \
 302                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize));               \
 303                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, NS_BIT, (pDesc)->word[3], (axiNs));                     \
 304         } while (0)
 305
 306 /*!
 307  * This macro sets the DOUT field of a HW descriptors to DLLI type
 308  * The LAST INDICATION is provided by the user
 309  *
 310  * \param pDesc pointer HW descriptor struct
 311  * \param doutAdr DOUT address
 312  * \param doutSize Data size in bytes
 313  * \param lastInd The last indication bit
 314  * \param axiNs AXI secure bit
 315  */
 316 #define HW_DESC_SET_DOUT_DLLI(pDesc, doutAdr, doutSize, axiNs ,lastInd)                                                         \
 317         do {                                                                                                                    \
 318                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (doutAdr)&UINT32_MAX );                \
 319                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD5, DOUT_ADDR_HIGH, (pDesc)->word[5], MSB64(doutAdr) );     \
 320                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_DMA_MODE, (pDesc)->word[3], DMA_DLLI);                     \
 321                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize));                       \
 322                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_LAST_IND, (pDesc)->word[3], lastInd);                      \
 323                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, NS_BIT, (pDesc)->word[3], (axiNs));                             \
 324         } while (0)
 325
 326 /*!
 327  * This macro sets the DOUT field of a HW descriptors to DLLI type
 328  * The LAST INDICATION is provided by the user
 329  *
 330  * \param pDesc pointer HW descriptor struct
 331  * \param doutAdr DOUT address
 332  * \param doutSize Data size in bytes
 333  * \param lastInd The last indication bit
 334  * \param axiNs AXI secure bit
 335  */
 336 #define HW_DESC_SET_DOUT_MLLI(pDesc, doutAdr, doutSize, axiNs ,lastInd)                                                         \
 337         do {                                                                                                                    \
 338                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (doutAdr)&UINT32_MAX );                \
 339                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD5, DOUT_ADDR_HIGH, (pDesc)->word[5], MSB64(doutAdr) );     \
 340                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_DMA_MODE, (pDesc)->word[3], DMA_MLLI);                     \
 341                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize));                       \
 342                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_LAST_IND, (pDesc)->word[3], lastInd);                      \
 343                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, NS_BIT, (pDesc)->word[3], (axiNs));                             \
 344         } while (0)
 345
 346 /*!
 347  * This macro sets the DOUT field of a HW descriptors to NO DMA mode. Used for NOP descriptor, register patches and
 348  * other special modes
 349  *
 350  * \param pDesc pointer HW descriptor struct
 351  * \param doutAdr DOUT address
 352  * \param doutSize Data size in bytes
 353  * \param registerWriteEnable Enables a write operation to a register
 354  */
 355 #define HW_DESC_SET_DOUT_NO_DMA(pDesc, doutAdr, doutSize, registerWriteEnable)                                                  \
 356         do {                                                                                                                    \
 357                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (uint32_t)(doutAdr));                  \
 358                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize));                       \
 359                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_LAST_IND, (pDesc)->word[3], (registerWriteEnable));        \
 360         } while (0)
 361
 362 /*!
 363  * This macro sets the word for the XOR operation.
 364  *
 365  * \param pDesc pointer HW descriptor struct
 366  * \param xorVal xor data value
 367  */
 368 #define HW_DESC_SET_XOR_VAL(pDesc, xorVal)                                                                              \
 369         do {                                                                                                            \
 370                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (uint32_t)(xorVal));           \
 371         } while (0)
 372
 373 /*!
 374  * This macro sets the XOR indicator bit in the descriptor
 375  *
 376  * \param pDesc pointer HW descriptor struct
 377  */
 378 #define HW_DESC_SET_XOR_ACTIVE(pDesc)                                                                                   \
 379         do {                                                                                                            \
 380                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, HASH_XOR_BIT, (pDesc)->word[3], 1);                     \
 381         } while (0)
 382
 383 /*!
 384  * This macro selects the AES engine instead of HASH engine when setting up combined mode with AES XCBC MAC
 385  *
 386  * \param pDesc pointer HW descriptor struct
 387  */
 388 #define HW_DESC_SET_AES_NOT_HASH_MODE(pDesc)                                                                            \
 389         do {                                                                                                            \
 390                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, AES_SEL_N_HASH, (pDesc)->word[4], 1);                   \
 391         } while (0)
 392
 393 /*!
 394  * This macro sets the DOUT field of a HW descriptors to SRAM mode
 395  * Note: No need to check SRAM alignment since host requests do not use SRAM and
 396  * adaptor will enforce alignment check.
 397  *
 398  * \param pDesc pointer HW descriptor struct
 399  * \param doutAdr DOUT address
 400  * \param doutSize Data size in bytes
 401  */
 402 #define HW_DESC_SET_DOUT_SRAM(pDesc, doutAdr, doutSize)                                                                 \
 403         do {                                                                                                            \
 404                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (uint32_t)(doutAdr));          \
 405                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_DMA_MODE, (pDesc)->word[3], DMA_SRAM);             \
 406                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize));               \
 407         } while (0)
 408
 409
 410 /*!
 411  * This macro sets the data unit size for XEX mode in data_out_addr[15:0]
 412  *
 413  * \param pDesc pointer HW descriptor struct
 414  * \param dataUnitSize data unit size for XEX mode
 415  */
 416 #define HW_DESC_SET_XEX_DATA_UNIT_SIZE(pDesc, dataUnitSize)                                                             \
 417         do {                                                                                                            \
 418                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (uint32_t)(dataUnitSize));     \
 419         } while (0)
 420
 421 /*!
 422  * This macro sets the number of rounds for Multi2 in data_out_addr[15:0]
 423  *
 424  * \param pDesc pointer HW descriptor struct
 425  * \param numRounds number of rounds for Multi2
 426 */
 427 #define HW_DESC_SET_MULTI2_NUM_ROUNDS(pDesc, numRounds)                                                                 \
 428         do {                                                                                                            \
 429                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (uint32_t)(numRounds));        \
 430         } while (0)
 431
 432 /*!
 433  * This macro sets the flow mode.
 434  *
 435  * \param pDesc pointer HW descriptor struct
 436  * \param flowMode Any one of the modes defined in [CC7x-DESC]
 437 */
 438
 439 #define HW_DESC_SET_FLOW_MODE(pDesc, flowMode)                                                                          \
 440         do {                                                                                                            \
 441                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, DATA_FLOW_MODE, (pDesc)->word[4], (flowMode));          \
 442         } while (0)
 443
 444 /*!
 445  * This macro sets the cipher mode.
 446  *
 447  * \param pDesc pointer HW descriptor struct
 448  * \param cipherMode Any one of the modes defined in [CC7x-DESC]
 449 */
 450 #define HW_DESC_SET_CIPHER_MODE(pDesc, cipherMode)                                                                      \
 451         do {                                                                                                            \
 452                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_MODE, (pDesc)->word[4], (cipherMode));           \
 453         } while (0)
 454
 455 /*!
 456  * This macro sets the cipher configuration fields.
 457  *
 458  * \param pDesc pointer HW descriptor struct
 459  * \param cipherConfig Any one of the modes defined in [CC7x-DESC]
 460 */
 461 #define HW_DESC_SET_CIPHER_CONFIG0(pDesc, cipherConfig)                                                                 \
 462         do {                                                                                                            \
 463                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_CONF0, (pDesc)->word[4], (cipherConfig));        \
 464         } while (0)
 465
 466 /*!
 467  * This macro sets the cipher configuration fields.
 468  *
 469  * \param pDesc pointer HW descriptor struct
 470  * \param cipherConfig Any one of the modes defined in [CC7x-DESC]
 471 */
 472 #define HW_DESC_SET_CIPHER_CONFIG1(pDesc, cipherConfig)                                                                 \
 473         do {                                                                                                            \
 474                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_CONF1, (pDesc)->word[4], (cipherConfig));        \
 475         } while (0)
 476
 477 /*!
 478  * This macro sets HW key configuration fields.
 479  *
 480  * \param pDesc pointer HW descriptor struct
 481  * \param hwKey The hw key number as in enun HwCryptoKey
 482 */
 483 #define HW_DESC_SET_HW_CRYPTO_KEY(pDesc, hwKey)                                                                         \
 484         do {                                                                                                            \
 485                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_DO, (pDesc)->word[4], (hwKey)&HW_KEY_MASK_CIPHER_DO);            \
 486                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_CONF2, (pDesc)->word[4], (hwKey>>HW_KEY_SHIFT_CIPHER_CFG2));     \
 487         } while (0)
 488
 489 /*!
 490  * This macro changes the bytes order of all setup-finalize descriptosets.
 491  *
 492  * \param pDesc pointer HW descriptor struct
 493  * \param swapConfig Any one of the modes defined in [CC7x-DESC]
 494 */
 495 #define HW_DESC_SET_BYTES_SWAP(pDesc, swapConfig)                                                                       \
 496         do {                                                                                                            \
 497                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, BYTES_SWAP, (pDesc)->word[4], (swapConfig));            \
 498         } while (0)
 499
 500 /*!
 501  * This macro sets the CMAC_SIZE0 mode.
 502  *
 503  * \param pDesc pointer HW descriptor struct
 504 */
 505 #define HW_DESC_SET_CMAC_SIZE0_MODE(pDesc)                                                                              \
 506         do {                                                                                                            \
 507                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CMAC_SIZE0, (pDesc)->word[4], 0x1);                     \
 508         } while (0)
 509
 510 /*!
 511  * This macro sets the key size for AES engine.
 512  *
 513  * \param pDesc pointer HW descriptor struct
 514  * \param keySize key size in bytes (NOT size code)
 515 */
 516 #define HW_DESC_SET_KEY_SIZE_AES(pDesc, keySize)                                                                        \
 517         do {                                                                                                            \
 518                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, KEY_SIZE, (pDesc)->word[4], ((keySize) >> 3) - 2);      \
 519         } while (0)
 520
 521 /*!
 522  * This macro sets the key size for DES engine.
 523  *
 524  * \param pDesc pointer HW descriptor struct
 525  * \param keySize key size in bytes (NOT size code)
 526 */
 527 #define HW_DESC_SET_KEY_SIZE_DES(pDesc, keySize)                                                                        \
 528         do {                                                                                                            \
 529                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, KEY_SIZE, (pDesc)->word[4], ((keySize) >> 3) - 1);      \
 530         } while (0)
 531
 532 /*!
 533  * This macro sets the descriptor's setup mode
 534  *
 535  * \param pDesc pointer HW descriptor struct
 536  * \param setupMode Any one of the setup modes defined in [CC7x-DESC]
 537 */
 538 #define HW_DESC_SET_SETUP_MODE(pDesc, setupMode)                                                                        \
 539         do {                                                                                                            \
 540                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, SETUP_OPERATION, (pDesc)->word[4], (setupMode));        \
 541         } while (0)
 542
 543 /*!
 544  * This macro sets the descriptor's cipher do
 545  *
 546  * \param pDesc pointer HW descriptor struct
 547  * \param cipherDo Any one of the cipher do defined in [CC7x-DESC]
 548 */
 549 #define HW_DESC_SET_CIPHER_DO(pDesc, cipherDo)                                                                                  \
 550         do {                                                                                                                    \
 551                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_DO, (pDesc)->word[4], (cipherDo)&HW_KEY_MASK_CIPHER_DO); \
 552         } while (0)
 553
 554 /*!
 555  * This macro sets the DIN field of a HW descriptors to star/stop monitor descriptor.
 556  * Used for performance measurements and debug purposes.
 557  *
 558  * \param pDesc pointer HW descriptor struct
 559  */
 560 #define HW_DESC_SET_DIN_MONITOR_CNTR(pDesc)                                                                             \
 561         do {                                                                                                            \
 562                 CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_MEASURE_CNTR, VALUE, (pDesc)->word[1], _HW_DESC_MONITOR_KICK);       \
 563         } while (0)
 564
 565
 566
 567 #endif /*__CC_HW_QUEUE_DEFS_H__*/