2 * Copyright (C) 2012-2017 ARM Limited or its affiliates.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 ARM CryptoCell Linux Crypto Driver
21 #ifndef __SSI_DRIVER_H__
22 #define __SSI_DRIVER_H__
24 #include "ssi_config.h"
26 #include <linux/workqueue.h>
28 #include <linux/interrupt.h>
30 #include <linux/dma-mapping.h>
31 #include <crypto/algapi.h>
32 #include <crypto/internal/skcipher.h>
33 #include <crypto/aes.h>
34 #include <crypto/sha.h>
35 #include <crypto/authenc.h>
36 #include <crypto/hash.h>
37 #include <linux/version.h>
39 #ifndef INT32_MAX /* Missing in Linux kernel */
40 #define INT32_MAX 0x7FFFFFFFL
43 /* Registers definitions from shared/hw/ree_include */
44 #include "dx_reg_base_host.h"
46 #define DX_CC_HOST_VIRT /* must be defined before including dx_cc_regs.h */
47 #include "cc_hw_queue_defs.h"
49 #include "dx_reg_common.h"
51 #include "ssi_sram_mgr.h"
52 #define CC_SUPPORT_SHA DX_DEV_SHA_MAX
53 #include "cc_crypto_ctx.h"
54 #include "ssi_sysfs.h"
55 #include "hash_defs.h"
57 #define DRV_MODULE_VERSION "3.0"
59 #define SSI_DEV_NAME_STR "cc715ree"
60 #define SSI_CC_HAS_AES_CCM 1
61 #define SSI_CC_HAS_AES_GCM 1
62 #define SSI_CC_HAS_AES_XTS 1
63 #define SSI_CC_HAS_AES_ESSIV 1
64 #define SSI_CC_HAS_AES_BITLOCKER 1
65 #define SSI_CC_HAS_AES_CTS 1
66 #define SSI_CC_HAS_MULTI2 0
67 #define SSI_CC_HAS_CMAC 1
69 #define SSI_AXI_IRQ_MASK ((1 << DX_AXIM_CFG_BRESPMASK_BIT_SHIFT) | (1 << DX_AXIM_CFG_RRESPMASK_BIT_SHIFT) | \
70 (1 << DX_AXIM_CFG_INFLTMASK_BIT_SHIFT) | (1 << DX_AXIM_CFG_COMPMASK_BIT_SHIFT))
72 #define SSI_AXI_ERR_IRQ_MASK (1 << DX_HOST_IRR_AXI_ERR_INT_BIT_SHIFT)
74 #define SSI_COMP_IRQ_MASK (1 << DX_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT)
76 /* TEE FIPS status interrupt */
77 #define SSI_GPR0_IRQ_MASK (1 << DX_HOST_IRR_GPR0_BIT_SHIFT)
79 #define SSI_CRA_PRIO 3000
81 #define MIN_HW_QUEUE_SIZE 50 /* Minimum size required for proper function */
83 #define MAX_REQUEST_QUEUE_SIZE 4096
84 #define MAX_MLLI_BUFF_SIZE 2080
85 #define MAX_ICV_NENTS_SUPPORTED 2
87 /* Definitions for HW descriptors DIN/DOUT fields */
90 /* AXI_ID is not actually the AXI ID of the transaction but the value of AXI_ID
91 field in the HW descriptor. The DMA engine +8 that value. */
94 #define SSI_LOG(level, format, ...) \
95 printk(level "cc715ree::%s: " format , __func__, ##__VA_ARGS__)
96 #define SSI_LOG_ERR(format, ...) SSI_LOG(KERN_ERR, format, ##__VA_ARGS__)
97 #define SSI_LOG_WARNING(format, ...) SSI_LOG(KERN_WARNING, format, ##__VA_ARGS__)
98 #define SSI_LOG_NOTICE(format, ...) SSI_LOG(KERN_NOTICE, format, ##__VA_ARGS__)
99 #define SSI_LOG_INFO(format, ...) SSI_LOG(KERN_INFO, format, ##__VA_ARGS__)
101 #define SSI_LOG_DEBUG(format, ...) SSI_LOG(KERN_DEBUG, format, ##__VA_ARGS__)
102 #else /* Debug log messages are removed at compile time for non-DEBUG config. */
103 #define SSI_LOG_DEBUG(format, ...) do {} while (0)
106 #define MIN(a, b) (((a) < (b)) ? (a) : (b))
107 #define MAX(a, b) (((a) > (b)) ? (a) : (b))
109 #define SSI_MAX_IVGEN_DMA_ADDRESSES 3
110 struct ssi_crypto_req {
111 void (*user_cb)(struct device *dev, void *req, void __iomem *cc_base);
113 dma_addr_t ivgen_dma_addr[SSI_MAX_IVGEN_DMA_ADDRESSES]; /* For the first 'ivgen_dma_addr_len' addresses of this array,
114 generated IV would be placed in it by send_request().
115 Same generated IV for all addresses! */
116 unsigned int ivgen_dma_addr_len; /* Amount of 'ivgen_dma_addr' elements to be filled. */
117 unsigned int ivgen_size; /* The generated IV size required, 8/16 B allowed. */
118 struct completion seq_compl; /* request completion */
119 #ifdef ENABLE_CYCLE_COUNT
120 enum stat_op op_type;
121 cycles_t submit_cycle;
127 * struct ssi_drvdata - driver private data context
128 * @cc_base: virt address of the CC registers
129 * @irq: device IRQ number
130 * @irq_mask: Interrupt mask shadow (1 for masked interrupts)
131 * @fw_ver: SeP loaded firmware version
134 struct resource *res_mem;
135 struct resource *res_irq;
136 void __iomem *cc_base;
137 #ifdef DX_BASE_ENV_REGS
138 void __iomem *env_base; /* ARM CryptoCell development FPGAs only */
143 /* Calibration time of start/stop
144 * monitor descriptors */
145 uint32_t monitor_null_cycles;
146 struct platform_device *plat_dev;
147 ssi_sram_addr_t mlli_sram_addr;
148 struct completion icache_setup_completion;
149 void *buff_mgr_handle;
151 void *blkcipher_handle;
152 void *request_mgr_handle;
154 void *sram_mgr_handle;
156 #ifdef ENABLE_CYCLE_COUNT
157 cycles_t isr_exit_cycles; /* Save for isr-to-tasklet latency */
159 uint32_t inflight_counter;
163 struct ssi_crypto_alg {
164 struct list_head entry;
166 int flow_mode; /* Note: currently, refers to the cipher mode only. */
168 struct ssi_drvdata *drvdata;
169 struct crypto_alg crypto_alg;
172 struct ssi_alg_template {
173 char name[CRYPTO_MAX_ALG_NAME];
174 char driver_name[CRYPTO_MAX_ALG_NAME];
175 unsigned int blocksize;
178 struct ablkcipher_alg ablkcipher;
179 struct blkcipher_alg blkcipher;
180 struct cipher_alg cipher;
181 struct compress_alg compress;
184 int flow_mode; /* Note: currently, refers to the cipher mode only. */
187 struct ssi_drvdata *drvdata;
190 struct async_gen_req_ctx {
191 dma_addr_t iv_dma_addr;
192 enum drv_crypto_direction op_type;
196 void dump_byte_array(const char *name, const uint8_t *the_array, unsigned long size);
198 #define dump_byte_array(name, array, size) do { \
202 #ifdef ENABLE_CYCLE_COUNT
203 #define DECL_CYCLE_COUNT_RESOURCES cycles_t _last_cycles_read
204 #define START_CYCLE_COUNT() do { _last_cycles_read = get_cycles(); } while (0)
205 #define END_CYCLE_COUNT(_stat_op_type, _stat_phase) update_host_stat(_stat_op_type, _stat_phase, get_cycles() - _last_cycles_read)
206 #define GET_START_CYCLE_COUNT() _last_cycles_read
207 #define START_CYCLE_COUNT_AT(_var) do { _var = get_cycles(); } while(0)
208 #define END_CYCLE_COUNT_AT(_var, _stat_op_type, _stat_phase) update_host_stat(_stat_op_type, _stat_phase, get_cycles() - _var)
210 #define DECL_CYCLE_COUNT_RESOURCES
211 #define START_CYCLE_COUNT() do { } while (0)
212 #define END_CYCLE_COUNT(_stat_op_type, _stat_phase) do { } while (0)
213 #define GET_START_CYCLE_COUNT() 0
214 #define START_CYCLE_COUNT_AT(_var) do { } while (0)
215 #define END_CYCLE_COUNT_AT(_var, _stat_op_type, _stat_phase) do { } while (0)
216 #endif /*ENABLE_CYCLE_COUNT*/
218 int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe);
219 void fini_cc_regs(struct ssi_drvdata *drvdata);
221 #endif /*__SSI_DRIVER_H__*/